From c1027b36455cf47d336d42e2e42a63f096f7e772 Mon Sep 17 00:00:00 2001
From: Daniel Friesel <derf@finalrewind.org>
Date: Tue, 11 Dec 2018 10:09:37 +0100
Subject: New architecture: msp430fr5994lp (MSP430FR5994 Launchpad)

Almost exclusively copypasted from msp430fr5969lp.
May be replaced by symlinks later on.
---
 src/arch/msp430fr5994lp/driver/spi_b.cc | 75 +++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 src/arch/msp430fr5994lp/driver/spi_b.cc

(limited to 'src/arch/msp430fr5994lp/driver/spi_b.cc')

diff --git a/src/arch/msp430fr5994lp/driver/spi_b.cc b/src/arch/msp430fr5994lp/driver/spi_b.cc
new file mode 100644
index 0000000..0fa71da
--- /dev/null
+++ b/src/arch/msp430fr5994lp/driver/spi_b.cc
@@ -0,0 +1,75 @@
+#include "driver/spi_b.h"
+#include <msp430.h>
+
+#ifndef F_I2C
+#define F_I2C 1000000UL
+#endif
+
+void SPI::setup()
+{
+	UCB0CTLW0 |= UCSWRST;
+
+	/* UCB0CLK Pin 2.2 */
+	P2SEL0 &= ~BIT2;
+	P2SEL1 |= BIT2;
+	P2DIR |= BIT2;
+
+	/* UCB0SIMO Pin 1.6 */
+	P1SEL0 &= ~BIT6;
+	P1SEL1 |= BIT6;
+	P1DIR |= BIT6;
+
+	/* UCB0SOMI Pin 1.7 */
+	P1SEL0 &= ~BIT7;
+	P1SEL1 |= BIT7;
+	P1DIR &= ~BIT7;
+	//P1REN |= BIT6;
+
+	UCB0CTLW0 = UCCKPH | UCMSB | UCMST | UCSYNC | UCMODE_0 | UCSSEL__SMCLK | UCSWRST;
+	UCB0BRW = (F_CPU/F_I2C)-1; // /16 -> 1MHz
+	// UCB0BRW = (F_CPU / F_I2C) - 1
+	UCB0CTLW0 &= ~UCSWRST;
+}
+
+static inline unsigned char clean_rxbuf()
+{
+	return UCB0RXBUF;
+}
+
+signed char SPI::xmit(unsigned char tx_len, unsigned char *tx_buf,
+		unsigned char rx_len, unsigned char *rx_buf)
+{
+	if (tx_len < 1) {
+		return -1;
+	}
+
+	while (UCB0STATW & UCBUSY) ;
+
+	if (!(UCB0IFG & UCTXIFG)) {
+		return -1;
+	}
+
+	UCB0IFG &= ~UCRXIFG;
+	UCB0TXBUF = tx_buf[0];
+
+	unsigned char tx_pos = 1;
+	unsigned char rx_pos = 0;
+
+	while (tx_pos < tx_len || rx_pos < rx_len) {
+		if ((tx_pos < tx_len) && (UCB0IFG & UCTXIFG)) {
+			UCB0TXBUF = tx_buf[tx_pos++];
+		}
+		if (UCB0IFG & UCRXIFG) {
+			if (rx_pos < rx_len) {
+				rx_buf[rx_pos] = UCB0RXBUF;
+			} else {
+				UCB0IFG &= ~UCRXIFG;
+			}
+			rx_pos++;
+		}
+	}
+	while (UCB0STATW & UCBUSY) ;
+	return 0;
+}
+
+SPI spi;
-- 
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