From 45c8997e49650fc86c4323304d67ca87c7ad1e64 Mon Sep 17 00:00:00 2001 From: Daniel Friesel Date: Mon, 30 Nov 2020 15:56:14 +0100 Subject: msp430fr5994: add experimental support for 32kHz operation via LFXT --- src/arch/msp430fr5994lp/arch.cc | 14 +++++++++++++- src/arch/msp430fr5994lp/driver/stdout.cc | 6 ++++++ 2 files changed, 19 insertions(+), 1 deletion(-) (limited to 'src/arch/msp430fr5994lp') diff --git a/src/arch/msp430fr5994lp/arch.cc b/src/arch/msp430fr5994lp/arch.cc index 9b243d1..024b246 100644 --- a/src/arch/msp430fr5994lp/arch.cc +++ b/src/arch/msp430fr5994lp/arch.cc @@ -37,6 +37,8 @@ void Arch::setup(void) // 8MHz DCO CSCTL0_H = CSKEY >> 8; CSCTL1 = DCOFSEL_0; +#elif F_CPU == 32768UL + CSCTL0_H = CSKEY >> 8; #else #error Unsupported F_CPU #endif @@ -50,7 +52,7 @@ void Arch::setup(void) CSCTL0_H = 0; -#ifdef WITH_LOOP +#if defined(WITH_LOOP) || F_CPU == 72368UL // enable LXFT for RTC CSCTL0_H = CSKEY >> 8; CSCTL4 &= ~LFXTOFF; @@ -82,6 +84,12 @@ void Arch::setup(void) TA0CTL |= TACLR; #endif /* TIMER_US */ +#if F_CPU == 32768UL + CSCTL0_H = CSKEY >> 8; + CSCTL2 = SELA__LFXTCLK | SELS__LFXTCLK | SELM__LFXTCLK; + CSCTL0_H = 0; +#endif + #if defined(WITH_LOOP) || defined(TIMER_S) // 1s per wakeup for loop. Independent of SMCLK/F_CPU TA1CTL = TASSEL__ACLK | ID__8 | MC__UP; @@ -153,6 +161,10 @@ void Arch::sleep_ms(unsigned int const ms) TA3CTL = TASSEL__SMCLK | ID__8; // /8 TA3EX0 = 0; // /1 -> /8 (125 kHz) TA3CCR0 = ms * 125; +#elif F_CPU == 32768UL + TA3CTL = TASSEL__SMCLK | ID__8; // /8 + TA3EX0 = 0; // /1 -> /8 (4.096 kHz) + TA3CCR0 = ms * 4; #else #error Unsupported F_CPU #endif /* F_CPU */ diff --git a/src/arch/msp430fr5994lp/driver/stdout.cc b/src/arch/msp430fr5994lp/driver/stdout.cc index b3e8b4d..f3c219a 100644 --- a/src/arch/msp430fr5994lp/driver/stdout.cc +++ b/src/arch/msp430fr5994lp/driver/stdout.cc @@ -32,6 +32,12 @@ void StandardOutput::setup() UCA0CTLW0 = UCSWRST | UCSSEL__SMCLK; UCA0MCTLW = 0x5500; UCA0BR0 = 8; +#elif F_CPU == 32768UL + // Limited to 9600 Baud + // 32768 / 9600 == 3.413333 -> UCOS16 = 0, UCBR0 = 3, UCBRF0 = 0, UCBRS0 = 0x92 ("0.4003") + UCA0CTLW0 = UCSWRST | UCSSEL__SMCLK; + UCA0MCTLW = 0x9200; + UCA0BR0 = 3; #else #error Unsupported F_CPU #endif -- cgit v1.2.3