From 531e1e0e57be542a63b6793611d33ca89a9ecab9 Mon Sep 17 00:00:00 2001 From: Daniel Friesel Date: Wed, 12 Aug 2020 15:33:26 +0200 Subject: stm32f446re: configurable clock speed --- src/arch/stm32f446re-nucleo/arch.cc | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'src/arch/stm32f446re-nucleo/arch.cc') diff --git a/src/arch/stm32f446re-nucleo/arch.cc b/src/arch/stm32f446re-nucleo/arch.cc index c0e2710..99e3e5f 100644 --- a/src/arch/stm32f446re-nucleo/arch.cc +++ b/src/arch/stm32f446re-nucleo/arch.cc @@ -10,8 +10,17 @@ void Arch::setup(void) { - // NUCLEO-F443RE uses 8MHz STLINK clock as input + // NUCLEO-F443RE uses 8MHz STLINK clock (MCO from STLINK MCU) as input + // (it is connected to OSC_IN -> HSE OSC) +#if F_CPU == 180000000UL + rcc_clock_setup_pll(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_180MHZ]); +#elif F_CPU == 168000000UL rcc_clock_setup_pll(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]); +#elif F_CPU == 84000000UL + rcc_clock_setup_pll(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_84MHZ]); +#else +#error Unsupported F_CPU +#endif // counter rcc_periph_clock_enable(RCC_TIM2); -- cgit v1.2.3