From 021e08eba3272e3e3f30b6175464e48792dff1d1 Mon Sep 17 00:00:00 2001 From: Birte Kristina Friesel Date: Fri, 26 Jan 2024 23:21:42 +0100 Subject: atmega2560: provide one DMX driver per extra UART --- src/arch/atmega2560/Kconfig | 3 +++ src/arch/atmega2560/Makefile.inc | 12 +++++++-- src/arch/atmega2560/driver/dmx.cc | 53 -------------------------------------- src/arch/atmega2560/driver/dmx1.cc | 53 ++++++++++++++++++++++++++++++++++++++ src/arch/atmega2560/driver/dmx2.cc | 53 ++++++++++++++++++++++++++++++++++++++ src/arch/atmega2560/driver/dmx3.cc | 53 ++++++++++++++++++++++++++++++++++++++ 6 files changed, 172 insertions(+), 55 deletions(-) delete mode 100644 src/arch/atmega2560/driver/dmx.cc create mode 100644 src/arch/atmega2560/driver/dmx1.cc create mode 100644 src/arch/atmega2560/driver/dmx2.cc create mode 100644 src/arch/atmega2560/driver/dmx3.cc (limited to 'src/arch') diff --git a/src/arch/atmega2560/Kconfig b/src/arch/atmega2560/Kconfig index d93a808..a2814b0 100644 --- a/src/arch/atmega2560/Kconfig +++ b/src/arch/atmega2560/Kconfig @@ -7,18 +7,21 @@ bool "DMX1 Output on PD3 (D18)" help TX: PD3 (UART1) (D18) select meta_driver_dmx +select meta_driver_dmx1 config arch_atmega2560_driver_dmx2 bool "DMX2 Output on PH1 (D16)" help TX: PH1 (UART2) (D16) select meta_driver_dmx +select meta_driver_dmx2 config arch_atmega2560_driver_dmx3 bool "DMX3 Output on PJ1 (D14)" help TX: PJ1 (UART3) (D14) select meta_driver_dmx +select meta_driver_dmx3 config arch_atmega2560_driver_i2c bool "I2C" diff --git a/src/arch/atmega2560/Makefile.inc b/src/arch/atmega2560/Makefile.inc index 39821da..6d82a1c 100644 --- a/src/arch/atmega2560/Makefile.inc +++ b/src/arch/atmega2560/Makefile.inc @@ -83,8 +83,16 @@ ifdef CONFIG_arch_atmega2560_driver_adc CXX_TARGETS += src/arch/atmega2560/driver/adc.cc endif -ifdef CONFIG_arch_atmega2560_driver_dmx - CXX_TARGETS += src/arch/atmega2560/driver/dmx.cc +ifdef CONFIG_arch_atmega2560_driver_dmx1 + CXX_TARGETS += src/arch/atmega2560/driver/dmx1.cc +endif + +ifdef CONFIG_arch_atmega2560_driver_dmx2 + CXX_TARGETS += src/arch/atmega2560/driver/dmx2.cc +endif + +ifdef CONFIG_arch_atmega2560_driver_dmx3 + CXX_TARGETS += src/arch/atmega2560/driver/dmx3.cc endif ifdef CONFIG_arch_atmega2560_driver_spi diff --git a/src/arch/atmega2560/driver/dmx.cc b/src/arch/atmega2560/driver/dmx.cc deleted file mode 100644 index 894ef99..0000000 --- a/src/arch/atmega2560/driver/dmx.cc +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2022 Birte Kristina Friesel - * - * SPDX-License-Identifier: BSD-2-Clause - */ -#include -#include "arch.h" -#include "driver/dmx.h" -#include "driver/gpio.h" - -#undef BAUD -#define BAUD 250000UL -#include - -void DMX::setup() -{ - UBRR3H = UBRRH_VALUE; - UBRR3L = UBRRL_VALUE; - -#if USE_2X - UCSR3A |= _BV(U2X3); -#else - UCSR3A &= ~_BV(U2X3); -#endif - - UCSR3B = _BV(TXEN3); - UCSR3C = _BV(USBS3) | _BV(UCSZ31) | _BV(UCSZ30); // MSB first, 8 data bits, 2 stop bits, no parity -} - -void DMX::write() -{ - // Disable UART for reset and mark signals - UCSR3B &= ~_BV(TXEN3); - gpio.output(GPIO::pj1, 0); - arch.delay_us(88); // break / reset - gpio.output(GPIO::pj1, 1); - arch.delay_us(8); // mark - UCSR3B |= _BV(TXEN3); // causes line to go high - for (uint8_t i = 0; i < 32; i++) { - while (!(UCSR3A & _BV(UDRE3))); - UDR3 = frames[i]; - } - for (uint8_t i = 0; i < 258 - num_frames; i++) { - while (!(UCSR3A & _BV(UDRE3))); - UDR3 = 0; - } - for (uint8_t i = 0; i < 255; i++) { - while (!(UCSR3A & _BV(UDRE3))); - UDR3 = 0; - } -} - -DMX dmx; diff --git a/src/arch/atmega2560/driver/dmx1.cc b/src/arch/atmega2560/driver/dmx1.cc new file mode 100644 index 0000000..1724591 --- /dev/null +++ b/src/arch/atmega2560/driver/dmx1.cc @@ -0,0 +1,53 @@ +/* + * Copyright 2022 Birte Kristina Friesel + * + * SPDX-License-Identifier: BSD-2-Clause + */ +#include +#include "arch.h" +#include "driver/dmx1.h" +#include "driver/gpio.h" + +#undef BAUD +#define BAUD 250000UL +#include + +void DMX1::setup() +{ + UBRR1H = UBRRH_VALUE; + UBRR1L = UBRRL_VALUE; + +#if USE_2X + UCSR1A |= _BV(U2X1); +#else + UCSR1A &= ~_BV(U2X1); +#endif + + UCSR1B = _BV(TXEN1); + UCSR1C = _BV(USBS1) | _BV(UCSZ11) | _BV(UCSZ10); // MSB first, 8 data bits, 2 stop bits, no parity +} + +void DMX1::write() +{ + // Disable UART for reset and mark signals + UCSR1B &= ~_BV(TXEN1); + gpio.output(GPIO::pd3, 0); + arch.delay_us(88); // break / reset + gpio.output(GPIO::pd3, 1); + arch.delay_us(8); // mark + UCSR1B |= _BV(TXEN1); // causes line to go high + for (uint8_t i = 0; i < 32; i++) { + while (!(UCSR1A & _BV(UDRE1))); + UDR1 = frames[i]; + } + for (uint8_t i = 0; i < 258 - num_frames; i++) { + while (!(UCSR1A & _BV(UDRE1))); + UDR1 = 0; + } + for (uint8_t i = 0; i < 255; i++) { + while (!(UCSR1A & _BV(UDRE1))); + UDR1 = 0; + } +} + +DMX1 dmx1; diff --git a/src/arch/atmega2560/driver/dmx2.cc b/src/arch/atmega2560/driver/dmx2.cc new file mode 100644 index 0000000..9b5d35f --- /dev/null +++ b/src/arch/atmega2560/driver/dmx2.cc @@ -0,0 +1,53 @@ +/* + * Copyright 2022 Birte Kristina Friesel + * + * SPDX-License-Identifier: BSD-2-Clause + */ +#include +#include "arch.h" +#include "driver/dmx2.h" +#include "driver/gpio.h" + +#undef BAUD +#define BAUD 250000UL +#include + +void DMX2::setup() +{ + UBRR2H = UBRRH_VALUE; + UBRR2L = UBRRL_VALUE; + +#if USE_2X + UCSR2A |= _BV(U2X2); +#else + UCSR2A &= ~_BV(U2X2); +#endif + + UCSR2B = _BV(TXEN2); + UCSR2C = _BV(USBS2) | _BV(UCSZ21) | _BV(UCSZ20); // MSB first, 8 data bits, 2 stop bits, no parity +} + +void DMX2::write() +{ + // Disable UART for reset and mark signals + UCSR2B &= ~_BV(TXEN2); + gpio.output(GPIO::ph1, 0); + arch.delay_us(88); // break / reset + gpio.output(GPIO::ph1, 1); + arch.delay_us(8); // mark + UCSR2B |= _BV(TXEN2); // causes line to go high + for (uint8_t i = 0; i < 32; i++) { + while (!(UCSR2A & _BV(UDRE2))); + UDR2 = frames[i]; + } + for (uint8_t i = 0; i < 258 - num_frames; i++) { + while (!(UCSR2A & _BV(UDRE2))); + UDR2 = 0; + } + for (uint8_t i = 0; i < 255; i++) { + while (!(UCSR2A & _BV(UDRE2))); + UDR2 = 0; + } +} + +DMX2 dmx2; diff --git a/src/arch/atmega2560/driver/dmx3.cc b/src/arch/atmega2560/driver/dmx3.cc new file mode 100644 index 0000000..0f6db4e --- /dev/null +++ b/src/arch/atmega2560/driver/dmx3.cc @@ -0,0 +1,53 @@ +/* + * Copyright 2022 Birte Kristina Friesel + * + * SPDX-License-Identifier: BSD-2-Clause + */ +#include +#include "arch.h" +#include "driver/dmx3.h" +#include "driver/gpio.h" + +#undef BAUD +#define BAUD 250000UL +#include + +void DMX3::setup() +{ + UBRR3H = UBRRH_VALUE; + UBRR3L = UBRRL_VALUE; + +#if USE_2X + UCSR3A |= _BV(U2X3); +#else + UCSR3A &= ~_BV(U2X3); +#endif + + UCSR3B = _BV(TXEN3); + UCSR3C = _BV(USBS3) | _BV(UCSZ31) | _BV(UCSZ30); // MSB first, 8 data bits, 2 stop bits, no parity +} + +void DMX3::write() +{ + // Disable UART for reset and mark signals + UCSR3B &= ~_BV(TXEN3); + gpio.output(GPIO::pj1, 0); + arch.delay_us(88); // break / reset + gpio.output(GPIO::pj1, 1); + arch.delay_us(8); // mark + UCSR3B |= _BV(TXEN3); // causes line to go high + for (uint8_t i = 0; i < 32; i++) { + while (!(UCSR3A & _BV(UDRE3))); + UDR3 = frames[i]; + } + for (uint8_t i = 0; i < 258 - num_frames; i++) { + while (!(UCSR3A & _BV(UDRE3))); + UDR3 = 0; + } + for (uint8_t i = 0; i < 255; i++) { + while (!(UCSR3A & _BV(UDRE3))); + UDR3 = 0; + } +} + +DMX3 dmx3; -- cgit v1.2.3