From 17831e691af5152e9e1bdd8588e150810c1836a6 Mon Sep 17 00:00:00 2001
From: Daniel Friesel <derf@finalrewind.org>
Date: Mon, 15 Oct 2018 12:26:11 +0200
Subject: MSP430: Support several CPU speeds

---
 src/arch/msp430fr5969lp/arch.cc | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/arch/msp430fr5969lp/arch.cc b/src/arch/msp430fr5969lp/arch.cc
index 04a52c9..7de978c 100644
--- a/src/arch/msp430fr5969lp/arch.cc
+++ b/src/arch/msp430fr5969lp/arch.cc
@@ -9,13 +9,34 @@ void Arch::setup(void)
 
 	PM5CTL0 &= ~LOCKLPM5;
 
-	FRCTL0 = FWPW;
-	FRCTL0_L = 0x10;
-	FRCTL0_H = 0xff;
+	/*
+	 * Note: arch drivers assume SMCLK freq == F_CPU
+	 */
+
+#if F_CPU == 16000000UL
+	FRCTL0 = FWPW; // unlock FRAM Control
+	FRCTL0_L = 0x10; // one wait state before FRAM access (required for 8MHz < F_CPU <= 16 MHz)
+	FRCTL0_H = 0xff; // lock FRAM control by writing an invalid password
 
 	// 16MHz DCO
 	CSCTL0_H = CSKEY >> 8;
 	CSCTL1 = DCORSEL | DCOFSEL_4;
+#elif F_CPU == 8000000UL
+	// 8MHz DCO
+	CSCTL0_H = CSKEY >> 8;
+	CSCTL1 = DCOFSEL_6;
+#elif F_CPU == 4000000UL
+	// 8MHz DCO
+	CSCTL0_H = CSKEY >> 8;
+	CSCTL1 = DCOFSEL_3;
+#elif F_CPU == 1000000UL
+	// 8MHz DCO
+	CSCTL0_H = CSKEY >> 8;
+	CSCTL1 = DCOFSEL_0;
+#else
+#error Unsupported F_CPU
+#endif
+
 #ifdef WITH_LOOP
 	CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;
 #else
-- 
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