From 68f92431e5706b4bed64ad37f0f26e8eef57c11e Mon Sep 17 00:00:00 2001
From: Daniel Friesel <daniel.friesel@uos.de>
Date: Tue, 19 Jul 2022 13:09:19 +0200
Subject: tc1796: set PLL to 150 MHz; implement delay_us/delay_ms

---
 src/arch/infineon-tc1796-mock/arch.cc | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

(limited to 'src')

diff --git a/src/arch/infineon-tc1796-mock/arch.cc b/src/arch/infineon-tc1796-mock/arch.cc
index e219da5..8905f9c 100644
--- a/src/arch/infineon-tc1796-mock/arch.cc
+++ b/src/arch/infineon-tc1796-mock/arch.cc
@@ -5,12 +5,33 @@
  */
 #include "arch.h"
 
+extern "C" {
+#include <machine/wdtcon.h>
+#include <tc1796b/scu.h>
+#include <tc1796b/pmi.h>
+}
+
 #ifdef __acweaving
 #define __delay_cycles(x)
 #endif
 
+#define OF_BYP 29
+#define OF_NDIV 16
+#define OF_PDIV 13
+#define OF_KDIV 8
+#define OF_VCOSEL 6
+#define OF_SYSFS 2
+
 void Arch::setup(void)
 {
+	/*
+	 * 20 MHz Crystal -> 150 MHz clock
+	 * PLL_CLC := (NDIV = 29; PDIV = 0; KDIV = 3; VCOSEL = 2)
+	 */
+	unlock_wdtcon();
+	(*(unsigned int*)0xf0000040) = (29 << OF_NDIV) | (0 << OF_PDIV) | (3 << OF_KDIV) | (2 << OF_VCOSEL);
+	//PMI_CON0.bits.CCBYP = 0;
+	lock_wdtcon();
 }
 
 #ifdef CONFIG_wakeup
@@ -26,13 +47,24 @@ volatile bool sleep_done = false;
 
 void Arch::sleep_ms(unsigned int const ms)
 {
+	delay_ms(ms);
 }
 
 void Arch::delay_us(unsigned int const us)
 {
+	for (unsigned int i = 0; i < us; i++) {
+		for (unsigned int c = 0; c < F_CPU/1000000; c++) {
+			asm volatile("nop");
+		}
+	}
 }
 void Arch::delay_ms(unsigned int const ms)
 {
+	for (unsigned int i = 0; i < ms; i++) {
+		for (unsigned int c = 0; c < F_CPU/1000; c++) {
+			asm volatile("nop");
+		}
+	}
 }
 
 void Arch::idle_loop(void)
-- 
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