Add Hercules RM46L8 Launchpad support (Cortex R4F)

128 files changed, 43930 insertions, 0 deletions

diff --git a/.gitignore b/.gitignore
index 2648f2b..4f4d22a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,5 @@
 *.o
+*.obj
 *.su
 /.config
 /.config.old
diff --git a/include/arch/rm46l8lp/driver/counter.h b/include/arch/rm46l8lp/driver/counter.h
new file mode 100644
index 0000000..ee4b595
--- /dev/null
+++ b/include/arch/rm46l8lp/driver/counter.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2020 Daniel Friesel
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#ifndef COUNTER_H
+#define COUNTER_H
+
+#include "rti.h"
+#include <stdint.h>
+
+typedef uint32_t counter_value_t;
+typedef uint32_t counter_overflow_t;
+
+class Counter {
+	private:
+		Counter(const Counter &copy);
+
+	public:
+		uint32_t value;
+		uint32_t overflow;
+
+		Counter() : overflow(0) {}
+
+		inline void start() {
+			rtiREG1->CNT[0].UCx = 0;
+			rtiREG1->CNT[0].FRCx = 0;
+			rtiREG1->GCTRL |= ((uint32)1 << (rtiCOUNTER_BLOCK0 & 3));
+		}
+
+		inline void stop() {
+			rtiREG1->GCTRL &= ~(uint32)((uint32)1 << (rtiCOUNTER_BLOCK0 & 3));
+			overflow = rtiREG1->CNT[0].FRCx;
+			value = rtiREG1->CNT[0].UCx;
+		}
+};
+
+extern Counter counter;
+
+#endif
diff --git a/include/arch/rm46l8lp/driver/gpio.h b/include/arch/rm46l8lp/driver/gpio.h
new file mode 100644
index 0000000..0cefae1
--- /dev/null
+++ b/include/arch/rm46l8lp/driver/gpio.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2022 Daniel Friesel
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#ifndef GPIO_H
+#define GPIO_H
+
+#include "gio.h"
+
+class GPIO {
+	private:
+		GPIO(const GPIO &copy);
+
+	public:
+		GPIO () {}
+
+		enum Pin : unsigned char {
+			a_0 = 0, a_1, a_2, a_3, a_4, a_5, a_6, a_7,
+			b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7,
+			PIN_INVALID
+		};
+
+		inline void setup() {
+			gioInit();
+		}
+		inline void led_on(unsigned char id = 0) {
+			if (id == 0) {
+				gioSetBit(gioPORTB,1, 1);
+			} else {
+				gioSetBit(gioPORTB,2, 1);
+			}
+		}
+		inline void led_off(unsigned char id = 0) {
+			if (id == 0) {
+				gioSetBit(gioPORTB,1, 0);
+			} else {
+				gioSetBit(gioPORTB,2, 0);
+			}
+		}
+		inline void led_toggle(unsigned char id = 0) {
+			if (id == 0) {
+				gioToggleBit(gioPORTB,1);
+			} else {
+				gioToggleBit(gioPORTB,2);
+			}
+		}
+		inline void input(unsigned char const pin) {
+			// TODO
+		}
+		inline void input(unsigned char const pin, unsigned char const pull) {
+			// TODO
+		}
+		inline void output(unsigned char const pin) {
+			// TODO
+		}
+		inline void output(unsigned char const pin, unsigned char const value) {
+			// TODO
+		}
+		inline unsigned char read(unsigned char const pin) {
+			// TODO
+			return 0;
+		}
+		inline void write(unsigned char const pin, unsigned char value) {
+			// TODO
+		}
+		inline void write_mask(unsigned char const pin_base, unsigned char set_mask, unsigned char clear_mask) {
+			// TODO
+		}
+};
+
+extern GPIO gpio;
+
+#endif
diff --git a/include/arch/rm46l8lp/driver/stdout.h b/include/arch/rm46l8lp/driver/stdout.h
new file mode 100644
index 0000000..b701dc1
--- /dev/null
+++ b/include/arch/rm46l8lp/driver/stdout.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2022 Daniel Friesel
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#ifndef STANDARDOUTPUT_H
+#define STANDARDOUTPUT_H
+
+#include "object/outputstream.h"
+
+class StandardOutput : public OutputStream {
+	private:
+		StandardOutput(const StandardOutput &copy);
+
+	public:
+		StandardOutput () {}
+		void setup();
+
+		virtual void put(char c) override;
+};
+
+extern StandardOutput kout;
+
+#endif
diff --git a/include/arch/rm46l8lp/driver/uptime.h b/include/arch/rm46l8lp/driver/uptime.h
new file mode 100644
index 0000000..b4e7523
--- /dev/null
+++ b/include/arch/rm46l8lp/driver/uptime.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2020 Daniel Friesel
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#ifndef UPTIME_H
+#define UPTIME_H
+
+class Uptime {
+	private:
+		Uptime(const Uptime &copy);
+#ifdef TIMER_S
+		unsigned int seconds;
+#endif
+
+	public:
+#ifdef TIMER_S
+		Uptime () : seconds(0) {}
+#else
+		Uptime () {}
+#endif
+#ifdef TIMER_S
+		inline unsigned int get_s() { return seconds; }
+		inline void tick_s() { seconds++; }
+#endif
+};
+
+extern Uptime uptime;
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/Device_RM46.h b/include/arch/rm46l8lp/halcogen/Device_RM46.h
new file mode 100644
index 0000000..991fcdf
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/Device_RM46.h
@@ -0,0 +1,111 @@
+/**********************************************************************************************************************
+ *  FILE DESCRIPTION
+ *  -------------------------------------------------------------------------------------------------------------------
+ *         File:  Device_RM46.c
+ *      Project:  Tms570_TIFEEDriver
+ *       Module:  TIFEEDriver
+ *    Generator:  None
+ *
+ *  Description:  This file defines the number of sectors.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author:  Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version        Date         Author               Change ID        Description
+ *--------------------------------------------------------------------------------------------------------------------- 
+ * 01.15.00		  06Jun2014    Vishwanath Reddy 	                 History Added.
+ *********************************************************************************************************************/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+ /*********************************************************************************************************************
+ * INCLUDES
+ *********************************************************************************************************************/
+
+#ifndef DEVICE_RM46_H
+#define DEVICE_RM46_H
+
+
+/** @def DEVICE_CONFIGURATION_VERSION
+*   @brief Device Configuration Version
+*
+*   @note Indicates the current version of the device files
+*/
+#define DEVICE_CONFIGURATION_VERSION 0U             /* Indicates the current version of the device files */
+
+/** @def DEVICE_NUMBER_OF_FLASH_BANKS
+*   @brief Number of Flash Banks
+*
+*   @note Defines the number of Flash Banks on the device
+*/
+#define DEVICE_NUMBER_OF_FLASH_BANKS 1U             /* Defines the number of Flash Banks on the device */
+
+
+/** @def DEVICE_BANK_MAX_NUMBER_OF_SECTORS
+*   @brief Maximum number of Sectors
+*
+*   @note Defines the maxium number of sectors in all banks
+*/
+#define DEVICE_BANK_MAX_NUMBER_OF_SECTORS 4U        /* Defines the maxium number of sectors in all banks */
+
+/** @def DEVICE_BANK1_NUMBER_OF_SECTORS
+*   @brief Number of Sectors
+*
+*   @note Defines the number of sectors in bank1
+*/
+#define DEVICE_BANK1_NUMBER_OF_SECTORS 4U           /* Defines the number of sectors in bank1 */
+
+
+/** @def DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS
+*   @brief Number of Sectors
+*
+*   @note Defines the number of Read Cycle Thresholds 
+*/
+#define DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS 4U   /* Defines the number of Read Cycle Thresholds */
+
+
+/* Include Files */
+#ifndef _PLATFORM_TYPES_H_
+#define _PLATFORM_TYPES_H_
+#endif
+#include "F021.h"
+#include "hal_stdtypes.h"
+#include "Device_types.h"
+
+#endif /* DEVICE_RM46_H */
+
+/* End of File */
diff --git a/include/arch/rm46l8lp/halcogen/Device_TMS570LS12.h b/include/arch/rm46l8lp/halcogen/Device_TMS570LS12.h
new file mode 100644
index 0000000..0fdd093
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/Device_TMS570LS12.h
@@ -0,0 +1,111 @@
+/**********************************************************************************************************************
+ *  FILE DESCRIPTION
+ *  -------------------------------------------------------------------------------------------------------------------
+ *         File:  Device_TMS570LS12.h
+ *      Project:  Tms570_TIFEEDriver
+ *       Module:  TIFEEDriver
+ *    Generator:  None
+ *
+ *  Description:  This file defines the number of sectors.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author:  Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version        Date         Author               Change ID        Description
+ *--------------------------------------------------------------------------------------------------------------------- 
+ * 01.15.00		  06Jun2014    Vishwanath Reddy 	                 History Added.
+ *********************************************************************************************************************/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+ /*********************************************************************************************************************
+ * INCLUDES
+ *********************************************************************************************************************/
+
+#ifndef DEVICE_TMS570LS12x_H
+#define DEVICE_TMS570LS12x_H
+
+
+/** @def DEVICE_CONFIGURATION_VERSION
+*   @brief Device Configuration Version
+*
+*   @note Indicates the current version of the device files
+*/
+#define DEVICE_CONFIGURATION_VERSION 0U             /* Indicates the current version of the device files */
+
+/** @def DEVICE_NUMBER_OF_FLASH_BANKS
+*   @brief Number of Flash Banks
+*
+*   @note Defines the number of Flash Banks on the device
+*/
+#define DEVICE_NUMBER_OF_FLASH_BANKS 1U             /* Defines the number of Flash Banks on the device */
+
+
+/** @def DEVICE_BANK_MAX_NUMBER_OF_SECTORS
+*   @brief Maximum number of Sectors
+*
+*   @note Defines the maxium number of sectors in all banks
+*/
+#define DEVICE_BANK_MAX_NUMBER_OF_SECTORS 4U        /* Defines the maxium number of sectors in all banks */
+
+/** @def DEVICE_BANK1_NUMBER_OF_SECTORS
+*   @brief Number of Sectors
+*
+*   @note Defines the number of sectors in bank1
+*/
+#define DEVICE_BANK1_NUMBER_OF_SECTORS 4U           /* Defines the number of sectors in bank1 */
+
+
+/** @def DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS
+*   @brief Number of Sectors
+*
+*   @note Defines the number of Read Cycle Thresholds 
+*/
+#define DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS 4U   /* Defines the number of Read Cycle Thresholds */
+
+
+/* Include Files */
+#ifndef _PLATFORM_TYPES_H_
+#define _PLATFORM_TYPES_H_
+#endif
+#include "F021.h"
+#include "hal_stdtypes.h"
+#include "Device_types.h"
+
+#endif /* DEVICE_TMS570LS12x_H */
+
+/* End of File */
diff --git a/include/arch/rm46l8lp/halcogen/Device_header.h b/include/arch/rm46l8lp/halcogen/Device_header.h
new file mode 100644
index 0000000..d7c50f1
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/Device_header.h
@@ -0,0 +1,67 @@
+/**********************************************************************************************************************
+ *  FILE DESCRIPTION
+ *  -------------------------------------------------------------------------------------------------------------------
+ *         File:  Device_header.h
+ *      Project:  Tms570_TIFEEDriver
+ *       Module:  TIFEEDriver
+ *    Generator:  None
+ *
+ *  Description:  This file includes the header file.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author:  Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version        Date         Author               Change ID        Description
+ *--------------------------------------------------------------------------------------------------------------------- 
+ * 01.15.00		  06Jun2014    Vishwanath Reddy 	                 History Added.
+ *********************************************************************************************************************/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+ /*********************************************************************************************************************
+ * INCLUDES
+ *********************************************************************************************************************/
+
+#ifndef TI_FEE_DEVICEHEADER_H
+#define TI_FEE_DEVICEHEADER_H
+ 
+/* Uncomment the appropriate include file depending on the device you are using */
+#include "Device_RM46.h"
+
+/* End of file */
+#endif
+
diff --git a/include/arch/rm46l8lp/halcogen/Device_types.h b/include/arch/rm46l8lp/halcogen/Device_types.h
new file mode 100644
index 0000000..4f945e2
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/Device_types.h
@@ -0,0 +1,116 @@
+/**********************************************************************************************************************
+ *  FILE DESCRIPTION
+ *  -------------------------------------------------------------------------------------------------------------------
+ *         File:  Device_types.h
+ *      Project:  Tms570_TIFEEDriver
+ *       Module:  TIFEEDriver
+ *    Generator:  None
+ *
+ *  Description:  This file defines the structures.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author:  Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version        Date         Author               Change ID        Description
+ *--------------------------------------------------------------------------------------------------------------------- 
+ * 01.15.00		  06Jun2014    Vishwanath Reddy 	                 History Added.
+ *********************************************************************************************************************/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+ /*********************************************************************************************************************
+ * INCLUDES
+ *********************************************************************************************************************/
+
+
+#ifndef DEVICE_TYPES_H
+#define DEVICE_TYPES_H
+
+#include "hal_stdtypes.h"
+
+/* Enum to describe the type of error handling on the device */
+typedef enum
+{
+   Device_ErrorHandlingNone,                /* Device has no error handling */
+   Device_ErrorHandlingParity,              /* Device has parity error handling */
+   Device_ErrorHandlingEcc                  /* Device has ECC error handling */
+} Device_FlashErrorCorrectionProcessType;
+
+/* Enum to describe the ARM core on the device*/
+typedef enum
+{
+	Device_CoreNone,      /* To indicate that the device has a single core */
+	Device_Arm7,		  /* To indicate that the device has a ARM7 core	*/
+	Device_CortexR4,	  /* To indicate that the device has a CortexR4 core */
+	Device_CortexM3	      /* To indicate that the device has a CortexM3 core */
+}Device_ArmCoreType;
+
+/* Structure defines an individual sector within a bank */
+typedef struct
+{   
+   Fapi_FlashSectorType Device_Sector;										   /* Sector number */ 
+   uint32 Device_SectorStartAddress;                                           /* Starting address of the sector */
+   uint32 Device_SectorLength;                                                 /* Length of the sector */
+   uint32 Device_MaxWriteCycles;                                               /* Number of cycles the sector is rated for */
+   uint32 Device_EccAddress;
+   uint32 Device_EccLength;
+} Device_SectorType;
+
+/* Structure defines an individual bank */
+typedef struct
+{  
+   Fapi_FmcRegistersType * Device_ControlRegister;	
+   Fapi_FlashBankType Device_Core;                                                     /* Core number for this bank */       
+   Device_SectorType Device_SectorInfo[DEVICE_BANK_MAX_NUMBER_OF_SECTORS];             /* Array of the Sectors within a bank */
+} Device_BankType;
+
+/* Structure defines the Flash structure of the device */
+typedef struct
+{
+   uint8 Device_DeviceName[12];                                                  /* Device name */
+   uint32 Device_EngineeringId;                                                  /* Device Engineering ID */
+   Device_FlashErrorCorrectionProcessType Device_FlashErrorHandlingProcessInfo;  /* Indicates which type of bit Error handling is on the device */   
+   Device_ArmCoreType	Device_MasterCore;									     /* Indicates the Master core type on the device */   
+   boolean Device_SupportsInterrupts;                                            /* Indicates if the device supports Flash interrupts for processing Flash */   
+   uint32 Device_NominalWriteTime;                                               /* Nominal time for one write command operation in uS */
+   uint32 Device_MaximumWriteTime;                                               /* Maximum time for one write command operation in uS */ 
+   Device_BankType Device_BankInfo[DEVICE_NUMBER_OF_FLASH_BANKS];                /* Array of Banks on the device */
+} Device_FlashType;
+
+#endif /* DEVICE_TYPES_H */
+
+/* End of File */
diff --git a/include/arch/rm46l8lp/halcogen/MemMap.h b/include/arch/rm46l8lp/halcogen/MemMap.h
new file mode 100644
index 0000000..5abae66
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/MemMap.h
@@ -0,0 +1,70 @@
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef __MEM_MAP_H__
+#define __MEM_MAP_H__
+/*FEE*/
+#ifdef FEE_START_SEC_VAR_INIT_UNSPECIFIED
+#pragma SET_DATA_SECTION("FEE_DATA_SECTION")
+#undef FEE_START_SEC_VAR_INIT_UNSPECIFIED
+#endif
+
+#ifdef FEE_STOP_SEC_VAR_INIT_UNSPECIFIED
+#pragma SET_DATA_SECTION()
+#undef FEE_STOP_SEC_VAR_INIT_UNSPECIFIED
+#endif
+
+#ifdef FEE_START_SEC_CONST_UNSPECIFIED
+#pragma SET_DATA_SECTION("FEE_CONST_SECTION")
+#undef FEE_START_SEC_CONST_UNSPECIFIED
+#endif
+
+#ifdef FEE_STOP_SEC_CONST_UNSPECIFIED
+#pragma SET_DATA_SECTION()
+#undef FEE_STOP_SEC_CONST_UNSPECIFIED
+#endif
+
+#ifdef FEE_START_SEC_CODE
+#pragma SET_CODE_SECTION("FEE_TEXT_SECTION")
+#undef FEE_START_SEC_CODE
+#endif
+
+#ifdef FEE_STOP_SEC_CODE
+#pragma SET_CODE_SECTION()
+#undef FEE_STOP_SEC_CODE
+#endif
+
+
+#endif  /* __MEM_MAP_H__ */
diff --git a/include/arch/rm46l8lp/halcogen/adc.h b/include/arch/rm46l8lp/halcogen/adc.h
new file mode 100644
index 0000000..53979d4
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/adc.h
@@ -0,0 +1,311 @@
+/** @file adc.h
+*   @brief ADC Driver Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the ADC driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __ADC_H__
+#define __ADC_H__
+
+#include "reg_adc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* ADC General Definitions */
+
+/** @def adcGROUP0
+*   @brief Alias name for ADC event group
+*
+*   @note This value should be used for API argument @a group
+*/
+#define adcGROUP0 0U
+
+/** @def adcGROUP1
+*   @brief Alias name for ADC group 1
+*
+*   @note This value should be used for API argument @a group
+*/
+#define adcGROUP1 1U
+
+/** @def adcGROUP2
+*   @brief Alias name for ADC group 2
+*
+*   @note This value should be used for API argument @a group
+*/
+#define adcGROUP2 2U
+
+/** @def ADC_12_BIT_MODE
+*   @brief Alias name for ADC 12-bit mode of operation
+*/
+#define ADC_12_BIT_MODE 0x80000000U
+
+/** @enum adcResolution
+*   @brief Alias names for data resolution
+*   This enumeration is used to provide alias names for the data resolution:
+*     - 12 bit resolution
+*     - 10 bit resolution
+*     - 8  bit resolution
+*/
+enum adcResolution
+{
+    ADC_12_BIT = 0x00000000U, /**< Alias for 12 bit data resolution */
+    ADC_10_BIT = 0x00000100U, /**< Alias for 10 bit data resolution */
+    ADC_8_BIT  = 0x00000200U  /**< Alias for 8 bit data resolution  */
+};
+
+/** @enum adcFiFoStatus
+*   @brief Alias names for FiFo status
+*   This enumeration is used to provide alias names for the current FiFo states:
+*     - FiFo is not full
+*     - FiFo is full
+*     - FiFo overflow occurred
+*/
+
+enum adcFiFoStatus
+{
+    ADC_FIFO_IS_NOT_FULL = 0U, /**< Alias for FiFo is not full       */
+    ADC_FIFO_IS_FULL     = 1U, /**< Alias for FiFo is full           */
+    ADC_FIFO_OVERFLOW    = 3U  /**< Alias for FiFo overflow occurred  */
+};
+
+/** @enum adcConversionStatus
+*   @brief Alias names for conversion status
+*   This enumeration is used to provide alias names for the current conversion states:
+*     - Conversion is not finished
+*     - Conversion is finished
+*/
+
+enum adcConversionStatus
+{
+    ADC_CONVERSION_IS_NOT_FINISHED = 0U, /**< Alias for current conversion is not finished */
+    ADC_CONVERSION_IS_FINISHED     = 8U  /**< Alias for current conversion is  finished    */
+};
+
+/** @enum adc1HwTriggerSource
+*   @brief Alias names for hardware trigger source
+*   This enumeration is used to provide alias names for the hardware trigger sources:
+*/
+
+enum adc1HwTriggerSource
+{
+	ADC1_EVENT = 0U,       /**< Alias for event pin             */
+	ADC1_HET1_8 = 1U,      /**< Alias for HET1 pin 8            */
+	ADC1_HET1_10 = 2U,     /**< Alias for HET1 pin 10           */
+	ADC1_RTI_COMP0 = 3U,   /**< Alias for RTI compare 0 match   */
+	ADC1_HET1_12 = 4U,     /**< Alias for HET1 pin 12           */
+	ADC1_HET1_14 = 5U,     /**< Alias for HET1 pin 14           */
+	ADC1_GIOB0 = 6U,       /**< Alias for GIO port b pin 0      */
+	ADC1_GIOB1 = 7U,       /**< Alias for GIO port b pin 1      */
+
+	ADC1_HET2_5 = 1U,      /**< Alias for HET2 pin 5            */
+	ADC1_HET1_27 = 2U,     /**< Alias for HET1 pin 27           */
+	ADC1_HET1_17 = 4U,     /**< Alias for HET1 pin 17           */
+	ADC1_HET1_19 = 5U,     /**< Alias for HET1 pin 19           */
+	ADC1_HET1_11 = 6U,     /**< Alias for HET1 pin 11           */
+	ADC1_HET2_13 = 7U,     /**< Alias for HET2 pin 13           */
+
+	ADC1_EPWM_B = 1U,      /**< Alias for B Signal EPWM         */
+	ADC1_EPWM_A1 = 3U,     /**< Alias for A1 Signal EPWM        */	
+	ADC1_HET2_1 = 5U,      /**< Alias for HET2 pin 1            */
+	ADC1_EPWM_A2 = 6U,     /**< Alias for A2 Signal EPWM        */
+	ADC1_EPWM_AB = 7U      /**< Alias for AB Signal EPWM        */	
+
+};
+
+/** @enum adc2HwTriggerSource
+*   @brief Alias names for hardware trigger source
+*   This enumeration is used to provide alias names for the hardware trigger sources:
+*/
+
+enum adc2HwTriggerSource
+{
+	ADC2_EVENT = 0U,       /**< Alias for event pin             */
+	ADC2_HET1_8 = 1U,      /**< Alias for HET1 pin 8            */
+	ADC2_HET1_10 = 2U,     /**< Alias for HET1 pin 10           */
+	ADC2_RTI_COMP0 = 3U,   /**< Alias for RTI compare 0 match   */
+	ADC2_HET1_12 = 4U,     /**< Alias for HET1 pin 12           */
+	ADC2_HET1_14 = 5U,     /**< Alias for HET1 pin 14           */
+	ADC2_GIOB0 = 6U,       /**< Alias for GIO port b pin 0      */
+	ADC2_GIOB1 = 7U,       /**< Alias for GIO port b pin 1      */
+	ADC2_HET2_5 = 1U,      /**< Alias for HET2 pin 5            */
+	ADC2_HET1_27 = 2U,     /**< Alias for HET1 pin 27           */
+	ADC2_HET1_17 = 4U,     /**< Alias for HET1 pin 17           */
+	ADC2_HET1_19 = 5U,     /**< Alias for HET1 pin 19           */
+	ADC2_HET1_11 = 6U,     /**< Alias for HET1 pin 11           */
+	ADC2_HET2_13 = 7U,     /**< Alias for HET2 pin 13           */
+	
+	ADC2_EPWM_B = 1U,      /**< Alias for B Signal EPWM         */
+	ADC2_EPWM_A1 = 3U,     /**< Alias for A1 Signal EPWM        */	
+	ADC2_HET2_1 = 5U,      /**< Alias for HET2 pin 1            */
+	ADC2_EPWM_A2 = 6U,     /**< Alias for A2 Signal EPWM        */
+	ADC2_EPWM_AB = 7U      /**< Alias for AB Signal EPWM        */	
+
+};
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @struct adcData
+*   @brief ADC Conversion data structure
+*
+*   This type is used to pass adc conversion data.
+*/
+/** @typedef adcData_t
+*   @brief ADC Data Type Definition
+*/
+typedef struct adcData
+{
+    uint32            id;     /**< Channel/Pin Id        */
+    uint16 value;  /**< Conversion data value */
+} adcData_t;
+
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+typedef struct adc_config_reg
+{           
+    uint32 CONFIG_OPMODECR;
+    uint32 CONFIG_CLOCKCR;
+    uint32 CONFIG_GxMODECR[3U];
+    uint32 CONFIG_G0SRC;
+    uint32 CONFIG_G1SRC;
+    uint32 CONFIG_G2SRC;
+    uint32 CONFIG_BNDCR;
+    uint32 CONFIG_BNDEND;
+    uint32 CONFIG_G0SAMP;
+    uint32 CONFIG_G1SAMP;
+    uint32 CONFIG_G2SAMP;
+    uint32 CONFIG_G0SAMPDISEN;
+    uint32 CONFIG_G1SAMPDISEN;
+    uint32 CONFIG_G2SAMPDISEN;
+    uint32 CONFIG_PARCR;
+}adc_config_reg_t;
+
+#define ADC1_OPMODECR_CONFIGVALUE		0x81140001U
+#define ADC1_CLOCKCR_CONFIGVALUE		(7U)
+
+#define ADC1_G0MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U)
+#define ADC1_G1MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U)
+#define ADC1_G2MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U)
+
+#define ADC1_G0SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC1_EVENT)
+#define ADC1_G1SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC1_EVENT)
+#define ADC1_G2SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC1_EVENT)
+
+#define ADC1_BNDCR_CONFIGVALUE			((uint32)((uint32)8U << 16U)|(8U + 8U))
+#define ADC1_BNDEND_CONFIGVALUE			(2U)
+
+#define ADC1_G0SAMP_CONFIGVALUE			(1U)
+#define ADC1_G1SAMP_CONFIGVALUE			(0U)
+#define ADC1_G2SAMP_CONFIGVALUE			(1U)
+
+#define ADC1_G0SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
+#define ADC1_G1SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
+#define ADC1_G2SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
+
+#define ADC1_PARCR_CONFIGVALUE			(0x00000005U)
+
+
+/** 
+ *  @defgroup ADC ADC
+ *  @brief Analog To Digital Converter Module.
+ *  
+ *  The microcontroller includes two 12-bit ADC modules with selectable 10-bit or 12-bit resolution
+ *
+ *	Related Files
+ *   - reg_adc.h
+ *   - adc.h
+ *   - adc.c
+ *  @addtogroup ADC
+ *  @{
+ */
+ 
+/* ADC Interface Functions */
+
+void adcInit(void);
+void adcStartConversion(adcBASE_t *adc, uint32 group);
+void adcStopConversion(adcBASE_t *adc, uint32 group);
+void adcResetFiFo(adcBASE_t *adc, uint32 group);
+uint32  adcGetData(adcBASE_t *adc, uint32 group, adcData_t *data);
+uint32  adcIsFifoFull(adcBASE_t *adc, uint32 group);
+uint32  adcIsConversionComplete(adcBASE_t *adc, uint32 group);
+void adcEnableNotification(adcBASE_t *adc, uint32 group);
+void adcDisableNotification(adcBASE_t *adc, uint32 group);
+void adcCalibration(adcBASE_t *adc);
+uint32 adcMidPointCalibration(adcBASE_t *adc);
+void adcSetEVTPin(adcBASE_t *adc, uint32 value);
+uint32 adcGetEVTPin(adcBASE_t *adc);
+
+void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type);
+void adc2GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type);
+
+/** @fn void adcNotification(adcBASE_t *adc, uint32 group)
+*   @brief Group notification
+*   @param[in] adc Pointer to ADC node:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group number of ADC node:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   @note This function has to be provide by the user.
+*/
+void adcNotification(adcBASE_t *adc, uint32 group);
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/can.h b/include/arch/rm46l8lp/halcogen/can.h
new file mode 100644
index 0000000..54f3ca4
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/can.h
@@ -0,0 +1,729 @@
+/** @file can.h
+*   @brief CAN Driver Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the CAN driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __CAN_H__
+#define __CAN_H__
+
+#include "reg_can.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* CAN General Definitions */
+
+/** @def canLEVEL_ACTIVE
+*   @brief Alias name for CAN error operation level active (Error counter 0-31)  
+*/
+#define canLEVEL_ACTIVE 0x00U
+
+/** @def canLEVEL_PASSIVE
+*   @brief Alias name for CAN error operation level passive (Error counter 32-63)  
+*/
+#define canLEVEL_PASSIVE 0x20U
+
+/** @def canLEVEL_WARNING
+*   @brief Alias name for CAN error operation level warning (Error counter 64-127)  
+*/
+#define canLEVEL_WARNING 0x40U
+
+/** @def canLEVEL_BUS_OFF
+*   @brief Alias name for CAN error operation level bus off (Error counter 128-255)  
+*/
+#define canLEVEL_BUS_OFF 0x80U
+
+/** @def canLEVEL_PARITY_ERR
+*   @brief Alias name for CAN Parity error (Error counter 256-511)  
+*/
+#define canLEVEL_PARITY_ERR 0x100U
+
+/** @def canLEVEL_TxOK
+*   @brief Alias name for CAN Sucessful Transmission
+*/
+#define canLEVEL_TxOK 0x08U
+
+/** @def canLEVEL_RxOK
+*   @brief Alias name for CAN Sucessful Reception
+*/
+#define canLEVEL_RxOK 0x10U
+
+/** @def canLEVEL_WakeUpPnd
+*   @brief Alias name for CAN Initiated a WakeUp to system
+*/
+#define canLEVEL_WakeUpPnd 0x200U
+
+/** @def canLEVEL_PDA
+*   @brief Alias name for CAN entered low power mode successfully.
+*/
+#define canLEVEL_PDA 0x400U
+
+/** @def canERROR_NO
+*   @brief Alias name for no CAN error occurred 
+*/
+#define canERROR_OK 0U
+
+/** @def canERROR_STUFF
+*   @brief Alias name for CAN stuff error an RX message 
+*/
+#define canERROR_STUFF 1U
+
+/** @def canERROR_FORMAT
+*   @brief Alias name for CAN form/format error an RX message 
+*/
+#define canERROR_FORMAT 2U
+
+/** @def canERROR_ACKNOWLEDGE
+*   @brief Alias name for CAN TX message wasn't acknowledged  
+*/
+#define canERROR_ACKNOWLEDGE 3U
+
+/** @def canERROR_BIT1
+*   @brief Alias name for CAN TX message sending recessive level but monitoring dominant  
+*/
+#define canERROR_BIT1 4U
+
+/** @def canERROR_BIT0
+*   @brief Alias name for CAN TX message sending dominant level but monitoring recessive  
+*/
+#define canERROR_BIT0 5U
+
+/** @def canERROR_CRC
+*   @brief Alias name for CAN RX message received wrong CRC  
+*/
+#define canERROR_CRC 6U
+
+/** @def canERROR_NO
+*   @brief Alias name for CAN no message has send or received since last call of CANGetLastError  
+*/
+#define canERROR_NO 7U
+
+/** @def canMESSAGE_BOX1
+*   @brief Alias name for CAN message box 1
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX1 1U
+
+/** @def canMESSAGE_BOX2
+*   @brief Alias name for CAN message box 2
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX2 2U
+
+/** @def canMESSAGE_BOX3
+*   @brief Alias name for CAN message box 3
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX3 3U
+
+/** @def canMESSAGE_BOX4
+*   @brief Alias name for CAN message box 4
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX4 4U
+
+/** @def canMESSAGE_BOX5
+*   @brief Alias name for CAN message box 5
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX5 5U
+
+/** @def canMESSAGE_BOX6
+*   @brief Alias name for CAN message box 6
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX6 6U
+
+/** @def canMESSAGE_BOX7
+*   @brief Alias name for CAN message box 7
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX7 7U
+
+/** @def canMESSAGE_BOX8
+*   @brief Alias name for CAN message box 8
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX8 8U
+
+/** @def canMESSAGE_BOX9
+*   @brief Alias name for CAN message box 9
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX9 9U
+
+/** @def canMESSAGE_BOX10
+*   @brief Alias name for CAN message box 10
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX10 10U
+
+/** @def canMESSAGE_BOX11
+*   @brief Alias name for CAN message box 11
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX11 11U
+
+/** @def canMESSAGE_BOX12
+*   @brief Alias name for CAN message box 12
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX12 12U
+
+/** @def canMESSAGE_BOX13
+*   @brief Alias name for CAN message box 13
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX13 13U
+
+/** @def canMESSAGE_BOX14
+*   @brief Alias name for CAN message box 14
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX14 14U
+
+/** @def canMESSAGE_BOX15
+*   @brief Alias name for CAN message box 15
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX15 15U
+
+/** @def canMESSAGE_BOX16
+*   @brief Alias name for CAN message box 16
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX16 16U
+
+/** @def canMESSAGE_BOX17
+*   @brief Alias name for CAN message box 17
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX17 17U
+
+/** @def canMESSAGE_BOX18
+*   @brief Alias name for CAN message box 18
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX18 18U
+
+/** @def canMESSAGE_BOX19
+*   @brief Alias name for CAN message box 19
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX19 19U
+
+/** @def canMESSAGE_BOX20
+*   @brief Alias name for CAN message box 20
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX20 20U
+
+/** @def canMESSAGE_BOX21
+*   @brief Alias name for CAN message box 21
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX21 21U
+
+/** @def canMESSAGE_BOX22
+*   @brief Alias name for CAN message box 22
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX22 22U
+
+/** @def canMESSAGE_BOX23
+*   @brief Alias name for CAN message box 23
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX23 23U
+
+/** @def canMESSAGE_BOX24
+*   @brief Alias name for CAN message box 24
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX24 24U
+
+/** @def canMESSAGE_BOX25
+*   @brief Alias name for CAN message box 25
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX25 25U
+
+/** @def canMESSAGE_BOX26
+*   @brief Alias name for CAN message box 26
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX26 26U
+
+/** @def canMESSAGE_BOX27
+*   @brief Alias name for CAN message box 27
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX27 27U
+
+/** @def canMESSAGE_BOX28
+*   @brief Alias name for CAN message box 28
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX28 28U
+
+/** @def canMESSAGE_BOX29
+*   @brief Alias name for CAN message box 29
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX29 29U
+
+/** @def canMESSAGE_BOX30
+*   @brief Alias name for CAN message box 30
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX30 30U
+
+/** @def canMESSAGE_BOX31
+*   @brief Alias name for CAN message box 31
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX31 31U
+
+/** @def canMESSAGE_BOX32
+*   @brief Alias name for CAN message box 32
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX32 32U
+
+/** @def canMESSAGE_BOX33
+*   @brief Alias name for CAN message box 33
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX33 33U
+
+/** @def canMESSAGE_BOX34
+*   @brief Alias name for CAN message box 34
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX34 34U
+
+/** @def canMESSAGE_BOX35
+*   @brief Alias name for CAN message box 35
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX35 35U
+
+/** @def canMESSAGE_BOX36
+*   @brief Alias name for CAN message box 36
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX36 36U
+
+/** @def canMESSAGE_BOX37
+*   @brief Alias name for CAN message box 37
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX37 37U
+
+/** @def canMESSAGE_BOX38
+*   @brief Alias name for CAN message box 38
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX38 38U
+
+/** @def canMESSAGE_BOX39
+*   @brief Alias name for CAN message box 39
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX39 39U
+
+/** @def canMESSAGE_BOX40
+*   @brief Alias name for CAN message box 40
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX40 40U
+
+/** @def canMESSAGE_BOX41
+*   @brief Alias name for CAN message box 41
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX41 41U
+
+/** @def canMESSAGE_BOX42
+*   @brief Alias name for CAN message box 42
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX42 42U
+
+/** @def canMESSAGE_BOX43
+*   @brief Alias name for CAN message box 43
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX43 43U
+
+/** @def canMESSAGE_BOX44
+*   @brief Alias name for CAN message box 44
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX44 44U
+
+/** @def canMESSAGE_BOX45
+*   @brief Alias name for CAN message box 45
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX45 45U
+
+/** @def canMESSAGE_BOX46
+*   @brief Alias name for CAN message box 46
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX46 46U
+
+/** @def canMESSAGE_BOX47
+*   @brief Alias name for CAN message box 47
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX47 47U
+
+/** @def canMESSAGE_BOX48
+*   @brief Alias name for CAN message box 48
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX48 48U
+
+/** @def canMESSAGE_BOX49
+*   @brief Alias name for CAN message box 49
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX49 49U
+
+/** @def canMESSAGE_BOX50
+*   @brief Alias name for CAN message box 50
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX50 50U
+
+/** @def canMESSAGE_BOX51
+*   @brief Alias name for CAN message box 51
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX51 51U
+
+/** @def canMESSAGE_BOX52
+*   @brief Alias name for CAN message box 52
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX52 52U
+
+/** @def canMESSAGE_BOX53
+*   @brief Alias name for CAN message box 53
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX53 53U
+
+/** @def canMESSAGE_BOX54
+*   @brief Alias name for CAN message box 54
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX54 54U
+
+/** @def canMESSAGE_BOX55
+*   @brief Alias name for CAN message box 55
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX55 55U
+
+/** @def canMESSAGE_BOX56
+*   @brief Alias name for CAN message box 56
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX56 56U
+
+/** @def canMESSAGE_BOX57
+*   @brief Alias name for CAN message box 57
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX57 57U
+
+/** @def canMESSAGE_BOX58
+*   @brief Alias name for CAN message box 58
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX58 58U
+
+/** @def canMESSAGE_BOX59
+*   @brief Alias name for CAN message box 59
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX59 59U
+
+/** @def canMESSAGE_BOX60
+*   @brief Alias name for CAN message box 60
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX60 60U
+
+/** @def canMESSAGE_BOX61
+*   @brief Alias name for CAN message box 61
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX61 61U
+
+/** @def canMESSAGE_BOX62
+*   @brief Alias name for CAN message box 62
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX62 62U
+
+/** @def canMESSAGE_BOX63
+*   @brief Alias name for CAN message box 63
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX63 63U
+
+/** @def canMESSAGE_BOX64
+*   @brief Alias name for CAN message box 64
+*
+*   @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX64 64U
+
+
+/** @enum canloopBackType
+*   @brief canLoopback type definition
+*/
+/** @typedef canloopBackType_t
+*   @brief canLoopback type Type Definition
+*
+*   This type is used to select the can module Loopback type Digital or Analog loopback.
+*/
+typedef enum canloopBackType 
+{
+    Internal_Lbk = 0x00000010U, 
+    External_Lbk = 0x00000100U,
+	Internal_Silent_Lbk = 0x00000018U
+}canloopBackType_t;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/* Configuration registers */
+typedef struct can_config_reg
+{
+    uint32 CONFIG_CTL;
+    uint32 CONFIG_ES;
+    uint32 CONFIG_BTR;
+    uint32 CONFIG_TEST;
+    uint32 CONFIG_ABOTR;
+    uint32 CONFIG_INTMUX0;
+    uint32 CONFIG_INTMUX1;
+    uint32 CONFIG_INTMUX2;
+    uint32 CONFIG_INTMUX3;   
+    uint32 CONFIG_TIOC;
+    uint32 CONFIG_RIOC;
+} can_config_reg_t;
+
+
+
+/** 
+ *  @defgroup CAN CAN
+ *  @brief Controller Area Network Module.
+ *  
+ *  The Controller Area Network is a high-integrity, serial, multi-master communication protocol for distributed
+ *  real-time applications. This CAN module is implemented according to ISO 11898-1 and is suitable for
+ *  industrial, automotive and general embedded communications
+ *
+ *    Related Files
+ *   - reg_can.h
+ *   - can.h
+ *   - can.c
+ *  @addtogroup CAN
+ *  @{
+ */
+ 
+/* CAN Interface Functions */
+
+void   canInit(void);
+uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data);
+uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data);
+uint32 canSendRemoteFrame(canBASE_t *node, uint32 messageBox);
+uint32 canFillMessageObjectData(canBASE_t *node, uint32 messageBox, const uint8 * data);
+uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox);
+uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox);
+uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox);
+uint32 canGetLastError(canBASE_t *node);
+uint32 canGetErrorLevel(canBASE_t *node);
+void   canEnableErrorNotification(canBASE_t *node);
+void   canDisableErrorNotification(canBASE_t *node);
+void   canEnableStatusChangeNotification(canBASE_t *node);
+void   canDisableStatusChangeNotification(canBASE_t *node);
+void   canEnableloopback(canBASE_t *node, canloopBackType_t Loopbacktype);
+void   canDisableloopback(canBASE_t *node);
+void   canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir);
+void   canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue);
+uint32 canIoTxGetBit(canBASE_t *node);
+uint32 canIoRxGetBit(canBASE_t *node);
+uint32 canGetID(canBASE_t *node, uint32 messageBox);
+void canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal);
+
+/** @fn void canErrorNotification(canBASE_t *node, uint32 notification)
+*   @brief Error notification
+*   @param[in] node Pointer to CAN node:
+*              - canREG1: CAN1 node pointer
+*              - canREG2: CAN2 node pointer
+*              - canREG3: CAN3 node pointer
+*   @param[in] notification Error notification code:
+*           - canLEVEL_PASSIVE    (0x20) : When RX- or TX error counter are between 32 and 63     
+*           - canLEVEL_WARNING    (0x40) : When RX- or TX error counter are between 64 and 127     
+*           - canLEVEL_BUS_OFF    (0x80) : When RX- or TX error counter are between 128 and 255  
+*           - canLEVEL_PARITY_ERR (0x100): When RX- or TX error counter are above 256
+*           
+*   @note This function has to be provide by the user.
+*/
+void canErrorNotification(canBASE_t *node, uint32 notification);
+
+/** @fn void canStatusChangeNotification(canBASE_t *node, uint32 notification)
+*   @brief Status Change notification
+*   @param[in] node Pointer to CAN node:
+*              - canREG1: CAN1 node pointer
+*              - canREG2: CAN2 node pointer
+*              - canREG3: CAN3 node pointer
+*   @param[in] notification Status change notification code:
+*           - canLEVEL_TxOK      (0x08) : When successful transmission     
+*           - canLEVEL_RxOK      (0x10) : When successful reception     
+*           - canLEVEL_WakeUpPnd (0x200): When successful WakeUp to system initiated
+*           - canLEVEL_PDA       (0x400): When successful low power mode entrance
+*           
+*   @note This function has to be provide by the user.
+*/
+void canStatusChangeNotification(canBASE_t *node, uint32 notification);
+
+/** @fn void canMessageNotification(canBASE_t *node, uint32 messageBox)
+*   @brief Message notification
+*   @param[in] node Pointer to CAN node:
+*              - canREG1: CAN1 node pointer
+*              - canREG2: CAN2 node pointer
+*              - canREG3: CAN3 node pointer
+*   @param[in] messageBox Message box number of CAN node:
+*              - canMESSAGE_BOX1: CAN message box 1
+*              - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+*              - canMESSAGE_BOX64: CAN message box 64
+*
+*   @note This function has to be provide by the user.
+*/
+void canMessageNotification(canBASE_t *node, uint32 messageBox);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/crc.h b/include/arch/rm46l8lp/halcogen/crc.h
new file mode 100644
index 0000000..aa115ea
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/crc.h
@@ -0,0 +1,326 @@
+/** @file CRC.h
+*   @brief CRC Driver Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the CRC driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __CRC_H__
+#define __CRC_H__
+
+#include "reg_crc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* CRC General Definitions */
+
+/** @def CRCLEVEL_ACTIVE
+*   @brief Alias name for CRC error operation level active 
+*/
+#define CRCLEVEL_ACTIVE 0x00U
+
+
+/** @def CRC_AUTO
+*   @brief Alias name for CRC auto mode
+*/
+#define CRC_AUTO 0x00000001U
+
+
+/** @def CRC_SEMI_CPU
+*   @brief Alias name for semi cpu mode setting
+*/
+#define CRC_SEMI_CPU 0x00000002U
+
+
+/** @def CRC_FULL_CPU
+*   @brief Alias name for CRC cpu full mode
+*/
+#define CRC_FULL_CPU 0x00000003U
+
+
+/** @def CRC_CH4_TO
+*   @brief Alias name for channel4 time out interrupt flag
+*/
+#define CRC_CH4_TO 0x10000000U
+
+/** @def CRC_CH4_UR
+*   @brief Alias name for channel4 underrun interrupt flag
+*/
+#define CRC_CH4_UR 0x08000000U
+
+/** @def CRC_CH4_OR
+*   @brief Alias name for channel4 overrun interrupt flag
+*/
+#define CRC_CH4_OR 0x04000000U
+
+/** @def CRC_CH4_FAIL
+*   @brief Alias name for channel4 crc fail interrupt flag
+*/
+#define CRC_CH4_FAIL 0x02000000U
+
+/** @def CRC_CH4_CC
+*   @brief Alias name for channel4 compression complete interrupt flag
+*/
+#define CRC_CH4_CC 0x01000000U
+
+/** @def CRC_CH3_TO
+*   @brief Alias name for channel3 time out interrupt flag
+*/
+#define CRC_CH3_TO 0x00100000U
+
+/** @def CRC_CH3_UR
+*   @brief Alias name for channel3 underrun interrupt flag
+*/
+#define CRC_CH3_UR 0x00080000U
+
+/** @def CRC_CH3_OR
+*   @brief Alias name for channel3 overrun interrupt flag
+*/
+#define CRC_CH3_OR 0x00040000U
+
+/** @def CRC_CH3_FAIL
+*   @brief Alias name for channel3 crc fail interrupt flag
+*/
+#define CRC_CH3_FAIL 0x00020000U
+
+/** @def CRC_CH3_CC
+*   @brief Alias name for channel3 compression complete interrupt flag
+*/
+#define CRC_CH3_CC 0x00010000U
+
+/** @def CRC_CH2_TO
+*   @brief Alias name for channel2 time out interrupt flag
+*/
+#define CRC_CH2_TO 0x00001000U
+
+/** @def CRC_CH2_UR
+*   @brief Alias name for channel2 underrun interrupt flag
+*/
+#define CRC_CH2_UR 0x00000800U
+
+/** @def CRC_CH2_OR
+*   @brief Alias name for channel2 overrun interrupt flag  
+*/
+#define CRC_CH2_OR 0x00000400U
+
+/** @def CRC_CH2_FAIL
+*   @brief Alias name for channel2 crc fail interrupt flag 
+*/
+#define CRC_CH2_FAIL 0x00000200U
+
+/** @def CRC_CH2_CC
+*   @brief Alias name for channel2 compression complete interrupt flag  
+*/
+#define CRC_CH2_CC 0x00000100U
+
+/** @def CRC_CH1_TO
+*   @brief Alias name for channel1 time out interrupt flag 
+*/
+#define CRC_CH1_TO 0x00000010U
+
+/** @def CRC_CH1_UR
+*   @brief Alias name for channel1 underrun interrupt flag
+*/
+#define CRC_CH1_UR 0x00000008U
+
+
+/** @def CRC_CH1_OR
+*   @brief Alias name for channel1 overrun interrupt flag  
+*/
+#define CRC_CH1_OR 0x00000004U
+
+/** @def CRC_CH1_FAIL
+*   @brief Alias name for channel1 crc fail interrupt flag  
+*/
+#define CRC_CH1_FAIL 0x00000002U
+
+/** @def CRC_CH1_CC
+*   @brief Alias name for channel1 compression complete interrupt flag    
+*/
+#define CRC_CH1_CC 0x00000001U
+
+/** @def CRC_CH1
+*   @brief Alias name for channel1 
+*/
+#define CRC_CH1    0x00000000U
+
+/** @def CRC_CH1
+*   @brief Alias name for channel2 
+*/
+#define CRC_CH2    0x00000001U
+
+/** @def CRC_CH3
+*   @brief Alias name for channel3 
+*/
+#define CRC_CH3    0x00000002U
+
+/** @def CRC_CH4
+*   @brief Alias name for channel4 
+*/
+#define CRC_CH4    0x00000003U
+
+/** @struct crcModConfig
+*   @brief CRC mode specific parameters 
+*
+*   This type is used to pass crc mode specific parameters 
+*/
+/** @typedef crcModConfig_t
+*   @brief CRC Data Type Definition
+*/
+typedef struct crcModConfig
+{
+    uint32 mode;     /**< Mode of operation        */
+    uint32 crc_channel;     /**< CRC channel-0,1       */
+    uint64 * src_data_pat;  /**< Pattern data */
+    uint32 data_length;  /**< Pattern data length.Number of 64 bit size word*/
+} crcModConfig_t;
+
+/** @struct crcConfig
+*   @brief CRC configuration for different modes
+*
+*   This type is used to pass crc configuration
+*/
+/** @typedef crcConfig_t
+*   @brief CRC Data Type Definition
+*/
+typedef struct crcConfig
+{
+    uint32 crc_channel;     /**< CRC channel-0,1         */
+    uint32 mode;     /**< Mode of operation        */
+    uint32 pcount;     /**< Pattern count*/
+    uint32 scount;     /**< Sector count  */
+    uint32 wdg_preload;  /**< Watchdog period */
+    uint32 block_preload;  /**< Block period*/
+
+} crcConfig_t;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+typedef struct crc_config_reg
+{
+    uint32 CONFIG_CTRL0;
+	uint32 CONFIG_CTRL1;
+	uint32 CONFIG_CTRL2;
+    uint32 CONFIG_INTS;
+    uint32 CONFIG_PCOUNT_REG1;
+    uint32 CONFIG_SCOUNT_REG1;
+    uint32 CONFIG_WDTOPLD1;
+    uint32 CONFIG_BCTOPLD1;
+    uint32 CONFIG_PCOUNT_REG2;
+    uint32 CONFIG_SCOUNT_REG2;
+    uint32 CONFIG_WDTOPLD2;
+    uint32 CONFIG_BCTOPLD2;
+}crc_config_reg_t;
+		
+#define CRC_CTRL0_CONFIGVALUE			0x00000000U
+#define CRC_CTRL1_CONFIGVALUE			0x00000000U
+#define CRC_CTRL2_CONFIGVALUE			((uint32)((uint32)0U << 4U) | (uint32)(CRC_FULL_CPU)  | (uint32)((uint32)CRC_FULL_CPU << 8U))
+#define CRC_INTS_CONFIGVALUE			(0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U)
+#define CRC_PCOUNT_REG1_CONFIGVALUE		(0x00000000U)
+#define CRC_SCOUNT_REG1_CONFIGVALUE		(0x00000000U)
+#define CRC_WDTOPLD1_CONFIGVALUE		(0x00000000U)
+#define CRC_BCTOPLD1_CONFIGVALUE		(0x00000000U)
+#define CRC_PCOUNT_REG2_CONFIGVALUE		(0x00000000U)
+#define CRC_SCOUNT_REG2_CONFIGVALUE		(0x00000000U)
+#define CRC_WDTOPLD2_CONFIGVALUE		(0x00000000U)
+#define CRC_BCTOPLD2_CONFIGVALUE		(0x00000000U)
+
+/** 
+ *  @defgroup CRC CRC
+ *  @brief Cyclic Redundancy Check Controller Module.
+ *  
+ *  The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check) to verify the
+ *  integrity of memory system. A signature representing the contents of the memory is obtained when the
+ *  contents of the memory are read into CRC controller. The responsibility of CRC controller is to calculate
+ *  the signature for a set of data and then compare the calculated signature value against a pre-determined
+ *  good signature value. CRC controller supports two channels to perform CRC calculation on multiple
+ *  memories in parallel and can be used on any memory system.
+ *
+ *	Related Files
+ *   - reg_crc.h
+ *   - crc.h
+ *   - crc.c
+ *  @addtogroup CRC
+ *  @{
+ */
+ 
+/* CRC Interface Functions */
+void crcInit(void);
+void crcSendPowerDown(crcBASE_t *crc);
+void crcSignGen(crcBASE_t *crc,crcModConfig_t *param);
+void crcSetConfig(crcBASE_t *crc,crcConfig_t *param);
+uint64 crcGetPSASig(crcBASE_t *crc,uint32 channel);
+uint64 crcGetSectorSig(crcBASE_t *crc,uint32 channel);
+uint32 crcGetFailedSector(crcBASE_t *crc,uint32 channel);
+uint32 crcGetIntrPend(crcBASE_t *crc,uint32 channel);
+void crcChannelReset(crcBASE_t *crc,uint32 channel);
+void crcEnableNotification(crcBASE_t *crc, uint32 flags);
+void crcDisableNotification(crcBASE_t *crc, uint32 flags);
+void crcGetConfigValue(crc_config_reg_t *config_reg, config_value_type_t type);
+
+/** @fn void crcNotification(crcBASE_t *crc, uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] crc   - crc module base address
+*   @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt.  The parameter passed to the callback is a copy of the 
+* interrupt flag register.
+*/
+void crcNotification(crcBASE_t *crc, uint32 flags);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/dcc.h b/include/arch/rm46l8lp/halcogen/dcc.h
new file mode 100644
index 0000000..e04d771
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/dcc.h
@@ -0,0 +1,306 @@
+/** @file dcc.h
+*   @brief DCC Driver Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __DCC_H__
+#define __DCC_H__
+
+#include "reg_dcc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* DCC General Definitions */
+
+/** @def dcc1CNT0_CLKSRC_HFLPO
+*   @brief Alias name for DCC1 Counter 0 Clock Source HFLPO
+*
+*   This is an alias name for the Clock Source HFLPO for DCC1 Counter 0.
+*
+*   @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc1CNT0_CLKSRC_HFLPO 0x00000005U
+
+/** @def dcc1CNT0_CLKSRC_TCK
+*   @brief Alias name for DCC1 Counter 0 Clock Source TCK
+*
+*   This is an alias name for the Clock Source TCK for DCC1 Counter 0.
+*
+*   @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc1CNT0_CLKSRC_TCK 0x0000000AU
+
+/** @def dcc1CNT0_CLKSRC_OSCIN
+*   @brief Alias name for DCC1 Counter 0 Clock Source OSCIN
+*
+*   This is an alias name for the Clock Source OSCIN for DCC1 Counter 0.
+*
+*   @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc1CNT0_CLKSRC_OSCIN 0x0000000FU
+
+/** @def dcc1CNT1_CLKSRC_PLL1
+*   @brief Alias name for DCC1 Counter 1 Clock Source PLL1
+*
+*   This is an alias name for the Clock Source PLL for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U
+
+/** @def dcc1CNT1_CLKSRC_PLL2
+*   @brief Alias name for DCC1 Counter 1 Clock Source PLL2
+*
+*   This is an alias name for the Clock Source OSCIN for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U
+
+/** @def dcc1CNT1_CLKSRC_LFLPO
+*   @brief Alias name for DCC1 Counter 1 Clock Source LFLPO
+*
+*   This is an alias name for the Clock Source LFLPO for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_LFLPO 0x0000A002U
+
+/** @def dcc1CNT1_CLKSRC_HFLPO
+*   @brief Alias name for DCC1 Counter 1 Clock Source HFLPO
+*
+*   This is an alias name for the Clock Source HFLPO for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_HFLPO 0x0000A003U
+
+/** @def dcc1CNT1_CLKSRC_EXTCLKIN1
+*   @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN1
+*
+*   This is an alias name for the Clock Source EXTCLKIN1 for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_EXTCLKIN1 0x0000A005U
+
+/** @def dcc1CNT1_CLKSRC_EXTCLKIN2
+*   @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN2
+*
+*   This is an alias name for the Clock Source EXTCLKIN2 for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_EXTCLKIN2 0x0000A006U
+
+/** @def dcc1CNT1_CLKSRC_VCLK
+*   @brief Alias name for DCC1 Counter 1 Clock Source VCLK
+*
+*   This is an alias name for the Clock Source VCLK for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_VCLK 0x0000A008U
+
+/** @def dcc1CNT1_CLKSRC_N2HET1_31
+*   @brief Alias name for DCC1 Counter 1 Clock Source N2HET1_31
+*
+*   This is an alias name for the Clock Source N2HET1_31 for DCC1 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_N2HET1_31 0x0000500FU
+
+/** @def dcc2CNT0_CLKSRC_TCK
+*   @brief Alias name for DCC2 Counter 0 Clock Source TCK
+*
+*   This is an alias name for the Clock Source TCK for DCC2 Counter 0.
+*
+*   @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc2CNT0_CLKSRC_TCK 0x0000000AU
+
+/** @def dcc1CNT0_CLKSRC_OSCIN
+*   @brief Alias name for DCC1 Counter 0 Clock Source OSCIN
+*
+*   This is an alias name for the Clock Source OSCIN for DCC2 Counter 0.
+*
+*   @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc2CNT0_CLKSRC_OSCIN 0x0000000FU
+
+/** @def dcc2CNT1_CLKSRC_VCLK
+*   @brief Alias name for DCC2 Counter 1 Clock Source VCLK
+*
+*   This is an alias name for the Clock Source VCLK for DCC2 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc2CNT1_CLKSRC_VCLK 0x0000A008U
+
+/** @def dcc2CNT1_CLKSRC_N2HET1_0
+*   @brief Alias name for DCC2 Counter 1 Clock Source N2HET2_0
+*
+*   This is an alias name for the Clock Source N2HET2_0 for DCC2 Counter 1.
+*
+*   @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc2CNT1_CLKSRC_N2HET1_0 0x0000500FU
+
+/** @def dccNOTIFICATION_DONE
+*   @brief Alias name for DCC Done notification
+*
+*   This is an alias name for the DCC Done notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define dccNOTIFICATION_DONE 0x0000A000U
+
+/** @def dccNOTIFICATION_ERROR
+*   @brief Alias name for DCC Error notification
+*
+*   This is an alias name for the DCC Error notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define dccNOTIFICATION_ERROR 0x000000A0U
+
+
+/** @enum dcc1clocksource
+*   @brief Alias names for dcc clock sources
+*
+*   This enumeration is used to provide alias names for the clock sources:
+*/
+enum dcc1clocksource
+{
+    DCC1_CNT0_HF_LPO    = 0x5U,    /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
+    DCC1_CNT0_TCK       = 0xAU,    /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/
+    DCC1_CNT0_OSCIN     = 0xFU,    /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
+
+    DCC1_CNT1_PLL1      = 0x0U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/
+    DCC1_CNT1_PLL2      = 0x1U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/
+    DCC1_CNT1_LF_LPO    = 0x2U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/
+    DCC1_CNT1_HF_LPO    = 0x3U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/
+    DCC1_CNT1_EXTCLKIN1 = 0x5U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/
+    DCC1_CNT1_EXTCLKIN2 = 0x6U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/
+    DCC1_CNT1_VCLK      = 0x8U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
+    DCC1_CNT1_N2HET1_31 = 0xAU     /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
+};
+
+/** @enum dcc2clocksource
+*   @brief Alias names for dcc clock sources
+*
+*   This enumeration is used to provide alias names for the clock sources:
+*/
+enum dcc2clocksource
+{
+    DCC2_CNT0_OSCIN      = 0xFU,    /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
+    DCC2_CNT0_TCK        = 0xAU,    /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
+    
+    DCC2_CNT1_VCLK       = 0x8U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
+    DCC2_CNT1_N2HET2_0   = 0xAU     /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
+};
+
+/* Configuration registers */
+typedef struct dcc_config_reg
+{
+    uint32 CONFIG_GCTRL;
+    uint32 CONFIG_CNT0SEED;
+    uint32 CONFIG_VALID0SEED;
+    uint32 CONFIG_CNT1SEED;
+    uint32 CONFIG_CNT1CLKSRC;
+    uint32 CONFIG_CNT0CLKSRC;
+} dcc_config_reg_t;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/**
+ *  @defgroup DCC DCC
+ *  @brief Dual-Clock Comparator Module
+ *
+ *  The primary purpose of a DCC module is to measure the frequency of a clock signal using a second
+ *  known clock signal as a reference. This capability can be used to ensure the correct frequency range for
+ *  several different device clock sources, thereby enhancing the system safety metrics.
+ *
+ *    Related Files
+ *   - reg_dcc.h
+ *   - dcc.h
+ *   - dcc.c
+ *  @addtogroup DCC
+ *  @{
+ */
+
+/* DCC Interface Functions */
+void dccInit(void);
+void dccSetCounter0Seed(dccBASE_t  *dcc, uint32 cnt0seed);
+void dccSetTolerance(dccBASE_t  *dcc, uint32 valid0seed);
+void dccSetCounter1Seed(dccBASE_t  *dcc, uint32 cnt1seed);
+void dccSetSeed(dccBASE_t  *dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed);
+void dccSelectClockSource(dccBASE_t  *dcc, uint32 cnt0_Clock_Source, uint32 cnt1_Clock_Source);
+void dccEnable(dccBASE_t  *dcc);
+void dccDisable(dccBASE_t  *dcc);
+uint32 dccGetErrStatus(dccBASE_t  *dcc);
+
+void dccEnableNotification(dccBASE_t  *dcc, uint32 notification);
+void dccDisableNotification(dccBASE_t  *dcc, uint32 notification);
+void dcc1GetConfigValue(dcc_config_reg_t *config_reg, config_value_type_t type);
+void dcc2GetConfigValue(dcc_config_reg_t *config_reg, config_value_type_t type);
+/** @fn void dccNotification(dccBASE_t  *dcc,uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] dcc   - dcc module base address
+*   @param[in] flags - status flags
+*
+* This is a callback function provided by the application.  It is call when
+* a dcc is complete or detected error.
+*/
+void dccNotification(dccBASE_t  *dcc,uint32 flags);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/ecap.h b/include/arch/rm46l8lp/halcogen/ecap.h
new file mode 100644
index 0000000..dd76b8c
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/ecap.h
@@ -0,0 +1,260 @@
+/** @file ecap.h
+*   @brief ECAP Driver Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the ECAP driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __ECAP_H__
+#define __ECAP_H__
+
+#include "reg_ecap.h"
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+/** @brief Enumeration to define the capture (CAP) interrupts
+*/
+typedef enum
+{
+    ecapInt_CTR_CMP = 0x0080U,    /*< Denotes CTR = CMP interrupt        */
+    ecapInt_CTR_PRD = 0x0040U,    /*< Denotes CTR = PRD interrupt        */
+    ecapInt_CTR_OVF = 0x0020U,    /*< Denotes CTROVF interrupt           */
+    ecapInt_CEVT4   = 0x0010U,    /*< Denotes CEVT4 interrupt            */
+    ecapInt_CEVT3   = 0x0008U,    /*< Denotes CEVT3 interrupt            */
+    ecapInt_CEVT2   = 0x0004U,    /*< Denotes CEVT2 interrupt            */
+    ecapInt_CEVT1   = 0x0002U,    /*< Denotes CEVT1 interrupt            */
+    ecapInt_Global  = 0x0001U,    /*< Denotes Capture global interrupt   */
+    ecapInt_All     = 0x00FFU     /*< Denotes All interrupts             */
+} ecapInterrupt_t;
+
+/** @brief Enumeration to define the capture (CAP) prescaler values
+*/
+typedef enum
+{
+    ecapPrescale_By_1  = ((uint16)0U << 9U),   /*< Divide by 1   */
+    ecapPrescale_By_2  = ((uint16)1U << 9U),   /*< Divide by 2   */
+    ecapPrescale_By_4  = ((uint16)2U << 9U),   /*< Divide by 4   */
+    ecapPrescale_By_6  = ((uint16)3U << 9U),   /*< Divide by 6   */
+    ecapPrescale_By_8  = ((uint16)4U << 9U),   /*< Divide by 8   */
+    ecapPrescale_By_10 = ((uint16)5U << 9U),   /*< Divide by 10  */
+    ecapPrescale_By_12 = ((uint16)6U << 9U),   /*< Divide by 12  */
+    ecapPrescale_By_14 = ((uint16)7U << 9U),   /*< Divide by 14  */
+    ecapPrescale_By_16 = ((uint16)8U << 9U),   /*< Divide by 16  */
+    ecapPrescale_By_18 = ((uint16)9U << 9U),   /*< Divide by 18  */
+    ecapPrescale_By_20 = ((uint16)10U << 9U),  /*< Divide by 20  */
+    ecapPrescale_By_22 = ((uint16)11U << 9U),  /*< Divide by 22  */
+    ecapPrescale_By_24 = ((uint16)12U << 9U),  /*< Divide by 24  */
+    ecapPrescale_By_26 = ((uint16)13U << 9U),  /*< Divide by 26  */
+    ecapPrescale_By_28 = ((uint16)14U << 9U),  /*< Divide by 28  */
+    ecapPrescale_By_30 = ((uint16)15U << 9U),  /*< Divide by 30  */
+    ecapPrescale_By_32 = ((uint16)16U << 9U),  /*< Divide by 32  */
+    ecapPrescale_By_34 = ((uint16)17U << 9U),  /*< Divide by 34  */
+    ecapPrescale_By_36 = ((uint16)18U << 9U),  /*< Divide by 36  */
+    ecapPrescale_By_38 = ((uint16)19U << 9U),  /*< Divide by 38  */
+    ecapPrescale_By_40 = ((uint16)20U << 9U),  /*< Divide by 40  */
+    ecapPrescale_By_42 = ((uint16)21U << 9U),  /*< Divide by 42  */
+    ecapPrescale_By_44 = ((uint16)22U << 9U),  /*< Divide by 44  */
+    ecapPrescale_By_46 = ((uint16)23U << 9U),  /*< Divide by 46  */
+    ecapPrescale_By_48 = ((uint16)24U << 9U),  /*< Divide by 48  */
+    ecapPrescale_By_50 = ((uint16)25U << 9U),  /*< Divide by 50  */
+    ecapPrescale_By_52 = ((uint16)26U << 9U),  /*< Divide by 52  */
+    ecapPrescale_By_54 = ((uint16)27U << 9U),  /*< Divide by 54  */
+    ecapPrescale_By_56 = ((uint16)28U << 9U),  /*< Divide by 56  */
+    ecapPrescale_By_58 = ((uint16)29U << 9U),  /*< Divide by 58  */
+    ecapPrescale_By_60 = ((uint16)30U << 9U),  /*< Divide by 60  */
+    ecapPrescale_By_62 = ((uint16)31U << 9U)   /*< Divide by 62  */
+} ecapPrescale_t;
+
+/** @brief Enumeration to define the Sync Out options
+*/
+typedef enum
+{
+    SyncOut_SyncIn = ((uint16)0U << 6U),   /*< Sync In used for Sync Out   */
+    SyncOut_CTRPRD = ((uint16)1U << 6U),   /*< CTR = PRD used for Sync Out */
+    SyncOut_None   = ((uint16)2U << 6U)    /*< Disables Sync Out           */
+} ecapSyncOut_t;
+
+/** @brief Enumeration to define the Polarity
+*/
+typedef enum
+{
+    RISING_EDGE  = 0U,
+    FALLING_EDGE = 1U
+}ecapEdgePolarity_t;
+
+typedef enum
+{
+    ACTIVE_HIGH = 0U,
+    ACTIVE_LOW  = 1U
+}ecapAPWMPolarity_t;
+
+/** @brief Enumeration to define the Mode of operation
+*/
+typedef enum
+{
+    CONTINUOUS = 0U,
+    ONE_SHOT   = 1U
+}ecapMode_t;
+
+/** @brief Enumeration to define the capture events
+*/
+typedef enum
+{
+    CAPTURE_EVENT1 = 0U,
+    CAPTURE_EVENT2 = 1U,
+    CAPTURE_EVENT3 = 2U,
+    CAPTURE_EVENT4 = 3U
+}ecapEvent_t ;
+
+typedef enum
+{
+    RESET_ENABLE  = 1U,
+    RESET_DISABLE = 0U
+}ecapReset_t ;
+
+typedef struct ecap_config_reg
+ {
+   uint32 CONFIG_CTRPHS;
+   uint16 CONFIG_ECCTL1;
+   uint16 CONFIG_ECCTL2;
+   uint16 CONFIG_ECEINT;
+}ecap_config_reg_t;
+
+#define ECAP1_CTRPHS_CONFIGVALUE    0x00000000U
+#define ECAP1_ECCTL1_CONFIGVALUE    ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP1_ECCTL2_CONFIGVALUE	((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP1_ECEINT_CONFIGVALUE	(0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U  | 0x0000U)
+
+#define ECAP2_CTRPHS_CONFIGVALUE    0x00000000U
+#define ECAP2_ECCTL1_CONFIGVALUE    ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP2_ECCTL2_CONFIGVALUE	((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP2_ECEINT_CONFIGVALUE	(0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U  | 0x0000U)
+
+#define ECAP3_CTRPHS_CONFIGVALUE    0x00000000U
+#define ECAP3_ECCTL1_CONFIGVALUE    ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP3_ECCTL2_CONFIGVALUE	((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP3_ECEINT_CONFIGVALUE	(0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U  | 0x0000U)
+
+#define ECAP4_CTRPHS_CONFIGVALUE    0x00000000U
+#define ECAP4_ECCTL1_CONFIGVALUE    ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP4_ECCTL2_CONFIGVALUE	((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP4_ECEINT_CONFIGVALUE	(0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U  | 0x0000U)
+
+#define ECAP5_CTRPHS_CONFIGVALUE    0x00000000U
+#define ECAP5_ECCTL1_CONFIGVALUE    ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP5_ECCTL2_CONFIGVALUE	((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP5_ECEINT_CONFIGVALUE	(0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U  | 0x0000U)
+
+#define ECAP6_CTRPHS_CONFIGVALUE    0x00000000U
+#define ECAP6_ECCTL1_CONFIGVALUE    ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP6_ECCTL2_CONFIGVALUE	((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP6_ECEINT_CONFIGVALUE	(0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U  | 0x0000U)
+
+/**
+ *  @defgroup eCAP eCAP
+ *  @brief Enhanced Capture Module.
+ *
+ *  The enhanced Capture (eCAP) module is essential in systems where accurate timing of external events is
+ *  important. This microcontroller implements 6 instances of the eCAP module.
+ *
+ *	Related Files
+ *   - reg_ecap.h
+ *   - ecap.h
+ *   - ecap.c
+ *  @addtogroup eCAP
+ *  @{
+ */
+void ecapInit(void);
+void ecapSetCounter(ecapBASE_t *ecap, uint32 value);
+void ecapEnableCounterLoadOnSync(ecapBASE_t *ecap, uint32 phase);
+void ecapDisableCounterLoadOnSync(ecapBASE_t *ecap);
+void ecapSetEventPrescaler(ecapBASE_t *ecap, ecapPrescale_t prescale);
+void ecapSetCaptureEvent1(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable);
+void ecapSetCaptureEvent2(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable);
+void ecapSetCaptureEvent3(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable);
+void ecapSetCaptureEvent4(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable);
+void ecapSetCaptureMode(ecapBASE_t *ecap, ecapMode_t capMode, ecapEvent_t event);
+void ecapEnableCapture(ecapBASE_t *ecap);
+void ecapDisableCapture(ecapBASE_t *ecap);
+void ecapStartCounter(ecapBASE_t *ecap);
+void ecapStopCounter(ecapBASE_t *ecap);
+void ecapSetSyncOut(ecapBASE_t *ecap, ecapSyncOut_t syncOutSrc);
+void ecapEnableAPWMmode(ecapBASE_t *ecap, ecapAPWMPolarity_t pwmPolarity, uint32 period, uint32 duty);
+void ecapDisableAPWMMode(ecapBASE_t *ecap);
+void ecapEnableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts);
+void ecapDisableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts);
+uint16 ecapGetEventStatus(ecapBASE_t *ecap, ecapInterrupt_t events);
+void ecapClearFlag(ecapBASE_t *ecap, ecapInterrupt_t events);
+uint32 ecapGetCAP1(ecapBASE_t *ecap);
+uint32 ecapGetCAP2(ecapBASE_t *ecap);
+uint32 ecapGetCAP3(ecapBASE_t *ecap);
+uint32 ecapGetCAP4(ecapBASE_t *ecap);
+void ecap1GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+void ecap2GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+void ecap3GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+void ecap4GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+void ecap5GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+void ecap6GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+
+/** @brief Interrupt callback
+*   @param[in] ecap	 Handle to CAP object
+*   @param[in] flags Copy of  interrupt flags
+*/
+void ecapNotification(ecapBASE_t *ecap,uint16 flags);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif /*extern "C"  */
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+#endif /*end of _CAP_H_ definition  */
diff --git a/include/arch/rm46l8lp/halcogen/emac.h b/include/arch/rm46l8lp/halcogen/emac.h
new file mode 100644
index 0000000..c568cd7
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/emac.h
@@ -0,0 +1,404 @@
+/**
+ *  \file   emac.h
+ *
+ *  \brief  EMAC APIs and macros.
+ *
+ *   This file contains the driver API prototypes and macro definitions.
+ */
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __EMAC_H__
+#define __EMAC_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_common.h"
+#include "hw_reg_access.h"
+#include "hw_emac.h"
+#include "hw_emac_ctrl.h"
+#include "mdio.h"
+#include "phy_dp83640.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/*****************************************************************************/
+/*
+** Macros which can be used as speed parameter to the API EMACRMIISpeedSet
+*/
+#define EMAC_RMIISPEED_10MBPS                 (0x00000000U)
+#define EMAC_RMIISPEED_100MBPS                (0x00008000U)
+
+/* Macros for enabling taken as inputs from HALCoGen GUI. */
+#define EMAC_TX_ENABLE					(1U)				
+#define EMAC_RX_ENABLE					(1U)
+#define EMAC_MII_ENABLE					(1U)
+#define EMAC_FULL_DUPLEX_ENABLE			(1U)
+#define EMAC_LOOPBACK_ENABLE			(0U)
+#define EMAC_BROADCAST_ENABLE			(1U)
+#define EMAC_UNICAST_ENABLE				(1U)
+#define EMAC_CHANNELNUMBER					(0U)
+#define EMAC_PHYADDRESS						(0U)
+
+/*
+ * Macros to indicate EMAC Channel Numbers
+ */
+#define EMAC_CHANNEL_0						  (0x00000000U)
+#define EMAC_CHANNEL_1						  (0x00000001U)
+#define EMAC_CHANNEL_2						  (0x00000002U)
+#define EMAC_CHANNEL_3						  (0x00000003U)
+#define EMAC_CHANNEL_4						  (0x00000004U)
+#define EMAC_CHANNEL_5						  (0x00000005U)
+#define EMAC_CHANNEL_6						  (0x00000006U)
+#define EMAC_CHANNEL_7						  (0x00000007U)
+/* Macros which can be used as duplexMode parameter to the API 
+** EMACDuplexSet
+*/
+#define EMAC_DUPLEX_FULL                      (0x00000001U)
+#define EMAC_DUPLEX_HALF                      (0x00000000U)
+
+/*
+** Macros which can be used as matchFilt  parameters to the API 
+** EMACMACAddrSet
+*/
+/* Address not used to match/filter incoming packets */
+#define EMAC_MACADDR_NO_MATCH_NO_FILTER       (0x00000000U)
+
+/* Address will be used to filter incoming packets */
+#define EMAC_MACADDR_FILTER                   (0x00100000U)
+
+/* Address will be used to match incoming packets */
+#define EMAC_MACADDR_MATCH                    (0x00180000U)
+
+/*
+** Macros which can be passed as eoiFlag to EMACRxIntAckToClear API
+*/
+#define EMAC_INT_CORE0_RX                     (0x1U)
+#define EMAC_INT_CORE1_RX                     (0x5U)
+#define EMAC_INT_CORE2_RX                     (0x9U)
+
+/*
+** Macros which can be passed as eoiFlag to EMACTxIntAckToClear API
+*/
+#define EMAC_INT_CORE0_TX                     (0x2U)
+#define EMAC_INT_CORE1_TX                     (0x6U)
+#define EMAC_INT_CORE2_TX                     (0xAU)
+/* Base Addresses */
+#define EMAC_CTRL_RAM_0_BASE      0xFC520000U
+#define EMAC_0_BASE               0xFCF78000U
+#define EMAC_CTRL_0_BASE          0xFCF78800U
+#define MDIO_0_BASE               0xFCF78900U
+
+/*MAC address length*/
+#define EMAC_HWADDR_LEN 	      6U
+#define MAX_EMAC_INSTANCE 	      1U
+#define SIZE_EMAC_CTRL_RAM        0x2000U
+#define MAX_TRANSFER_UNIT         1514U
+#define MAX_RX_PBUF_ALLOC 		  (10U)
+#define MIN_PKT_LEN               60U
+#define MIN_PACKET_SIZE          (46U)
+
+
+
+
+#define EMAC_BUF_DESC_OWNER       0x20000000U
+#define EMAC_BUF_DESC_SOP         0x80000000U
+#define EMAC_BUF_DESC_EOP         0x40000000U
+#define EMAC_BUF_DESC_EOQ         0x10000000U
+
+#define EMAC_NETSTATREGS(n)	((uint32)0x200U + (uint32)((n)*4U))
+
+/* Error Signalling Macros */
+#define EMAC_ERR_CONNECT		   0x2U /* Not connected.  */
+#define EMAC_ERR_OK				   0x1U /* No error, everything OK. */
+
+
+/* Macros for Configuration Value Registers */
+#define EMAC_TXCONTROL_CONFIGVALUE 0x00000001U
+#define EMAC_RXCONTROL_CONFIGVALUE 0x00000001U
+#define EMAC_TXINTMASKSET_CONFIGVALUE 0x00000001U
+#define EMAC_TXINTMASKCLEAR_CONFIGVALUE 0x00000001U
+#define EMAC_RXINTMASKSET_CONFIGVALUE 0x00000001U
+#define EMAC_RXINTMASKCLEAR_CONFIGVALUE 0x00000001U
+#define EMAC_MACSRCADDRHI_CONFIGVALUE ((uint32)((uint32)0xFFU << 24U) | (uint32)((uint32)0xFFU << 16U) | (uint32)((uint32)0xFFU << 8U) | (uint32)((uint32)0xFFU))
+#define EMAC_MACSRCADDRLO_CONFIGVALUE ((uint32)((uint32)0xFFU << 8U) | (uint32)((uint32)0xFFU))
+#define EMAC_MDIOCONTROL_CONFIGVALUE 0x4114001FU
+#define EMAC_C0RXEN_CONFIGVALUE 0x00000001U
+#define EMAC_C0TXEN_CONFIGVALUE 0x00000001U
+
+/* Structure to store pending status from the Tx Interrupt Status Registers. */
+typedef struct emac_tx_int_status{
+	volatile uint32 intstatmasked; /* Pending interrupt status read from the Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) */
+	volatile uint32 intstatraw; /* Pending interrupt status read from the Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) */
+}emac_tx_int_status_t;
+
+/* Structure to store pending status from the Rx Interrupt Status Registers. */
+typedef struct emac_rx_int_status{
+
+	volatile uint32 intstatmasked_pend; /* Reads RXnPEND value from the Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) */
+	volatile uint32 intstatmasked_threshpend; /* Reads RXnTRHESHPEND value from the Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) */
+
+	volatile uint32 intstatraw_pend; /* Reads RXnPEND value from the Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) */
+	volatile uint32 intstatraw_threshpend; /* Reads RXnTRHESHPEND value from the Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) */
+
+}emac_rx_int_status_t;
+
+/* EMAC TX Buffer descriptor data structure - Refer TRM for details about the buffer descriptor structure.*/
+typedef struct emac_tx_bd {
+  volatile struct emac_tx_bd *next;
+  volatile uint32 bufptr; /* Pointer to the actual Buffer storing the data to be transmitted. */
+  volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each) */
+  volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/
+}emac_tx_bd_t;
+
+/* EMAC RX Buffer descriptor data structure - Refer TRM for details about the buffer descriptor structure. */
+typedef struct emac_rx_bd {
+  volatile struct emac_rx_bd *next; /*Used as a pointer for next element in the linked list of descriptors.*/
+  volatile uint32 bufptr; /*Pointer to the actual Buffer which will store the received data.*/
+  volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each)*/
+  volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/
+}emac_rx_bd_t;
+
+/**
+ * Helper struct to hold the data used to operate on a particular
+ * receive channel
+ */
+typedef struct rxch_struct {
+  volatile emac_rx_bd_t *free_head; /*Used to point to the free buffer descriptor which can receive new data.*/
+  volatile emac_rx_bd_t *active_head; /*Used to point to the active descriptor in the chain which is receiving.*/
+  volatile emac_rx_bd_t *active_tail; /*Used to point to the last descriptor in the chain.*/
+}rxch_t;
+
+/**
+ * Helper struct to hold the data used to operate on a particular
+ * transmit channel
+ */
+typedef struct txch_struct {
+  volatile emac_tx_bd_t *free_head; /*Used to point to the free buffer descriptor which can transmit new data.*/
+  volatile emac_tx_bd_t *active_tail; /*Used to point to the last descriptor in the chain.*/
+  volatile emac_tx_bd_t *next_bd_to_process; /*Used to point to the next descriptor in the chain to be processed.*/
+}txch_t;
+/**
+ * Helper struct to hold private data used to operate the ethernet interface.
+ */
+typedef struct hdkif_struct {
+  /* MAC Address of the Module. */	
+  uint8_t mac_addr[6];
+
+  /* emac base address */
+  uint32 emac_base;
+
+  /* emac controller base address */
+  volatile uint32 emac_ctrl_base;
+  volatile uint32 emac_ctrl_ram;
+
+  /* mdio base address */
+  volatile uint32 mdio_base;
+
+  /* phy parameters for this instance - for future use */
+  uint32 phy_addr;
+  boolean (*phy_autoneg)(uint32 param1, uint32 param2, uint16 param3);
+  boolean (*phy_partnerability)(uint32 param4, uint32 param5, uint16* param6);
+
+  /* The tx/rx channels for the interface */
+  txch_t txchptr;
+  rxch_t rxchptr;
+}hdkif_t;
+
+/*Ethernet Frame Structure */
+typedef struct ethernet_frame
+{
+	uint8 dest_addr[6]; /* Destination MAC Address */
+	uint8 src_addr[6]; /*Source MAC Address. */
+	uint16 frame_length; /* Data Frame Length */
+	uint8 data[1500]; /* Data */
+}ethernet_frame_t;
+
+/* Struct used to take packet data input from the user for transmit APIs. */
+typedef struct pbuf_struct {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf_struct *next;
+
+  /**
+  * Pointer to the actual ethernet packet/packet fragment to be transmitted.
+  * The packet needs to be in the following format:
+  * |Destination MAC Address (6 bytes)| Source MAC Address (6 bytes)| Length/Type (2 bytes)| Data (46- 1500 bytes)
+  * The data can be split up over multiple pbufs which are linked as a linked list.
+  **/
+  uint8 *payload;
+
+  /**
+   * total length of this buffer and all next buffers in chain
+   * belonging to the same packet.
+   *
+   * For non-queue packet chains this is the invariant:
+   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+   */
+  uint16 tot_len;
+
+  /** length of this buffer */
+  uint16 len;
+
+}pbuf_t;
+
+/* Structure to hold the values of the EMAC Configuration Registers. */
+typedef struct emac_config_reg_struct {
+/* EMAC Module Register Values */
+uint32 TXCONTROL; /* Transmit Control Register. */
+uint32 RXCONTROL; /* Receive Control Register */
+uint32 TXINTMASKSET; /* Transmit Interrupt Mask Set Register */
+uint32 TXINTMASKCLEAR; /* Transmit Interrupt Clear Register */
+uint32 RXINTMASKSET; /* Receive Interrupt Mask Set Register */
+uint32 RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/
+uint32 MACSRCADDRHI; /*MAC Source Address High Bytes Register*/
+uint32 MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/
+
+/*MDIO Module Registers */
+uint32 MDIOCONTROL; /*MDIO Control Register. */
+
+/* EMAC Control Module Registers */
+uint32 C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/
+uint32 C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/
+}emac_config_reg_t;
+/*****************************************************************************/
+/** 
+ *  @defgroup EMACMDIO EMAC/MDIO
+ *  @brief Ethernet Media Access Controller/Management Data Input/Output.
+ *  
+ *  The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHY
+ *  configuration and status monitoring.
+ *
+ *  Both the EMAC and the MDIO modules interface to the system core through a custom interface that
+ *  allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
+ *  module and is considered integral to the EMAC/MDIO peripheral
+ *
+ *	Related Files
+ *   - emac.h
+ *   - emac.c
+ *   - hw_emac.h
+ *   - hw_emac_ctrl.h
+ *   - hw_mdio.h
+ *   - hw_reg_access.h	
+ *   - mdio.h
+ *   - mdio.c
+ *  @addtogroup EMACMDIO
+ *  @{
+ */
+/*
+** Prototypes for the APIs
+*/
+extern uint32 EMACLinkSetup(hdkif_t *hdkif);
+extern void EMACInstConfig(hdkif_t *hdkif);
+extern void EMACTxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase,
+                                 uint32 ctrlCore, uint32 channel);
+extern void EMACTxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase,
+                                  uint32 ctrlCore, uint32 channel);
+extern void EMACRxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase,
+                                 uint32 ctrlCore, uint32 channel);
+extern void EMACRxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase,
+                                   uint32 ctrlCore, uint32 channel);
+extern void EMACRMIISpeedSet(uint32 emacBase, uint32 speed);
+extern void EMACDuplexSet(uint32 emacBase, uint32 duplexMode);
+extern void EMACTxEnable(uint32 emacBase);
+extern void EMACTxDisable(uint32 emacBase);
+extern void EMACRxEnable(uint32 emacBase);
+extern void EMACRxDisable(uint32 emacBase);
+extern void EMACTxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr,
+                                  uint32 channel);
+extern void EMACRxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr,
+                                  uint32 channel);
+extern void EMACInit(uint32 emacCtrlBase, uint32 emacBase);
+extern void EMACMACSrcAddrSet(uint32 emacBase, uint8 macAddr[6]);
+extern void EMACMACAddrSet(uint32 emacBase, uint32 channel,
+                           uint8 macAddr[6], uint32 matchFilt);
+extern void EMACMIIEnable(uint32 emacBase);
+extern void EMACMIIDisable(uint32 emacBase);
+extern void EMACRxUnicastSet(uint32 emacBase, uint32 channel);
+extern void EMACRxUnicastClear(uint32 emacBase, uint32 channel);
+extern void EMACCoreIntAck(uint32 emacBase, uint32 eoiFlag);
+extern void EMACTxCPWrite(uint32 emacBase, uint32 channel,
+                          uint32 comPtr);
+extern void EMACRxCPWrite(uint32 emacBase, uint32 channel,
+                          uint32 comPtr);
+extern void EMACRxBroadCastEnable(uint32 emacBase, uint32 channel);
+extern void EMACRxBroadCastDisable(uint32 emacBase, uint32 channel);
+extern void EMACRxMultiCastEnable(uint32 emacBase, uint32 channel);
+extern void EMACRxMultiCastDisable(uint32 emacBase, uint32 channel);
+extern void EMACNumFreeBufSet(uint32 emacBase, uint32 channel,
+                              uint32 nBuf);
+extern uint32 EMACIntVectorGet(uint32 emacBase);
+uint32 EMACHWInit(uint8_t macaddr[6U]);
+void EMACTxTeardown(uint32 emacBase, uint32 channel);
+void EMACRxTeardown(uint32 emacBase, uint32 channel);
+void EMACFrameSelect(uint32 emacBase, uint64 hashTable);
+void EMACTxPrioritySelect(uint32 emacBase, uint32 txPType);
+void EMACSoftReset(uint32 emacCtrlBase, uint32 emacBase);
+void EMACEnableIdleState(uint32 emacBase);
+void EMACDisableIdleState(uint32 emacBase);
+void EMACEnableLoopback(uint32 emacBase);
+void EMACDisableLoopback(uint32 emacBase);
+void EMACTxFlowControlEnable(uint32 emacBase);
+void EMACTxFlowControlDisable(uint32 emacBase);
+void EMACRxFlowControlEnable(uint32 emacBase);
+void EMACRxFlowControlDisable(uint32 emacBase);
+void EMACRxSetFlowThreshold(uint32 emacBase, uint32 channel, uint32 threshold);
+uint32 EMACReadNetStatRegisters(uint32 emacBase, uint32 statRegNo);
+void EMACDMAInit(hdkif_t *hdkif);
+boolean EMACTransmit(hdkif_t *hdkif, pbuf_t *pbuf);
+void EMACTxIntHandler(hdkif_t *hdkif);
+void EMACReceive(hdkif_t *hdkif);
+/* Notification Function to which received packets are passed after processing */
+void emacTxNotification(hdkif_t *hdkif);
+void emacRxNotification(hdkif_t *hdkif);
+void EMACTxIntStat(uint32 emacBase, uint32 channel, emac_tx_int_status_t *txintstat);
+void EMACRxIntStat(uint32 emacBase, uint32 channel, emac_rx_int_status_t *rxintstat);
+void EMACGetConfigValue(emac_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* __EMAC_H__ */
diff --git a/include/arch/rm46l8lp/halcogen/eqep.h b/include/arch/rm46l8lp/halcogen/eqep.h
new file mode 100644
index 0000000..63d1637
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/eqep.h
@@ -0,0 +1,716 @@
+/** @file eqep.h
+*   @brief EQEP Driver Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __eQEP_H__
+#define __eQEP_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "reg_eqep.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/*QDECCTL Register */
+#define eQEP_QDECCTL_QSRC					 ((uint16)((uint16)3U  << 14U))		/*<position counter source selection   */
+#define eQEP_QDECCTL_SOEN					 ((uint16)((uint16)1U  << 13U))		/*<sync output enable                  */
+#define eQEP_QDECCTL_SPSEL					 ((uint16)((uint16)1U  << 12U))		/*<sync output pin selection           */
+#define eQEP_QDECCTL_XCR				 	 ((uint16)((uint16)1U  << 11U))		/*<external clock rate                 */
+#define eQEP_QDECCTL_SWAP					 ((uint16)((uint16)1U  << 10U))		/*<swap quadrature clock inputs        */
+#define eQEP_QDECCTL_IGATE					 ((uint16)((uint16)1U  <<  9U))		/*<index pulse gating option           */
+#define eQEP_QDECCTL_QAP				 	 ((uint16)((uint16)1U  <<  8U))		/*<QEPA input polarity                 */
+#define eQEP_QDECCTL_QBP					 ((uint16)((uint16)1U  <<  7U))		/*<QEPB input polarity                 */
+#define eQEP_QDECCTL_QIP					 ((uint16)((uint16)1U  <<  6U))		/*<QEPI input polarity                 */
+#define eQEP_QDECCTL_QSP					 ((uint16)((uint16)1U  <<  5U))		/*<QEPS input polarity                 */
+
+/*QEPCTL Register */
+#define eQEP_QEPCTL_FREESOFT				 ((uint16)((uint16)3U << 14U))		/*<emulation control bit                                          */
+#define eQEP_QEPCTL_PCRM					 ((uint16)((uint16)3U << 12U))		/*<emulation control bit                                          */
+#define eQEP_QEPCTL_SEI						 ((uint16)((uint16)3U << 10U))		/*<strobe event initialization of position counter                */
+#define eQEP_QEPCTL_IEI						 ((uint16)((uint16)3U <<  8U))		/*<index event initialization of position counter                 */
+#define eQEP_QEPCTL_SWI						 ((uint16)((uint16)1U <<  7U))		/*<software initialization of position counter                    */
+#define eQEP_QEPCTL_SEL						 ((uint16)((uint16)1U <<  6U))		/*<strobe event latch of position counter                         */
+#define eQEP_QEPCTL_IEL						 ((uint16)((uint16)3U <<  4U))		/*<index event latch of position counter ((uint16)((uint16)software index marker)  */
+#define eQEP_QEPCTL_QPEN					 ((uint16)((uint16)1U <<  3U))		/*<quad position counter enable/software reset                    */
+#define eQEP_QEPCTL_QCLM					 ((uint16)((uint16)1U <<  2U))		/*<QEP capture latch mode                                         */
+#define eQEP_QEPCTL_UTE						 ((uint16)((uint16)1U <<  1U))		/*<QEP unit timer enable                                          */
+#define eQEP_QEPCTL_WDE						 ((uint16)((uint16)1U <<  0U))		/*<watchdog timer enable                                          */
+                                                                                                                                  
+/*QPOSCTL Register */                                                                                                                
+#define eQEP_QPOSCTL_PCSHDW					 ((uint16)((uint16)1U << 15U))	/*<position compare shadow enable                                     */
+#define eQEP_QPOSCTL_PCLOAD					 ((uint16)((uint16)1U << 14U))	/*<position compare shadow load mode                                  */
+#define eQEP_QPOSCTL_PCPOL					 ((uint16)((uint16)1U << 13U))	/*<load when QPOSCNT = QPOSCMP                                        */
+#define eQEP_QPOSCTL_PCE					 ((uint16)((uint16)1U << 12U))	/*<position compare enable/disable                                    */
+#define eQEP_QPOSCTL_PCSPW					 ((uint16)((uint16)4095U <<  0U))	/*<selection position compare sync output pulse width                 */
+
+/*QCAPCTL Register */
+#define eQEP_QCAPCTL_CEN					 ((uint16)((uint16)1U << 15U))	/*<enable QEP capture                */
+#define eQEP_QCAPCTL_CCPS					 ((uint16)((uint16)7U <<  4U))	/*<qep capture timer clock prescaler */ 
+#define eQEP_QCAPCTL_UPPS					 ((uint16)((uint16)15U <<  0U))	/*<unit position event prescaler     */ 
+
+/*QEINT Register */
+#define eQEP_QEINT_UTO						 ((uint16)((uint16)1U << 11U))	/*<unit timeout interrupt enable                    */
+#define eQEP_QEINT_IEL						 ((uint16)((uint16)1U << 10U))	/*<index event latch interrupt enable               */
+#define eQEP_QEINT_SEL						 ((uint16)((uint16)1U <<  9U))	/*<strobe event latch	interrupt enable            */
+#define eQEP_QEINT_PCM						 ((uint16)((uint16)1U <<  8U))	/*<position compare match interrupt enable	        */
+#define eQEP_QEINT_PCR						 ((uint16)((uint16)1U <<  7U))	/*<position compare ready interrupt enable          */
+#define eQEP_QEINT_PCO						 ((uint16)((uint16)1U <<  6U))	/*<position counter overflow interrupt enable       */
+#define eQEP_QEINT_PCU						 ((uint16)((uint16)1U <<  5U))	/*<position counter underflow interrupt enable      */
+#define eQEP_QEINT_WTO						 ((uint16)((uint16)1U <<  4U))	/*<watchdog time out interrupt enable               */
+#define eQEP_QEINT_QDC						 ((uint16)((uint16)1U <<  3U))	/*<quadrature direction change interrupt enable     */
+#define eQEP_QEINT_QPE						 ((uint16)((uint16)1U <<  2U))	/*<quadrature phase error interrupt enable          */
+#define eQEP_QEINT_PCE						 ((uint16)((uint16)1U <<  1U))	/*<position counter error interrupt enable          */
+																
+/*QFLG Register */
+#define eQEP_QFLG_UTO						 ((uint16)((uint16)1U << 11U))	/*<unit timeout interrupt flag                       */
+#define eQEP_QFLG_IEL						 ((uint16)((uint16)1U << 10U))	/*<index event latch interrupt flag                  */
+#define eQEP_QFLG_SEL						 ((uint16)((uint16)1U <<  9U))	/*<strobe event latch	interrupt flag               */
+#define eQEP_QFLG_PCM						 ((uint16)((uint16)1U <<  8U))	/*<position compare match interrupt flag             */
+#define eQEP_QFLG_PCR						 ((uint16)((uint16)1U <<  7U))	/*<position compare ready interrupt flag             */
+#define eQEP_QFLG_PCO						 ((uint16)((uint16)1U <<  6U))	/*<position counter overflow interrupt flag          */
+#define eQEP_QFLG_PCU						 ((uint16)((uint16)1U <<  5U))	/*<position counter underflow interrupt flag         */
+#define eQEP_QFLG_WTO						 ((uint16)((uint16)1U <<  4U))	/*<watchdog time out interrupt flag                  */
+#define eQEP_QFLG_QDC						 ((uint16)((uint16)1U <<  3U))	/*<quadrature direction change interrupt flag        */
+#define eQEP_QFLG_QPE						 ((uint16)((uint16)1U <<  2U))	/*<quadrature phase error interrupt flag             */
+#define eQEP_QFLG_PCE						 ((uint16)((uint16)1U <<  1U))	/*<position counter error interrupt flag             */
+
+/*QCLR Register */
+#define eQEP_QCLR_UTO						 ((uint16)((uint16)1U << 11U))	/*<clear unit timeout interrupt flag                  */
+#define eQEP_QCLR_IEL						 ((uint16)((uint16)1U << 10U))	/*<clear index event latch interrupt flag             */
+#define eQEP_QCLR_SEL						 ((uint16)((uint16)1U <<  9U))	/*<clear strobe event latch interrupt flag            */
+#define eQEP_QCLR_PCM						 ((uint16)((uint16)1U <<  8U))	/*<clear position compare match interrupt flag        */
+#define eQEP_QCLR_PCR						 ((uint16)((uint16)1U <<  7U))	/*<clear position compare ready interrupt flag        */
+#define eQEP_QCLR_PCO						 ((uint16)((uint16)1U <<  6U))	/*<clear position counter overflow interrupt flag     */
+#define eQEP_QCLR_PCU						 ((uint16)((uint16)1U <<  5U))	/*<clear position counter underflow interrupt flag    */
+#define eQEP_QCLR_WTO						 ((uint16)((uint16)1U <<  4U))	/*<clear watchdog time out interrupt flag             */
+#define eQEP_QCLR_QDC						 ((uint16)((uint16)1U <<  3U))	/*<clear quadrature direction change interrupt flag   */
+#define eQEP_QCLR_QPE						 ((uint16)((uint16)1U <<  2U))	/*<clear quadrature phase error interrupt flag        */
+#define eQEP_QCLR_PCE						 ((uint16)((uint16)1U <<  1U))	/*<clear position counter error interrupt flag        */
+
+/*QFRC Register */
+#define eQEP_QFRC_UTO						 ((uint16)((uint16)1U << 11U))	/*<force unit timeout interrupt                       */
+#define eQEP_QFRC_IEL						 ((uint16)((uint16)1U << 10U))	/*<force index event latch interrupt                  */
+#define eQEP_QFRC_SEL						 ((uint16)((uint16)1U <<  9U))	/*<force strobe event latch interrupt                 */
+#define eQEP_QFRC_PCM						 ((uint16)((uint16)1U <<  8U))	/*<force position compare match interrupt             */
+#define eQEP_QFRC_PCR						 ((uint16)((uint16)1U <<  7U))	/*<force position compare ready interrupt             */
+#define eQEP_QFRC_PCO						 ((uint16)((uint16)1U <<  6U))	/*<force position counter overflow interrupt          */
+#define eQEP_QFRC_PCU						 ((uint16)((uint16)1U <<  5U))	/*<force position counter underflow interrupt         */
+#define eQEP_QFRC_WTO						 ((uint16)((uint16)1U <<  4U))	/*<force watchdog time out interrupt                  */
+#define eQEP_QFRC_QDC						 ((uint16)((uint16)1U <<  3U))	/*<force quadrature direction change interrupt        */
+#define eQEP_QFRC_QPE						 ((uint16)((uint16)1U <<  2U))	/*<force quadrature phase error interrupt             */
+#define eQEP_QFRC_PCE						 ((uint16)((uint16)1U <<  1U))	/*<force position counter error interrupt             */
+
+/*QEPSTS Register */
+#define eQEP_QEPSTS_UPEVNT					((uint16)((uint16)1U << 7U))		/*<unit position event flag                       */
+#define eQEP_QEPSTS_FDF						((uint16)((uint16)1U << 6U))		/*<direction on the first index marker            */
+#define eQEP_QEPSTS_QDF						((uint16)((uint16)1U << 5U))		/*<quadrature direction flag                      */
+#define eQEP_QEPSTS_QDLF						((uint16)((uint16)1U << 4U))		/*<direction latch flag                           */
+#define eQEP_QEPSTS_COEF						((uint16)((uint16)1U << 3U))		/*<capture overflow error flag                    */
+#define eQEP_QEPSTS_CDEF						((uint16)((uint16)1U << 2U))		/*<capture direction error flag                   */
+#define eQEP_QEPSTS_FIMF						((uint16)((uint16)1U << 1U))		/*<first index marker flag                        */
+#define eQEP_QEPSTS_PCEF						((uint16)((uint16)1U << 0U))		/*<position counter error flag                    */
+                                                                                                                  
+/*PC mode  */                                                                                                        
+#define eQEP_QUADRATURE_COUNT                 0x00U                                                                
+#define eQEP_DIRECTION_COUNT                  0x01U
+#define eQEP_UP_COUNT                         0x02U
+#define eQEP_DOWN_COUNT                       0x03U
+
+/*External Clock Rate */ 
+#define eQEP_RESOLUTION_2x                    0x00U
+#define eQEP_RESOLUTION_1x                    0x01U
+
+/*Direction */
+#define eQEP_CLOCKWISE                        0x01U
+#define eQEP_COUNTERCLOCKWISE                 0x01U
+
+/*Edge */
+#define eQEP_RISING_EDGE                      0x00U
+#define eQEP_FALLING_EDGE                     0x01U
+#define eQEP_DIRECTON_DEPENDENT               0x01U
+
+/*Index event latch of position counter */ 
+#define eQEP_LATCH_RISING_EDGE                0x01U
+#define eQEP_LATCH_FALLING_EDGE               0x02U
+#define eQEP_LATCH_SW_INDEX_MARKER            0x03U
+
+/*Position counter reset mode */
+#define eQEP_INDEX_EVENT                      0x00U
+#define eQEP_MAX_POSITION                     0x01U
+#define eQEP_FIRST_INDEX_EVENT                0x02U
+#define eQEP_UNITTIME_EVENT                   0x03U
+
+/*eQEP capture timer clock prescaler and Unit position event prescaler */
+#define eQEP_PS_1                             0x00U
+#define eQEP_PS_2                             0x01U
+#define eQEP_PS_4                             0x02U
+#define eQEP_PS_8                             0x03U
+#define eQEP_PS_16                            0x04U
+#define eQEP_PS_32                            0x05U
+#define eQEP_PS_64                            0x06U
+#define eQEP_PS_128                           0x07U
+#define eQEP_PS_256                           0x08U
+#define eQEP_PS_512                           0x09U
+#define eQEP_PS_1024                          0x0AU
+#define eQEP_PS_2048                          0x0BU
+
+/*eQEP capture latch mode */
+#define eQEP_ON_POSITION_COUNTER_READ         0x00U
+#define eQEP_ON_UNIT_TIMOUT_EVENT             0x01U
+
+/*Sync output pin selection */
+#define eQEP_INDEX_PIN                        0x00U
+#define eQEP_STROBE_PIN                       0x01U
+
+/*Position-compare shadow load mode */
+#define eQEP_QPOSCNT_EQ_0                     0x00U
+#define eQEP_QPOSCNT_EQ_QPSCMP                0x01U
+
+/*Polarity of sync output */
+#define eQEP_ACTIVE_HIGH                      0x00U
+#define eQEP_ACTIVE_LOW                       0x01U
+
+/***************************************************************************
+* the typedefs
+*/
+/** @brief QEP counting mode
+*/
+typedef enum
+{
+	eQEP_Qsrc_Quad_Count_Mode=((uint16)0U << 14U),					/*<quadrature count mode                                          */
+	eQEP_Qsrc_Dir_Count_Mode=((uint16)1U << 14U),					/*<direction count mode                                           */
+	eQEP_Qsrc_Up_Count_Mode=((uint16)2U << 14U),						/*<up count mode for frequency measurement (QCLK=XCLK, QDIR=1U)   */
+	eQEP_Qsrc_Down_Count_Mode=((uint16)3U << 14U)					/*<down count mode for frequency measurement (QCLK=XCLK, QDIR=0U) */
+} eQEP_Qsrc_t;
+
+/** @brief Sync output pin selection
+*/
+typedef enum
+{	
+	eQEP_Spsel_Index_Pin_Sync_Output=((uint16)0U << 12U),			/*<index pin for sync output  */
+	eQEP_Spsel_Strobe_Pin_Sync_Output=((uint16)1U << 12U)			/*<strobe pin for sync output */ 
+} eQEP_Spsel_t;
+
+/** @brief External clock rate
+*/
+typedef enum
+{
+	eQEP_Xcr_2x_Res=((uint16)0U << 11U),								/*<2x resolution: count the rising/falling edge  */
+	eQEP_Xcr_1x_Res=((uint16)1U << 11U)								/*<1x resolution: count the rising edge only     */
+} eQEP_Xcr_t;
+
+/** @brief Swap A/B channels
+*/
+typedef enum
+{
+	eQEP_Swap_Not_Swapped=((uint16)0U << 10U),						/*<quad inputs not swapped  */
+	eQEP_Swap_Swapped=((uint16)1U << 10U)							/*<quad inputs swapped      */
+} eQEP_Swap_t;
+
+/** @brief Index gating
+*/
+typedef enum
+{
+	eQEP_Igate_Disable=((uint16)0U << 9U),							/*<disable gating of index pulse  */
+	eQEP_Igate_Enable=((uint16)1U << 9U)								/*<enable gating of index pulse   */
+} eQEP_Igate_t;
+
+/** @brief Channel A polarity
+*/
+typedef enum
+{
+	eQEP_Qap_No_Effect=((uint16)0U << 8U),							/*<no effect           */
+	eQEP_Qap_Inverted=((uint16)1U << 8U)								/*<negates QEPA input  */
+} eQEP_Qap_t;
+
+/** @brief Channel B polarity
+*/
+typedef enum
+{
+	eQEP_Qbp_No_Effect=((uint16)0U << 7U),							/*<no effect           */
+	eQEP_Qbp_Inverted=((uint16)1U << 7U)								/*<negates QEPB input  */
+} eQEP_Qbp_t;
+
+/** @brief Index polarity
+*/
+typedef enum
+{
+	eQEP_Qip_No_Effect=((uint16)0U << 6U),							/*<no effect          */
+	eQEP_Qip_Inverted=((uint16)1U << 6U)								/*<negates QEPI input */
+} eQEP_Qip_t;
+
+/** @brief Channel S polarity
+*/
+typedef enum
+{
+	eQEP_Qsp_No_Effect=((uint16)0U << 5U),								/*<no effect*/
+	eQEP_Qsp_Inverted=((uint16)1U << 5U)								/*<negates QEPS input */
+} eQEP_Qsp_t;
+
+/** @brief Emulation control bits
+*/
+typedef enum
+{
+	QEPCTL_Freesoft_Immediate_Halt=((uint16)0U << 14U),				/*<position, watchdog, unit timer, capture timer stops immediately                                       */
+	QEPCTL_Freesoft_Rollover_Halt=((uint16)1U << 14U),				/*<position, watchdog, unit timer continues until rollover, capture counts until next unit period event  */
+	QEPCTL_Freesoft_Unaffected_Halt=((uint16)2U << 14U)				/*<position, watchdog, unit timer, capture timer unaffected by emu suspend                               */
+} QEPCTL_Freesoft_t;
+
+/** @brief Position counter reset mode
+*/
+typedef enum
+{
+	QEPCTL_Pcrm_Index_Reset=((uint16)0U << 12U),					/*<position counter reset on index event      */
+	QEPCTL_Pcrm_Max_Reset=((uint16)1U << 12U),						/*<position counter reset on max position     */
+	QEPCTL_Pcrm_First_Index_Reset=((uint16)2U << 12U),				/*<position counter reset on first index event*/
+	QEPCTL_Pcrm_Unit_Time_Reset=((uint16)3U << 12U)					/*<position counter reset on unit time event  */
+} QEPCTL_Pcrm_t;
+
+/** @brief Strobe event initialization of position counter
+*/
+typedef enum
+{ 
+	QEPCTL_Sei_Nothing=((uint16)0U << 10U),							/*<does nothing                                       */
+	QEPCTL_Sei_Rising_Edge_Init=((uint16)2U << 10U),				/*<initializes on rising edge of QEPS signal          */
+	QEPCTL_Sei_Rising_Falling_Edge_Init=((uint16)3U << 10U)			/*<initializes on rising/falling edge of QEPS signal  */
+} QEPCTL_Sei_t;
+
+/** @brief Index event initialization of position counter
+*/
+typedef enum
+{
+	QEPCTL_Iei_Nothing=((uint16)0U << 8U),							/*<does nothing                               */
+	QEPCTL_Iei_Rising_Edge_Init=((uint16)2U << 8U),					/*<initializes on rising edge of QEPI signal  */
+	QEPCTL_Iei_Rising_Falling_Edge_Init=((uint16)3U << 8U)			/*<initializes on falling edge of QEPI signal */
+} QEPCTL_Iei_t;
+
+/** @brief Software initialization of position counter
+*/
+typedef enum
+{
+	QEPCTL_Swi_Nothing=((uint16)0U << 7U),							/*<does nothing                             */
+	QEPCTL_Swi_Auto_Init_Counter=((uint16)1U << 7U)					/*<init position counter (QPOSCNT=QPOSINIT) */
+} QEPCTL_Swi_t;
+
+/** @brief Strobe event latch of position counter
+*/
+typedef enum
+{
+	QEPCTL_Sel_Rising_Edge=((uint16)0U << 6U),						/*<Position counter latched on rising edge of QEPS strobe (QPOSSLAT = POSCCNT)                    */
+	QEPCTL_Sel_Rising_Falling_Edge=((uint16)1U << 6U)				/*<Clockwise: position counter latched on rising edge, counter clockwise: latched on falling edge */
+} QEPCTL_Sel_t;
+	
+/** @brief Index event latch of position counter (software index marker)
+*/
+typedef enum
+{
+	QEPCTL_Iel_Rising_Edge=((uint16)1U << 4U),						/*<latches position counter on rising edge of index signal  */
+	QEPCTL_Iel_Falling_Edge=((uint16)2U << 4U),						/*<ditto on falling edge of index signal                    */
+	QEPCTL_Iel_Software_Index_Marker=((uint16)3U << 4U)				/*<software index marker.  See data sheet.                  */
+} QEPCTL_Iel_t;
+
+/** @brief QEP capture latch mode
+*/
+typedef enum
+{
+	QEPCTL_Qclm_Latch_on_CPU_Read=((uint16)0U << 2U),					/*<latch on position counter read by cpu  */
+	QEPCTL_Qclm_Latch_on_Unit_Timeout=((uint16)1U << 2U)				/*<latch on unit time out                 */
+} QEPCTL_Qclm_t;
+
+/** @brief Position compare shadow enable
+*/
+typedef enum
+{
+	QPOSCTL_Pcshdw_Load_Immediate=((uint16)0U << 15U),				/*<shadow disabled, load immediate */
+	QPOSCTL_Pcshdw_Shadow_Enabled=((uint16)1U << 15U)				/*<shadow enabled                  */
+} QPOSCTL_Pcshdw_t;
+
+/** @brief Position compare shadow load mode
+*/
+typedef enum
+{
+	QPOSCTL_Pcload_Load_Posn_Count_Zero=((uint16)0U << 14U),			/*<load on qposcnt = 0          */
+	QPOSCTL_Pcload_Load_Posn_Count_Equal_Compare=((uint16)1U << 14U)	/*<load when qposcnt = qposcmp  */
+} QPOSCTL_Pcload_t;
+
+/** @brief Polarity of sync output
+*/
+typedef enum
+{
+	QPOSCTL_Pcpol_Active_High=((uint16)0U << 13U),					/*<active high pulse output  */
+	QPOSCTL_Pcpol_Active_Low=((uint16)1U << 13U)					/*<active low pulse output   */
+} QPOSCTL_Pcpol_t;
+
+/** @brief QEP capture timer clock prescaler
+*/
+typedef enum
+{
+	QCAPCTL_Ccps_Capture_Div_1=((uint16)0U << 4U),					/*<capclk = sysclkout/1   */
+	QCAPCTL_Ccps_Capture_Div_2=((uint16)1U << 4U),					/*<capclk = sysclkout/2   */
+	QCAPCTL_Ccps_Capture_Div_4=((uint16)2U << 4U),					/*<capclk = sysclkout/4   */
+	QCAPCTL_Ccps_Capture_Div_8=((uint16)3U << 4U),					/*<capclk = sysclkout/8   */
+	QCAPCTL_Ccps_Capture_Div_16=((uint16)4U << 4U),					/*<capclk = sysclkout/16  */
+	QCAPCTL_Ccps_Capture_Div_32=((uint16)5U << 4U),					/*<capclk = sysclkout/32  */
+	QCAPCTL_Ccps_Capture_Div_64=((uint16)6U << 4U),					/*<capclk = sysclkout/64  */
+	QCAPCTL_Ccps_Capture_Div_128=((uint16)7U << 4U)					/*<capclk = sysclkout/128 */
+} QCAPCTL_Ccps_t;
+
+/** @brief Unit position event prescaler
+*/
+typedef enum
+{
+	QCAPCTL_Upps_Div_1_Prescale=((uint16)0U << 0U),					/*<upevnt = qclk/1    */
+	QCAPCTL_Upps_Div_2_Prescale=((uint16)1U << 0U),					/*<upevnt = qclk/2    */
+	QCAPCTL_Upps_Div_4_Prescale=((uint16)2U << 0U),					/*<upevnt = qclk/4    */
+	QCAPCTL_Upps_Div_8_Prescale=((uint16)3U << 0U),					/*<upevnt = qclk/8    */
+	QCAPCTL_Upps_Div_16_Prescale=((uint16)4U << 0U),				/*<upevnt = qclk/16   */
+	QCAPCTL_Upps_Div_32_Prescale=((uint16)5U << 0U),				/*<upevnt = qclk/32   */
+	QCAPCTL_Upps_Div_64_Prescale=((uint16)6U << 0U),				/*<upevnt = qclk/64   */
+	QCAPCTL_Upps_Div_128_Prescale=((uint16)7U << 0U),				/*<upevnt = qclk/128  */
+	QCAPCTL_Upps_Div_256_Prescale=((uint16)8U << 0U),				/*<upevnt = qclk/256  */
+	QCAPCTL_Upps_Div_512_Prescale=((uint16)9U << 0U),				/*<upevnt = qclk/512  */
+	QCAPCTL_Upps_Div_1024_Prescale=((uint16)10U << 0U),				/*<upevnt = qclk/1024 */
+	QCAPCTL_Upps_Div_2048_Prescale=((uint16)11U << 0U)				/*<upevnt = qclk/2048 */
+} QCAPCTL_Upps_t;
+
+/** @brief QEP interrupt enable flags
+*/
+typedef enum
+{
+	QEINT_Uto=((uint16)1U << 11U),									    /*<unit time out interrupt enable                      */
+	QEINT_Iel=((uint16)1U << 10U),								     	/*<index event latch interrupt enable                  */
+	QEINT_Sel=((uint16)1U << 9U),										/*<strobe event latch interrupt enable                 */
+	QEINT_Pcm=((uint16)1U << 8U),										/*<position compare match interrupt enable             */
+	QEINT_Pcr=((uint16)1U << 7U),										/*<position compare ready interrupt enable             */
+	QEINT_Pco=((uint16)1U << 6U),										/*<position compare overflow interrupt enable          */
+	QEINT_Pcu=((uint16)1U << 5U),										/*<position compare underflow interrupt enable         */
+	QEINT_Wto=((uint16)1U << 4U),										/*<position compare watchdog time out interrupt enable */
+	QEINT_Qdc=((uint16)1U << 3U),										/*<quadrature direction change interrupt enable        */
+	QEINT_Qpe=((uint16)1U << 2U),										/*<quadrature phase error interrupt enable             */
+	QEINT_Pce=((uint16)1U << 1U)										/*<position counter interrupt enable                   */
+} QEINT_t;                                                                                                             
+            
+/* Configuration registers */
+typedef struct eqep_config_reg
+{
+    uint32 CONFIG_QPOSINIT;
+    uint32 CONFIG_QPOSMAX;
+    uint32 CONFIG_QPOSCMP;
+    uint32 CONFIG_QUPRD;
+    uint16 CONFIG_QWDPRD;
+    uint16 CONFIG_QDECCTL;
+    uint16 CONFIG_QEPCTL;
+    uint16 CONFIG_QCAPCTL;
+    uint16 CONFIG_QPOSCTL;	
+	uint16 CONFIG_QEINT;
+} eqep_config_reg_t;		
+
+#define EQEP1_QPOSINIT_CONFIGVALUE ((uint32)0x00000000U)
+#define EQEP1_QPOSMAX_CONFIGVALUE ((uint32)0x00000000U)
+#define EQEP1_QPOSCMP_CONFIGVALUE ((uint32)0x00000000U)
+#define EQEP1_QUPRD_CONFIGVALUE ((uint32)0x00000000U)
+#define EQEP1_QWDPRD_CONFIGVALUE ((uint16) 0x0000U)
+#define EQEP1_QDECCTL_CONFIGVALUE ((uint16)((uint16)((uint16)eQEP_DIRECTION_COUNT << 14U)\
+								   | (uint16)((uint16)0U << 13U)\
+								   | (uint16)((uint16)eQEP_INDEX_PIN << 12U)\
+								   | (uint16)((uint16)eQEP_RESOLUTION_1x << 11U)\
+								   | (uint16)((uint16)0U << 10U)\
+								   | (uint16)((uint16)0U << 9U)\
+								   | (uint16)((uint16)0U << 8U)\
+								   | (uint16)((uint16)0U << 7U)\
+								   | (uint16)((uint16)0U << 6U)\
+								   | (uint16)((uint16)0U << 5U)\
+								   | (uint16)0x0000U))
+					 
+#define EQEP1_QEPCTL_CONFIGVALUE ((uint16)((uint16)((uint16)eQEP_MAX_POSITION << 12U)\
+								   | (uint16)((uint16)0U << 11U)\
+								   | (uint16)((uint16)eQEP_DIRECTON_DEPENDENT << 10U)\
+								   | (uint16)((uint16)0U << 9U)\
+								   | (uint16)((uint16)eQEP_RISING_EDGE << 8U)\
+								   | (uint16)((uint16)0U << 7U)\
+								   | (uint16)((uint16)eQEP_RISING_EDGE << 6U)\
+								   | (uint16)((uint16)eQEP_LATCH_RISING_EDGE << 4U)\
+								   | (uint16)((uint16)eQEP_ON_POSITION_COUNTER_READ << 2U)\
+								   | (uint16)0x0000U))
+					 
+#define EQEP1_QCAPCTL_CONFIGVALUE ((uint16)((uint16)((uint16)eQEP_PS_8 << 4U)\
+								   | (uint16)((uint16)eQEP_PS_512)\
+								   | (uint16)0x0000U))
+								   
+#define EQEP1_QPOSCTL_CONFIGVALUE ((uint16)((uint16)((uint16)0U << 15U)\
+								   | (uint16)((uint16)eQEP_QPOSCNT_EQ_QPSCMP << 14U)\
+								   | (uint16)((uint16)eQEP_ACTIVE_HIGH << 13U)\
+								   | (uint16)((uint16)0x000U)\
+								   | (uint16)0x0000U))
+					   
+#define EQEP1_QEINT_CONFIGVALUE ((uint16)((uint16)((uint16)0U << 11U)\
+								   | (uint16)((uint16)0U << 10U)\
+								   | (uint16)((uint16)0U << 9U)\
+								   | (uint16)((uint16)0U << 8U)\
+								   | (uint16)((uint16)0U << 7U)\
+								   | (uint16)((uint16)0U << 6U)\
+								   | (uint16)((uint16)0U << 5U)\
+								   | (uint16)((uint16)0U << 4U)\
+								   | (uint16)((uint16)0U << 3U)\
+								   | (uint16)((uint16)0U << 2U)\
+								   | (uint16)((uint16)0U << 1U)))   
+#define EQEP2_QPOSINIT_CONFIGVALUE ((uint32)0x00000000U)
+#define EQEP2_QPOSMAX_CONFIGVALUE ((uint32)0x00000000U)
+#define EQEP2_QPOSCMP_CONFIGVALUE ((uint32)0U)
+#define EQEP2_QUPRD_CONFIGVALUE ((uint32) 0U)
+#define EQEP2_QWDPRD_CONFIGVALUE ((uint16) 0U)
+#define EQEP2_QDECCTL_CONFIGVALUE ((uint16)((uint16)((uint16)eQEP_DIRECTION_COUNT << 14U)\
+								   | (uint16)((uint16)0U << 13U)\
+								   | (uint16)((uint16)eQEP_INDEX_PIN << 12U)\
+								   | (uint16)((uint16)eQEP_RESOLUTION_1x << 11U)\
+								   | (uint16)((uint16)0U << 10U)\
+								   | (uint16)((uint16)0U << 9U)\
+								   | (uint16)((uint16)0U << 8U)\
+								   | (uint16)((uint16)0U << 7U)\
+								   | (uint16)((uint16)0U << 6U)\
+								   | (uint16)((uint16)0U << 5U)\
+								   | (uint16)0x0000U))
+					 
+#define EQEP2_QEPCTL_CONFIGVALUE ((uint16)((uint16)((uint16)eQEP_MAX_POSITION << 12U)\
+								   | (uint16)((uint16)0U << 11U)\
+								   | (uint16)((uint16)eQEP_DIRECTON_DEPENDENT << 10U)\
+								   | (uint16)((uint16)0U << 9U)\
+								   | (uint16)((uint16)eQEP_RISING_EDGE << 8U)\
+								   | (uint16)((uint16)0U << 7U)\
+								   | (uint16)((uint16)eQEP_RISING_EDGE << 6U)\
+								   | (uint16)((uint16)eQEP_LATCH_RISING_EDGE << 4U)\
+								   | (uint16)((uint16)eQEP_ON_POSITION_COUNTER_READ << 2U)\
+								   | (uint16)0x0000U))
+					 
+#define EQEP2_QCAPCTL_CONFIGVALUE ((uint16)((uint16)((uint16)eQEP_PS_8 << 4U)\
+								   | ((uint16)eQEP_PS_512)\
+								   | (uint16)0x0000U))
+								   
+#define EQEP2_QPOSCTL_CONFIGVALUE ((uint16)((uint16)((uint16)0U << 15U)\
+								   | (uint16)((uint16)eQEP_QPOSCNT_EQ_QPSCMP << 14U)\
+								   | (uint16)((uint16)eQEP_ACTIVE_HIGH << 13U)\
+								   | (uint16)((uint16)0U)\
+								   | (uint16)0x0000U))
+					   
+#define EQEP2_QEINT_CONFIGVALUE ((uint16)((uint16)((uint16)0U << 11U)\
+								   | (uint16)((uint16)0U << 10U)\
+								   | (uint16)((uint16)0U << 9U)\
+								   | (uint16)((uint16)0U << 8U)\
+								   | (uint16)((uint16)0U << 7U)\
+								   | (uint16)((uint16)0U << 6U)\
+								   | (uint16)((uint16)0U << 5U)\
+								   | (uint16)((uint16)0U << 4U)\
+								   | (uint16)((uint16)0U << 3U)\
+								   | (uint16)((uint16)0U << 2U)\
+								   | (uint16)((uint16)0U << 1U)))	
+								   
+/**
+ *  @defgroup eQEP eQEP
+ *  @brief Enhanced QEP Module.
+ *  
+ *  The enhanced quadrature encoder pulse (eQEP) module is used for direct interface with a linear or rotary
+ *  incremental encoder to get position, direction, and speed information from a rotating machine for use in a
+ *  high-performance motion and position-control system. This microcontroller implements 2 instances of the
+ *  eQEP module.
+ *
+ *	Related Files
+ *   - reg_eqep.h
+ *   - eqep.h
+ *   - eqep.c
+ *  @addtogroup eQEP
+ *  @{
+ */
+
+/***************************************************************************
+*the function prototypes
+*/
+
+void QEPInit(void);
+
+
+void eqepClearAllInterruptFlags (eqepBASE_t *eqep);
+
+
+void eqepClearInterruptFlag (eqepBASE_t *eqep, QEINT_t QEINT_type);
+
+
+void eqepClearPosnCounter (eqepBASE_t *eqep);
+
+
+void eqepDisableAllInterrupts (eqepBASE_t *eqep);
+
+void eqepDisableCapture (eqepBASE_t *eqep);
+
+
+void eqepDisableGateIndex (eqepBASE_t *eqep);
+
+void eqepDisableInterrupt (eqepBASE_t *eqep, QEINT_t QEINT_type);
+
+void eqepDisablePosnCompare (eqepBASE_t *eqep);
+
+void eqepDisablePosnCompareShadow (eqepBASE_t *eqep);
+
+
+void eqepDisableSyncOut (eqepBASE_t *eqep);
+
+void eqepDisableUnitTimer (eqepBASE_t *eqep);
+
+void eqepDisableWatchdog (eqepBASE_t *eqep);
+
+void eqepEnableCapture (eqepBASE_t *eqep);
+
+void eqepEnableCounter (eqepBASE_t *eqep);
+
+void eqepEnableGateIndex (eqepBASE_t *eqep);
+
+void eqepEnableInterrupt (eqepBASE_t *eqep, QEINT_t QEINT_type);
+
+void eqepEnablePosnCompare (eqepBASE_t *eqep);
+
+void eqepEnablePosnCompareShadow (eqepBASE_t *eqep);
+
+void eqepEnableSyncOut (eqepBASE_t *eqep);
+
+void eqepEnableUnitTimer (eqepBASE_t *eqep);
+
+void eqepEnableWatchdog (eqepBASE_t *eqep);
+
+void eqepForceInterrupt (eqepBASE_t *eqep, QEINT_t QEINT_type);
+
+uint16 eqepReadCapturePeriodLatch (eqepBASE_t *eqep);
+
+uint16 eqepReadCaptureTimerLatch (eqepBASE_t *eqep);
+
+uint16 eqepReadInterruptFlag (eqepBASE_t *eqep, QEINT_t QEINT_type);
+
+uint32 eqepReadPosnCompare (eqepBASE_t *eqep);
+
+uint32 eqepReadPosnCount (eqepBASE_t *eqep);
+
+uint32 eqepReadPosnIndexLatch (eqepBASE_t *eqep);
+
+uint32 eqepReadPosnLatch (eqepBASE_t *eqep);
+
+uint32 eqepReadPosnStrobeLatch (eqepBASE_t *eqep);
+
+uint16 eqepReadStatus (eqepBASE_t *eqep);
+
+void eqepResetCounter (eqepBASE_t *eqep);
+
+void eqepSetCaptureLatchMode (eqepBASE_t *eqep, QEPCTL_Qclm_t QEPCTL_Qclm);
+
+void eqepSetCapturePeriod (eqepBASE_t *eqep, uint16 period);
+
+void eqepSetCapturePrescale (eqepBASE_t *eqep, QCAPCTL_Ccps_t QCAPCTL_Ccps);
+
+void eqepSetEmuControl (eqepBASE_t *eqep, QEPCTL_Freesoft_t QEPCTL_Freesoft);
+
+void eqepSetExtClockRate (eqepBASE_t *eqep, eQEP_Xcr_t eQEP_Xcr);
+
+void eqepSetIndexEventInit (eqepBASE_t *eqep, QEPCTL_Iei_t QEPCTL_Iei);
+
+void eqepSetIndexEventLatch (eqepBASE_t *eqep, QEPCTL_Iel_t QEPCTL_Iel);
+
+void eqepSetIndexPolarity (eqepBASE_t *eqep, eQEP_Qip_t eQEP_Qip);
+
+void eqepSetMaxPosnCount (eqepBASE_t *eqep, uint32 max_count);
+
+void eqepSetPosnComparePulseWidth (eqepBASE_t *eqep, uint16 pulse_width);
+
+void eqepSetPosnCompareShadowLoad (eqepBASE_t *eqep, QPOSCTL_Pcload_t QPOSCTL_Pcload);
+
+void eqepSetPosnCountResetMode (eqepBASE_t *eqep, QEPCTL_Pcrm_t QEPCTL_Pcrm);
+
+void eqepSetPosnInitCount (eqepBASE_t *eqep, uint32 init_count);
+
+void eqepSetSelectSyncPin (eqepBASE_t *eqep, eQEP_Spsel_t eQEP_SPsel);
+
+void eqepSetSoftInit (eqepBASE_t *eqep, QEPCTL_Swi_t QEPCTL_Swi);
+
+void eqepSetStrobeEventInit (eqepBASE_t *eqep, QEPCTL_Sei_t QEPCTL_Sei);
+
+void eqepSetStrobeEventLatch (eqepBASE_t *eqep, QEPCTL_Sel_t QEPCTL_Sel);
+
+void eqepSetStrobePolarity (eqepBASE_t *eqep, eQEP_Qsp_t eQEP_Qsp);
+
+void eqepSetSwapQuadInputs (eqepBASE_t *eqep, eQEP_Swap_t eQEP_Swap);
+
+void eqepSetSynchOutputComparePolarity (eqepBASE_t *eqep, QPOSCTL_Pcpol_t QPOSCTL_Pcpol);
+
+void eqepSetUnitPeriod (eqepBASE_t *eqep, uint32 unit_period);
+
+void eqepSetUnitPosnPrescale (eqepBASE_t *eqep, QCAPCTL_Upps_t QCAPCTL_Upps);
+
+void eqepSetWatchdogPeriod (eqepBASE_t *eqep, uint16 watchdog_period);
+
+void eqepSetupStrobeEventLatch (eqepBASE_t *eqep, QEPCTL_Sel_t QEPCTL_Sel);
+
+void eqepSetAPolarity (eqepBASE_t *eqep, eQEP_Qap_t eQEP_Qap);
+
+void eqepSetBPolarity (eqepBASE_t *eqep, eQEP_Qbp_t eQEP_Qbp);
+
+void eqepSetQEPSource (eqepBASE_t *eqep, eQEP_Qsrc_t eQEP_Qsrc);
+
+void eqepWritePosnCompare (eqepBASE_t *eqep, uint32 posn);
+
+/** @brief Interrupt callback
+*   @param[in] eqep		Handle to QEP object
+*   @param[in] flags			Copy of  interrupt flags
+*/
+void 	eqepNotification(eqepBASE_t *eqep,uint16 flags);
+
+void eqep1GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type);
+void eqep2GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type);
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif /*end of _eQEP_H_ definition */
diff --git a/include/arch/rm46l8lp/halcogen/errata_SSWF021_45.h b/include/arch/rm46l8lp/halcogen/errata_SSWF021_45.h
new file mode 100644
index 0000000..14beb20
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/errata_SSWF021_45.h
@@ -0,0 +1,49 @@
+/** @file errata_SSWF021_45.c 
+*   @brief errata for PLLs 
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef INCLUDE_ERRATA_SSWF021_45_H_
+#define INCLUDE_ERRATA_SSWF021_45_H_
+
+uint32 _errata_SSWF021_45_both_plls(uint32 count);
+uint32 _errata_SSWF021_45_pll1(uint32 count);
+uint32 _errata_SSWF021_45_pll2(uint32 count);
+
+
+#endif /* INCLUDE_ERRATA_SSWF021_45_H_ */
diff --git a/include/arch/rm46l8lp/halcogen/errata_SSWF021_45_defs.h b/include/arch/rm46l8lp/halcogen/errata_SSWF021_45_defs.h
new file mode 100644
index 0000000..c8a5734
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/errata_SSWF021_45_defs.h
@@ -0,0 +1,205 @@
+/** @file errata_SSWF021_45.c 
+*   @brief errata for PLLs 
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef INCLUDE_ERRATA_SSWF021_45_DEFS_H_
+#define INCLUDE_ERRATA_SSWF021_45_DEFS_H_
+
+typedef unsigned int uint32_t;
+typedef uint32_t uint32;
+typedef volatile struct systemBase1
+{
+    uint32 SYSPC1;                 /* 0x0000 */
+    uint32 SYSPC2;                 /* 0x0004 */
+    uint32 SYSPC3;                 /* 0x0008 */
+    uint32 SYSPC4;                 /* 0x000C */
+    uint32 SYSPC5;                 /* 0x0010 */
+    uint32 SYSPC6;                 /* 0x0014 */
+    uint32 SYSPC7;                 /* 0x0018 */
+    uint32 SYSPC8;                 /* 0x001C */
+    uint32 SYSPC9;                 /* 0x0020 */
+    uint32 SSWPLL1;                /* 0x0024 */
+    uint32 SSWPLL2;                /* 0x0028 */
+    uint32 SSWPLL3;                /* 0x002C */
+    uint32 CSDIS;                  /* 0x0030 */
+    uint32 CSDISSET;               /* 0x0034 */
+    uint32 CSDISCLR;               /* 0x0038 */
+    uint32 CDDIS;                  /* 0x003C */
+    uint32 CDDISSET;               /* 0x0040 */
+    uint32 CDDISCLR;               /* 0x0044 */
+    uint32 GHVSRC;                 /* 0x0048 */
+    uint32 VCLKASRC;               /* 0x004C */
+    uint32 RCLKSRC;                /* 0x0050 */
+    uint32 CSVSTAT;                /* 0x0054 */
+    uint32 MSTGCR;                 /* 0x0058 */
+    uint32 MINITGCR;               /* 0x005C */
+    uint32 MSINENA;                /* 0x0060 */
+    uint32 MSTFAIL;                /* 0x0064 */
+    uint32 MSTCGSTAT;              /* 0x0068 */
+    uint32 MINISTAT;               /* 0x006C */
+    uint32 PLLCTL1;                /* 0x0070 */
+    uint32 PLLCTL2;                /* 0x0074 */
+    uint32 SYSPC10;                /* 0x0078 */
+    uint32 DIEIDL;                 /* 0x007C */
+    uint32 DIEIDH;                 /* 0x0080 */
+    uint32 VRCTL;                  /* 0x0084 */
+    uint32 LPOMONCTL;              /* 0x0088 */
+    uint32 CLKTEST;                /* 0x008C */
+    uint32 DFTCTRLREG1;            /* 0x0090 */
+    uint32 DFTCTRLREG2;            /* 0x0094 */
+    uint32   rsvd1;                /* 0x0098 */
+    uint32   rsvd2;                /* 0x009C */
+    uint32 GPREG1;                 /* 0x00A0 */
+    uint32 BTRMSEL;                /* 0x00A4 */
+    uint32 IMPFASTS;               /* 0x00A8 */
+    uint32 IMPFTADD;               /* 0x00AC */
+    uint32 SSISR1;                 /* 0x00B0 */
+    uint32 SSISR2;                 /* 0x00B4 */
+    uint32 SSISR3;                 /* 0x00B8 */
+    uint32 SSISR4;                 /* 0x00BC */
+    uint32 RAMGCR;                 /* 0x00C0 */
+    uint32 BMMCR1;                 /* 0x00C4 */
+    uint32 BMMCR2;                 /* 0x00C8 */
+    uint32 CPURSTCR;               /* 0x00CC */
+	uint32 CLKCNTL;                /* 0x00D0 */
+    uint32 ECPCNTL;                /* 0x00D4 */
+    uint32 DSPGCR;                 /* 0x00D8 */
+    uint32 DEVCR1;                 /* 0x00DC */
+    uint32 SYSECR;                 /* 0x00E0 */
+    uint32 SYSESR;                 /* 0x00E4 */
+    uint32 SYSTASR;                /* 0x00E8 */
+    uint32 GBLSTAT;                /* 0x00EC */
+    uint32 DEV;                    /* 0x00F0 */
+    uint32 SSIVEC;                 /* 0x00F4 */
+    uint32 SSIF;                   /* 0x00F8 */
+} systemBASE1_t;
+
+typedef volatile struct systemBase2
+{
+    uint32 PLLCTL3;        /* 0x0000 */
+    uint32   rsvd1;        /* 0x0004 */
+    uint32 STCCLKDIV;      /* 0x0008 */
+    uint32   rsvd2[6U];     /* 0x000C */
+    uint32 ECPCNTRL0;      /* 0x0024 */
+    uint32   rsvd3[5U];     /* 0x0028 */
+    uint32 CLK2CNTL;       /* 0x003C */
+    uint32 VCLKACON1;      /* 0x0040 */
+    uint32  rsvd4[11U];     /* 0x0044 */
+    uint32  CLKSLIP;       /* 0x0070 */
+    uint32  rsvd5[30U];   	 /* 0x0074 */
+    uint32  EFC_CTLEN;     /* 0x00EC */
+    uint32  DIEIDL_REG0;   /* 0x00F0 */
+    uint32  DIEIDH_REG1;   /* 0x00F4 */
+    uint32  DIEIDL_REG2;   /* 0x00F8 */
+    uint32  DIEIDH_REG3;   /* 0x00FC */
+} systemBASE2_t;
+
+typedef volatile struct esmBase
+{
+    uint32 EEPAPR1;           /* 0x0000                 */
+    uint32 DEPAPR1;           /* 0x0004                 */
+    uint32 IESR1;             /* 0x0008                 */
+    uint32 IECR1;             /* 0x000C                 */
+    uint32 ILSR1;             /* 0x0010                 */
+    uint32 ILCR1;             /* 0x0014                 */
+    uint32 SR1[3U];           /* 0x0018, 0x001C, 0x0020 */
+    uint32 EPSR;              /* 0x0024                 */
+    uint32 IOFFHR;            /* 0x0028                 */
+    uint32 IOFFLR;            /* 0x002C                 */
+    uint32 LTCR;              /* 0x0030                 */
+    uint32 LTCPR;             /* 0x0034                 */
+    uint32 EKR;               /* 0x0038                 */
+    uint32 SSR2;              /* 0x003C                 */
+    uint32 IEPSR4;            /* 0x0040                 */
+    uint32 IEPCR4;            /* 0x0044                 */
+    uint32 IESR4;             /* 0x0048                 */
+    uint32 IECR4;             /* 0x004C                 */
+    uint32 ILSR4;             /* 0x0050                 */
+    uint32 ILCR4;             /* 0x0054                 */
+    uint32 SR4[3U];           /* 0x0058, 0x005C, 0x0060 */
+} esmBASE_t;
+
+typedef volatile struct dccBase
+{
+    uint32 GCTRL;      	    /**< 0x0000: DCC Control Register		*/
+    uint32 REV;      		/**< 0x0004: DCC Revision Id Register 	*/
+    uint32 CNT0SEED;    	/**< 0x0008: DCC Counter0 Seed Register	*/
+    uint32 VALID0SEED;      /**< 0x000C: DCC Valid0 Seed Register 	*/
+    uint32 CNT1SEED;		/**< 0x0010: DCC Counter1 Seed Register 	*/
+    uint32 STAT; 			/**< 0x0014: DCC Status Register 		*/
+    uint32 CNT0;    		/**< 0x0018: DCC Counter0 Value Register 	*/
+    uint32 VALID0;    	    /**< 0x001C: DCC Valid0 Value Register 	*/
+    uint32 CNT1;      	    /**< 0x0020: DCC Counter1 Value Register	*/
+    uint32 CNT1CLKSRC;   	/**< 0x0024: DCC Counter1 Clock Source Selection Register 	*/
+    uint32 CNT0CLKSRC;   	/**< 0x0028: DCC Counter0 Clock Source Selection Register 	*/
+} dccBASE_t;
+
+enum dcc1clocksource
+{
+    DCC1_CNT0_HF_LPO    = 0x5U,    /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
+    DCC1_CNT0_TCK       = 0xAU,    /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/
+    DCC1_CNT0_OSCIN     = 0xFU,    /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
+
+    DCC1_CNT1_PLL1      = 0x0U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/
+    DCC1_CNT1_PLL2      = 0x1U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/
+    DCC1_CNT1_LF_LPO    = 0x2U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/
+    DCC1_CNT1_HF_LPO    = 0x3U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/
+    DCC1_CNT1_EXTCLKIN1 = 0x5U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/
+    DCC1_CNT1_EXTCLKIN2 = 0x6U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/
+    DCC1_CNT1_VCLK      = 0x8U,    /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
+    DCC1_CNT1_N2HET1_31 = 0xAU     /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
+};
+
+#define SYS_CLKSRC_PLL1 0x00000002U
+#define SYS_CLKSRC_PLL2 0x00000040U
+#define SYS_CLKCNTRL_PENA 0x00000100U
+#define ESM_SR1_PLL1SLIP 0x400U
+#define ESM_SR4_PLL2SLIP 0x400U
+#define PLL1 0x08
+#define PLL2 0x80
+#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U
+#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U
+
+#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)
+#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)
+#define esmREG ((esmBASE_t *)0xFFFFF500U)
+#define dccREG1   ((dccBASE_t *)0xFFFFEC00U)
+
+
+#endif /* INCLUDE_ERRATA_SSWF021_45_DEFS_H_ */
diff --git a/include/arch/rm46l8lp/halcogen/esm.h b/include/arch/rm46l8lp/halcogen/esm.h
new file mode 100644
index 0000000..8c29e8a
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/esm.h
@@ -0,0 +1,956 @@
+/** @file esm.h
+*   @brief Error Signaling Module Driver Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the Esm driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __ESM_H__
+#define __ESM_H__
+
+#include "reg_esm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* ESM General Definitions */
+
+/** @def esmGROUP1
+*   @brief Alias name for ESM group 1
+*
+*   This is an alias name for the ESM group 1.
+*
+*   @note This value should be used for API argument @a group
+*/
+#define esmGROUP1 0U
+
+/** @def esmGROUP2
+*   @brief Alias name for ESM group 2
+*
+*   This is an alias name for the ESM group 2.
+*
+*   @note This value should be used for API argument @a group
+*/
+#define esmGROUP2 1U
+
+/** @def esmGROUP3
+*   @brief Alias name for ESM group 3
+*
+*   This is an alias name for the ESM group 3.
+*
+*   @note This value should be used for API argument @a group
+*/
+#define esmGROUP3 2U
+
+/** @def esmCHANNEL0
+*   @brief Alias name for ESM group x channel 0
+*
+*   This is an alias name for the ESM group x channel 0.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL0 0x0000000000000001ULL
+
+/** @def esmCHANNEL1
+*   @brief Alias name for ESM group x channel 1
+*
+*   This is an alias name for the ESM group x channel 1.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL1 0x0000000000000002ULL
+
+/** @def esmCHANNEL2
+*   @brief Alias name for ESM group x channel 2
+*
+*   This is an alias name for the ESM group x channel 2.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL2 0x0000000000000004ULL
+
+/** @def esmCHANNEL3
+*   @brief Alias name for ESM group x channel 3
+*
+*   This is an alias name for the ESM group x channel 3.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL3 0x0000000000000008ULL
+
+/** @def esmCHANNEL4
+*   @brief Alias name for ESM group x channel 4
+*
+*   This is an alias name for the ESM group x channel 4.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL4 0x0000000000000010ULL
+
+/** @def esmCHANNEL5
+*   @brief Alias name for ESM group x channel 5
+*
+*   This is an alias name for the ESM group x channel 5.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL5 0x0000000000000020ULL
+
+/** @def esmCHANNEL6
+*   @brief Alias name for ESM group x channel 6
+*
+*   This is an alias name for the ESM group x channel 6.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL6 0x0000000000000040ULL
+
+/** @def esmCHANNEL7
+*   @brief Alias name for ESM group x channel 7
+*
+*   This is an alias name for the ESM group x channel 7.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL7 0x0000000000000080ULL
+
+/** @def esmCHANNEL8
+*   @brief Alias name for ESM group x channel 8
+*
+*   This is an alias name for the ESM group x channel 8.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL8 0x0000000000000100ULL
+
+/** @def esmCHANNEL9
+*   @brief Alias name for ESM group x channel 9
+*
+*   This is an alias name for the ESM group x channel 9.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL9 0x0000000000000200ULL
+
+/** @def esmCHANNEL10
+*   @brief Alias name for ESM group x channel 10
+*
+*   This is an alias name for the ESM group x channel 10.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL10 0x0000000000000400ULL
+
+/** @def esmCHANNEL11
+*   @brief Alias name for ESM group x channel 11
+*
+*   This is an alias name for the ESM group x channel 11.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL11 0x0000000000000800ULL
+
+/** @def esmCHANNEL12
+*   @brief Alias name for ESM group x channel 12
+*
+*   This is an alias name for the ESM group x channel 12.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL12 0x0000000000001000ULL
+
+/** @def esmCHANNEL13
+*   @brief Alias name for ESM group x channel 13
+*
+*   This is an alias name for the ESM group x channel 13.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL13 0x0000000000002000ULL
+
+/** @def esmCHANNEL14
+*   @brief Alias name for ESM group x channel 14
+*
+*   This is an alias name for the ESM group x channel 14.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL14 0x0000000000004000ULL
+
+/** @def esmCHANNEL15
+*   @brief Alias name for ESM group x channel 15
+*
+*   This is an alias name for the ESM group x channel 15.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL15 0x0000000000008000ULL
+
+/** @def esmCHANNEL16
+*   @brief Alias name for ESM group x channel 16
+*
+*   This is an alias name for the ESM group x channel 16.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL16 0x0000000000010000ULL
+
+/** @def esmCHANNEL17
+*   @brief Alias name for ESM group x channel 17
+*
+*   This is an alias name for the ESM group x channel 17.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL17 0x0000000000020000ULL
+
+/** @def esmCHANNEL18
+*   @brief Alias name for ESM group x channel 18
+*
+*   This is an alias name for the ESM group x channel 18.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL18 0x0000000000040000ULL
+
+/** @def esmCHANNEL19
+*   @brief Alias name for ESM group x channel 19
+*
+*   This is an alias name for the ESM group x channel 19.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL19 0x0000000000080000ULL
+
+/** @def esmCHANNEL20
+*   @brief Alias name for ESM group x channel 20
+*
+*   This is an alias name for the ESM group x channel 20.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL20 0x0000000000100000ULL
+
+/** @def esmCHANNEL21
+*   @brief Alias name for ESM group x channel 21
+*
+*   This is an alias name for the ESM group x channel 21.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL21 0x0000000000200000ULL
+
+/** @def esmCHANNEL22
+*   @brief Alias name for ESM group x channel 22
+*
+*   This is an alias name for the ESM group x channel 22.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL22 0x0000000000400000ULL
+
+/** @def esmCHANNEL23
+*   @brief Alias name for ESM group x channel 23
+*
+*   This is an alias name for the ESM group x channel 23.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL23 0x0000000000800000ULL
+
+/** @def esmCHANNEL24
+*   @brief Alias name for ESM group x channel 24
+*
+*   This is an alias name for the ESM group x channel 24.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL24 0x0000000001000000ULL
+
+/** @def esmCHANNEL25
+*   @brief Alias name for ESM group x channel 25
+*
+*   This is an alias name for the ESM group x channel 25.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL25 0x0000000002000000ULL
+
+/** @def esmCHANNEL26
+*   @brief Alias name for ESM group x channel 26
+*
+*   This is an alias name for the ESM group x channel 26.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL26 0x0000000004000000ULL
+
+/** @def esmCHANNEL27
+*   @brief Alias name for ESM group x channel 27
+*
+*   This is an alias name for the ESM group x channel 27.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL27 0x0000000008000000ULL
+
+/** @def esmCHANNEL28
+*   @brief Alias name for ESM group x channel 28
+*
+*   This is an alias name for the ESM group x channel 28.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL28 0x0000000010000000ULL
+
+/** @def esmCHANNEL29
+*   @brief Alias name for ESM group x channel 29
+*
+*   This is an alias name for the ESM group x channel 29.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL29 0x0000000020000000ULL
+
+/** @def esmCHANNEL30
+*   @brief Alias name for ESM group x channel 30
+*
+*   This is an alias name for the ESM group x channel 30.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL30 0x0000000040000000ULL
+
+/** @def esmCHANNEL31
+*   @brief Alias name for ESM group x channel 31
+*
+*   This is an alias name for the ESM group x channel 31.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL31 0x0000000080000000ULL
+
+/** @def esmCHANNEL32
+*   @brief Alias name for ESM group x channel 32
+*
+*   This is an alias name for the ESM group x channel 32.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL32 0x0000000100000000ULL
+
+/** @def esmCHANNEL33
+*   @brief Alias name for ESM group x channel 33
+*
+*   This is an alias name for the ESM group x channel 33.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL33 0x0000000200000000ULL
+
+/** @def esmCHANNEL34
+*   @brief Alias name for ESM group x channel 34
+*
+*   This is an alias name for the ESM group x channel 34.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL34 0x0000000400000000ULL
+
+/** @def esmCHANNEL35
+*   @brief Alias name for ESM group x channel 35
+*
+*   This is an alias name for the ESM group x channel 35.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL35 0x0000000800000000ULL
+
+/** @def esmCHANNEL36
+*   @brief Alias name for ESM group x channel 36
+*
+*   This is an alias name for the ESM group x channel 36.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL36 0x0000001000000000ULL
+
+/** @def esmCHANNEL37
+*   @brief Alias name for ESM group x channel 37
+*
+*   This is an alias name for the ESM group x channel 37.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL37 0x0000002000000000ULL
+
+/** @def esmCHANNEL38
+*   @brief Alias name for ESM group x channel 38
+*
+*   This is an alias name for the ESM group x channel 38.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL38 0x0000004000000000ULL
+
+/** @def esmCHANNEL39
+*   @brief Alias name for ESM group x channel 39
+*
+*   This is an alias name for the ESM group x channel 39.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL39 0x0000008000000000ULL
+
+/** @def esmCHANNEL40
+*   @brief Alias name for ESM group x channel 40
+*
+*   This is an alias name for the ESM group x channel 40.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL40 0x0000010000000000ULL
+
+/** @def esmCHANNEL41
+*   @brief Alias name for ESM group x channel 41
+*
+*   This is an alias name for the ESM group x channel 41.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL41 0x0000020000000000ULL
+
+/** @def esmCHANNEL42
+*   @brief Alias name for ESM group x channel 42
+*
+*   This is an alias name for the ESM group x channel 42.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL42 0x0000040000000000ULL
+
+/** @def esmCHANNEL43
+*   @brief Alias name for ESM group x channel 43
+*
+*   This is an alias name for the ESM group x channel 43.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL43 0x0000080000000000ULL
+
+/** @def esmCHANNEL44
+*   @brief Alias name for ESM group x channel 44
+*
+*   This is an alias name for the ESM group x channel 44.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL44 0x0000100000000000ULL
+
+/** @def esmCHANNEL45
+*   @brief Alias name for ESM group x channel 45
+*
+*   This is an alias name for the ESM group x channel 45.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL45 0x0000200000000000ULL
+
+/** @def esmCHANNEL46
+*   @brief Alias name for ESM group x channel 46
+*
+*   This is an alias name for the ESM group x channel 46.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL46 0x0000400000000000ULL
+
+/** @def esmCHANNEL47
+*   @brief Alias name for ESM group x channel 47
+*
+*   This is an alias name for the ESM group x channel 47.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL47 0x0000800000000000ULL
+
+/** @def esmCHANNEL48
+*   @brief Alias name for ESM group x channel 48
+*
+*   This is an alias name for the ESM group x channel 48.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL48 0x0001000000000000ULL
+
+/** @def esmCHANNEL49
+*   @brief Alias name for ESM group x channel 49
+*
+*   This is an alias name for the ESM group x channel 49.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL49 0x0002000000000000ULL
+
+/** @def esmCHANNEL50
+*   @brief Alias name for ESM group x channel 50
+*
+*   This is an alias name for the ESM group x channel 50.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL50 0x0004000000000000ULL
+
+/** @def esmCHANNEL51
+*   @brief Alias name for ESM group x channel 51
+*
+*   This is an alias name for the ESM group x channel 51.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL51 0x0008000000000000ULL
+
+/** @def esmCHANNEL52
+*   @brief Alias name for ESM group x channel 52
+*
+*   This is an alias name for the ESM group x channel 52.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL52 0x0010000000000000ULL
+
+/** @def esmCHANNEL53
+*   @brief Alias name for ESM group x channel 53
+*
+*   This is an alias name for the ESM group x channel 53.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL53 0x0020000000000000ULL
+
+/** @def esmCHANNEL54
+*   @brief Alias name for ESM group x channel 54
+*
+*   This is an alias name for the ESM group x channel 54.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL54 0x0040000000000000ULL
+
+/** @def esmCHANNEL55
+*   @brief Alias name for ESM group x channel 55
+*
+*   This is an alias name for the ESM group x channel 55.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL55 0x0080000000000000ULL
+
+/** @def esmCHANNEL56
+*   @brief Alias name for ESM group x channel 56
+*
+*   This is an alias name for the ESM group x channel 56.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL56 0x0100000000000000ULL
+
+/** @def esmCHANNEL57
+*   @brief Alias name for ESM group x channel 57
+*
+*   This is an alias name for the ESM group x channel 57.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL57 0x0200000000000000ULL
+
+/** @def esmCHANNEL58
+*   @brief Alias name for ESM group x channel 58
+*
+*   This is an alias name for the ESM group x channel 58.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL58 0x0400000000000000ULL
+
+/** @def esmCHANNEL59
+*   @brief Alias name for ESM group x channel 59
+*
+*   This is an alias name for the ESM group x channel 59.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL59 0x0800000000000000ULL
+
+/** @def esmCHANNEL60
+*   @brief Alias name for ESM group x channel 60
+*
+*   This is an alias name for the ESM group x channel 60.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL60 0x1000000000000000ULL
+
+/** @def esmCHANNEL61
+*   @brief Alias name for ESM group x channel 61
+*
+*   This is an alias name for the ESM group x channel 61.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL61 0x2000000000000000ULL
+
+/** @def esmCHANNEL62
+*   @brief Alias name for ESM group x channel 62
+*
+*   This is an alias name for the ESM group x channel 62.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL62 0x4000000000000000ULL
+
+/** @def esmCHANNEL63
+*   @brief Alias name for ESM group x channel 63
+*
+*   This is an alias name for the ESM group x channel 63.
+*
+*   @note This value should be used for API argument @a channel
+*/
+#define esmCHANNEL63 0x8000000000000000ULL
+
+/** @typedef esmSelfTestFlag_t
+*   @brief ESM Self-Test Status Type Definition
+*
+*   This type is used to represent ESM Self-Test Status.
+*/
+typedef enum esmSelfTestFlag 
+{
+    esmSelfTest_Passed = 0U,
+	esmSelfTest_Active = 1U,
+	esmSelfTest_NotStarted = 2U,
+    esmSelfTest_Failed = 3U
+}esmSelfTestFlag_t;
+
+/* Configuration registers */
+typedef struct esm_config_reg
+{
+    uint32 CONFIG_EEPAPR1;
+    uint32 CONFIG_IESR1;
+    uint32 CONFIG_ILSR1;
+    uint32 CONFIG_LTCPR;
+	uint32 CONFIG_EKR;  
+    uint32 CONFIG_IEPSR4;
+    uint32 CONFIG_IESR4;
+    uint32 CONFIG_ILSR4;
+} esm_config_reg_t;
+
+/* Configuration registers initial value */
+#define ESM_EEPAPR1_CONFIGVALUE	((uint32)((uint32)1U << 31U)\
+                               | (uint32)((uint32)0U << 30U)\
+                               | (uint32)((uint32)0U << 29U)\
+                               | (uint32)((uint32)0U << 28U)\
+                               | (uint32)((uint32)0U << 27U)\
+                               | (uint32)((uint32)0U << 26U)\
+                               | (uint32)((uint32)0U << 25U)\
+                               | (uint32)((uint32)0U << 24U)\
+                               | (uint32)((uint32)0U << 23U)\
+                               | (uint32)((uint32)0U << 22U)\
+                               | (uint32)((uint32)0U << 21U)\
+                               | (uint32)((uint32)0U << 20U)\
+                               | (uint32)((uint32)0U << 19U)\
+                               | (uint32)((uint32)0U << 18U)\
+                               | (uint32)((uint32)0U << 17U)\
+                               | (uint32)((uint32)0U << 16U)\
+                               | (uint32)((uint32)0U << 15U)\
+                               | (uint32)((uint32)0U << 14U)\
+                               | (uint32)((uint32)0U << 13U)\
+                               | (uint32)((uint32)0U << 12U)\
+                               | (uint32)((uint32)1U << 11U)\
+                               | (uint32)((uint32)1U << 10U)\
+                               | (uint32)((uint32)0U <<  9U)\
+                               | (uint32)((uint32)0U <<  8U)\
+                               | (uint32)((uint32)0U <<  7U)\
+                               | (uint32)((uint32)0U <<  6U)\
+                               | (uint32)((uint32)0U <<  5U)\
+                               | (uint32)((uint32)0U <<  4U)\
+                               | (uint32)((uint32)0U <<  3U)\
+                               | (uint32)((uint32)0U <<  2U)\
+                               | (uint32)((uint32)0U <<  1U)\
+                               | (uint32)((uint32)0U <<  0U))
+#define ESM_IESR1_CONFIGVALUE	((uint32)((uint32)1U << 31U)\
+                               | (uint32)((uint32)0U << 30U)\
+                               | (uint32)((uint32)0U << 29U)\
+                               | (uint32)((uint32)1U << 28U)\
+                               | (uint32)((uint32)1U << 27U)\
+                               | (uint32)((uint32)1U << 26U)\
+                               | (uint32)((uint32)0U << 25U)\
+                               | (uint32)((uint32)0U << 24U)\
+                               | (uint32)((uint32)0U << 23U)\
+                               | (uint32)((uint32)0U << 22U)\
+                               | (uint32)((uint32)0U << 21U)\
+                               | (uint32)((uint32)0U << 20U)\
+                               | (uint32)((uint32)0U << 19U)\
+                               | (uint32)((uint32)0U << 18U)\
+                               | (uint32)((uint32)0U << 17U)\
+                               | (uint32)((uint32)0U << 16U)\
+                               | (uint32)((uint32)0U << 15U)\
+                               | (uint32)((uint32)0U << 14U)\
+                               | (uint32)((uint32)0U << 13U)\
+                               | (uint32)((uint32)0U << 12U)\
+                               | (uint32)((uint32)1U << 11U)\
+                               | (uint32)((uint32)1U << 10U)\
+                               | (uint32)((uint32)0U <<  9U)\
+                               | (uint32)((uint32)0U <<  8U)\
+                               | (uint32)((uint32)0U <<  7U)\
+                               | (uint32)((uint32)1U <<  6U)\
+                               | (uint32)((uint32)0U <<  5U)\
+                               | (uint32)((uint32)0U <<  4U)\
+                               | (uint32)((uint32)0U <<  3U)\
+                               | (uint32)((uint32)0U <<  2U)\
+                               | (uint32)((uint32)0U <<  1U)\
+                               | (uint32)((uint32)0U <<  0U))
+#define ESM_ILSR1_CONFIGVALUE   ((uint32)((uint32)0U << 31U)\
+                               | (uint32)((uint32)0U << 30U)\
+                               | (uint32)((uint32)0U << 29U)\
+                               | (uint32)((uint32)0U << 28U)\
+                               | (uint32)((uint32)0U << 27U)\
+                               | (uint32)((uint32)0U << 26U)\
+                               | (uint32)((uint32)0U << 25U)\
+                               | (uint32)((uint32)0U << 24U)\
+                               | (uint32)((uint32)0U << 23U)\
+                               | (uint32)((uint32)0U << 22U)\
+                               | (uint32)((uint32)0U << 21U)\
+                               | (uint32)((uint32)0U << 20U)\
+                               | (uint32)((uint32)0U << 19U)\
+                               | (uint32)((uint32)0U << 18U)\
+                               | (uint32)((uint32)0U << 17U)\
+                               | (uint32)((uint32)0U << 16U)\
+                               | (uint32)((uint32)0U << 15U)\
+                               | (uint32)((uint32)0U << 14U)\
+                               | (uint32)((uint32)0U << 13U)\
+                               | (uint32)((uint32)0U << 12U)\
+                               | (uint32)((uint32)0U << 11U)\
+                               | (uint32)((uint32)0U << 10U)\
+                               | (uint32)((uint32)0U <<  9U)\
+                               | (uint32)((uint32)0U <<  8U)\
+                               | (uint32)((uint32)0U <<  7U)\
+                               | (uint32)((uint32)0U <<  6U)\
+                               | (uint32)((uint32)0U <<  5U)\
+                               | (uint32)((uint32)0U <<  4U)\
+                               | (uint32)((uint32)0U <<  3U)\
+                               | (uint32)((uint32)0U <<  2U)\
+                               | (uint32)((uint32)0U <<  1U)\
+                               | (uint32)((uint32)0U <<  0U))
+#define ESM_LTCPR_CONFIGVALUE	 (16384U - 1U)
+#define ESM_EKR_CONFIGVALUE      0U
+#define ESM_IEPSR4_CONFIGVALUE ((uint32)((uint32)0U << 31U)\
+                              | (uint32)((uint32)0U << 30U)\
+                              | (uint32)((uint32)0U << 29U)\
+                              | (uint32)((uint32)0U << 28U)\
+                              | (uint32)((uint32)0U << 27U)\
+                              | (uint32)((uint32)0U << 26U)\
+                              | (uint32)((uint32)0U << 25U)\
+                              | (uint32)((uint32)0U << 24U)\
+                              | (uint32)((uint32)0U << 23U)\
+                              | (uint32)((uint32)0U << 22U)\
+                              | (uint32)((uint32)0U << 21U)\
+                              | (uint32)((uint32)0U << 20U)\
+                              | (uint32)((uint32)0U << 19U)\
+                              | (uint32)((uint32)0U << 18U)\
+                              | (uint32)((uint32)0U << 17U)\
+                              | (uint32)((uint32)0U << 16U)\
+                              | (uint32)((uint32)0U << 15U)\
+                              | (uint32)((uint32)0U << 14U)\
+                              | (uint32)((uint32)0U << 13U)\
+                              | (uint32)((uint32)0U << 12U)\
+                              | (uint32)((uint32)0U << 11U)\
+                              | (uint32)((uint32)0U << 10U)\
+                              | (uint32)((uint32)0U <<  9U)\
+                              | (uint32)((uint32)0U <<  8U)\
+                              | (uint32)((uint32)0U <<  7U)\
+                              | (uint32)((uint32)0U <<  6U)\
+                              | (uint32)((uint32)0U <<  5U)\
+                              | (uint32)((uint32)0U <<  4U)\
+                              | (uint32)((uint32)0U <<  3U)\
+                              | (uint32)((uint32)0U <<  2U)\
+                              | (uint32)((uint32)0U <<  1U)\
+                              | (uint32)((uint32)0U <<  0U))
+#define ESM_IESR4_CONFIGVALUE ((uint32)((uint32)0U << 31U)\
+                             | (uint32)((uint32)0U << 30U)\
+                             | (uint32)((uint32)0U << 29U)\
+                             | (uint32)((uint32)0U << 28U)\
+                             | (uint32)((uint32)0U << 27U)\
+                             | (uint32)((uint32)0U << 26U)\
+                             | (uint32)((uint32)0U << 25U)\
+                             | (uint32)((uint32)0U << 24U)\
+                             | (uint32)((uint32)0U << 23U)\
+                             | (uint32)((uint32)0U << 22U)\
+                             | (uint32)((uint32)0U << 21U)\
+                             | (uint32)((uint32)0U << 20U)\
+                             | (uint32)((uint32)0U << 19U)\
+                             | (uint32)((uint32)0U << 18U)\
+                             | (uint32)((uint32)0U << 17U)\
+                             | (uint32)((uint32)0U << 16U)\
+                             | (uint32)((uint32)0U << 15U)\
+                             | (uint32)((uint32)0U << 14U)\
+                             | (uint32)((uint32)0U << 13U)\
+                             | (uint32)((uint32)0U << 12U)\
+                             | (uint32)((uint32)0U << 11U)\
+                             | (uint32)((uint32)1U << 10U)\
+                             | (uint32)((uint32)1U <<  9U)\
+                             | (uint32)((uint32)1U <<  8U)\
+                             | (uint32)((uint32)0U <<  7U)\
+                             | (uint32)((uint32)0U <<  6U)\
+                             | (uint32)((uint32)0U <<  5U)\
+                             | (uint32)((uint32)0U <<  4U)\
+                             | (uint32)((uint32)0U <<  3U)\
+                             | (uint32)((uint32)0U <<  2U)\
+                             | (uint32)((uint32)0U <<  1U)\
+                             | (uint32)((uint32)0U <<  0U))
+#define ESM_ILSR4_CONFIGVALUE ((uint32)((uint32)0U << 31U)\
+                             | (uint32)((uint32)0U << 30U)\
+                             | (uint32)((uint32)0U << 29U)\
+                             | (uint32)((uint32)0U << 28U)\
+                             | (uint32)((uint32)0U << 27U)\
+                             | (uint32)((uint32)0U << 26U)\
+                             | (uint32)((uint32)0U << 25U)\
+                             | (uint32)((uint32)0U << 24U)\
+                             | (uint32)((uint32)0U << 23U)\
+                             | (uint32)((uint32)0U << 22U)\
+                             | (uint32)((uint32)0U << 21U)\
+                             | (uint32)((uint32)0U << 20U)\
+                             | (uint32)((uint32)0U << 19U)\
+                             | (uint32)((uint32)0U << 18U)\
+                             | (uint32)((uint32)0U << 17U)\
+                             | (uint32)((uint32)0U << 16U)\
+                             | (uint32)((uint32)0U << 15U)\
+                             | (uint32)((uint32)0U << 14U)\
+                             | (uint32)((uint32)0U << 13U)\
+                             | (uint32)((uint32)0U << 12U)\
+                             | (uint32)((uint32)0U << 11U)\
+                             | (uint32)((uint32)0U << 10U)\
+                             | (uint32)((uint32)0U <<  9U)\
+                             | (uint32)((uint32)0U <<  8U)\
+                             | (uint32)((uint32)0U <<  7U)\
+                             | (uint32)((uint32)0U <<  6U)\
+                             | (uint32)((uint32)0U <<  5U)\
+                             | (uint32)((uint32)0U <<  4U)\
+                             | (uint32)((uint32)0U <<  3U)\
+                             | (uint32)((uint32)0U <<  2U)\
+                             | (uint32)((uint32)0U <<  1U)\
+                             | (uint32)((uint32)0U <<  0U))
+
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** 
+ *  @defgroup ESM ESM
+ *  @brief Error Signaling Module.
+ *  
+ *  The ESM module aggregates device errors and provides internal and external error response based on error severity.
+ *
+ *	Related Files
+ *   - reg_esm.h
+ *   - esm.h
+ *   - esm.c
+ *  @addtogroup ESM
+ *  @{
+ */
+ 
+/* Esm Interface Functions */
+void   esmInit(void);
+uint32 esmError(void);
+void   esmEnableError(uint64 channels);
+void   esmDisableError(uint64 channels);
+void   esmTriggerErrorPinReset(void);
+void   esmActivateNormalOperation(void);
+void   esmEnableInterrupt(uint64 channels);
+void   esmDisableInterrupt(uint64 channels);
+void   esmSetInterruptLevel(uint64 channels, uint64 flags);
+void   esmClearStatus(uint32 group, uint64 channels);
+void   esmClearStatusBuffer(uint64 channels);
+void   esmSetCounterPreloadValue(uint32 value);
+
+uint64 esmGetStatus(uint32 group, uint64 channels);
+uint64 esmGetStatusBuffer(uint64 channels);
+
+esmSelfTestFlag_t esmEnterSelfTest(void);
+esmSelfTestFlag_t esmSelfTestStatus(void);
+
+
+void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type);
+/** @fn void esmGroup1Notification(uint32 channel)
+*   @brief Interrupt callback
+*   @param[in] channel - Group 1 channel
+*
+*   This is a callback that is provided by the application and is called upon
+*   an interrupt. The parameter passed to the callback is group 1 channel caused the interrupt.
+*   @note Callback parameter channel is not a masked value. Do not use the macros esmCHANNELx for comparison.
+*/
+void esmGroup1Notification(uint32 channel);
+
+
+/** @fn void esmGroup2Notification(uint32 channel)
+*   @brief Interrupt callback
+*   @param[in] channel - Group 2 channel
+*
+*   This is a callback that is provided by the application and is called upon
+*   an interrupt. The parameter passed to the callback is group 2 channel caused the interrupt.
+*   @note Callback parameter channel is not a masked value. Do not use the macros esmCHANNELx for comparison.
+*/
+void esmGroup2Notification(uint32 channel);
+
+/**@}*/
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/etpwm.h b/include/arch/rm46l8lp/halcogen/etpwm.h
new file mode 100644
index 0000000..bdbbe85
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/etpwm.h
@@ -0,0 +1,744 @@
+/** @file etpwm.h
+*   @brief ETPWM Driver Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __ETPWM_H__
+#define __ETPWM_H__
+
+#include "reg_etpwm.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+#define COUNT_UP     (1U << 13U)
+#define COUNT_DOWN    0U
+
+/** @brief Enumeration to define the pulse width modulation (ETPWM) clock divider
+*   TBCLK = VCLK4 / (HSPCLKDIV � CLKDIV)
+*/
+typedef enum
+{
+    ClkDiv_by_1   = ((uint16)0U << 10U), /** CLKDIV = 1   */
+    ClkDiv_by_2   = ((uint16)1U << 10U), /** CLKDIV = 2   */
+    ClkDiv_by_4   = ((uint16)2U << 10U), /** CLKDIV = 4   */
+    ClkDiv_by_8   = ((uint16)3U << 10U), /** CLKDIV = 8   */
+    ClkDiv_by_16  = ((uint16)4U << 10U), /** CLKDIV = 16  */
+    ClkDiv_by_32  = ((uint16)5U << 10U), /** CLKDIV = 32  */
+    ClkDiv_by_64  = ((uint16)6U << 10U), /** CLKDIV = 64  */
+    ClkDiv_by_128 = ((uint16)7U << 10U)  /** CLKDIV = 128 */
+} etpwmClkDiv_t;
+
+/** @brief Enumeration to define the pulse width modulation (ETPWM) high speed clock divider
+*   TBCLK = VCLK4 / (HSPCLKDIV � CLKDIV)
+*/
+typedef enum
+{
+    HspClkDiv_by_1  = ((uint16)0U << 7U), /** HSPCLKDIV = 1   */
+    HspClkDiv_by_2  = ((uint16)1U << 7U), /** HSPCLKDIV = 2   */
+    HspClkDiv_by_4  = ((uint16)2U << 7U), /** HSPCLKDIV = 4   */
+    HspClkDiv_by_6  = ((uint16)3U << 7U), /** HSPCLKDIV = 8   */
+    HspClkDiv_by_8  = ((uint16)4U << 7U), /** HSPCLKDIV = 16  */
+    HspClkDiv_by_10 = ((uint16)5U << 7U), /** HSPCLKDIV = 32  */
+    HspClkDiv_by_12 = ((uint16)6U << 7U), /** HSPCLKDIV = 64  */
+    HspClkDiv_by_14 = ((uint16)7U << 7U)  /** HSPCLKDIV = 128 */
+} etpwmHspClkDiv_t;
+
+/** @brief Enumeration to select the source of Synchronization Output signal (EPWMxSYNCO)
+*/
+typedef enum
+{
+    SyncOut_EPWMxSYNCI = 0x00U, /** EPWMxSYNCI                */
+    SyncOut_CtrEqZero  = 0x10U, /** CTR = zero                */
+    SyncOut_CtrEqCmpB  = 0x20U, /** CTR = CMPB                */
+    SyncOut_Disable    = 0x30U  /** Disable EPWMxSYNCO signal */
+} etpwmSyncOut_t;
+
+/** @brief Enumeration to define the pulse width modulation (ETPWM) counter modes
+*/
+typedef enum
+{
+    CounterMode_Up     = 0U, /** Up-count mode                  */
+    Countermode_Down   = 1U, /** Down-count mode                */
+    CounterMode_UpDown = 2U, /** Up-down-count mode             */
+    CounterMode_Stop   = 3U  /** Stop - freeze counter operaton */
+} etpwmCounterMode_t;
+
+/** @brief Enumeration to the behavior of the ePWM time-base counter during emulation events
+*/
+typedef enum
+{
+    RunMode_SoftStopAfterIncr  = ((uint16)0U << 14U), /** Stop after the next time-base counter increment */
+    RunMode_SoftStopAfterDecr  = ((uint16)0U << 14U), /** Stop after the next time-base counter decrement */
+    RunMode_SoftStopAfterCycle = ((uint16)1U << 14U), /** Stop when counter completes a whole cycle       */
+    RunMode_FreeRun            = ((uint16)2U << 14U)  /** Free run                                        */
+} etpwmRunMode_t;
+
+/** @brief Enumeration to define the pulse width modulation (ETPWM) load modes
+*/
+typedef enum
+{                                                                      
+    LoadMode_CtrEqZero       = 0U, /** Load on CTR = Zero              */
+    LoadMode_CtrEqPeriod     = 1U, /** Load on CTR = PRD               */
+    LoadMode_CtrEqZeroPeriod = 2U, /** Load on CTR = Zero or CTR = PRD */
+    LoadMode_Freeze          = 3U  /** Freeze (no loads possible)      */
+} etpwmLoadMode_t;
+
+/** @brief Enumeration to define the pulse width modulation (ETPWM) trip zone sources
+*/
+typedef enum
+{
+    CycleByCycle_TZ1     = ((uint16)1U << 0U),
+    CycleByCycle_TZ2     = ((uint16)1U << 1U),
+    CycleByCycle_TZ3     = ((uint16)1U << 2U),
+    CycleByCycle_TZ4     = ((uint16)1U << 3U),
+    CycleByCycle_TZ5     = ((uint16)1U << 4U),
+    CycleByCycle_TZ6     = ((uint16)1U << 5U),
+    CycleByCycle_DCAEVT2 = ((uint16)1U << 6U),
+    CycleByCycle_DCBEVT2 = ((uint16)1U << 7U),
+    OneShot_TZ1          = ((uint16)1U << 8U),
+    OneShot_TZ2          = ((uint16)1U << 9U),
+    OneShot_TZ3          = ((uint16)1U << 10U),
+    OneShot_TZ4          = ((uint16)1U << 11U),
+    OneShot_TZ5          = ((uint16)1U << 12U),
+    OneShot_TZ6          = ((uint16)1U << 13U),
+    OneShot_DCAEVT1      = ((uint16)1U << 14U),
+    OneShot_DCBEVT1      = ((uint16)1U << 15U)
+} etpwmTripZoneSrc_t;
+
+/** @brief Enumeration to define the pulse width modulation (ETPWM) trip events
+*/
+typedef enum
+{
+    CycleByCycleTrip = ((uint16)1U << 1U), /** Trip Zone Cycle-By-Cycle            */
+    OneShotTrip      = ((uint16)1U << 2U), /** TripZone One-shot                   */
+    DCAEVT1_inter    = ((uint16)1U << 3U), /** Digital Comparator Output A Event 1 */
+    DCAEVT2_inter    = ((uint16)1U << 4U), /** Digital Comparator Output A Event 2 */
+    DCBEVT1_inter    = ((uint16)1U << 5U), /** Digital Comparator Output B Event 1 */
+    DCBEVT2_inter    = ((uint16)1U << 6U)  /** Digital Comparator Output B Event 2 */
+}etpwmTrip_t;
+
+/** @brief Enumeration to define the sources for EPWMx_INT, SOCA or SOCB
+*/
+typedef enum
+{
+    NO_EVENT      = 0U, /** Reserved                                             */
+    DCAEVT1       = 0U, /** DCAEVT1.soc event                                    */
+    DCBEVT1       = 0U, /** DCBEVT1.soc event                                    */
+    CTR_ZERO      = 1U, /** Event CTR = Zero                                     */
+    CTR_PRD       = 2U, /** Event CTR = PRD                                      */
+    CTR_ZERO_PRD  = 3U, /** Event CTR = Zero or CTR = PRD                        */
+    CTR_UP_CMPA   = 4U, /** Event CTR = CMPA when when the timer is incrementing */
+    CTR_D0WM_CMPA = 5U, /** Event CTR = CMPA when when the timer is decrementing */
+    CTR_UP_CMPB   = 6U, /** Event CTR = CMPB when when the timer is incrementing */
+    CTR_D0WM_CMPB = 7U  /** Event CTR = CMPB when when the timer is decrementing */
+} etpwmEventSrc_t;
+
+/** @brief Enumeration to define the period of EPWMx_INT, SOCA or SOCB
+*/
+typedef enum
+{
+    EventPeriod_Disable     = 0U, /** Disable EPWMx_INT/SOCA/SOCB event counter              */
+    EventPeriod_FirstEvent  = 1U, /** Generate EPWMx_INT/SOCA/SOCB pulse on the first event  */
+    EventPeriod_SecondEvent = 2U, /** Generate EPWMx_INT/SOCA/SOCB pulse on the second event */
+    EventPeriod_ThirdEvent  = 3U  /** Generate EPWMx_INT/SOCA/SOCB pulse on the third event  */
+}etpwmEventPeriod_t;
+
+/** @brief Enumeration to define the output events from ETPWMx
+*/
+typedef enum
+{
+    Event_Interrupt = 1U, /** EPWM Interrupt        */
+    Event_SOCA      = 4U, /** Start Of Conversion A */
+    Event_SOCB      = 8U  /** Start Of conversion B */
+}etpwmEvent_t;
+
+/** @brief Enumeration to define the pulse width modulation (ETPWM) action qualifiers
+*   
+*   @note This enum should be use to populate the struct passed as the parameter 
+*   to the APIs etpwmSetActionQualPwmA and etpwmSetActionQualPwmB
+*/
+typedef enum
+{
+    ActionQual_Disabled = 0U, /** Do nothing (action disabled)           */
+    ActionQual_Clear    = 1U, /** Clear: force EPTWMxA/ETPWMB output low */
+    ActionQual_Set      = 2U, /** Set: force ETPWMxA/ETPWMxB output high */
+    ActionQual_Toggle   = 3U, /** Toggle EPWMxA/ETPWMxB output           */
+	
+    ForceSize_ActionQual = 0xFFFFU  /** Do not use (Makes sure that etpwmActionQual_t is at least 16 bits wide)  */
+} etpwmActionQual_t;
+
+/** @brief Enumeration to define the DeadBand input mode
+*   
+*   @note This enum should be use to populate the struct passed as the parameter 
+*   to the API etpwmEnableDeadBand
+*/
+typedef enum
+{
+    PWMA_RED_FED      = 0x00U,   /** Source of Rising edge delay: ETPWMxA, Source of Falling edge delay: ETPWMxA */
+    PWMA_FED_PWMB_RED = 0x10U,   /** Source of Rising edge delay: ETPWMxB, Source of Falling edge delay: ETPWMxA */
+    PWMA_RED_PWMB_FED = 0x20U,   /** Source of Rising edge delay: ETPWMxA, Source of Falling edge delay: ETPWMxB */
+    PWMB_RED_FED      = 0x30U,   /** Source of Rising edge delay: ETPWMxB, Source of Falling edge delay: ETPWMxB */
+   
+    ForceSize_DBInput = 0xFFFFU  /** Do not use (Makes sure that etpwmDeadBandInputMode_t is at least 16 bits wide)  */
+} etpwmDeadBandInputMode_t;
+
+/** @brief Enumeration to define the DeadBand output mode
+*   
+*   @note This enum should be use to populate the struct passed as the parameter 
+*   to the API etpwmEnableDeadBand
+*/
+typedef enum
+{                                                                                                                                     
+    PWMA_PWMB_NIL      = 0U,     /** Deadband generation is bypassed for both output signals                                       */
+    PWMA_NIL_PWMB_FED  = 1U,     /** Disable rising-edge delay. The falling-edge delayed signal is seen on output EPWMxB.          */
+    PWMA_RED_PWMB_NIL  = 2U,     /** Disable falling-edge delay. The rising-edge delayed signal is seen on output EPWMxA.          */
+    PWMB_FED_PWMA_RED  = 3U,     /** Rising-edge delayed signal on output EPWMxA and falling-edge delayed signal on output EPWMxB. */
+    
+	ForceSize_DBOutput = 0xFFFFU /** Do not use (Makes sure that etpwmDeadBandOutputMode_t is at least 16 bits wide)  */
+} etpwmDeadBandOutputMode_t;
+
+/** @brief Enumeration to define the DeadBand polarity
+*   
+*   @note This enum should be use to populate the struct passed as the parameter 
+*   to the API etpwmEnableDeadBand
+*
+*/
+typedef enum
+{
+    DisableInvert    = ((uint16)0U << 2U), /** Neither EPWMxA nor EPWMxB is inverted */
+    Invert_PWMA      = ((uint16)1U << 2U), /** EPWMxA is inverted                    */
+    Invert_PWMB      = ((uint16)2U << 2U), /** EPWMxB is inverted                    */
+    Invert_PWMA_PWMB = ((uint16)3U << 2U), /** Both EPWMxA and EPWMxB are inverted   */
+	
+    ForceSize_DBPol = 0xFFFFU /** Do not use (Makes sure that etpwmDeadBandPolarity_t is at least 16 bits wide)  */
+} etpwmDeadBandPolarity_t;
+
+/** @brief Enumeration to define the action on EPWMA/EPWMB when a trip event happens
+*   
+*   @note This enum should be use to populate the struct passed as the parameter 
+*   to the API etpwmSetTripAction
+*
+*/
+typedef enum
+{
+    TripZoneState_HighImp   = 0U, /** High-Impedance state */
+    TripZoneState_EPWM_High = 1U, /** Force to High state  */
+    TripZoneState_EPWM_Low  = 2U, /** Force to Low state   */
+    TripZoneState_DoNothing = 3U, /** Do nothing           */
+
+    ForceSize_TripZoneState = 0xFFFFU /** Do not use (Makes sure that etpwmTripZoneState_t is at least 16 bits wide)  */
+} etpwmTripZoneState_t;
+
+/** @brief Enumeration to define One-Shot Pulse Width in chopper submodule
+*   
+*   @note This enum should be use to populate the struct passed as the parameter 
+*   to the API etpwmEnableChopping
+*
+*/
+typedef enum
+{
+    ChoppingPulseWidth_8_VCLK4   = ((uint16)0U << 1U),  /** 1 x VCLK4/8 wide  */
+    ChoppingPulseWidth_16_VCLK4  = ((uint16)1U << 1U),  /** 2 x VCLK4/8 wide  */
+    ChoppingPulseWidth_24_VCLK4  = ((uint16)2U << 1U),  /** 3 x VCLK4/8 wide  */
+    ChoppingPulseWidth_32_VCLK4  = ((uint16)3U << 1U),  /** 4 x VCLK4/8 wide  */
+    ChoppingPulseWidth_40_VCLK4  = ((uint16)4U << 1U),  /** 5 x VCLK4/8 wide  */
+    ChoppingPulseWidth_48_VCLK4  = ((uint16)5U << 1U),  /** 6 x VCLK4/8 wide  */
+    ChoppingPulseWidth_56_VCLK4  = ((uint16)6U << 1U),  /** 7 x VCLK4/8 wide  */
+    ChoppingPulseWidth_64_VCLK4  = ((uint16)7U << 1U),  /** 8 x VCLK4/8 wide  */
+    ChoppingPulseWidth_72_VCLK4  = ((uint16)8U << 1U),  /** 9 x VCLK4/8 wide  */
+    ChoppingPulseWidth_80_VCLK4  = ((uint16)9U << 1U),  /** 10 x VCLK4/8 wide */
+    ChoppingPulseWidth_88_VCLK4  = ((uint16)10U << 1U), /** 11 x VCLK4/8 wide */
+    ChoppingPulseWidth_96_VCLK4  = ((uint16)11U << 1U), /** 12 x VCLK4/8 wide */
+    ChoppingPulseWidth_104_VCLK4 = ((uint16)12U << 1U), /** 13 x VCLK4/8 wide */
+    ChoppingPulseWidth_112_VCLK4 = ((uint16)13U << 1U), /** 14 x VCLK4/8 wide */
+    ChoppingPulseWidth_120_VCLK4 = ((uint16)14U << 1U), /** 15 x VCLK4/8 wide */
+    ChoppingPulseWidth_128_VCLK4 = ((uint16)15U << 1U), /** 16 x VCLK4/8 wide */
+	
+    ForceSize_ChopPulseWidth = 0xFFFFU /** Do not use (Makes sure that etpwmChoppingPulseWidth_t is at least 16 bits wide)  */
+} etpwmChoppingPulseWidth_t;
+
+/** @brief Enumeration to define Chopping Clock Frequency
+*   
+*   @note This enum should be use to populate the struct passed as the parameter 
+*   to the API etpwmEnableChopping
+*
+*/
+typedef enum
+{
+    ChoppingClkFreq_VCLK4_by_8  = ((uint16)0U << 5U), /** VCLK4/8 divided by 1 */
+    ChoppingClkFreq_VCLK4_by_16 = ((uint16)1U << 5U), /** VCLK4/8 divided by 2 */
+    ChoppingClkFreq_VCLK4_by_24 = ((uint16)2U << 5U), /** VCLK4/8 divided by 3 */
+    ChoppingClkFreq_VCLK4_by_32 = ((uint16)3U << 5U), /** VCLK4/8 divided by 4 */
+    ChoppingClkFreq_VCLK4_by_40 = ((uint16)4U << 5U), /** VCLK4/8 divided by 5 */
+    ChoppingClkFreq_VCLK4_by_48 = ((uint16)5U << 5U), /** VCLK4/8 divided by 6 */
+    ChoppingClkFreq_VCLK4_by_56 = ((uint16)6U << 5U), /** VCLK4/8 divided by 7 */
+    ChoppingClkFreq_VCLK4_by_64 = ((uint16)7U << 5U), /** VCLK4/8 divided by 8 */
+
+    ForceSize_ChopClkFreq = 0xFFFFU /** Do not use (Makes sure that etpwmChoppingClkFreq_t is at least 16 bits wide)  */
+}etpwmChoppingClkFreq_t;
+
+/** @brief Enumeration to define Chopping Clock duty cycle
+*   
+*   @note This enum should be use to populate the struct passed as the parameter 
+*   to the API etpwmEnableChopping
+*
+*/
+typedef enum
+{
+    ChoppingDutyCycle_One_Eighth    = 0x0000U, /** Duty = 1/8 (12.5%) */
+    ChoppingDutyCycle_Two_Eighths   = 0x0100U, /** Duty = 2/8 (25.0%) */
+    ChoppingDutyCycle_Three_Eighths = 0x0200U, /** Duty = 3/8 (37.5%) */
+    ChoppingDutyCycle_Four_Eighths  = 0x0300U, /** Duty = 4/8 (50.0%) */
+    ChoppingDutyCycle_Five_Eighths  = 0x0400U, /** Duty = 5/8 (62.5%) */
+    ChoppingDutyCycle_Six_Eighths   = 0x0500U, /** Duty = 6/8 (75.0%) */
+    ChoppingDutyCycle_Seven_Eighths = 0x0600U, /** Duty = 7/8 (87.5%) */
+
+    ForceSize_ChopDuty = 0xFFFFU /** Do not use (Makes sure that etpwmChoppingDutyCycle_t is at least 16 bits wide)  */
+} etpwmChoppingDutyCycle_t;
+
+/** @brief Enumeration to define Digital Compare Input
+*   
+*   @note This enum should be use to populate the struct passed as the parameter 
+*   to the API etpwmEnableDigitalCompareEvents
+*
+*/
+typedef enum
+{
+	TZ1 = 0U,
+	TZ2 = 1U,
+	TZ3 = 2U,
+
+    ForceSize_DCInput = 0xFFFFU /** Do not use (Makes sure that etpwmDCInput_t is at least 16 bits wide)  */
+}etpwmDCInput_t;
+
+/** @brief Enumeration to define Digital Compare Output selection
+*   
+*   @note This enum should be use to populate the struct passed as the parameter 
+*   to the API etpwmEnableDigitalCompareEvents.
+*   @note DCAH_Low, DCAH_High, DCAL_Low, DCAL_High, DCAL_High_DCAH_Low should be used only for selecting DCAEVT1_event and DCAEVT2_event
+*   and DCBH_Low, DCBH_High, DCBL_Low, DCBL_High, DCBL_High_DCBH_Low should be used only for selecting DCBEVT1_event and DCBEVT2_event
+*
+*/
+typedef enum
+{
+	Event_Disabled     = 0U,  /** Event Disabled */
+
+	DCAH_Low           = 1U,  /** DCAEVTx selection : DCAH = low,  DCAL = don't care  */
+	DCAH_High          = 2U,  /** DCAEVTx selection : DCAH = high, DCAL = don't care  */
+	DCAL_Low           = 3U,  /** DCAEVTx selection : DCAL = low,  DCAH = don't care  */
+	DCAL_High          = 4U,  /** DCAEVTx selection : DCAL = high, DCAH = don't care  */
+	DCAL_High_DCAH_Low = 5U,  /** DCAEVTx selection : DCAL = high, DCAH = low         */
+
+	DCBH_Low           = 1U,  /** DCBEVTx selection : DCBH = low,  DCBL = don't care  */
+	DCBH_High          = 2U,  /** DCBEVTx selection : DCBH = high, DCBL = don't care  */
+	DCBL_Low           = 3U,  /** DCBEVTx selection : DCBL = low,  DCBH = don't care  */
+	DCBL_High          = 4U,  /** DCBEVTx selection : DCBL = high, DCBH = don't care  */
+	DCBL_High_DCBH_low = 5U,  /** DCBEVTx selection : DCBL = high, DCBH = low         */
+
+    ForceSize_DCSelect = 0xFFFFU /** Do not use (Makes sure that etpwmDCInput_t is at least 16 bits wide)  */
+}etpwmDCOutputSelect_t;
+
+/** @brief ETPWMx Action Qualifier configuration
+*/
+typedef struct
+{
+    etpwmActionQual_t CtrEqZero_Action;
+    etpwmActionQual_t CtrEqPeriod_Action;
+    etpwmActionQual_t CtrEqCmpAUp_Action;
+    etpwmActionQual_t CtrEqCmpADown_Action;
+    etpwmActionQual_t CtrEqCmpBUp_Action;
+    etpwmActionQual_t CtrEqCmpBDown_Action;
+}etpwmActionQualConfig_t;
+
+/** @brief ETPWMx Deadband configuration
+*/
+typedef struct
+{
+    etpwmDeadBandInputMode_t inputmode;
+    etpwmDeadBandOutputMode_t outputmode;
+    etpwmDeadBandPolarity_t polarity;
+    boolean halfCycleEnable;
+}etpwmDeadBandConfig_t;
+
+/** @brief ETPWMx Chopper configuration
+*/
+typedef struct
+{
+    etpwmChoppingPulseWidth_t oswdth;
+    etpwmChoppingClkFreq_t freq;
+    etpwmChoppingDutyCycle_t duty;
+}etpwmChoppingConfig_t;
+
+/** @brief ETPWMx Trip action configuration
+*/
+typedef struct
+{
+    etpwmTripZoneState_t TripEvent_ActionOnPWMA;
+    etpwmTripZoneState_t TripEvent_ActionOnPWMB;
+    etpwmTripZoneState_t DCAEVT1_ActionOnPWMA;
+    etpwmTripZoneState_t DCAEVT2_ActionOnPWMA;
+    etpwmTripZoneState_t DCBEVT1_ActionOnPWMB;
+    etpwmTripZoneState_t DCBEVT2_ActionOnPWMB;
+}etpwmTripActionConfig_t;
+
+/** @brief ETPWMx Digital Compare configuration
+*/
+typedef struct
+{
+	etpwmDCInput_t DCAH_src;
+	etpwmDCInput_t DCAL_src;
+	etpwmDCInput_t DCBH_src;
+	etpwmDCInput_t DCBL_src;
+	etpwmDCOutputSelect_t DCAEVT1_event;
+	etpwmDCOutputSelect_t DCAEVT2_event;
+	etpwmDCOutputSelect_t DCBEVT1_event;
+	etpwmDCOutputSelect_t DCBEVT2_event;
+}etpwmDigitalCompareConfig_t;
+
+typedef struct etpwm_config_reg
+{
+    uint16 CONFIG_TBCTL;
+    uint16 CONFIG_TBPHS;
+    uint16 CONFIG_TBPRD;
+    uint16 CONFIG_CMPCTL;
+    uint16 CONFIG_CMPA;
+    uint16 CONFIG_CMPB;
+    uint16 CONFIG_AQCTLA;
+    uint16 CONFIG_AQCTLB;
+    uint16 CONFIG_DBCTL;
+    uint16 CONFIG_DBRED;
+    uint16 CONFIG_DBFED;
+    uint16 CONFIG_TZSEL;
+    uint16 CONFIG_TZDCSEL;
+    uint16 CONFIG_TZCTL;
+    uint16 CONFIG_TZEINT;
+    uint16 CONFIG_ETSEL;
+    uint16 CONFIG_ETPS;
+    uint16 CONFIG_PCCTL;
+    uint16 CONFIG_DCTRIPSEL;
+    uint16 CONFIG_DCACTL;
+    uint16 CONFIG_DCBCTL;
+    uint16 CONFIG_DCFCTL;
+    uint16 CONFIG_DCCAPCTL;
+    uint16 CONFIG_DCFWINDOW;
+    uint16 CONFIG_DCFWINDOWCNT;
+} etpwm_config_reg_t;
+
+#define ETPWM1_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
+#define ETPWM1_TBPHS_CONFIGVALUE          0x00000000U
+#define ETPWM1_TBPRD_CONFIGVALUE          1000U
+#define ETPWM1_CMPCTL_CONFIGVALUE         0x00000000U
+#define ETPWM1_CMPA_CONFIGVALUE           50U
+#define ETPWM1_CMPB_CONFIGVALUE           50U
+#define ETPWM1_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
+#define ETPWM1_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
+#define ETPWM1_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM1_DBRED_CONFIGVALUE          1U
+#define ETPWM1_DBFED_CONFIGVALUE          1U
+#define ETPWM1_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+#define ETPWM1_TZDCSEL_CONFIGVALUE        0x00000000U
+#define ETPWM1_TZCTL_CONFIGVALUE          0x00000000U
+#define ETPWM1_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
+#define ETPWM1_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
+#define ETPWM1_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
+#define ETPWM1_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM1_DCTRIPSEL_CONFIGVALUE      0x00000000U
+#define ETPWM1_DCACTL_CONFIGVALUE         0x00000000U
+#define ETPWM1_DCBCTL_CONFIGVALUE         0x00000000U
+#define ETPWM1_DCFCTL_CONFIGVALUE         0x00000000U
+#define ETPWM1_DCCAPCTL_CONFIGVALUE       0x00000000U
+#define ETPWM1_DCFWINDOW_CONFIGVALUE      0x00000000U
+#define ETPWM1_DCFWINDOWCNT_CONFIGVALUE   0x00000000U
+
+#define ETPWM2_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
+#define ETPWM2_TBPHS_CONFIGVALUE          0x00000000U
+#define ETPWM2_TBPRD_CONFIGVALUE          1000U
+#define ETPWM2_CMPCTL_CONFIGVALUE         0x00000000U
+#define ETPWM2_CMPA_CONFIGVALUE           50U
+#define ETPWM2_CMPB_CONFIGVALUE           50U
+#define ETPWM2_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
+#define ETPWM2_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
+#define ETPWM2_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM2_DBRED_CONFIGVALUE          1U
+#define ETPWM2_DBFED_CONFIGVALUE          1U
+#define ETPWM2_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+#define ETPWM2_TZDCSEL_CONFIGVALUE        0x00000000U
+#define ETPWM2_TZCTL_CONFIGVALUE          0x00000000U
+#define ETPWM2_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
+#define ETPWM2_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
+#define ETPWM2_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
+#define ETPWM2_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM2_DCTRIPSEL_CONFIGVALUE      0x00000000U
+#define ETPWM2_DCACTL_CONFIGVALUE         0x00000000U
+#define ETPWM2_DCBCTL_CONFIGVALUE         0x00000000U
+#define ETPWM2_DCFCTL_CONFIGVALUE         0x00000000U
+#define ETPWM2_DCCAPCTL_CONFIGVALUE       0x00000000U
+#define ETPWM2_DCFWINDOW_CONFIGVALUE      0x00000000U
+#define ETPWM2_DCFWINDOWCNT_CONFIGVALUE   0x00000000U
+
+#define ETPWM3_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
+#define ETPWM3_TBPHS_CONFIGVALUE          0x00000000U
+#define ETPWM3_TBPRD_CONFIGVALUE          1000U
+#define ETPWM3_CMPCTL_CONFIGVALUE         0x00000000U
+#define ETPWM3_CMPA_CONFIGVALUE           50U
+#define ETPWM3_CMPB_CONFIGVALUE           50U
+#define ETPWM3_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
+#define ETPWM3_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
+#define ETPWM3_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM3_DBRED_CONFIGVALUE          1U
+#define ETPWM3_DBFED_CONFIGVALUE          1U
+#define ETPWM3_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+#define ETPWM3_TZDCSEL_CONFIGVALUE        0x00000000U
+#define ETPWM3_TZCTL_CONFIGVALUE          0x00000000U
+#define ETPWM3_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
+#define ETPWM3_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
+#define ETPWM3_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
+#define ETPWM3_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM3_DCTRIPSEL_CONFIGVALUE      0x00000000U
+#define ETPWM3_DCACTL_CONFIGVALUE         0x00000000U
+#define ETPWM3_DCBCTL_CONFIGVALUE         0x00000000U
+#define ETPWM3_DCFCTL_CONFIGVALUE         0x00000000U
+#define ETPWM3_DCCAPCTL_CONFIGVALUE       0x00000000U
+#define ETPWM3_DCFWINDOW_CONFIGVALUE      0x00000000U
+#define ETPWM3_DCFWINDOWCNT_CONFIGVALUE   0x00000000U
+
+#define ETPWM4_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
+#define ETPWM4_TBPHS_CONFIGVALUE          0x00000000U
+#define ETPWM4_TBPRD_CONFIGVALUE          1000U
+#define ETPWM4_CMPCTL_CONFIGVALUE         0x00000000U
+#define ETPWM4_CMPA_CONFIGVALUE           50U
+#define ETPWM4_CMPB_CONFIGVALUE           50U
+#define ETPWM4_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
+#define ETPWM4_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
+#define ETPWM4_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM4_DBRED_CONFIGVALUE          1U
+#define ETPWM4_DBFED_CONFIGVALUE          1U
+#define ETPWM4_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+#define ETPWM4_TZDCSEL_CONFIGVALUE        0x00000000U
+#define ETPWM4_TZCTL_CONFIGVALUE          0x00000000U
+#define ETPWM4_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
+#define ETPWM4_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
+#define ETPWM4_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
+#define ETPWM4_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM4_DCTRIPSEL_CONFIGVALUE      0x00000000U
+#define ETPWM4_DCACTL_CONFIGVALUE         0x00000000U
+#define ETPWM4_DCBCTL_CONFIGVALUE         0x00000000U
+#define ETPWM4_DCFCTL_CONFIGVALUE         0x00000000U
+#define ETPWM4_DCCAPCTL_CONFIGVALUE       0x00000000U
+#define ETPWM4_DCFWINDOW_CONFIGVALUE      0x00000000U
+#define ETPWM4_DCFWINDOWCNT_CONFIGVALUE   0x00000000U
+
+#define ETPWM5_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
+#define ETPWM5_TBPHS_CONFIGVALUE          0x00000000U
+#define ETPWM5_TBPRD_CONFIGVALUE          1000U
+#define ETPWM5_CMPCTL_CONFIGVALUE         0x00000000U
+#define ETPWM5_CMPA_CONFIGVALUE           50U
+#define ETPWM5_CMPB_CONFIGVALUE           50U
+#define ETPWM5_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
+#define ETPWM5_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
+#define ETPWM5_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM5_DBRED_CONFIGVALUE          1U
+#define ETPWM5_DBFED_CONFIGVALUE          1U
+#define ETPWM5_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+#define ETPWM5_TZDCSEL_CONFIGVALUE        0x00000000U
+#define ETPWM5_TZCTL_CONFIGVALUE          0x00000000U
+#define ETPWM5_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
+#define ETPWM5_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
+#define ETPWM5_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
+#define ETPWM5_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM5_DCTRIPSEL_CONFIGVALUE      0x00000000U
+#define ETPWM5_DCACTL_CONFIGVALUE         0x00000000U
+#define ETPWM5_DCBCTL_CONFIGVALUE         0x00000000U
+#define ETPWM5_DCFCTL_CONFIGVALUE         0x00000000U
+#define ETPWM5_DCCAPCTL_CONFIGVALUE       0x00000000U
+#define ETPWM5_DCFWINDOW_CONFIGVALUE      0x00000000U
+#define ETPWM5_DCFWINDOWCNT_CONFIGVALUE   0x00000000U
+
+#define ETPWM6_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
+#define ETPWM6_TBPHS_CONFIGVALUE          0x00000000U
+#define ETPWM6_TBPRD_CONFIGVALUE          1000U
+#define ETPWM6_CMPCTL_CONFIGVALUE         0x00000000U
+#define ETPWM6_CMPA_CONFIGVALUE           50U
+#define ETPWM6_CMPB_CONFIGVALUE           50U
+#define ETPWM6_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
+#define ETPWM6_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
+#define ETPWM6_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM6_DBRED_CONFIGVALUE          1U
+#define ETPWM6_DBFED_CONFIGVALUE          1U
+#define ETPWM6_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+#define ETPWM6_TZDCSEL_CONFIGVALUE        0x00000000U
+#define ETPWM6_TZCTL_CONFIGVALUE          0x00000000U
+#define ETPWM6_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
+#define ETPWM6_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
+#define ETPWM6_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
+#define ETPWM6_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM6_DCTRIPSEL_CONFIGVALUE      0x00000000U
+#define ETPWM6_DCACTL_CONFIGVALUE         0x00000000U
+#define ETPWM6_DCBCTL_CONFIGVALUE         0x00000000U
+#define ETPWM6_DCFCTL_CONFIGVALUE         0x00000000U
+#define ETPWM6_DCCAPCTL_CONFIGVALUE       0x00000000U
+#define ETPWM6_DCFWINDOW_CONFIGVALUE      0x00000000U
+#define ETPWM6_DCFWINDOWCNT_CONFIGVALUE   0x00000000U
+
+#define ETPWM7_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
+#define ETPWM7_TBPHS_CONFIGVALUE          0x00000000U
+#define ETPWM7_TBPRD_CONFIGVALUE          1000U
+#define ETPWM7_CMPCTL_CONFIGVALUE         0x00000000U
+#define ETPWM7_CMPA_CONFIGVALUE           50U
+#define ETPWM7_CMPB_CONFIGVALUE           50U
+#define ETPWM7_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
+#define ETPWM7_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
+#define ETPWM7_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM7_DBRED_CONFIGVALUE          1U
+#define ETPWM7_DBFED_CONFIGVALUE          1U
+#define ETPWM7_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+#define ETPWM7_TZDCSEL_CONFIGVALUE        0x00000000U
+#define ETPWM7_TZCTL_CONFIGVALUE          0x00000000U
+#define ETPWM7_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
+#define ETPWM7_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
+#define ETPWM7_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
+#define ETPWM7_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM7_DCTRIPSEL_CONFIGVALUE      0x00000000U
+#define ETPWM7_DCACTL_CONFIGVALUE         0x00000000U
+#define ETPWM7_DCBCTL_CONFIGVALUE         0x00000000U
+#define ETPWM7_DCFCTL_CONFIGVALUE         0x00000000U
+#define ETPWM7_DCCAPCTL_CONFIGVALUE       0x00000000U
+#define ETPWM7_DCFWINDOW_CONFIGVALUE      0x00000000U
+#define ETPWM7_DCFWINDOWCNT_CONFIGVALUE   0x00000000U	
+
+/**
+ *  @defgroup ePWM ePWM
+ *  @brief Enhanced Pulse Width Modulator.
+ *  
+ *  The enhanced pulse width modulator (ePWM) peripheral is a key element in controlling many of the power
+ *  electronic systems found in both commercial and industrial equipments. The features supported by the
+ *  ePWM make it especially suitable for digital motor control.
+ *
+ *    Related Files
+ *   - HL_reg_etpwm.h
+ *   - HL_etpwm.h
+ *   - HL_etpwm.c
+ *  @addtogroup ePWM
+ *  @{
+ */
+void etpwmInit(void);
+void etpwmStartTBCLK(void);
+void etpwmStopTBCLK(void);
+
+void etpwmSetClkDiv(etpwmBASE_t *etpwm, etpwmClkDiv_t clkdiv, etpwmHspClkDiv_t hspclkdiv);
+void etpwmSetTimebasePeriod(etpwmBASE_t *etpwm, uint16 period);
+void etpwmSetCount(etpwmBASE_t *etpwm, uint16 count);
+void etpwmDisableTimebasePeriodShadowMode(etpwmBASE_t *etpwm);
+void etpwmEnableTimebasePeriodShadowMode(etpwmBASE_t *etpwm);
+void etpwmEnableCounterLoadOnSync(etpwmBASE_t *etpwm, uint16 phase, uint16 direction);
+void etpwmDisableCounterLoadOnSync(etpwmBASE_t *etpwm);
+void etpwmSetSyncOut(etpwmBASE_t *etpwm, etpwmSyncOut_t syncOutSrc);
+void etpwmSetCounterMode(etpwmBASE_t *etpwm, etpwmCounterMode_t countermode);
+void etpwmTriggerSWSync(etpwmBASE_t *etpwm);
+void etpwmSetRunMode(etpwmBASE_t *etpwm, etpwmRunMode_t runmode);
+
+void etpwmSetCmpA(etpwmBASE_t *etpwm, uint16 value);
+void etpwmSetCmpB(etpwmBASE_t *etpwm, uint16 value);
+void etpwmEnableCmpAShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode);
+void etpwmDisableCmpAShadowMode(etpwmBASE_t *etpwm);
+void etpwmEnableCmpBShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode);
+void etpwmDisableCmpBShadowMode(etpwmBASE_t *etpwm);
+
+void etpwmSetActionQualPwmA(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig);
+void etpwmSetActionQualPwmB(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig);
+
+void etpwmEnableDeadBand(etpwmBASE_t *etpwm, etpwmDeadBandConfig_t deadbandconfig);
+void etpwmDisableDeadband(etpwmBASE_t *etpwm);
+void etpwmSetDeadBandDelay(etpwmBASE_t *etpwm, uint16 Rdelay, uint16 Fdelay);
+
+void etpwmEnableChopping(etpwmBASE_t *etpwm, etpwmChoppingConfig_t choppingconfig);
+void etpwmDisableChopping(etpwmBASE_t *etpwm);
+
+void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources);
+void etpwmDisableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources);
+void etpwmSetTripAction(etpwmBASE_t *etpwm, etpwmTripActionConfig_t tripactionconfig);
+
+void etpwmEnableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts);
+void etpwmDisableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts);
+void etpwmClearTripCondition(etpwmBASE_t *etpwm, etpwmTrip_t trips);
+void etpwmClearTripInterruptFlag(etpwmBASE_t *etpwm);
+void etpwmForceTripEvent(etpwmBASE_t *etpwm, etpwmTrip_t trip);
+void etpwmEnableSOCA(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod);
+void etpwmDisableSOCA(etpwmBASE_t *etpwm);
+void etpwmEnableSOCB(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod);
+void etpwmDisableSOCB(etpwmBASE_t *etpwm);
+void etpwmEnableInterrupt(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod);
+void etpwmDisableInterrupt(etpwmBASE_t *etpwm);
+uint16 etpwmGetEventStatus(etpwmBASE_t *etpwm);
+void etpwmClearEventFlag(etpwmBASE_t *etpwm, etpwmEvent_t events);
+void etpwmTriggerEvent(etpwmBASE_t *etpwm, etpwmEvent_t events);
+void etpwmEnableDigitalCompareEvents(etpwmBASE_t *etpwm, etpwmDigitalCompareConfig_t digitalcompareconfig);
+void etpwm1GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type);
+void etpwm2GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type);
+void etpwm3GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type);
+void etpwm4GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type);
+void etpwm5GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type);
+void etpwm6GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type);
+void etpwm7GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type);
+/** @brief     Notification for ETPWMx Interrupts
+*   @param[in] node  The pulse width modulation (ETPWM) object handle
+*/
+void etpwmNotification(etpwmBASE_t *node);
+
+/** @brief     Notification for ETPWM Trip zone Interrupts
+*   @param[in] node  The pulse width modulation (ETPWM) object handle
+*   @param[in] flags  Event and Interrupt flag.
+*/
+void etpwmTripNotification(etpwmBASE_t *node,uint16 flags);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+#endif  /* end of _ETPWM_H_ definition */
diff --git a/include/arch/rm46l8lp/halcogen/fee_interface.h b/include/arch/rm46l8lp/halcogen/fee_interface.h
new file mode 100644
index 0000000..d15580e
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/fee_interface.h
@@ -0,0 +1,193 @@
+/**********************************************************************************************************************
+ *  FILE DESCRIPTION
+ *  -------------------------------------------------------------------------------------------------------------------
+ *         File:  fee_interface.h
+ *      Project:  Tms570_TIFEEDriver
+ *       Module:  FEE Driver
+ *    Generator:  None
+ *
+ *  Description:  This file is interfce between Autosar FEE and TI FEE.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author:  Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version        Date         Author               Change ID        Description
+ *---------------------------------------------------------------------------------------------------------------------
+ * 00.01.00       07Sept2012    Vishwanath Reddy     0000000000000    Initial Version
+ * 00.01.01       14Sept2012    Vishwanath Reddy     0000000000000    Review changes
+ * 00.01.02       30Nov2012     Vishwanath Reddy     SDOCM00097786    Misra Fixes, Memory segmentation changes.
+ * 00.01.03       14Jan2013     Vishwanath Reddy     SDOCM00098510    Changes as requested by Vector.
+ * 00.01.06		  11Mar2013	  	Vishwanath Reddy     SDOCM00099152    Added feature : copying of unconfigured blocks. 
+ * 00.01.07		  15Mar2013	  	Vishwanath Reddy     SDOCM00099152    Added feature : Number of 8 bytes writes, fixed 
+																	  issue with copy blocks. 
+ * 00.01.08		  05Apr2013	    Vishwanath Reddy     SDOCM00099152    Added feature :CRC check for unconfigured blocks,
+																	  Main function modified to complete writes as fast 
+																	  as possible, Added Non polling mode support.
+ * 01.12.00		  13Dec2013     Vishwanath Reddy     SDOCM00105412    Traceability tags added. 
+ *                                                                    MISRA C fixes.
+ * 01.21.00		  15Oct2014     Vishwanath Reddy     SDOCM00113379    RAM Optimization changes. Added mew ,acro 
+ *                                                                    TI_FEE_TOTAL_BLOCKS_DATASETS 
+ * 01.22.00		  26Dec2014     Vishwanath Reddy     SDOCM00114423    Following new macros added.
+ *                                                                    TI_FEE_VIRTUALSECTOR_SIZE, 
+ *                                                                    TI_FEE_PHYSICALSECTOR_SIZE, 
+ *                                                                    TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC. 
+ * 01.23.00		  12Oct2015     Vishwanath Reddy     SDOCM00119455    Update version history.
+ * 01.23.01		  17Nov2015     Vishwanath Reddy     SDOCM00120161    Updated version history.
+ * 01.23.02		  10Mar2016     Vishwanath Reddy     SDOCM00121622    Updated version history.
+ * 01.23.03       04Aug2016     Vishwanath Reddy     SDOCM00122571    Update patch version FEE_SW_PATCH_VERSION.
+ * 01.23.04		  12Aug2016     Vishwanath Reddy     SDOCM00122592    TI_FEE_CHECK_BANK7_ACCESS is always turned on.
+ *                                                                    FEE_FLASH_CRC_ENABLE is renamed to 
+ *                                                                    FEE_FLASH_CHECKSUM_ENABLE. 
+ *                                                                    New macro FEE_USEPARTIALERASEDSECTOR added.
+ * 01.23.05		  05Dec2017     Prathap Srinivasan   HERCULES_SW-5082 Update version history for AUTOSAR FEE
+ *                                                                    (This corresponds to TI FEE 1.19.04.)
+ *********************************************************************************************************************/
+   
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef FEE_INTERFACE_H
+#define FEE_INTERFACE_H
+
+
+#include "ti_fee_cfg.h"
+
+#if(TI_FEE_DRIVER == 0U) /* Include following macros only in Autosar Context */
+#include "fee_cfg.h"
+#include "nvm.h" 
+
+#define Fee_None 0x00U	/* Take no action on single bit errors, (respond with corrected data), */
+						/* return error for uncorrectable error reads (multi bit errors for ECC or parity failures). */
+						/* For devices with no ECC (they may have parity or not) the only valid option is none. */
+#define Fee_Fix 0x01U	/* single bit "zero" error will be fixed by reprogramming, single bit "one" error */
+						/* will be fixed by marking the current entry as invalid and copying the data to a new entry,*/
+						/* return error for uncorrectable error reads (multi bit errors for ECC or parity failures). */
+
+#define TI_Fee_None 0x00U	/* Take no action on single bit errors, (respond with corrected data), */
+							/* return error for uncorrectable error reads(multibit errors for ECC or parity failures)*/
+							/* For devices with no ECC (they may have parity or not) the only valid option is none. */
+#define TI_Fee_Fix 0x01U	/* single bit "zero" error will be fixed by reprogramming, single bit "one" error */
+							/* will be fixed by marking the current entry as invalid and copying the data to a new 
+							   entry, */
+							/* return error for uncorrectable error reads (multi bit errors for ECC or parity 
+							   failures)*/
+							
+
+#if(FEE_FLASH_ERROR_CORRECTION_HANDLING == Fee_Fix)
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - TI_Fee_Fix is a symbolic constant."*/
+#define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING 	TI_Fee_Fix
+#else
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - TI_Fee_None is a symbolic constant."*/
+#define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING 	TI_Fee_None
+#endif
+
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_MAXIMUM_BLOCKING_TIME is a symbolic constant"*/
+#define TI_FEE_MAXIMUM_BLOCKING_TIME 			FEE_MAXIMUM_BLOCKING_TIME
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_OPERATING_FREQUENCY is a symbolic constant."*/
+#define TI_FEE_OPERATING_FREQUENCY 				FEE_OPERATING_FREQUENCY
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_FLASH_ERROR_CORRECTION_ENABLE is a symbolic constant."*/
+#define TI_FEE_FLASH_ERROR_CORRECTION_ENABLE 	FEE_FLASH_ERROR_CORRECTION_ENABLE
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_FLASH_CHECKSUM_ENABLE is a symbolic constant."*/
+#define TI_FEE_FLASH_CHECKSUM_ENABLE			FEE_FLASH_CHECKSUM_ENABLE
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_FLASH_WRITECOUNTER_SAVE is a symbolic constant."*/
+#define TI_FEE_FLASH_WRITECOUNTER_SAVE 			FEE_FLASH_WRITECOUNTER_SAVE
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - NVM_DATASET_SELECTION_BITS is a symbolic constant."*/
+#define TI_FEE_DATASELECT_BITS 					NVM_DATASET_SELECTION_BITS
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_EEPS is a symbolic constant."*/
+#define TI_FEE_NUMBER_OF_EEPS  					FEE_NUMBER_OF_EEPS
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_INDEX is a symbolic constant."*/
+#define TI_FEE_INDEX                    		FEE_INDEX
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_PAGE_OVERHEAD is a symbolic constant."*/
+#define TI_FEE_PAGE_OVERHEAD            		FEE_PAGE_OVERHEAD
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_BLOCK_OVERHEAD is a symbolic constant."*/
+#define TI_FEE_BLOCK_OVERHEAD           		FEE_BLOCK_OVERHEAD
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_VIRTUAL_PAGE_SIZE is a symbolic constant."*/
+#define TI_FEE_VIRTUAL_PAGE_SIZE        		FEE_VIRTUAL_PAGE_SIZE
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_VIRTUAL_SECTOR_OVERHEAD is a symbolic constant."*/
+#define TI_FEE_VIRTUAL_SECTOR_OVERHEAD  		FEE_VIRTUAL_SECTOR_OVERHEAD
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY is a symbolic constant."*/
+#define TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY  		FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_EIGHTBYTEWRITES is a symbolic constant."*/
+#define TI_FEE_NUMBER_OF_EIGHTBYTEWRITES  		FEE_NUMBER_OF_EIGHTBYTEWRITES
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NVM_JOB_END_NOTIFICATION is a symbolic constant."*/
+#define TI_FEE_NVM_JOB_END_NOTIFICATION			FEE_NVM_JOB_END_NOTIFICATION
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NVM_JOB_ERROR_NOTIFICATION is a symbolic constant."*/
+#define TI_FEE_NVM_JOB_ERROR_NOTIFICATION		FEE_NVM_JOB_ERROR_NOTIFICATION
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_POLLING_MODE is a symbolic constant."*/
+#define TI_FEE_POLLING_MODE						FEE_POLLING_MODE
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_CHECK_BANK7_ACCESS is a symbolic constant."*/
+#ifndef FEE_CHECK_BANK7_ACCESS
+#define TI_FEE_CHECK_BANK7_ACCESS				STD_ON
+#else
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_CHECK_BANK7_ACCESS is a symbolic constant."*/
+#define TI_FEE_CHECK_BANK7_ACCESS				STD_ON
+#endif
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_TOTAL_BLOCKS_DATASETS is a symbolic constant."*/
+#define TI_FEE_TOTAL_BLOCKS_DATASETS			FEE_TOTAL_BLOCKS_DATASETS
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_VIRTUALSECTOR_SIZE is a symbolic constant."*/
+#define TI_FEE_VIRTUALSECTOR_SIZE				FEE_VIRTUALSECTOR_SIZE
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_PHYSICALSECTOR_SIZE is a symbolic constant."*/
+#define TI_FEE_PHYSICALSECTOR_SIZE				FEE_PHYSICALSECTOR_SIZE
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC is a symbolic constant."*/
+#define TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC	FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_USEPARTIALERASEDSECTOR is a symbolic constant."*/
+#define TI_FEE_USEPARTIALERASEDSECTOR			FEE_USEPARTIALERASEDSECTOR
+
+/*----------------------------------------------------------------------------*/
+/* Virtual Sector Configuration                                               */
+
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS is a symbolic constant."*/
+/*SAFETYMCUSW 61 X MR:1.4,5.1 <APPROVED> "Reason - Similar Identifier name is required here."*/
+#define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS 		FEE_NUMBER_OF_VIRTUAL_SECTORS
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 is a symbolic constant."*/
+/*SAFETYMCUSW 384 S MR:1.4,5.1 <APPROVED> "Reason - Similar Identifier name is required here."*/
+/*SAFETYMCUSW 61 X MR:1.4,5.1 <APPROVED> "Reason - Similar Identifier name is required here."*/
+#define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1	FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1
+
+
+/*----------------------------------------------------------------------------*/
+/* Block Configuration                                                        */
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_BLOCKS is a symbolic constant."*/
+#define TI_FEE_NUMBER_OF_BLOCKS  				FEE_NUMBER_OF_BLOCKS
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - TI_FEE_VARIABLE_DATASETS is a symbolic constant."*/
+#define TI_FEE_VARIABLE_DATASETS  				STD_ON
+
+
+#endif	/* TI_FEE_DRIVER */
+
+#endif /* FEE_INTERFACE_H */
+/**********************************************************************************************************************
+ *  END OF FILE: fee_interface.h
+ *********************************************************************************************************************/
diff --git a/include/arch/rm46l8lp/halcogen/gio.h b/include/arch/rm46l8lp/halcogen/gio.h
new file mode 100644
index 0000000..4b33e2b
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/gio.h
@@ -0,0 +1,174 @@
+/** @file gio.h
+*   @brief GIO Driver Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __GIO_H__
+#define __GIO_H__
+
+#include "reg_gio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+typedef struct gio_config_reg
+{
+    uint32 CONFIG_INTDET;
+    uint32 CONFIG_POL;
+    uint32 CONFIG_INTENASET;
+    uint32 CONFIG_LVLSET;
+
+	uint32 CONFIG_PORTADIR;
+	uint32 CONFIG_PORTAPDR;
+	uint32 CONFIG_PORTAPSL;
+	uint32 CONFIG_PORTAPULDIS;
+
+	uint32 CONFIG_PORTBDIR;
+	uint32 CONFIG_PORTBPDR;
+	uint32 CONFIG_PORTBPSL;
+	uint32 CONFIG_PORTBPULDIS;
+}gio_config_reg_t;
+
+#define GIO_INTDET_CONFIGVALUE    0U
+#define GIO_POL_CONFIGVALUE	      ((uint32)((uint32)0U << 0U) \
+								 | (uint32)((uint32)0U << 1U) \
+								 | (uint32)((uint32)0U << 2U) \
+								 | (uint32)((uint32)0U << 3U) \
+								 | (uint32)((uint32)0U << 4U) \
+								 | (uint32)((uint32)0U << 5U) \
+								 | (uint32)((uint32)0U << 6U) \
+								 | (uint32)((uint32)0U << 7U) \
+								 | (uint32)((uint32)0U << 8U) \
+								 | (uint32)((uint32)0U << 9U) \
+								 | (uint32)((uint32)0U << 10U)\
+								 | (uint32)((uint32)0U << 11U)\
+								 | (uint32)((uint32)0U << 12U)\
+								 | (uint32)((uint32)0U << 13U)\
+								 | (uint32)((uint32)0U << 14U)\
+								 | (uint32)((uint32)0U << 15U))
+
+
+#define GIO_INTENASET_CONFIGVALUE ((uint32)((uint32)0U << 0U) \
+							     | (uint32)((uint32)0U << 1U) \
+							     | (uint32)((uint32)0U << 2U) \
+							     | (uint32)((uint32)0U << 3U) \
+							     | (uint32)((uint32)0U << 4U) \
+							     | (uint32)((uint32)0U << 5U) \
+							     | (uint32)((uint32)0U << 6U) \
+							     | (uint32)((uint32)0U << 7U) \
+								 | (uint32)((uint32)0U << 8U) \
+								 | (uint32)((uint32)0U << 9U) \
+								 | (uint32)((uint32)0U << 10U)\
+								 | (uint32)((uint32)0U << 11U)\
+								 | (uint32)((uint32)0U << 12U)\
+								 | (uint32)((uint32)0U << 13U)\
+								 | (uint32)((uint32)0U << 14U)\
+								 | (uint32)((uint32)0U << 15U))
+
+#define GIO_LVLSET_CONFIGVALUE    ((uint32)((uint32)0U << 0U) \
+								 | (uint32)((uint32)0U << 1U) \
+								 | (uint32)((uint32)0U << 2U) \
+								 | (uint32)((uint32)0U << 3U) \
+								 | (uint32)((uint32)0U << 4U) \
+								 | (uint32)((uint32)0U << 5U) \
+								 | (uint32)((uint32)0U << 6U) \
+								 | (uint32)((uint32)0U << 7U) \
+								 | (uint32)((uint32)0U << 8U) \
+								 | (uint32)((uint32)0U << 9U) \
+								 | (uint32)((uint32)0U << 10U)\
+								 | (uint32)((uint32)0U << 11U)\
+								 | (uint32)((uint32)0U << 12U)\
+								 | (uint32)((uint32)0U << 13U)\
+								 | (uint32)((uint32)0U << 14U)\
+								 | (uint32)((uint32)0U << 15U))
+
+#define GIO_PORTADIR_CONFIGVALUE	((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTAPDR_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTAPSL_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTAPULDIS_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) |(uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+
+#define GIO_PORTBDIR_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTBPDR_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTBPSL_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTBPULDIS_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) |(uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+
+
+/**
+ *  @defgroup GIO GIO
+ *  @brief General-Purpose Input/Output Module.
+ *
+ *  The GIO module provides the family of devices with input/output (I/O) capability.
+ *  The I/O pins are bidirectional and bit-programmable.
+ *  The GIO module also supports external interrupt capability.
+ *
+ *	Related Files
+ *   - reg_gio.h
+ *   - gio.h
+ *   - gio.c
+ *  @addtogroup GIO
+ *  @{
+ */
+
+/* GIO Interface Functions */
+void gioInit(void);
+void gioSetDirection(gioPORT_t *port, uint32 dir);
+void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value);
+void gioSetPort(gioPORT_t *port, uint32 value);
+uint32 gioGetBit(gioPORT_t *port, uint32 bit);
+uint32 gioGetPort(gioPORT_t *port);
+void gioToggleBit(gioPORT_t *port, uint32 bit);
+void gioEnableNotification(gioPORT_t *port, uint32 bit);
+void gioDisableNotification(gioPORT_t *port, uint32 bit);
+void gioNotification(gioPORT_t *port, uint32 bit);
+void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/hal_stdtypes.h b/include/arch/rm46l8lp/halcogen/hal_stdtypes.h
new file mode 100644
index 0000000..f3189ff
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/hal_stdtypes.h
@@ -0,0 +1,196 @@
+/** @file hal_stdtypes.h
+*   @brief HALCoGen standard types header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Type and Global definitions which are relevant for all drivers.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __HAL_STDTYPES_H__
+#define __HAL_STDTYPES_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+/************************************************************/
+/* Type Definitions                                         */
+/************************************************************/
+#ifndef _UINT64_DECLARED
+typedef uint64_t uint64;
+#define	_UINT64_DECLARED
+#endif
+
+#ifndef _UINT32_DECLARED
+typedef uint32_t uint32;
+#define	_UINT32_DECLARED
+#endif
+
+#ifndef _UINT16_DECLARED
+typedef uint16_t uint16;
+#define	_UINT16_DECLARED
+#endif
+
+#ifndef _UINT8_DECLARED
+typedef uint8_t uint8;
+#define	_UINT8_DECLARED
+#endif
+
+#ifndef _BOOLEAN_DECLARED
+#ifdef __cplusplus
+typedef bool boolean;
+#else
+typedef _Bool boolean;
+#endif
+#define	_BOOLEAN_DECLARED
+#endif
+
+#ifndef _SINT64_DECLARED
+typedef int64_t sint64;
+#define	_SINT64_DECLARED
+#endif
+
+#ifndef _SINT32_DECLARED
+typedef int32_t sint32;
+#define	_SINT32_DECLARED
+#endif
+
+#ifndef _SINT16_DECLARED
+typedef int16_t sint16;
+#define	_SINT16_DECLARED
+#endif
+
+#ifndef _SINT8_DECLARED
+typedef int8_t sint8;
+#define	_SINT8_DECLARED
+#endif
+
+#ifndef _FLOAT32_DECLARED
+typedef float float32;
+#define	_FLOAT32_DECLARED
+#endif
+
+#ifndef _FLOAT64_DECLARED
+typedef double float64;
+#define	_FLOAT64_DECLARED
+#endif
+
+
+typedef uint8 Std_ReturnType;
+
+typedef struct
+{
+    uint16 vendorID;
+    uint16 moduleID;
+    uint8  instanceID;
+    uint8  sw_major_version;
+    uint8  sw_minor_version;
+    uint8  sw_patch_version;
+} Std_VersionInfoType;
+
+/*****************************************************************************/
+/* SYMBOL DEFINITIONS                                                        */
+/*****************************************************************************/
+#ifndef STATUSTYPEDEFINED
+  #define STATUSTYPEDEFINED
+  #define E_OK     0x00U
+
+  typedef unsigned char StatusType;
+#endif
+
+#ifndef E_NOT_OK
+#define E_NOT_OK   0x01U
+#endif
+
+#ifndef STD_ON
+#define STD_ON     0x01U
+#endif
+
+#ifndef STD_OFF
+#define STD_OFF    0x00U
+#endif
+
+
+/************************************************************/
+/* Global Definitions                                       */
+/************************************************************/
+/** @def NULL
+*   @brief NULL definition
+*/
+
+#ifndef NULL
+	/*SAFETYMCUSW 218 S MR:20.2 <APPROVED> "Custom Type Definition." */
+    #define NULL ((void *) 0U)
+#endif
+
+/*****************************************************************************/
+/* Define:       NULL_PTR                                                    */
+/* Description:  Void pointer to 0                                           */
+/*****************************************************************************/
+#ifndef NULL_PTR
+	#define NULL_PTR ((void *)0x0)
+#endif
+
+/** @def TRUE
+*   @brief definition for TRUE
+*/
+#ifndef TRUE
+    #define TRUE true
+#endif
+
+/** @def FALSE
+*   @brief BOOLEAN definition for FALSE
+*/
+#ifndef FALSE
+    #define FALSE false
+#endif
+
+/*****************************************************************************/
+/* Define:       NULL_PTR                                                    */
+/* Description:  Void pointer to 0                                           */
+/*****************************************************************************/
+#ifndef NULL_PTR
+#define NULL_PTR ((void *)0x0U)
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#endif /* __HAL_STDTYPES_H__ */
diff --git a/include/arch/rm46l8lp/halcogen/het.h b/include/arch/rm46l8lp/halcogen/het.h
new file mode 100644
index 0000000..68b1e0c
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/het.h
@@ -0,0 +1,671 @@
+/** @file het.h
+*   @brief HET Driver Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __HET_H__
+#define __HET_H__
+
+#include "reg_het.h"
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @def pwm0
+*   @brief Pwm signal 0
+*
+*   Alias for pwm signal 0
+*/
+#define pwm0 0U
+
+/** @def pwm1
+*   @brief Pwm signal 1
+*
+*   Alias for pwm signal 1
+*/
+#define pwm1 1U
+
+/** @def pwm2
+*   @brief Pwm signal 2
+*
+*   Alias for pwm signal 2
+*/
+#define pwm2 2U
+
+/** @def pwm3
+*   @brief Pwm signal 3
+*
+*   Alias for pwm signal 3
+*/
+#define pwm3 3U
+
+/** @def pwm4
+*   @brief Pwm signal 4
+*
+*   Alias for pwm signal 4
+*/
+#define pwm4 4U
+
+/** @def pwm5
+*   @brief Pwm signal 5
+*
+*   Alias for pwm signal 5
+*/
+#define pwm5 5U
+
+/** @def pwm6
+*   @brief Pwm signal 6
+*
+*   Alias for pwm signal 6
+*/
+#define pwm6 6U
+
+/** @def pwm7
+*   @brief Pwm signal 7
+*
+*   Alias for pwm signal 7
+*/
+#define pwm7 7U
+
+
+/** @def edge0
+*   @brief Edge signal 0
+*
+*   Alias for edge signal 0
+*/
+#define edge0 0U
+
+/** @def edge1
+*   @brief Edge signal 1
+*
+*   Alias for edge signal 1
+*/
+#define edge1 1U
+
+/** @def edge2
+*   @brief Edge signal 2
+*
+*   Alias for edge signal 2
+*/
+#define edge2 2U
+
+/** @def edge3
+*   @brief Edge signal 3
+*
+*   Alias for edge signal 3
+*/
+#define edge3 3U
+
+/** @def edge4
+*   @brief Edge signal 4
+*
+*   Alias for edge signal 4
+*/
+#define edge4 4U
+
+/** @def edge5
+*   @brief Edge signal 5
+*
+*   Alias for edge signal 5
+*/
+#define edge5 5U
+
+/** @def edge6
+*   @brief Edge signal 6
+*
+*   Alias for edge signal 6
+*/
+#define edge6 6U
+
+/** @def edge7
+*   @brief Edge signal 7
+*
+*   Alias for edge signal 7
+*/
+#define edge7 7U
+
+
+/** @def cap0
+*   @brief Capture signal 0
+*
+*   Alias for capture signal 0
+*/
+#define cap0 0U
+
+/** @def cap1
+*   @brief Capture signal 1
+*
+*   Alias for capture signal 1
+*/
+#define cap1 1U
+
+/** @def cap2
+*   @brief Capture signal 2
+*
+*   Alias for capture signal 2
+*/
+#define cap2 2U
+
+/** @def cap3
+*   @brief Capture signal 3
+*
+*   Alias for capture signal 3
+*/
+#define cap3 3U
+
+/** @def cap4
+*   @brief Capture signal 4
+*
+*   Alias for capture signal 4
+*/
+#define cap4 4U
+
+/** @def cap5
+*   @brief Capture signal 5
+*
+*   Alias for capture signal 5
+*/
+#define cap5 5U
+
+/** @def cap6
+*   @brief Capture signal 6
+*
+*   Alias for capture signal 6
+*/
+#define cap6 6U
+
+/** @def cap7
+*   @brief Capture signal 7
+*
+*   Alias for capture signal 7
+*/
+#define cap7 7U
+
+/** @def pwmEND_OF_DUTY
+*   @brief Pwm end of duty
+*
+*   Alias for pwm end of duty notification
+*/
+#define pwmEND_OF_DUTY 2U
+
+/** @def pwmEND_OF_PERIOD
+*   @brief Pwm end of period
+*
+*   Alias for pwm end of period notification
+*/
+#define pwmEND_OF_PERIOD 4U
+
+/** @def pwmEND_OF_BOTH
+*   @brief Pwm end of duty and period
+*
+*   Alias for pwm end of duty and period notification
+*/
+#define pwmEND_OF_BOTH 6U
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @struct hetBase
+*   @brief HET Register Definition
+*
+*   This structure is used to access the HET module registers.
+*/
+/** @typedef hetBASE_t
+*   @brief HET Register Frame Type Definition
+*
+*   This type is used to access the HET Registers.
+*/
+
+enum hetPinSelect
+{
+    PIN_HET_0 = 0U,
+    PIN_HET_1 = 1U,
+    PIN_HET_2 = 2U,
+    PIN_HET_3 = 3U,
+    PIN_HET_4 = 4U,
+    PIN_HET_5 = 5U,
+    PIN_HET_6 = 6U,
+    PIN_HET_7 = 7U,
+    PIN_HET_8 = 8U,
+    PIN_HET_9 = 9U,
+    PIN_HET_10 = 10U,
+    PIN_HET_11 = 11U,
+    PIN_HET_12 = 12U,
+    PIN_HET_13 = 13U,
+    PIN_HET_14 = 14U,
+    PIN_HET_15 = 15U,
+    PIN_HET_16 = 16U,
+    PIN_HET_17 = 17U,
+    PIN_HET_18 = 18U,
+    PIN_HET_19 = 19U,
+    PIN_HET_20 = 20U,
+    PIN_HET_21 = 21U,
+    PIN_HET_22 = 22U,
+    PIN_HET_23 = 23U,
+    PIN_HET_24 = 24U,
+    PIN_HET_25 = 25U,
+    PIN_HET_26 = 26U,
+    PIN_HET_27 = 27U,
+    PIN_HET_28 = 28U,
+    PIN_HET_29 = 29U,
+    PIN_HET_30 = 30U,
+    PIN_HET_31 = 31U
+};
+
+
+/** @struct hetSignal
+*   @brief HET Signal Definition
+*
+*   This structure is used to define a pwm signal.
+*/
+/** @typedef hetSIGNAL_t
+*   @brief HET Signal Type Definition
+*
+*   This type is used to access HET Signal Information.
+*/
+typedef struct hetSignal
+{
+	uint32 duty;   /**< Duty cycle in % of the period  */
+	float64   period; /**< Period in us                   */
+} hetSIGNAL_t;
+
+
+/* Configuration registers */
+typedef struct het_config_reg
+{
+    uint32 CONFIG_GCR;
+    uint32 CONFIG_PFR;
+    uint32 CONFIG_INTENAS;
+    uint32 CONFIG_INTENAC;
+    uint32 CONFIG_PRY;
+    uint32 CONFIG_AND;
+    uint32 CONFIG_HRSH;
+    uint32 CONFIG_XOR;
+    uint32 CONFIG_DIR;
+    uint32 CONFIG_PDR;	
+	uint32 CONFIG_PULDIS;
+	uint32 CONFIG_PSL;	
+	uint32 CONFIG_PCR;	
+} het_config_reg_t;
+
+/* Configuration registers initial value for HET1*/
+#define HET1_DIR_CONFIGVALUE     ((uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U)
+
+#define HET1_PDR_CONFIGVALUE     ((uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00008000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U)
+								
+#define HET1_PULDIS_CONFIGVALUE  ((uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U)								
+								
+#define HET1_PSL_CONFIGVALUE     ((uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+                                | (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00008000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U)								
+								
+#define HET1_HRSH_CONFIGVALUE    ((uint32)0x00008000U \
+								| (uint32)0x00004000U \
+								| (uint32)0x00002000U \
+								| (uint32)0x00001000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000008U \
+								| (uint32)0x00000004U \
+								| (uint32)0x00000002U \
+								| (uint32)0x00000001U)
+
+#define HET1_AND_CONFIGVALUE     ((uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U)								
+								
+#define HET1_XOR_CONFIGVALUE     ((uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U)								
+								
+#define HET1_PFR_CONFIGVALUE    (((uint32)6U << 8U) | (uint32)0U)
+
+
+#define HET1_PRY_CONFIGVALUE     ((uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U)
+								
+#define HET1_INTENAC_CONFIGVALUE ((uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U)
+								
+#define HET1_INTENAS_CONFIGVALUE ((uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U \
+								| (uint32)0x00000000U)
+
+#define HET1_PCR_CONFIGVALUE     ((uint32)0x00000005U)
+#define HET1_GCR_CONFIGVALUE      0x00030001U
+
+
+
+
+/** 
+ *  @defgroup HET HET
+ *  @brief HighEnd Timer Module.
+ *  
+ *  The HET is a software-controlled timer with a dedicated specialized timer micromachine and a set of 30 instructions.
+ *  The HET micromachine is connected to a port of up to 32 input/output (I/O) pins.
+ *
+ *	Related Files
+ *   - reg_het.h
+ *   - het.h
+ *   - het.c
+ *   - reg_htu.h
+ *   - htu.h
+ *   - std_nhet.h
+ *  @addtogroup HET
+ *  @{
+ */
+ 
+/* HET Interface Functions */
+void hetInit(void);
+
+/* PWM Interface Functions */
+void   pwmStart(hetRAMBASE_t * hetRAM,uint32 pwm);
+void   pwmStop(hetRAMBASE_t * hetRAM,uint32 pwm);
+void   pwmSetDuty(hetRAMBASE_t * hetRAM,uint32 pwm, uint32 pwmDuty);
+void   pwmSetSignal(hetRAMBASE_t * hetRAM,uint32 pwm, hetSIGNAL_t signal);
+void   pwmGetSignal(hetRAMBASE_t * hetRAM,uint32 pwm, hetSIGNAL_t *signal);
+void   pwmEnableNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification);
+void   pwmDisableNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification);
+void   pwmNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification);
+
+/* Edge Interface Functions */
+void   edgeResetCounter(hetRAMBASE_t * hetRAM,uint32 edge);
+uint32 edgeGetCounter(hetRAMBASE_t * hetRAM,uint32 edge);
+void   edgeEnableNotification(hetBASE_t * hetREG,uint32 edge);
+void   edgeDisableNotification(hetBASE_t * hetREG,uint32 edge);
+void   edgeNotification(hetBASE_t * hetREG,uint32 edge);
+
+/* Captured Signal Interface Functions */
+void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t *signal);
+
+/* Timestamp Interface Functions */
+void   hetResetTimestamp(hetRAMBASE_t * hetRAM);
+uint32 hetGetTimestamp(hetRAMBASE_t * hetRAM);
+void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type);
+
+/** @fn void hetNotification(hetBASE_t *het, uint32 offset)
+*   @brief het interrupt callback
+*   @param[in] het - Het module base address
+*              - hetREG1: HET1 module base address pointer
+*              - hetREG2: HET2 module base address pointer
+*   @param[in] offset - het interrupt offset / Source number
+*
+*   @note This function has to be provide by the user.
+*
+* This is a interrupt callback that is provided by the application and is call upon
+* an het interrupt.  The parameter passed to the callback is a copy of the interrupt 
+* offset register which is used to decode the interrupt source.
+*/
+void hetNotification(hetBASE_t *het, uint32 offset);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/htu.h b/include/arch/rm46l8lp/halcogen/htu.h
new file mode 100644
index 0000000..e17deea
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/htu.h
@@ -0,0 +1,71 @@
+/** @file htu.h
+*   @brief HTU Driver Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __HTU_H__
+#define __HTU_H__
+
+#include "reg_htu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* HTU General Definitions */
+
+#define HTU1PARLOC		(*(volatile uint32 *)0xFF4E0200U)
+#define HTU2PARLOC		(*(volatile uint32 *)0xFF4C0200U)
+
+#define HTU1RAMLOC		(*(volatile uint32 *)0xFF4E0000U)
+#define HTU2RAMLOC		(*(volatile uint32 *)0xFF4C0000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/hw_emac.h b/include/arch/rm46l8lp/halcogen/hw_emac.h
new file mode 100644
index 0000000..438c479
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/hw_emac.h
@@ -0,0 +1,1489 @@
+/*
+ * hw_emac1.h
+ */
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_EMAC_H_
+#define _HW_EMAC_H_
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#define EMAC_BASE               (0xFCF78000U)
+#define EMAC_CTRL_BASE          (0xFCF78800U)
+#define EMAC_CTRL_RAM_BASE      (0xFC520000U)
+
+#define EMAC_TXREVID		    (0x0U)
+#define EMAC_TXCONTROL		    (0x4U)
+#define EMAC_TXTEARDOWN		    (0x8U)
+#define EMAC_RXREVID		    (0x10U)
+#define EMAC_RXCONTROL		    (0x14U)
+#define EMAC_RXTEARDOWN		    (0x18U)
+#define EMAC_TXINTSTATRAW	    (0x80U)
+#define EMAC_TXINTSTATMASKED	(0x84U)
+#define EMAC_TXINTMASKSET	    (0x88U)
+#define EMAC_TXINTMASKCLEAR	    (0x8CU)
+#define EMAC_MACINVECTOR	    (0x90U)
+#define EMAC_MACEOIVECTOR	    (0x94U)
+#define EMAC_RXINTSTATRAW	    (0xA0U)
+#define EMAC_RXINTSTATMASKED	(0xA4U)
+#define EMAC_RXINTMASKSET	    (0xA8U)
+#define EMAC_RXINTMASKCLEAR	    (0xACU)
+#define EMAC_MACINTSTATRAW	    (0xB0U)
+#define EMAC_MACINTSTATMASKED	(0xB4U)
+#define EMAC_MACINTMASKSET	    (0xB8U)
+#define EMAC_MACINTMASKCLEAR	(0xBCU)
+#define EMAC_RXMBPENABLE	    (0x100U)
+#define EMAC_RXUNICASTSET	    (0x104U)
+#define EMAC_RXUNICASTCLEAR   	(0x108U)
+#define EMAC_RXMAXLEN		    (0x10CU)
+#define EMAC_RXBUFFEROFFSET	    (0x110U)
+#define EMAC_RXFILTERLOWTHRESH	(0x114U)
+#define EMAC_RXFLOWTHRESH(n)	((uint32)0x120U + (uint32)((n) * 4U))
+#define EMAC_RXFREEBUFFER(n)	((uint32)0x140U + (uint32)((n) * 4U))
+#define EMAC_MACCONTROL		    (0x160U)
+#define EMAC_MACSTATUS		    (0x164U)
+#define EMAC_EMCONTROL		    (0x168U)
+#define EMAC_FIFOCONTROL	    (0x16CU)
+#define EMAC_MACCONFIG		    (0x170U)
+#define EMAC_SOFTRESET		    (0x174U)
+#define EMAC_MACSRCADDRLO	    (0x1D0U)
+#define EMAC_MACSRCADDRHI	    (0x1D4U)
+#define EMAC_MACHASH1		    (0x1D8U)
+#define EMAC_MACHASH2		    (0x1DCU)
+#define EMAC_BOFFTEST		    (0x1E0U)
+#define EMAC_TPACETEST		    (0x1E4U)
+#define EMAC_RXPAUSE		    (0x1E8U)
+#define EMAC_TXPAUSE		    (0x1ECU)
+#define EMAC_RXGOODFRAMES	    (0x200U)
+#define EMAC_RXBCASTFRAMES	    (0x204U)
+#define EMAC_RXMCASTFRAMES	    (0x208U)
+#define EMAC_RXPAUSEFRAMES	    (0x20CU)
+#define EMAC_RXCRCERRORS	    (0x210U)
+#define EMAC_RXALIGNCODEERRORS	(0x214U)
+#define EMAC_RXOVERSIZED	    (0x218U)
+#define EMAC_RXJABBER		    (0x21CU)
+#define EMAC_RXUNDERSIZED	    (0x220U)
+#define EMAC_RXFRAGMENTS	    (0x224U)
+#define EMAC_RXFILTERED		    (0x228U)
+#define EMAC_RXQOSFILTERED	    (0x22CU)
+#define EMAC_RXOCTETS		    (0x230U)
+#define EMAC_TXGOODFRAMES	    (0x234U)
+#define EMAC_TXBCASTFRAMES	    (0x238U)
+#define EMAC_TXMCASTFRAMES	    (0x23CU)
+#define EMAC_TXPAUSEFRAMES	    (0x240U)
+#define EMAC_TXDEFERRED		    (0x244U)
+#define EMAC_TXCOLLISION	    (0x248U)
+#define EMAC_TXSINGLECOLL	    (0x24CU)
+#define EMAC_TXMULTICOLL	    (0x250U)
+#define EMAC_TXEXCESSIVECOLL	(0x254U)
+#define EMAC_TXLATECOLL		    (0x258U)
+#define EMAC_TXUNDERRUN		    (0x25CU)
+#define EMAC_TXCARRIERSENSE   	(0x260U)
+#define EMAC_TXOCTETS		    (0x264U)
+#define EMAC_FRAME64		    (0x268U)
+#define EMAC_FRAME65T127	    (0x26CU)
+#define EMAC_FRAME128T255	    (0x270U)
+#define EMAC_FRAME256T511	    (0x274U)
+#define EMAC_FRAME512T1023	    (0x278U)
+#define EMAC_FRAME1024TUP	    (0x27CU)
+#define EMAC_NETOCTETS		    (0x208U)
+#define EMAC_RXSOFOVERRUNS	    (0x284U)
+#define EMAC_RXMOFOVERRUNS	    (0x288U)
+#define EMAC_RXDMAOVERRUNS	    (0x28CU)
+#define EMAC_MACADDRLO          (0x500U)
+#define EMAC_MACADDRHI          (0x504U)
+#define EMAC_MACINDEX           (0x508U)
+#define EMAC_TXHDP(n)		    ((uint32)0x600U + (uint32)((n) * 4U))
+#define EMAC_RXHDP(n)		    ((uint32)0x620U + (uint32)((n) * 4U))
+#define EMAC_TXCP(n)		    ((uint32)0x640U + (uint32)((n) * 4U))
+#define EMAC_RXCP(n)		    ((uint32)0x660U + (uint32)((n) * 4U))
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* TXREVID */
+
+#define EMAC_TXREVID_TXREV      (0xFFFFFFFFU)
+#define EMAC_TXREVID_TXREV_SHIFT     (0x00000000U)
+
+
+/* TXCONTROL */
+
+
+#define EMAC_TXCONTROL_TXEN     (0x00000001U)
+#define EMAC_TXCONTROL_TXEN_SHIFT    (0x00000000U)
+#define EMAC_TXCONTROL_TXDIS	(0x00000000U)
+
+
+/* TXTEARDOWN */
+
+#define EMAC_TXTEARDOWN_TXTDNCH (0x00000007U)
+#define EMAC_TXTEARDOWN_TXTDNCH_SHIFT (0x00000000U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA0 (0x00000000U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA1 (0x00000001U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA2 (0x00000002U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA3 (0x00000003U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA4 (0x00000004U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA5 (0x00000005U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA6 (0x00000006U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA7 (0x00000007U)
+
+
+/* RXREVID */
+
+#define EMAC_RXREVID_RXREV      (0xFFFFFFFFU)
+#define EMAC_RXREVID_RXREV_SHIFT     (0x00000000U)
+
+
+/* RXCONTROL */
+
+
+#define EMAC_RXCONTROL_RXEN     (0x00000001U)
+#define EMAC_RXCONTROL_RXEN_SHIFT    (0x00000000U)
+#define EMAC_RXCONTROL_RXDIS     (0x00000000U)
+
+/* RXTEARDOWN */
+
+
+
+#define EMAC_RXTEARDOWN_RXTDNCH (0x00000007U)
+#define EMAC_RXTEARDOWN_RXTDNCH_SHIFT (0x00000000U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA0 (0x00000000U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA1 (0x00000001U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA2 (0x00000002U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA3 (0x00000003U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA4 (0x00000004U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA5 (0x00000005U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA6 (0x00000006U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA7 (0x00000007U)
+
+
+/* TXINTSTATRAW */
+
+
+#define EMAC_TXINTSTATRAW_TX7PEND (0x00000080U)
+#define EMAC_TXINTSTATRAW_TX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_TXINTSTATRAW_TX6PEND (0x00000040U)
+#define EMAC_TXINTSTATRAW_TX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_TXINTSTATRAW_TX5PEND (0x00000020U)
+#define EMAC_TXINTSTATRAW_TX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_TXINTSTATRAW_TX4PEND (0x00000010U)
+#define EMAC_TXINTSTATRAW_TX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_TXINTSTATRAW_TX3PEND (0x00000008U)
+#define EMAC_TXINTSTATRAW_TX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_TXINTSTATRAW_TX2PEND (0x00000004U)
+#define EMAC_TXINTSTATRAW_TX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_TXINTSTATRAW_TX1PEND (0x00000002U)
+#define EMAC_TXINTSTATRAW_TX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_TXINTSTATRAW_TX0PEND (0x00000001U)
+#define EMAC_TXINTSTATRAW_TX0PEND_SHIFT (0x00000000U)
+
+
+/* TXINTSTATMASKED */
+
+
+#define EMAC_TXINTSTATMASKED_TX7PEND (0x00000080U)
+#define EMAC_TXINTSTATMASKED_TX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_TXINTSTATMASKED_TX6PEND (0x00000040U)
+#define EMAC_TXINTSTATMASKED_TX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_TXINTSTATMASKED_TX5PEND (0x00000020U)
+#define EMAC_TXINTSTATMASKED_TX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_TXINTSTATMASKED_TX4PEND (0x00000010U)
+#define EMAC_TXINTSTATMASKED_TX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_TXINTSTATMASKED_TX3PEND (0x00000008U)
+#define EMAC_TXINTSTATMASKED_TX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_TXINTSTATMASKED_TX2PEND (0x00000004U)
+#define EMAC_TXINTSTATMASKED_TX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_TXINTSTATMASKED_TX1PEND (0x00000002U)
+#define EMAC_TXINTSTATMASKED_TX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_TXINTSTATMASKED_TX0PEND (0x00000001U)
+#define EMAC_TXINTSTATMASKED_TX0PEND_SHIFT (0x00000000U)
+
+
+/* TXINTMASKSET */
+
+
+#define EMAC_TXINTMASKSET_TX7MASK (0x00000080U)
+#define EMAC_TXINTMASKSET_TX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_TXINTMASKSET_TX6MASK (0x00000040U)
+#define EMAC_TXINTMASKSET_TX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_TXINTMASKSET_TX5MASK (0x00000020U)
+#define EMAC_TXINTMASKSET_TX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_TXINTMASKSET_TX4MASK (0x00000010U)
+#define EMAC_TXINTMASKSET_TX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_TXINTMASKSET_TX3MASK (0x00000008U)
+#define EMAC_TXINTMASKSET_TX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_TXINTMASKSET_TX2MASK (0x00000004U)
+#define EMAC_TXINTMASKSET_TX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_TXINTMASKSET_TX1MASK (0x00000002U)
+#define EMAC_TXINTMASKSET_TX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_TXINTMASKSET_TX0MASK (0x00000001U)
+#define EMAC_TXINTMASKSET_TX0MASK_SHIFT (0x00000000U)
+
+
+/* TXINTMASKCLEAR */
+
+
+#define EMAC_TXINTMASKCLEAR_TX7MASK (0x00000080U)
+#define EMAC_TXINTMASKCLEAR_TX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_TXINTMASKCLEAR_TX6MASK (0x00000040U)
+#define EMAC_TXINTMASKCLEAR_TX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_TXINTMASKCLEAR_TX5MASK (0x00000020U)
+#define EMAC_TXINTMASKCLEAR_TX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_TXINTMASKCLEAR_TX4MASK (0x00000010U)
+#define EMAC_TXINTMASKCLEAR_TX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_TXINTMASKCLEAR_TX3MASK (0x00000008U)
+#define EMAC_TXINTMASKCLEAR_TX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_TXINTMASKCLEAR_TX2MASK (0x00000004U)
+#define EMAC_TXINTMASKCLEAR_TX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_TXINTMASKCLEAR_TX1MASK (0x00000002U)
+#define EMAC_TXINTMASKCLEAR_TX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_TXINTMASKCLEAR_TX0MASK (0x00000001U)
+#define EMAC_TXINTMASKCLEAR_TX0MASK_SHIFT (0x00000000U)
+
+
+/* MACINVECTOR */
+
+
+#define EMAC_MACINVECTOR_STATPEND (0x08000000U)
+#define EMAC_MACINVECTOR_STATPEND_SHIFT (0x0000001BU)
+
+#define EMAC_MACINVECTOR_HOSTPEND (0x04000000U)
+#define EMAC_MACINVECTOR_HOSTPEND_SHIFT (0x0000001AU)
+
+#define EMAC_MACINVECTOR_LINKINT0 (0x02000000U)
+#define EMAC_MACINVECTOR_LINKINT0_SHIFT (0x00000019U)
+
+#define EMAC_MACINVECTOR_USERINT0 (0x01000000U)
+#define EMAC_MACINVECTOR_USERINT0_SHIFT (0x00000018U)
+
+#define EMAC_MACINVECTOR_TXPEND (0x00FF0000U)
+#define EMAC_MACINVECTOR_TXPEND_SHIFT (0x00000010U)
+
+#define EMAC_MACINVECTOR_RXTHRESHPEND (0x0000FF00U)
+#define EMAC_MACINVECTOR_RXTHRESHPEND_SHIFT (0x00000008U)
+
+#define EMAC_MACINVECTOR_RXPEND (0x000000FFU)
+#define EMAC_MACINVECTOR_RXPEND_SHIFT (0x00000000U)
+
+
+/* MACEOIVECTOR */
+
+
+#define EMAC_MACEOIVECTOR_INTVECT (0x0000001FU)
+#define EMAC_MACEOIVECTOR_INTVECT_SHIFT (0x00000000U)
+/*----INTVECT Tokens----*/
+#define EMAC_MACEOIVECTOR_INTVECT_C0RXTHRESH (0x00000000U)
+#define EMAC_MACEOIVECTOR_INTVECT_C0RX (0x00000001U)
+#define EMAC_MACEOIVECTOR_INTVECT_C0TX (0x00000002U)
+#define EMAC_MACEOIVECTOR_INTVECT_C0MISC (0x00000003U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1RXTHRESH (0x00000004U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1RX (0x00000005U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1TX (0x00000006U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1MISC (0x00000007U)
+
+
+/* RXINTSTATRAW */
+
+
+#define EMAC_RXINTSTATRAW_RX7THRESHPEND (0x00008000U)
+#define EMAC_RXINTSTATRAW_RX7THRESHPEND_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTSTATRAW_RX6THRESHPEND (0x00004000U)
+#define EMAC_RXINTSTATRAW_RX6THRESHPEND_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTSTATRAW_RX5THRESHPEND (0x00002000U)
+#define EMAC_RXINTSTATRAW_RX5THRESHPEND_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTSTATRAW_RX4THRESHPEND (0x00001000U)
+#define EMAC_RXINTSTATRAW_RX4THRESHPEND_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTSTATRAW_RX3THRESHPEND (0x00000800U)
+#define EMAC_RXINTSTATRAW_RX3THRESHPEND_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTSTATRAW_RX2THRESHPEND (0x00000400U)
+#define EMAC_RXINTSTATRAW_RX2THRESHPEND_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTSTATRAW_RX1THRESHPEND (0x00000200U)
+#define EMAC_RXINTSTATRAW_RX1THRESHPEND_SHIFT (0x00000009U)
+
+#define EMAC_RXINTSTATRAW_RX0THRESHPEND (0x00000100U)
+#define EMAC_RXINTSTATRAW_RX0THRESHPEND_SHIFT (0x00000008U)
+
+#define EMAC_RXINTSTATRAW_RX7PEND (0x00000080U)
+#define EMAC_RXINTSTATRAW_RX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_RXINTSTATRAW_RX6PEND (0x00000040U)
+#define EMAC_RXINTSTATRAW_RX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_RXINTSTATRAW_RX5PEND (0x00000020U)
+#define EMAC_RXINTSTATRAW_RX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_RXINTSTATRAW_RX4PEND (0x00000010U)
+#define EMAC_RXINTSTATRAW_RX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_RXINTSTATRAW_RX3PEND (0x00000008U)
+#define EMAC_RXINTSTATRAW_RX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_RXINTSTATRAW_RX2PEND (0x00000004U)
+#define EMAC_RXINTSTATRAW_RX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_RXINTSTATRAW_RX1PEND (0x00000002U)
+#define EMAC_RXINTSTATRAW_RX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_RXINTSTATRAW_RX0PEND (0x00000001U)
+#define EMAC_RXINTSTATRAW_RX0PEND_SHIFT (0x00000000U)
+
+
+/* RXINTSTATMASKED */
+
+
+#define EMAC_RXINTSTATMASKED_RX7THRESHPEND (0x00008000U)
+#define EMAC_RXINTSTATMASKED_RX7THRESHPEND_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTSTATMASKED_RX6THRESHPEND (0x00004000U)
+#define EMAC_RXINTSTATMASKED_RX6THRESHPEND_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTSTATMASKED_RX5THRESHPEND (0x00002000U)
+#define EMAC_RXINTSTATMASKED_RX5THRESHPEND_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTSTATMASKED_RX4THRESHPEND (0x00001000U)
+#define EMAC_RXINTSTATMASKED_RX4THRESHPEND_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTSTATMASKED_RX3THRESHPEND (0x00000800U)
+#define EMAC_RXINTSTATMASKED_RX3THRESHPEND_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTSTATMASKED_RX2THRESHPEND (0x00000400U)
+#define EMAC_RXINTSTATMASKED_RX2THRESHPEND_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTSTATMASKED_RX1THRESHPEND (0x00000200U)
+#define EMAC_RXINTSTATMASKED_RX1THRESHPEND_SHIFT (0x00000009U)
+
+#define EMAC_RXINTSTATMASKED_RX0THRESHPEND (0x00000100U)
+#define EMAC_RXINTSTATMASKED_RX0THRESHPEND_SHIFT (0x00000008U)
+
+#define EMAC_RXINTSTATMASKED_RX7PEND (0x00000080U)
+#define EMAC_RXINTSTATMASKED_RX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_RXINTSTATMASKED_RX6PEND (0x00000040U)
+#define EMAC_RXINTSTATMASKED_RX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_RXINTSTATMASKED_RX5PEND (0x00000020U)
+#define EMAC_RXINTSTATMASKED_RX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_RXINTSTATMASKED_RX4PEND (0x00000010U)
+#define EMAC_RXINTSTATMASKED_RX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_RXINTSTATMASKED_RX3PEND (0x00000008U)
+#define EMAC_RXINTSTATMASKED_RX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_RXINTSTATMASKED_RX2PEND (0x00000004U)
+#define EMAC_RXINTSTATMASKED_RX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_RXINTSTATMASKED_RX1PEND (0x00000002U)
+#define EMAC_RXINTSTATMASKED_RX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_RXINTSTATMASKED_RX0PEND (0x00000001U)
+#define EMAC_RXINTSTATMASKED_RX0PEND_SHIFT (0x00000000U)
+
+
+/* RXINTMASKSET */
+
+
+#define EMAC_RXINTMASKSET_RX7THRESHMASK (0x00008000U)
+#define EMAC_RXINTMASKSET_RX7THRESHMASK_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTMASKSET_RX6THRESHMASK (0x00004000U)
+#define EMAC_RXINTMASKSET_RX6THRESHMASK_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTMASKSET_RX5THRESHMASK (0x00002000U)
+#define EMAC_RXINTMASKSET_RX5THRESHMASK_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTMASKSET_RX4THRESHMASK (0x00001000U)
+#define EMAC_RXINTMASKSET_RX4THRESHMASK_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTMASKSET_RX3THRESHMASK (0x00000800U)
+#define EMAC_RXINTMASKSET_RX3THRESHMASK_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTMASKSET_RX2THRESHMASK (0x00000400U)
+#define EMAC_RXINTMASKSET_RX2THRESHMASK_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTMASKSET_RX1THRESHMASK (0x00000200U)
+#define EMAC_RXINTMASKSET_RX1THRESHMASK_SHIFT (0x00000009U)
+
+#define EMAC_RXINTMASKSET_RX0THRESHMASK (0x00000100U)
+#define EMAC_RXINTMASKSET_RX0THRESHMASK_SHIFT (0x00000008U)
+
+#define EMAC_RXINTMASKSET_RX7MASK (0x00000080U)
+#define EMAC_RXINTMASKSET_RX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_RXINTMASKSET_RX6MASK (0x00000040U)
+#define EMAC_RXINTMASKSET_RX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_RXINTMASKSET_RX5MASK (0x00000020U)
+#define EMAC_RXINTMASKSET_RX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_RXINTMASKSET_RX4MASK (0x00000010U)
+#define EMAC_RXINTMASKSET_RX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_RXINTMASKSET_RX3MASK (0x00000008U)
+#define EMAC_RXINTMASKSET_RX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_RXINTMASKSET_RX2MASK (0x00000004U)
+#define EMAC_RXINTMASKSET_RX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_RXINTMASKSET_RX1MASK (0x00000002U)
+#define EMAC_RXINTMASKSET_RX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_RXINTMASKSET_RX0MASK (0x00000001U)
+#define EMAC_RXINTMASKSET_RX0MASK_SHIFT (0x00000000U)
+
+
+/* RXINTMASKCLEAR */
+
+
+#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK (0x00008000U)
+#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK (0x00004000U)
+#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK (0x00002000U)
+#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK (0x00001000U)
+#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK (0x00000800U)
+#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK (0x00000400U)
+#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK (0x00000200U)
+#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK_SHIFT (0x00000009U)
+
+#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK (0x00000100U)
+#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK_SHIFT (0x00000008U)
+
+#define EMAC_RXINTMASKCLEAR_RX7MASK (0x00000080U)
+#define EMAC_RXINTMASKCLEAR_RX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_RXINTMASKCLEAR_RX6MASK (0x00000040U)
+#define EMAC_RXINTMASKCLEAR_RX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_RXINTMASKCLEAR_RX5MASK (0x00000020U)
+#define EMAC_RXINTMASKCLEAR_RX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_RXINTMASKCLEAR_RX4MASK (0x00000010U)
+#define EMAC_RXINTMASKCLEAR_RX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_RXINTMASKCLEAR_RX3MASK (0x00000008U)
+#define EMAC_RXINTMASKCLEAR_RX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_RXINTMASKCLEAR_RX2MASK (0x00000004U)
+#define EMAC_RXINTMASKCLEAR_RX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_RXINTMASKCLEAR_RX1MASK (0x00000002U)
+#define EMAC_RXINTMASKCLEAR_RX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_RXINTMASKCLEAR_RX0MASK (0x00000001U)
+#define EMAC_RXINTMASKCLEAR_RX0MASK_SHIFT (0x00000000U)
+
+
+/* MACINTSTATRAW */
+
+
+#define EMAC_MACINTSTATRAW_HOSTPEND (0x00000002U)
+#define EMAC_MACINTSTATRAW_HOSTPEND_SHIFT (0x00000001U)
+
+#define EMAC_MACINTSTATRAW_STATPEND (0x00000001U)
+#define EMAC_MACINTSTATRAW_STATPEND_SHIFT (0x00000000U)
+
+
+/* MACINTSTATMASKED */
+
+
+#define EMAC_MACINTSTATMASKED_HOSTPEND (0x00000002U)
+#define EMAC_MACINTSTATMASKED_HOSTPEND_SHIFT (0x00000001U)
+
+#define EMAC_MACINTSTATMASKED_STATPEND (0x00000001U)
+#define EMAC_MACINTSTATMASKED_STATPEND_SHIFT (0x00000000U)
+
+
+/* MACINTMASKSET */
+
+
+#define EMAC_MACINTMASKSET_HOSTMASK (0x00000002U)
+#define EMAC_MACINTMASKSET_HOSTMASK_SHIFT (0x00000001U)
+
+#define EMAC_MACINTMASKSET_STATMASK (0x00000001U)
+#define EMAC_MACINTMASKSET_STATMASK_SHIFT (0x00000000U)
+
+
+/* MACINTMASKCLEAR */
+
+
+#define EMAC_MACINTMASKCLEAR_HOSTMASK (0x00000002U)
+#define EMAC_MACINTMASKCLEAR_HOSTMASK_SHIFT (0x00000001U)
+
+#define EMAC_MACINTMASKCLEAR_STATMASK (0x00000001U)
+#define EMAC_MACINTMASKCLEAR_STATMASK_SHIFT (0x00000000U)
+
+
+/* RXMBPENABLE */
+
+
+#define EMAC_RXMBPENABLE_RXPASSCRC (0x40000000U)
+#define EMAC_RXMBPENABLE_RXPASSCRC_SHIFT (0x0000001EU)
+#define EMAC_RXMBPENABLE_RXQOSEN (0x20000000U)
+#define EMAC_RXMBPENABLE_RXQOSEN_SHIFT (0x0000001DU)
+#define EMAC_RXMBPENABLE_RXNOCHAIN (0x10000000U)
+#define EMAC_RXMBPENABLE_RXNOCHAIN_SHIFT (0x0000001CU)
+#define EMAC_RXMBPENABLE_RXCMFEN (0x01000000U)
+#define EMAC_RXMBPENABLE_RXCMFEN_SHIFT (0x00000018U)
+#define EMAC_RXMBPENABLE_RXCSFEN (0x00800000U)
+#define EMAC_RXMBPENABLE_RXCSFEN_SHIFT (0x00000017U)
+#define EMAC_RXMBPENABLE_RXCEFEN (0x00400000U)
+#define EMAC_RXMBPENABLE_RXCEFEN_SHIFT (0x00000016U)
+#define EMAC_RXMBPENABLE_RXCAFEN (0x00200000U)
+#define EMAC_RXMBPENABLE_RXCAFEN_SHIFT (0x00000015U)
+/*----RXCAFEN Tokens----*/
+#define EMAC_RXMBPENABLE_RXPROMCH (0x00070000U)
+#define EMAC_RXMBPENABLE_RXPROMCH_SHIFT (0x00000010U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA0 (0x00000000U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA1 (0x00000001U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA2 (0x00000002U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA3 (0x00000003U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA4 (0x00000004U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA5 (0x00000005U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA6 (0x00000006U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA7 (0x00000007U)
+
+
+#define EMAC_RXMBPENABLE_RXBROADEN (0x00002000U)
+#define EMAC_RXMBPENABLE_RXBROADEN_SHIFT (0x0000000DU)
+#define EMAC_RXMBPENABLE_RXBROADCH (0x00000700U)
+#define EMAC_RXMBPENABLE_RXBROADCH_SHIFT (0x00000008U)
+/*----RXBROADCH Tokens----*/
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA0 (0x00000000U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA1 (0x00000001U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA2 (0x00000002U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA3 (0x00000003U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA4 (0x00000004U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA5 (0x00000005U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA6 (0x00000006U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA7 (0x00000007U)
+
+
+#define EMAC_RXMBPENABLE_RXMULTEN (0x00000020U)
+#define EMAC_RXMBPENABLE_RXMULTEN_SHIFT (0x00000005U)
+#define EMAC_RXMBPENABLE_RXMULTCH (0x00000007U)
+#define EMAC_RXMBPENABLE_RXMULTCH_SHIFT (0x00000000U)
+/*----RXMULTCH Tokens----*/
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA0 (0x00000000U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA1 (0x00000001U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA2 (0x00000002U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA3 (0x00000003U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA4 (0x00000004U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA5 (0x00000005U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA6 (0x00000006U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA7 (0x00000007U)
+
+
+/* RXUNICASTSET */
+
+
+#define EMAC_RXUNICASTSET_RXCH7EN (0x00000080U)
+#define EMAC_RXUNICASTSET_RXCH7EN_SHIFT (0x00000007U)
+#define EMAC_RXUNICASTSET_RXCH6EN (0x00000040U)
+#define EMAC_RXUNICASTSET_RXCH6EN_SHIFT (0x00000006U)
+#define EMAC_RXUNICASTSET_RXCH5EN (0x00000020U)
+#define EMAC_RXUNICASTSET_RXCH5EN_SHIFT (0x00000005U)
+#define EMAC_RXUNICASTSET_RXCH4EN (0x00000010U)
+#define EMAC_RXUNICASTSET_RXCH4EN_SHIFT (0x00000004U)
+#define EMAC_RXUNICASTSET_RXCH3EN (0x00000008U)
+#define EMAC_RXUNICASTSET_RXCH3EN_SHIFT (0x00000003U)
+#define EMAC_RXUNICASTSET_RXCH2EN (0x00000004U)
+#define EMAC_RXUNICASTSET_RXCH2EN_SHIFT (0x00000002U)
+#define EMAC_RXUNICASTSET_RXCH1EN (0x00000002U)
+#define EMAC_RXUNICASTSET_RXCH1EN_SHIFT (0x00000001U)
+#define EMAC_RXUNICASTSET_RXCH0EN (0x00000001U)
+#define EMAC_RXUNICASTSET_RXCH0EN_SHIFT (0x00000000U)
+
+/* RXUNICASTCLEAR */
+
+
+#define EMAC_RXUNICASTCLEAR_RXCH7EN (0x00000080U)
+#define EMAC_RXUNICASTCLEAR_RXCH7EN_SHIFT (0x00000007U)
+#define EMAC_RXUNICASTCLEAR_RXCH6EN (0x00000040U)
+#define EMAC_RXUNICASTCLEAR_RXCH6EN_SHIFT (0x00000006U)
+#define EMAC_RXUNICASTCLEAR_RXCH5EN (0x00000020U)
+#define EMAC_RXUNICASTCLEAR_RXCH5EN_SHIFT (0x00000005U)
+#define EMAC_RXUNICASTCLEAR_RXCH4EN (0x00000010U)
+#define EMAC_RXUNICASTCLEAR_RXCH4EN_SHIFT (0x00000004U)
+#define EMAC_RXUNICASTCLEAR_RXCH3EN (0x00000008U)
+#define EMAC_RXUNICASTCLEAR_RXCH3EN_SHIFT (0x00000003U)
+#define EMAC_RXUNICASTCLEAR_RXCH2EN (0x00000004U)
+#define EMAC_RXUNICASTCLEAR_RXCH2EN_SHIFT (0x00000002U)
+#define EMAC_RXUNICASTCLEAR_RXCH1EN (0x00000002U)
+#define EMAC_RXUNICASTCLEAR_RXCH1EN_SHIFT (0x00000001U)
+#define EMAC_RXUNICASTCLEAR_RXCH0EN (0x00000001U)
+#define EMAC_RXUNICASTCLEAR_RXCH0EN_SHIFT (0x00000000U)
+
+/* RXMAXLEN */
+
+
+#define EMAC_RXMAXLEN_RXMAXLEN  (0x0000FFFFU)
+#define EMAC_RXMAXLEN_RXMAXLEN_SHIFT (0x00000000U)
+
+
+/* RXBUFFEROFFSET */
+
+
+#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET (0x0000FFFFU)
+#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_SHIFT (0x00000000U)
+
+
+/* RXFILTERLOWTHRESH */
+
+
+#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH (0x000000FFU)
+#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_SHIFT (0x00000000U)
+
+
+/* RX0FLOWTHRESH */
+
+
+#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH (0x000000FFU)
+#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX1FLOWTHRESH */
+
+
+#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH (0x000000FFU)
+#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX2FLOWTHRESH */
+
+
+#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH (0x000000FFU)
+#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX3FLOWTHRESH */
+
+
+#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH (0x000000FFU)
+#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX4FLOWTHRESH */
+
+
+#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH (0x000000FFU)
+#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX5FLOWTHRESH */
+
+
+#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH (0x000000FFU)
+#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX6FLOWTHRESH */
+
+
+#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH (0x000000FFU)
+#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX7FLOWTHRESH */
+
+
+#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH (0x000000FFU)
+#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX0FREEBUFFER */
+
+
+#define EMAC_RX0FREEBUFFER_RX0FREEBUF (0x0000FFFFU)
+#define EMAC_RX0FREEBUFFER_RX0FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX1FREEBUFFER */
+
+
+#define EMAC_RX1FREEBUFFER_RX1FREEBUF (0x0000FFFFU)
+#define EMAC_RX1FREEBUFFER_RX1FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX2FREEBUFFER */
+
+
+#define EMAC_RX2FREEBUFFER_RX2FREEBUF (0x0000FFFFU)
+#define EMAC_RX2FREEBUFFER_RX2FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX3FREEBUFFER */
+
+
+#define EMAC_RX3FREEBUFFER_RX3FREEBUF (0x0000FFFFU)
+#define EMAC_RX3FREEBUFFER_RX3FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX4FREEBUFFER */
+
+
+#define EMAC_RX4FREEBUFFER_RX4FREEBUF (0x0000FFFFU)
+#define EMAC_RX4FREEBUFFER_RX4FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX5FREEBUFFER */
+
+
+#define EMAC_RX5FREEBUFFER_RX5FREEBUF (0x0000FFFFU)
+#define EMAC_RX5FREEBUFFER_RX5FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX6FREEBUFFER */
+
+
+#define EMAC_RX6FREEBUFFER_RX6FREEBUF (0x0000FFFFU)
+#define EMAC_RX6FREEBUFFER_RX6FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX7FREEBUFFER */
+
+
+#define EMAC_RX7FREEBUFFER_RX7FREEBUF (0x0000FFFFU)
+#define EMAC_RX7FREEBUFFER_RX7FREEBUF_SHIFT (0x00000000U)
+
+
+/* MACCONTROL */
+
+
+
+
+
+#define EMAC_MACCONTROL_RMIISPEED (0x00008000U)
+#define EMAC_MACCONTROL_RMIISPEED_SHIFT (0x0000000FU)
+#define EMAC_MACCONTROL_RXOFFLENBLOCK (0x00004000U)
+#define EMAC_MACCONTROL_RXOFFLENBLOCK_SHIFT (0x0000000EU)
+#define EMAC_MACCONTROL_RXOWNERSHIP (0x00002000U)
+#define EMAC_MACCONTROL_RXOWNERSHIP_SHIFT (0x0000000DU)
+#define EMAC_MACCONTROL_CMDIDLE (0x00000800U)
+#define EMAC_MACCONTROL_CMDIDLE_SHIFT (0x0000000BU)
+#define EMAC_MACCONTROL_TXSHORTGAPEN (0x00000400U)
+#define EMAC_MACCONTROL_TXSHORTGAPEN_SHIFT (0x0000000AU)
+#define EMAC_MACCONTROL_TXPTYPE (0x00000200U)
+#define EMAC_MACCONTROL_TXPTYPE_SHIFT (0x00000009U)
+#define EMAC_MACCONTROL_TXPACE  (0x00000040U)
+#define EMAC_MACCONTROL_TXPACE_SHIFT (0x00000006U)
+#define EMAC_MACCONTROL_GMIIEN  (0x00000020U)
+#define EMAC_MACCONTROL_GMIIEN_SHIFT (0x00000005U)
+#define EMAC_MACCONTROL_TXFLOWEN (0x00000010U)
+#define EMAC_MACCONTROL_TXFLOWEN_SHIFT (0x00000004U)
+#define EMAC_MACCONTROL_RXBUFFERFLOWEN (0x00000008U)
+#define EMAC_MACCONTROL_RXBUFFERFLOWEN_SHIFT (0x00000003U)
+#define EMAC_MACCONTROL_LOOPBACK (0x00000002U)
+#define EMAC_MACCONTROL_LOOPBACK_SHIFT (0x00000001U)
+#define EMAC_MACCONTROL_FULLDUPLEX (0x00000001U)
+#define EMAC_MACCONTROL_FULLDUPLEX_SHIFT (0x00000000U)
+
+
+/* MACSTATUS */
+
+#define EMAC_MACSTATUS_IDLE     (0x80000000U)
+#define EMAC_MACSTATUS_IDLE_SHIFT    (0x0000001FU)
+#define EMAC_MACSTATUS_TXERRCODE (0x00F00000U)
+#define EMAC_MACSTATUS_TXERRCODE_SHIFT (0x00000014U)
+/*----TXERRCODE Tokens----*/
+#define EMAC_MACSTATUS_TXERRCODE_NOERROR (0x00000000U)
+#define EMAC_MACSTATUS_TXERRCODE_SOPERROR (0x00000001U)
+#define EMAC_MACSTATUS_TXERRCODE_OWNERSHIP (0x00000002U)
+#define EMAC_MACSTATUS_TXERRCODE_NOEOP (0x00000003U)
+#define EMAC_MACSTATUS_TXERRCODE_NULLPTR (0x00000004U)
+#define EMAC_MACSTATUS_TXERRCODE_NULLEN (0x00000005U)
+#define EMAC_MACSTATUS_TXERRCODE_LENERROR (0x00000006U)
+
+
+#define EMAC_MACSTATUS_TXERRCH  (0x00070000U)
+#define EMAC_MACSTATUS_TXERRCH_SHIFT (0x00000010U)
+/*----TXERRCH Tokens----*/
+#define EMAC_MACSTATUS_TXERRCH_CHA0  (0x00000000U)
+#define EMAC_MACSTATUS_TXERRCH_CHA1  (0x00000001U)
+#define EMAC_MACSTATUS_TXERRCH_CHA2  (0x00000002U)
+#define EMAC_MACSTATUS_TXERRCH_CHA3  (0x00000003U)
+#define EMAC_MACSTATUS_TXERRCH_CHA4  (0x00000004U)
+#define EMAC_MACSTATUS_TXERRCH_CHA5  (0x00000005U)
+#define EMAC_MACSTATUS_TXERRCH_CHA6  (0x00000006U)
+#define EMAC_MACSTATUS_TXERRCH_CHA7  (0x00000007U)
+
+#define EMAC_MACSTATUS_RXERRCODE (0x0000F000U)
+#define EMAC_MACSTATUS_RXERRCODE_SHIFT (0x0000000CU)
+/*----RXERRCODE Tokens----*/
+#define EMAC_MACSTATUS_RXERRCODE_NOERROR (0x00000000U)
+#define EMAC_MACSTATUS_RXERRCODE_OWNERSHIP (0x00000002U)
+#define EMAC_MACSTATUS_RXERRCODE_NULLPTR (0x00000004U)
+
+
+#define EMAC_MACSTATUS_RXERRCH  (0x00000700U)
+#define EMAC_MACSTATUS_RXERRCH_SHIFT (0x00000008U)
+/*----RXERRCH Tokens----*/
+#define EMAC_MACSTATUS_RXERRCH_CHA0  (0x00000000U)
+#define EMAC_MACSTATUS_RXERRCH_CHA1  (0x00000001U)
+#define EMAC_MACSTATUS_RXERRCH_CHA2  (0x00000002U)
+#define EMAC_MACSTATUS_RXERRCH_CHA3  (0x00000003U)
+#define EMAC_MACSTATUS_RXERRCH_CHA4  (0x00000004U)
+#define EMAC_MACSTATUS_RXERRCH_CHA5  (0x00000005U)
+#define EMAC_MACSTATUS_RXERRCH_CHA6  (0x00000006U)
+#define EMAC_MACSTATUS_RXERRCH_CHA7  (0x00000007U)
+
+
+
+
+#define EMAC_MACSTATUS_RXQOSACT (0x00000004U)
+#define EMAC_MACSTATUS_RXQOSACT_SHIFT (0x00000002U)
+#define EMAC_MACSTATUS_RXFLOWACT (0x00000002U)
+#define EMAC_MACSTATUS_RXFLOWACT_SHIFT (0x00000001U)
+#define EMAC_MACSTATUS_TXFLOWACT (0x00000001U)
+#define EMAC_MACSTATUS_TXFLOWACT_SHIFT (0x00000000U)
+
+/* EMCONTROL */
+
+
+#define EMAC_EMCONTROL_SOFT     (0x00000002U)
+#define EMAC_EMCONTROL_SOFT_SHIFT    (0x00000001U)
+
+#define EMAC_EMCONTROL_FREE     (0x00000001U)
+#define EMAC_EMCONTROL_FREE_SHIFT    (0x00000000U)
+
+
+/* FIFOCONTROL */
+
+
+#define EMAC_FIFOCONTROL_TXCELLTHRESH (0x00000003U)
+#define EMAC_FIFOCONTROL_TXCELLTHRESH_SHIFT (0x00000000U)
+
+
+/* MACCONFIG */
+
+#define EMAC_MACCONFIG_TXCELLDEPTH (0xFF000000U)
+#define EMAC_MACCONFIG_TXCELLDEPTH_SHIFT (0x00000018U)
+
+#define EMAC_MACCONFIG_RXCELLDEPTH (0x00FF0000U)
+#define EMAC_MACCONFIG_RXCELLDEPTH_SHIFT (0x00000010U)
+
+#define EMAC_MACCONFIG_ADDRESSTYPE (0x0000FF00U)
+#define EMAC_MACCONFIG_ADDRESSTYPE_SHIFT (0x00000008U)
+
+#define EMAC_MACCONFIG_MACCFIG  (0x000000FFU)
+#define EMAC_MACCONFIG_MACCFIG_SHIFT (0x00000000U)
+
+
+/* SOFTRESET */
+
+
+#define EMAC_SOFTRESET_SOFTRESET (0x00000001U)
+#define EMAC_SOFTRESET_SOFTRESET_SHIFT (0x00000000U)
+
+/* MACSRCADDRLO */
+
+
+#define EMAC_MACSRCADDRLO_MACSRCADDR0 (0x0000FF00U)
+#define EMAC_MACSRCADDRLO_MACSRCADDR0_SHIFT (0x00000008U)
+#define EMAC_MACSRCADDRLO_MACSRCADDR1 (0x000000FFU)
+#define EMAC_MACSRCADDRLO_MACSRCADDR1_SHIFT (0x00000000U)
+
+
+/* MACSRCADDRHI */
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR2 (0xFF000000U)
+#define EMAC_MACSRCADDRHI_MACSRCADDR2_SHIFT (0x00000018U)
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR3 (0x00FF0000U)
+#define EMAC_MACSRCADDRHI_MACSRCADDR3_SHIFT (0x00000010U)
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR4 (0x0000FF00U)
+#define EMAC_MACSRCADDRHI_MACSRCADDR4_SHIFT (0x00000008U)
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR5 (0x000000FFU)
+#define EMAC_MACSRCADDRHI_MACSRCADDR5_SHIFT (0x00000000U)
+
+
+/* MACHASH1 */
+
+#define EMAC_MACHASH1_MACHASH1  (0xFFFFFFFFU)
+#define EMAC_MACHASH1_MACHASH1_SHIFT (0x00000000U)
+
+
+/* MACHASH2 */
+
+#define EMAC_MACHASH2_MACHASH2  (0xFFFFFFFFU)
+#define EMAC_MACHASH2_MACHASH2_SHIFT (0x00000000U)
+
+
+/* BOFFTEST */
+
+
+#define EMAC_BOFFTEST_RNDNUM    (0x03FF0000U)
+#define EMAC_BOFFTEST_RNDNUM_SHIFT   (0x00000010U)
+
+#define EMAC_BOFFTEST_COLLCOUNT (0x0000F000U)
+#define EMAC_BOFFTEST_COLLCOUNT_SHIFT (0x0000000CU)
+
+
+#define EMAC_BOFFTEST_TXBACKOFF (0x000003FFU)
+#define EMAC_BOFFTEST_TXBACKOFF_SHIFT (0x00000000U)
+
+
+/* TPACETEST */
+
+
+#define EMAC_TPACETEST_PACEVAL  (0x0000001FU)
+#define EMAC_TPACETEST_PACEVAL_SHIFT (0x00000000U)
+
+
+/* RXPAUSE */
+
+
+#define EMAC_RXPAUSE_PAUSETIMER (0x0000FFFFU)
+#define EMAC_RXPAUSE_PAUSETIMER_SHIFT (0x00000000U)
+
+
+/* TXPAUSE */
+
+
+#define EMAC_TXPAUSE_PAUSETIMER (0x0000FFFFU)
+#define EMAC_TXPAUSE_PAUSETIMER_SHIFT (0x00000000U)
+
+
+/* RXGOODFRAMES */
+
+#define EMAC_RXGOODFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXGOODFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXBCASTFRAMES */
+
+#define EMAC_RXBCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXBCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXMCASTFRAMES */
+
+#define EMAC_RXMCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXMCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXPAUSEFRAMES */
+
+#define EMAC_RXPAUSEFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXPAUSEFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXCRCERRORS */
+
+#define EMAC_RXCRCERRORS_COUNT  (0xFFFFFFFFU)
+#define EMAC_RXCRCERRORS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXALIGNCODEERRORS */
+
+#define EMAC_RXALIGNCODEERRORS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXALIGNCODEERRORS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXOVERSIZED */
+
+#define EMAC_RXOVERSIZED_COUNT  (0xFFFFFFFFU)
+#define EMAC_RXOVERSIZED_COUNT_SHIFT (0x00000000U)
+
+
+/* RXJABBER */
+
+#define EMAC_RXJABBER_COUNT     (0xFFFFFFFFU)
+#define EMAC_RXJABBER_COUNT_SHIFT    (0x00000000U)
+
+
+/* RXUNDERSIZED */
+
+#define EMAC_RXUNDERSIZED_COUNT (0xFFFFFFFFU)
+#define EMAC_RXUNDERSIZED_COUNT_SHIFT (0x00000000U)
+
+
+/* RXFRAGMENTS */
+
+#define EMAC_RXFRAGMENTS_COUNT  (0xFFFFFFFFU)
+#define EMAC_RXFRAGMENTS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXFILTERED */
+
+#define EMAC_RXFILTERED_COUNT   (0xFFFFFFFFU)
+#define EMAC_RXFILTERED_COUNT_SHIFT  (0x00000000U)
+
+
+/* RXQOSFILTERED */
+
+#define EMAC_RXQOSFILTERED_COUNT (0xFFFFFFFFU)
+#define EMAC_RXQOSFILTERED_COUNT_SHIFT (0x00000000U)
+
+
+/* RXOCTETS */
+
+#define EMAC_RXOCTETS_COUNT     (0xFFFFFFFFU)
+#define EMAC_RXOCTETS_COUNT_SHIFT    (0x00000000U)
+
+
+/* TXGOODFRAMES */
+
+#define EMAC_TXGOODFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXGOODFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXBCASTFRAMES */
+
+#define EMAC_TXBCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXBCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXMCASTFRAMES */
+
+#define EMAC_TXMCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXMCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXPAUSEFRAMES */
+
+#define EMAC_TXPAUSEFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXPAUSEFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXDEFERRED */
+
+#define EMAC_TXDEFERRED_COUNT   (0xFFFFFFFFU)
+#define EMAC_TXDEFERRED_COUNT_SHIFT  (0x00000000U)
+
+
+/* TXCOLLISION */
+
+#define EMAC_TXCOLLISION_COUNT  (0xFFFFFFFFU)
+#define EMAC_TXCOLLISION_COUNT_SHIFT (0x00000000U)
+
+
+/* TXSINGLECOLL */
+
+#define EMAC_TXSINGLECOLL_COUNT (0xFFFFFFFFU)
+#define EMAC_TXSINGLECOLL_COUNT_SHIFT (0x00000000U)
+
+
+/* TXMULTICOLL */
+
+#define EMAC_TXMULTICOLL_COUNT  (0xFFFFFFFFU)
+#define EMAC_TXMULTICOLL_COUNT_SHIFT (0x00000000U)
+
+
+/* TXEXCESSIVECOLL */
+
+#define EMAC_TXEXCESSIVECOLL_COUNT (0xFFFFFFFFU)
+#define EMAC_TXEXCESSIVECOLL_COUNT_SHIFT (0x00000000U)
+
+
+/* TXLATECOLL */
+
+#define EMAC_TXLATECOLL_COUNT   (0xFFFFFFFFU)
+#define EMAC_TXLATECOLL_COUNT_SHIFT  (0x00000000U)
+
+
+/* TXUNDERRUN */
+
+#define EMAC_TXUNDERRUN_COUNT   (0xFFFFFFFFU)
+#define EMAC_TXUNDERRUN_COUNT_SHIFT  (0x00000000U)
+
+
+/* TXCARRIERSENSE */
+
+#define EMAC_TXCARRIERSENSE_COUNT (0xFFFFFFFFU)
+#define EMAC_TXCARRIERSENSE_COUNT_SHIFT (0x00000000U)
+
+
+/* TXOCTETS */
+
+#define EMAC_TXOCTETS_COUNT     (0xFFFFFFFFU)
+#define EMAC_TXOCTETS_COUNT_SHIFT    (0x00000000U)
+
+
+/* FRAME64 */
+
+#define EMAC_FRAME64_COUNT      (0xFFFFFFFFU)
+#define EMAC_FRAME64_COUNT_SHIFT     (0x00000000U)
+
+
+/* FRAME65T127 */
+
+#define EMAC_FRAME65T127_COUNT  (0xFFFFFFFFU)
+#define EMAC_FRAME65T127_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME128T255 */
+
+#define EMAC_FRAME128T255_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME128T255_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME256T511 */
+
+#define EMAC_FRAME256T511_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME256T511_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME512T1023 */
+
+#define EMAC_FRAME512T1023_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME512T1023_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME1024TUP */
+
+#define EMAC_FRAME1024TUP_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME1024TUP_COUNT_SHIFT (0x00000000U)
+
+
+/* NETOCTETS */
+
+#define EMAC_NETOCTETS_COUNT    (0xFFFFFFFFU)
+#define EMAC_NETOCTETS_COUNT_SHIFT   (0x00000000U)
+
+
+/* RXSOFOVERRUNS */
+
+#define EMAC_RXSOFOVERRUNS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXSOFOVERRUNS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXMOFOVERRUNS */
+
+#define EMAC_RXMOFOVERRUNS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXMOFOVERRUNS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXDMAOVERRUNS */
+
+#define EMAC_RXDMAOVERRUNS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXDMAOVERRUNS_COUNT_SHIFT (0x00000000U)
+
+
+/* MACADDRLO */
+
+
+#define EMAC_MACADDRLO_VALID    (0x00100000U)
+#define EMAC_MACADDRLO_VALID_SHIFT   (0x00000014U)
+#define EMAC_MACADDRLO_MATCHFILT (0x00080000U)
+#define EMAC_MACADDRLO_MATCHFILT_SHIFT (0x00000013U)
+#define EMAC_MACADDRLO_CHANNEL  (0x00070000U)
+#define EMAC_MACADDRLO_CHANNEL_SHIFT (0x00000010U)
+#define EMAC_MACADDRLO_MACADDR0 (0x0000FF00U)
+#define EMAC_MACADDRLO_MACADDR0_SHIFT (0x00000008U)
+#define EMAC_MACADDRLO_MACADDR1 (0x000000FFU)
+#define EMAC_MACADDRLO_MACADDR1_SHIFT (0x00000000U)
+
+
+/* MACADDRHI */
+
+#define EMAC_MACADDRHI_MACADDR2 (0xFF000000U)
+#define EMAC_MACADDRHI_MACADDR2_SHIFT (0x00000018U)
+
+#define EMAC_MACADDRHI_MACADDR3 (0x00FF0000U)
+#define EMAC_MACADDRHI_MACADDR3_SHIFT (0x00000010U)
+
+#define EMAC_MACADDRHI_MACADDR4 (0x0000FF00U)
+#define EMAC_MACADDRHI_MACADDR4_SHIFT (0x00000008U)
+
+#define EMAC_MACADDRHI_MACADDR5 (0x000000FFU)
+#define EMAC_MACADDRHI_MACADDR5_SHIFT (0x00000000U)
+
+
+/* MACINDEX */
+
+
+#define EMAC_MACINDEX_MACINDEX  (0x0000001FU)
+#define EMAC_MACINDEX_MACINDEX_SHIFT (0x00000000U)
+
+
+/* TX0HDP */
+
+#define EMAC_TX0HDP_TX0HDP      (0xFFFFFFFFU)
+#define EMAC_TX0HDP_TX0HDP_SHIFT     (0x00000000U)
+
+
+/* TX1HDP */
+
+#define EMAC_TX1HDP_TX1HDP      (0xFFFFFFFFU)
+#define EMAC_TX1HDP_TX1HDP_SHIFT     (0x00000000U)
+
+
+/* TX2HDP */
+
+#define EMAC_TX2HDP_TX2HDP      (0xFFFFFFFFU)
+#define EMAC_TX2HDP_TX2HDP_SHIFT     (0x00000000U)
+
+
+/* TX3HDP */
+
+#define EMAC_TX3HDP_TX3HDP      (0xFFFFFFFFU)
+#define EMAC_TX3HDP_TX3HDP_SHIFT     (0x00000000U)
+
+
+/* TX4HDP */
+
+#define EMAC_TX4HDP_TX4HDP      (0xFFFFFFFFU)
+#define EMAC_TX4HDP_TX4HDP_SHIFT     (0x00000000U)
+
+
+/* TX5HDP */
+
+#define EMAC_TX5HDP_TX5HDP      (0xFFFFFFFFU)
+#define EMAC_TX5HDP_TX5HDP_SHIFT     (0x00000000U)
+
+
+/* TX6HDP */
+
+#define EMAC_TX6HDP_TX6HDP      (0xFFFFFFFFU)
+#define EMAC_TX6HDP_TX6HDP_SHIFT     (0x00000000U)
+
+
+/* TX7HDP */
+
+#define EMAC_TX7HDP_TX7HDP      (0xFFFFFFFFU)
+#define EMAC_TX7HDP_TX7HDP_SHIFT     (0x00000000U)
+
+
+/* RX0HDP */
+
+#define EMAC_RX0HDP_RX0HDP      (0xFFFFFFFFU)
+#define EMAC_RX0HDP_RX0HDP_SHIFT     (0x00000000U)
+
+
+/* RX1HDP */
+
+#define EMAC_RX1HDP_RX1HDP      (0xFFFFFFFFU)
+#define EMAC_RX1HDP_RX1HDP_SHIFT     (0x00000000U)
+
+
+/* RX2HDP */
+
+#define EMAC_RX2HDP_RX2HDP      (0xFFFFFFFFU)
+#define EMAC_RX2HDP_RX2HDP_SHIFT     (0x00000000U)
+
+
+/* RX3HDP */
+
+#define EMAC_RX3HDP_RX3HDP      (0xFFFFFFFFU)
+#define EMAC_RX3HDP_RX3HDP_SHIFT     (0x00000000U)
+
+
+/* RX4HDP */
+
+#define EMAC_RX4HDP_RX4HDP      (0xFFFFFFFFU)
+#define EMAC_RX4HDP_RX4HDP_SHIFT     (0x00000000U)
+
+
+/* RX5HDP */
+
+#define EMAC_RX5HDP_RX5HDP      (0xFFFFFFFFU)
+#define EMAC_RX5HDP_RX5HDP_SHIFT     (0x00000000U)
+
+
+/* RX6HDP */
+
+#define EMAC_RX6HDP_RX6HDP      (0xFFFFFFFFU)
+#define EMAC_RX6HDP_RX6HDP_SHIFT     (0x00000000U)
+
+
+/* RX7HDP */
+
+#define EMAC_RX7HDP_RX7HDP      (0xFFFFFFFFU)
+#define EMAC_RX7HDP_RX7HDP_SHIFT     (0x00000000U)
+
+
+/* TX0CP */
+
+#define EMAC_TX0CP_TX0CP        (0xFFFFFFFFU)
+#define EMAC_TX0CP_TX0CP_SHIFT       (0x00000000U)
+
+
+/* TX1CP */
+
+#define EMAC_TX1CP_TX1CP        (0xFFFFFFFFU)
+#define EMAC_TX1CP_TX1CP_SHIFT       (0x00000000U)
+
+
+/* TX2CP */
+
+#define EMAC_TX2CP_TX2CP        (0xFFFFFFFFU)
+#define EMAC_TX2CP_TX2CP_SHIFT       (0x00000000U)
+
+
+/* TX3CP */
+
+#define EMAC_TX3CP_TX3CP        (0xFFFFFFFFU)
+#define EMAC_TX3CP_TX3CP_SHIFT       (0x00000000U)
+
+
+/* TX4CP */
+
+#define EMAC_TX4CP_TX4CP        (0xFFFFFFFFU)
+#define EMAC_TX4CP_TX4CP_SHIFT       (0x00000000U)
+
+
+/* TX5CP */
+
+#define EMAC_TX5CP_TX5CP        (0xFFFFFFFFU)
+#define EMAC_TX5CP_TX5CP_SHIFT       (0x00000000U)
+
+
+/* TX6CP */
+
+#define EMAC_TX6CP_TX6CP        (0xFFFFFFFFU)
+#define EMAC_TX6CP_TX6CP_SHIFT       (0x00000000U)
+
+
+/* TX7CP */
+
+#define EMAC_TX7CP_TX7CP        (0xFFFFFFFFU)
+#define EMAC_TX7CP_TX7CP_SHIFT       (0x00000000U)
+
+
+/* RX0CP */
+
+#define EMAC_RX0CP_RX0CP        (0xFFFFFFFFU)
+#define EMAC_RX0CP_RX0CP_SHIFT       (0x00000000U)
+
+
+/* RX1CP */
+
+#define EMAC_RX1CP_RX1CP        (0xFFFFFFFFU)
+#define EMAC_RX1CP_RX1CP_SHIFT       (0x00000000U)
+
+
+/* RX2CP */
+
+#define EMAC_RX2CP_RX2CP        (0xFFFFFFFFU)
+#define EMAC_RX2CP_RX2CP_SHIFT       (0x00000000U)
+
+
+/* RX3CP */
+
+#define EMAC_RX3CP_RX3CP        (0xFFFFFFFFU)
+#define EMAC_RX3CP_RX3CP_SHIFT       (0x00000000U)
+
+
+/* RX4CP */
+
+#define EMAC_RX4CP_RX4CP        (0xFFFFFFFFU)
+#define EMAC_RX4CP_RX4CP_SHIFT       (0x00000000U)
+
+
+/* RX5CP */
+
+#define EMAC_RX5CP_RX5CP        (0xFFFFFFFFU)
+#define EMAC_RX5CP_RX5CP_SHIFT       (0x00000000U)
+
+
+/* RX6CP */
+
+#define EMAC_RX6CP_RX6CP        (0xFFFFFFFFU)
+#define EMAC_RX6CP_RX6CP_SHIFT       (0x00000000U)
+
+
+/* RX7CP */
+
+#define EMAC_RX7CP_RX7CP        (0xFFFFFFFFU)
+#define EMAC_RX7CP_RX7CP_SHIFT       (0x00000000U)
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/hw_emac_ctrl.h b/include/arch/rm46l8lp/halcogen/hw_emac_ctrl.h
new file mode 100644
index 0000000..b13b1ff
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/hw_emac_ctrl.h
@@ -0,0 +1,91 @@
+/*
+ * hw_emac1.h
+ */
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_EMAC_CTRL_H_
+#define _HW_EMAC_CTRL_H_
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#define EMAC_CTRL_REVID              (0x0U)
+#define EMAC_CTRL_SOFTRESET          (0x4U)
+#define EMAC_CTRL_INTCONTROL         (0xCU)
+#define EMAC_CTRL_C0RXTHRESHEN       (0x10U)
+#define EMAC_CTRL_CnRXEN(n)          ((uint32)0x14u + (uint32)((uint32)(n) << 4))
+#define EMAC_CTRL_CnTXEN(n)          ((uint32)0x18u + (uint32)((uint32)(n) << 4))
+#define EMAC_CTRL_CnMISCEN(n)        ((uint32)0x1Cu + (uint32)((uint32)(n) << 4))
+#define EMAC_CTRL_CnRXTHRESHEN(n)    ((uint32)0x20u + (uint32)((uint32)(n) << 4))
+#define EMAC_CTRL_C0RXTHRESHSTAT     (0x40U)
+#define EMAC_CTRL_C0RXSTAT           (0x44U)
+#define EMAC_CTRL_C0TXSTAT           (0x48U)
+#define EMAC_CTRL_C0MISCSTAT         (0x4CU)
+#define EMAC_CTRL_C1RXTHRESHSTAT     (0x50U)
+#define EMAC_CTRL_C1RXSTAT           (0x54U)
+#define EMAC_CTRL_C1TXSTAT           (0x58U)
+#define EMAC_CTRL_C1MISCSTAT         (0x5CU)
+#define EMAC_CTRL_C2RXTHRESHSTAT     (0x60U)
+#define EMAC_CTRL_C2RXSTAT           (0x64U)
+#define EMAC_CTRL_C2TXSTAT           (0x68U)
+#define EMAC_CTRL_C2MISCSTAT         (0x6CU)
+#define EMAC_CTRL_C0RXIMAX           (0x70U)
+#define EMAC_CTRL_C0TXIMAX           (0x74U)
+#define EMAC_CTRL_C1RXIMAX           (0x78U)
+#define EMAC_CTRL_C1TXIMAX           (0x7CU)
+#define EMAC_CTRL_C2RXIMAX           (0x80U)
+#define EMAC_CTRL_C2TXIMAX           (0x84U)
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/hw_mdio.h b/include/arch/rm46l8lp/halcogen/hw_mdio.h
new file mode 100644
index 0000000..0f0393d
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/hw_mdio.h
@@ -0,0 +1,264 @@
+/*
+ * hw_mdio.h
+ */
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_MDIO_H_
+#define _HW_MDIO_H_
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#define MDIO_BASE               (0xFCF78900U)
+
+#define MDIO_REVID		        (0x0U)
+#define MDIO_CONTROL		    (0x4U)
+#define MDIO_ALIVE		        (0x8U)
+#define MDIO_LINK		        (0xCU)
+#define MDIO_LINKINTRAW		    (0x10U)
+#define MDIO_LINKINTMASKED	    (0x14U)
+#define MDIO_USERINTRAW		    (0x20U)
+#define MDIO_USERINTMASKED	    (0x24U)
+#define MDIO_USERINTMASKSET	    (0x28U)
+#define MDIO_USERINTMASKCLEAR	(0x2CU)
+#define MDIO_USERACCESS0	    (0x80U)
+#define MDIO_USERPHYSEL0	    (0x84U)
+#define MDIO_USERACCESS1	    (0x88U)
+#define MDIO_USERPHYSEL1	    (0x8CU)
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* REVID */
+
+#define MDIO_REVID_REV (0xFFFFFFFFU)
+#define MDIO_REVID_REV_SHIFT (0x00000000U)
+
+
+/* CONTROL */
+
+#define MDIO_CONTROL_IDLE (0x80000000U)
+#define MDIO_CONTROL_IDLE_SHIFT (0x0000001FU)
+/*----IDLE Tokens----*/
+#define MDIO_CONTROL_IDLE_NO (0x00000000U)
+#define MDIO_CONTROL_IDLE_YES (0x00000001U)
+
+#define MDIO_CONTROL_ENABLE (0x40000000U)
+#define MDIO_CONTROL_ENABLE_SHIFT (0x0000001EU)
+
+#define MDIO_CONTROL_HIGHEST_USER_CHANNEL (0x1F000000U)
+#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT (0x00000018U)
+
+
+#define MDIO_CONTROL_PREAMBLE (0x00100000U)
+#define MDIO_CONTROL_PREAMBLE_SHIFT (0x00000014U)
+/*----PREAMBLE Tokens----*/
+
+#define MDIO_CONTROL_FAULT (0x00080000U)
+#define MDIO_CONTROL_FAULT_SHIFT (0x00000013U)
+
+#define MDIO_CONTROL_FAULTENB (0x00040000U)
+#define MDIO_CONTROL_FAULTENB_SHIFT (0x00000012U)
+/*----FAULTENB Tokens----*/
+
+
+
+#define MDIO_CONTROL_CLKDIV (0x0000FFFFU)
+#define MDIO_CONTROL_CLKDIV_SHIFT (0x00000000U)
+/*----CLKDIV Tokens----*/
+
+
+/* ALIVE */
+
+#define MDIO_ALIVE_REGVAL (0xFFFFFFFFU)
+#define MDIO_ALIVE_REGVAL_SHIFT (0x00000000U)
+
+
+/* LINK */
+
+#define MDIO_LINK_REGVAL (0xFFFFFFFFU)
+#define MDIO_LINK_REGVAL_SHIFT (0x00000000U)
+
+
+/* LINKINTRAW */
+
+
+#define MDIO_LINKINTRAW_USERPHY1 (0x00000002U)
+#define MDIO_LINKINTRAW_USERPHY1_SHIFT (0x00000001U)
+
+#define MDIO_LINKINTRAW_USERPHY0 (0x00000001U)
+#define MDIO_LINKINTRAW_USERPHY0_SHIFT (0x00000000U)
+
+
+/* LINKINTMASKED */
+
+
+#define MDIO_LINKINTMASKED_USERPHY1 (0x00000002U)
+#define MDIO_LINKINTMASKED_USERPHY1_SHIFT (0x00000001U)
+
+#define MDIO_LINKINTMASKED_USERPHY0 (0x00000001U)
+#define MDIO_LINKINTMASKED_USERPHY0_SHIFT (0x00000000U)
+
+
+/* USERINTRAW */
+
+
+#define MDIO_USERINTRAW_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTRAW_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTRAW_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTRAW_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERINTMASKED */
+
+
+#define MDIO_USERINTMASKED_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTMASKED_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTMASKED_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTMASKED_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERINTMASKSET */
+
+
+#define MDIO_USERINTMASKSET_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTMASKSET_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERINTMASKCLEAR */
+
+
+#define MDIO_USERINTMASKCLEAR_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTMASKCLEAR_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERACCESS0 */
+
+#define MDIO_USERACCESS0_GO (0x80000000U)
+#define MDIO_USERACCESS0_GO_SHIFT (0x0000001FU)
+
+#define MDIO_USERACCESS0_WRITE (0x40000000U)
+#define MDIO_USERACCESS0_READ  (0x00000000U)
+#define MDIO_USERACCESS0_WRITE_SHIFT (0x0000001EU)
+
+#define MDIO_USERACCESS0_ACK (0x20000000U)
+#define MDIO_USERACCESS0_ACK_SHIFT (0x0000001DU)
+
+
+#define MDIO_USERACCESS0_REGADR (0x03E00000U)
+#define MDIO_USERACCESS0_REGADR_SHIFT (0x00000015U)
+
+#define MDIO_USERACCESS0_PHYADR (0x001F0000U)
+#define MDIO_USERACCESS0_PHYADR_SHIFT (0x00000010U)
+
+#define MDIO_USERACCESS0_DATA (0x0000FFFFU)
+#define MDIO_USERACCESS0_DATA_SHIFT (0x00000000U)
+
+
+/* USERPHYSEL0 */
+
+
+#define MDIO_USERPHYSEL0_LINKSEL (0x00000080U)
+#define MDIO_USERPHYSEL0_LINKSEL_SHIFT (0x00000007U)
+
+#define MDIO_USERPHYSEL0_LINKINTENB (0x00000040U)
+#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT (0x00000006U)
+
+
+#define MDIO_USERPHYSEL0_PHYADRMON (0x0000001FU)
+#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT (0x00000000U)
+
+
+/* USERACCESS1 */
+
+#define MDIO_USERACCESS1_GO (0x80000000U)
+#define MDIO_USERACCESS1_GO_SHIFT (0x0000001FU)
+
+#define MDIO_USERACCESS1_WRITE (0x40000000U)
+#define MDIO_USERACCESS1_WRITE_SHIFT (0x0000001EU)
+
+#define MDIO_USERACCESS1_ACK (0x20000000U)
+#define MDIO_USERACCESS1_ACK_SHIFT (0x0000001DU)
+
+
+#define MDIO_USERACCESS1_REGADR (0x03E00000U)
+#define MDIO_USERACCESS1_REGADR_SHIFT (0x00000015U)
+
+#define MDIO_USERACCESS1_PHYADR (0x001F0000U)
+#define MDIO_USERACCESS1_PHYADR_SHIFT (0x00000010U)
+
+#define MDIO_USERACCESS1_DATA (0x0000FFFFU)
+#define MDIO_USERACCESS1_DATA_SHIFT (0x00000000U)
+
+
+/* USERPHYSEL1 */
+
+
+#define MDIO_USERPHYSEL1_LINKSEL (0x00000080U)
+#define MDIO_USERPHYSEL1_LINKSEL_SHIFT (0x00000007U)
+
+#define MDIO_USERPHYSEL1_LINKINTENB (0x00000040U)
+#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT (0x00000006U)
+
+
+#define MDIO_USERPHYSEL1_PHYADRMON (0x0000001FU)
+#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT (0x00000000U)
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/hw_reg_access.h b/include/arch/rm46l8lp/halcogen/hw_reg_access.h
new file mode 100644
index 0000000..428dce9
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/hw_reg_access.h
@@ -0,0 +1,81 @@
+/*
+ * hw_reg_access.h
+ */
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_REG_ACCESS_H_
+#define _HW_REG_ACCESS_H_
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/*******************************************************************************
+*
+* Macros for hardware access, both direct and via the bit-band region.
+*
+*****************************************************************************/
+#define HWREG(x)                                                              \
+        (*((volatile uint32 *)(x)))
+#define HWREGH(x)                                                             \
+        (*((volatile uint16 *)(x)))
+#define HWREGB(x)                                                             \
+        (*((volatile uint8 *)(x)))
+#define HWREGBITW(x, b)                                                       \
+        (HWREG(((uint32)(x) & 0xF0000000U) | (uint32)0x02000000U |                \
+              (((uint32)(x) & 0x000FFFFFU) << 5U) | (uint32)((uint32)(b) << 2U)))
+#define HWREGBITH(x, b)                                                       \
+        (HWREGH(((uint32)(x) & 0xF0000000U) | (uint32)0x02000000U |               \
+               (((uint32)(x) & 0x000FFFFFU) << 5U) | (uint32)((uint32)(b) << 2U)))
+#define HWREGBITB(x, b)                                                       \
+        (HWREGB(((uint32)(x) & 0xF0000000U) | (uint32)0x02000000U |               \
+               (((uint32)(x) & 0x000FFFFFU) << 5U) | (uint32)((uint32)(b) << 2U)))
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HW_TYPES_H__ */
diff --git a/include/arch/rm46l8lp/halcogen/hw_usb.h b/include/arch/rm46l8lp/halcogen/hw_usb.h
new file mode 100644
index 0000000..4baf327
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/hw_usb.h
@@ -0,0 +1,276 @@
+/******************************************************************************
+ *
+ * hw_usb.h - Macros for use in accessing the USB registers.
+ *
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __HW_USB_H__
+#define __HW_USB_H__
+
+/** @brief Base address of memmory mapped Registers                           */
+#define USBD_0_BASE         0xFCF78A00u
+#define USB0_BASE           USBD_0_BASE
+
+typedef volatile struct {
+    uint16 rev;         /* Revision                                   */
+    
+    /** Endpoint registers  ***************************************************/
+    uint16 epnum;           /* Endpoint selection                     */
+    uint16 data;            /* Data                                   */
+    uint16 ctrl;            /* Control                                */
+    uint16 stat_flag;       /* Status                                 */
+    uint16 rxf_stat;        /* RX FIFO Status                         */
+    uint16 syscon1;         /* System configuration 1                 */
+    uint16 syscon2;         /* System configuration 2                 */
+    uint16 dev_stat;        /* Device status                          */
+    uint16 sof;             /* Start of frame                         */
+    uint16 irq_en;          /* Interrupt enable                       */
+    uint16 dma_irqen;       /* DMA Interrupt enable                   */
+    uint16 irqsrc;          /* Interrupt source                       */
+    uint16 epn_stat;        /* Non-ISO EP interrupt enable            */
+    uint16 dman_stat;       /* Non-ISO DMA interrupt enable           */
+    uint16 _rsvd1[1];       /* Reserved for reg holes                 */
+    
+    /** DMA Configuration   ***************************************************/
+    uint16 rxdma_cfg;       /* DMA Rx channels configuration          */
+    uint16 txdma_cfg;       /* DMA Tx channels configuration          */
+    uint16 data_dma;        /* DMA FIFO data                          */
+    uint16 txdma0;          /* Transmit DMA control 0                 */
+    uint16 txdma1;          /* Transmit DMA control 1                 */
+    uint16 txdma2;          /* Transmit DMA control 2                 */
+    uint16 _rsvd2[2];       /* Reserved for reg holes                 */
+    
+    uint16 dman_rxdma0;     /* Receive DMA control 0                  */
+    uint16 dman_rxdma1;     /* Receive DMA control 1                  */
+    uint16 dman_rxdma2;     /* Receive DMA control 2                  */
+    uint16 _rsvd3[5];       /* Reserved                               */
+
+    /** Endpoint Configuration  ***********************************************/
+    uint16 ep0;             /* Endpoint 0 Configuration               */
+
+    uint16 epn_rx[15];      /* RX EP configurations...                */
+    uint16 _rsvd4[1];       /* Reserved for reg holes                 */
+    
+    uint16 epn_tx[15];      /* TX EP configurations...                */
+} usbdRegs;
+
+/******************************************************************************\
+* Register Bit Masks 
+* (USBD_<Instance ID=0>_<Register Name>_<Bit Field Name> <Mask Value>
+\******************************************************************************/
+
+/* Endpoint selection *********************************************************/
+#define USBD_EP_NUM_SETUP_SEL                   (0x0040u)
+#define USBD_EP_NUM_EP_SEL                      (0x0020u)
+#define USBD_EP_NUM_EP_DIR                      (0x0010u)
+#define USBD_EP_NUM_EP_NUM_MASK                 (0x000Fu)
+
+/* Data ***********************************************************************/
+#define USBD_DATA_DATA                          (0xFFFFu)
+
+/* Control ********************************************************************/
+#define USBD_CTRL_CLR_HALT                      (0x0080u)
+#define USBD_CTRL_SET_HALT                      (0x0040u)
+#define USBD_CTRL_SET_FIFO_EN                   (0x0004u)
+#define USBD_CTRL_CLR_EP                        (0x0002u)
+#define USBD_CTRL_RESET_EP                      (0x0001u)
+
+/* Status *********************************************************************/
+#define USBD_STAT_FLG_NO_RXPACKET               (0x8000u)
+#define USBD_STAT_FLG_MISS_IN                   (0x4000u)
+#define USBD_STAT_FLG_DATA_FLUSH                (0x2000u)
+#define USBD_STAT_FLG_ISO_ERR                   (0x1000u)
+#define USBD_STAT_FLG_ISO_FIFO_EMPTY            (0x0200u)
+#define USBD_STAT_FLG_ISO_FIFO_FULL             (0x0100u)
+#define USBD_STAT_FLG_EP_HALTED                 (0x0040u)
+#define USBD_STAT_FLG_STALL                     (0x0020u)
+#define USBD_STAT_FLG_NAK                       (0x0010u)
+#define USBD_STAT_FLG_ACK                       (0x0008u)
+#define USBD_STAT_FLG_FIFO_EN                   (0x0004u)
+#define USBD_STAT_FLG_NON_ISO_FIFO_EMPTY        (0x0002u)
+#define USBD_STAT_FLG_NON_ISO_FIFO_FULL         (0x0001u)
+
+/* RX FIFO Status                    */
+#define USBD_RXFSTAT_RXF_COUNT                  (0x03FFu)
+
+/* System configuration 1 *****************************************************/
+#define USBD_SYSCON1_CFG_LOCK                   (0x0100u)
+#define USBD_SYSCON1_DATA_ENDIAN                (0x0080u)
+#define USBD_SYSCON1_DMA_ENDIAN                 (0x0040u)
+#define USBD_SYSCON1_NAK_EN                     (0x0010u)
+#define USBD_SYSCON1_AUTODEC_DIS                (0x0008u)
+#define USBD_SYSCON1_SELF_PWR                   (0x0004u)
+#define USBD_SYSCON1_SOFF_DIS                   (0x0002u)
+#define USBD_SYSCON1_PULLUP_EN                  (0x0001u)
+
+/* System configuration 2 *****************************************************/
+#define USBD_SYSCON2_RMT_WKP                    (0x0040u)
+#define USBD_SYSCON2_STALL_CMD                  (0x0020u)
+#define USBD_SYSCON2_DEV_CFG                    (0x0008u)
+#define USBD_SYSCON2_CLR_CFG                    (0x0004u)
+
+/* Device status **************************************************************/
+#define USBD_DEVSTAT_B_HNP_ENABLE               (0x0200u)
+#define USBD_DEVSTAT_A_HNP_SUPPORT              (0x0100u)
+#define USBD_DEVSTAT_A_ALT_HNP_SUPPORT          (0x0080u)
+#define USBD_DEVSTAT_R_WK_OK                    (0x0040u)
+#define USBD_DEVSTAT_USB_RESET                  (0x0020u)
+#define USBD_DEVSTAT_SUS                        (0x0010u)
+#define USBD_DEVSTAT_CFG                        (0x0008u)
+#define USBD_DEVSTAT_ADD                        (0x0004u)
+#define USBD_DEVSTAT_DEF                        (0x0002u)
+#define USBD_DEVSTAT_ATT                        (0x0001u)
+
+
+/* Start of frame *************************************************************/
+#define USBD_SOF_FT_LOCK                        (0x1000u)
+#define USBD_SOF_TS_OK                          (0x0800u)
+#define USBD_SOF_TS                             (0x07FFu)
+
+/* Interrupt enable ***********************************************************/
+#define USBD_IRQ_EN_SOF_IE                      (0x0080u)
+#define USBD_IRQ_EN_EPN_RX_IE                   (0x0020u)
+#define USBD_IRQ_EN_EPN_TX_IE                   (0x0010u)
+#define USBD_IRQ_EN_DS_CHG_IE                   (0x0008u)
+#define USBD_IRQ_EN_EP0_IE                      (0x0001u)
+
+/* DMA Interrupt enable *******************************************************/
+#define USBD_DMA_IRQ_EN_TX2_DONE_IE             (0x0400u)
+#define USBD_DMA_IRQ_EN_RX2_CNT_IE              (0x0200u)
+#define USBD_DMA_IRQ_EN_RX2_EOT_IE              (0x0100u)
+#define USBD_DMA_IRQ_EN_TX1_DONE_IE             (0x0040u)
+#define USBD_DMA_IRQ_EN_RX1_CNT_IE              (0x0020u)
+#define USBD_DMA_IRQ_EN_RX1_EOT_IE              (0x0010u)
+#define USBD_DMA_IRQ_EN_TX0_DONE_IE             (0x0004u)
+#define USBD_DMA_IRQ_EN_RX0_CNT_IE              (0x0002u)
+#define USBD_DMA_IRQ_EN_RX0_EOT_IE              (0x0001u)
+
+/* Interrupt source ***********************************************************/
+#define USBD_IRQ_SRC_TXN_DONE                   (0x0400u)
+#define USBD_IRQ_SRC_RXN_CNT                    (0x0200u)
+#define USBD_IRQ_SRC_RXN_EOT                    (0x0100u)
+#define USBD_IRQ_SRC_SOF                        (0x0080u)
+#define USBD_IRQ_SRC_EPN_RX                     (0x0020u)
+#define USBD_IRQ_SRC_EPN_TX                     (0x0010u)
+#define USBD_IRQ_SRC_DS_CHG                     (0x0008u)
+#define USBD_IRQ_SRC_SETUP                      (0x0004u)
+#define USBD_IRQ_SRC_EP0_RX                     (0x0002u)
+#define USBD_IRQ_SRC_EP0_TX                     (0x0001u)
+
+/* Non-ISO endpoint interrupt enable ******************************************/
+#define USBD_EPN_STAT_RX_IT_SRC                 (0x0F00u)
+#define USBD_EPN_STAT_TX_IT_SRC                 (0x000Fu)
+
+/* Non-ISO DMA interrupt enable ***********************************************/
+#define USBD_DMAN_STAT_RX_SB                    (0x1000u)
+#define USBD_DMAN_STAT_RX_IT_SRC                (0x0F00u)
+#define USBD_DMAN_STAT_TX_IT_SRC                (0x000Fu)
+
+/* DMA Receive channels configuration *****************************************/
+#define USBD_RXDMA_CFG_RX_REQ                   (0x1000u)
+#define USBD_RXDMA_CFG_RXDMA2_EP                (0x0F00u)
+#define USBD_RXDMA_CFG_RXDMA1_EP                (0x00F0u)
+#define USBD_RXDMA_CFG_RXDMA0_EP                (0x000Fu)
+
+/* DMA Transmit channels configuration ****************************************/
+#define USBD_TXDMA_CFG_TX_REQ                   (0x1000u)
+#define USBD_TXDMA_CFG_TXDMA2_EP                (0x0F00u)
+#define USBD_TXDMA_CFG_TXDMA1_EP                (0x00F0u)
+#define USBD_TXDMA_CFG_TXDMA0_EP                (0x000Fu)
+
+/* DMA FIFO data **************************************************************/
+#define USBD_DATA_DMA_DATA_DMA                  (0xFFFFu)
+
+/* Transmit DMA control 0 *****************************************************/
+#define USBD_TXDMA0_TX0_EOT                     (0x8000u)
+#define USBD_TXDMA0_TX0_START                   (0x4000u)
+#define USBD_TXDMA0_TX0_TSC                     (0x03FFu)
+
+/* Transmit DMA control 1 *****************************************************/
+#define USBD_TXDMA1_TX1_EOT                     (0x8000u)
+#define USBD_TXDMA1_TX1_START                   (0x4000u)
+#define USBD_TXDMA1_TX1_TSC                     (0x03FFu)
+#define USBD_TXDMA1_TX1_TSC_SHIFT               (0x0000u)
+
+/* Transmit DMA control 2 *****************************************************/
+#define USBD_TXDMA2_TX2_EOT                     (0x8000u)
+#define USBD_TXDMA2_TX2_START                   (0x4000u)
+#define USBD_TXDMA2_TX2_TSC                     (0x03FFu)
+
+/* Receive DMA control 0 ******************************************************/
+#define USBD_RXDMA0_RX0_STOP                    (0x8000u)
+#define USBD_RXDMA0_RX0_TC                      (0x00FFu)
+
+/* Receive DMA control 1 ******************************************************/
+#define USBD_RXDMA1_RX10_STOP                   (0x8000u)
+#define USBD_RXDMA1_RX1_TC                      (0x00FFu)
+
+/* Receive DMA control 2 ******************************************************/
+#define USBD_RXDMA2_RX2_STOP                    (0x8000u)
+#define USBD_RXDMA2_RX2_TC                      (0x00FFu)
+
+/* Endpoint 0 Configuration ***************************************************/
+#define USBD_EP0_SIZE                           (0x3000u)
+#define USBD_EP0_PTR                            (0x07FFu)
+
+/* Receive endpoint configurations... *****************************************/
+#define USBD_RX_EP_VALID                        (0x8000u)
+#define USBD_RX_EP_SIZEDB                       (0x4000u)
+#define USBD_RX_EP_SIZE                         (0x3000u)
+#define USBD_RX_EP_ISO                          (0x0800u)
+#define USBD_RX_EP_PTR                          (0x07FFu)
+
+/* Transmit endpoint configurations... ****************************************/
+#define USBD_TX_EP_VALID                        (0x8000u)
+#define USBD_TX_EP_SIZEDB                       (0x4000u)
+#define USBD_TX_EP_SIZE                         (0x3000u)
+#define USBD_TX_EP_ISO                          (0x0800u)
+#define USBD_TX_EP_PTR                          (0x07FFu)
+
+#define USBD_MAX_EP0_PTR                        (0xFFu)
+#define USBD_EP_RX_MAX                          (15u)
+#define USBD_EP_TX_MAX                          (15u)
+
+/** @brief Macro for setting a bit/s in a register (read, modify & write)     */
+#define USBD_REG_BIT_SET(reg,bit) reg |= ((uint16)(bit))
+/** @brief Macro for clearing a bit/s in a register (read, modify & write)    */
+#define USBD_REG_BIT_CLR(reg,bit) reg &= ((uint16)~((uint16)bit))
+/** @brief Macro for setting a bit/s in a register (write)                    */
+#define USBD_REG_SET_ONE(reg,value) reg = ((uint16)value)
+
+#endif /* __HW_USB_H__ */
diff --git a/include/arch/rm46l8lp/halcogen/i2c.h b/include/arch/rm46l8lp/halcogen/i2c.h
new file mode 100644
index 0000000..f76ebcd
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/i2c.h
@@ -0,0 +1,228 @@
+/** @file I2C.h
+*   @brief I2C Driver Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#include "reg_i2c.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @enum i2cMode
+*   @brief Alias names for i2c modes
+*   This enumeration is used to provide alias names for I2C modes:
+*/
+
+enum i2cMode
+{
+    I2C_FD_FORMAT   = 0x0008U,  /* Free Data Format    */
+    I2C_START_BYTE  = 0x0010U,
+    I2C_RESET_OUT   = 0x0020U,  I2C_RESET_IN   = 0x0000U,
+    I2C_DLOOPBACK   = 0x0040U,    
+    I2C_REPEATMODE  = 0x0080U,  /* In Master Mode only */ 
+    I2C_10BIT_AMODE = 0x0100U,  I2C_7BIT_AMODE = 0x0000U,
+    I2C_TRANSMITTER = 0x0200U,  I2C_RECEIVER   = 0x0000U,        
+    I2C_MASTER      = 0x0400U,  I2C_SLAVE      = 0x0000U,     
+    I2C_STOP_COND   = 0x0800U,  /* In Master Mode only */
+    I2C_START_COND  = 0x2000U,  /* In Master Mode only */    
+    I2C_FREE_RUN    = 0x4000U,
+    I2C_NACK_MODE   = 0x8000U
+};
+
+
+/** @enum i2cBitCount
+*   @brief Alias names for i2c bit count
+*   This enumeration is used to provide alias names for I2C bit count:
+*/
+
+enum i2cBitCount
+{
+    I2C_2_BIT   = 0x2U, 
+    I2C_3_BIT   = 0x3U, 
+    I2C_4_BIT   = 0x4U, 
+    I2C_5_BIT   = 0x5U, 
+    I2C_6_BIT   = 0x6U, 
+    I2C_7_BIT   = 0x7U,     
+    I2C_8_BIT   = 0x0U  
+};
+
+
+
+/** @enum i2cIntFlags
+*   @brief Interrupt Flag Definitions
+*
+*   Used with I2CEnableNotification, I2CDisableNotification
+*/
+enum i2cIntFlags
+{
+    I2C_AL_INT     = 0x0001U,  /* arbitration lost      */
+    I2C_NACK_INT   = 0x0002U,  /* no acknowledgment    */
+    I2C_ARDY_INT   = 0x0004U,  /* access ready          */
+    I2C_RX_INT     = 0x0008U,  /* receive data ready    */
+    I2C_TX_INT     = 0x0010U,  /* transmit data ready   */
+    I2C_SCD_INT    = 0x0020U,  /* stop condition detect */
+    I2C_AAS_INT    = 0x0040U   /* address as slave      */
+};
+
+
+/** @enum i2cStatFlags
+*   @brief Interrupt Status Definitions
+*
+*/
+enum i2cStatFlags
+{
+    I2C_AL         = 0x0001U,  /* arbitration lost          */
+    I2C_NACK       = 0x0002U,  /* no acknowledgement        */
+    I2C_ARDY       = 0x0004U,  /* access ready              */
+    I2C_RX         = 0x0008U,  /* receive data ready        */
+    I2C_TX         = 0x0010U,  /* transmit data ready       */
+    I2C_SCD        = 0x0020U,  /* stop condition detect     */
+    I2C_AD0        = 0x0100U,  /* address Zero Status       */
+    I2C_AAS        = 0x0200U,  /* address as slave          */
+    I2C_XSMT       = 0x0400U,  /* Transmit shift empty not  */	
+    I2C_RXFULL     = 0x0800U,  /* receive full              */
+    I2C_BUSBUSY    = 0x1000U,  /* bus busy                  */
+    I2C_NACKSNT    = 0x2000U,  /* No Ack Sent               */
+    I2C_SDIR       = 0x4000U   /* Slave Direction           */	
+};
+
+
+/** @enum i2cDMA
+*   @brief I2C DMA definitions 
+*
+*   Used before i2c transfer
+*/
+enum i2cDMA
+{
+    I2C_TXDMA   = 0x20U, 
+    I2C_RXDMA   = 0x10U 
+};
+
+/* Configuration registers */
+typedef struct i2c_config_reg
+{
+    uint32 CONFIG_OAR;
+    uint32 CONFIG_IMR;
+    uint32 CONFIG_CLKL;
+    uint32 CONFIG_CLKH;
+    uint32 CONFIG_CNT;
+    uint32 CONFIG_SAR;
+    uint32 CONFIG_MDR;
+    uint32 CONFIG_EMDR;
+    uint32 CONFIG_PSC;   
+    uint32 CONFIG_DMAC;
+    uint32 CONFIG_FUN;
+    uint32 CONFIG_DIR;
+    uint32 CONFIG_ODR;
+    uint32 CONFIG_PD;	
+	uint32 CONFIG_PSL;	
+} i2c_config_reg_t;
+
+
+/** 
+ *  @defgroup I2C I2C
+ *  @brief Inter-Integrated Circuit Module.
+ *  
+ *  The I2C is a multi-master communication module providing an interface between the Texas Instruments (TI) microcontroller
+ *  and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2Cbus.
+ *  This module will support any slave or master I2C compatible device.
+ *
+ *	Related Files
+ *   - reg_i2c.h
+ *   - i2c.h
+ *   - i2c.c
+ *  @addtogroup I2C
+ *  @{
+ */
+ 
+/* I2C Interface Functions */
+void    i2cInit(void);
+void    i2cSetOwnAdd(i2cBASE_t *i2c, uint32 oadd);
+void    i2cSetSlaveAdd(i2cBASE_t *i2c, uint32 sadd);
+void    i2cSetBaudrate(i2cBASE_t *i2c, uint32 baud);
+uint32  i2cIsTxReady(i2cBASE_t *i2c);
+void    i2cSendByte(i2cBASE_t *i2c, uint8 byte);
+void    i2cSend(i2cBASE_t *i2c, uint32 length, uint8 * data);
+uint32  i2cIsRxReady(i2cBASE_t *i2c);
+uint32  i2cIsStopDetected(i2cBASE_t *i2c);
+void    i2cClearSCD(i2cBASE_t *i2c);
+uint32  i2cRxError(i2cBASE_t *i2c);
+uint8   i2cReceiveByte(i2cBASE_t *i2c);
+void    i2cReceive(i2cBASE_t *i2c, uint32 length, uint8 * data);
+void    i2cEnableNotification(i2cBASE_t *i2c, uint32 flags);
+void    i2cDisableNotification(i2cBASE_t *i2c, uint32 flags);
+void    i2cSetStart(i2cBASE_t *i2c);
+void    i2cSetStop(i2cBASE_t *i2c);
+void    i2cSetCount(i2cBASE_t *i2c ,uint32 cnt);
+void    i2cEnableLoopback(i2cBASE_t *i2c);
+void    i2cDisableLoopback(i2cBASE_t *i2c);
+void    i2cSetMode(i2cBASE_t *i2c, uint32 mode);
+void    i2cGetConfigValue(i2c_config_reg_t *config_reg, config_value_type_t type);
+void i2cSetDirection(i2cBASE_t *i2c, uint32 dir);
+bool i2cIsMasterReady(i2cBASE_t *i2c);
+bool i2cIsBusBusy(i2cBASE_t *i2c);
+
+/** @fn void i2cNotification(i2cBASE_t *i2c, uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] i2c   - I2C module base address
+*   @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called apon
+* an interrupt.  The parameter passed to the callback is a copy of the 
+* interrupt flag register.
+*/
+void i2cNotification(i2cBASE_t *i2c, uint32 flags);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/lin.h b/include/arch/rm46l8lp/halcogen/lin.h
new file mode 100644
index 0000000..bc82bfe
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/lin.h
@@ -0,0 +1,333 @@
+/** @file lin.h
+*   @brief LIN Driver Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __LIN_H__
+#define __LIN_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "reg_lin.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @def LIN_BREAK_INT
+*   @brief Alias for break detect interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_BREAK_INT 0x00000001U
+
+
+/** @def LIN_WAKEUP_INT
+*   @brief Alias for wakeup interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_WAKEUP_INT 0x00000002U
+
+
+/** @def LIN_TO_INT
+*   @brief Alias for time out interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_TO_INT 0x00000010U
+
+
+/** @def LIN_TOAWUS_INT
+*   @brief Alias for time out after wakeup signal interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_TOAWUS_INT 0x00000040U
+
+
+/** @def LIN_TOA3WUS_INT
+*   @brief Alias for time out after 3 wakeup signals interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_TOA3WUS_INT 0x00000080U
+
+
+/** @def LIN_TX_READY
+*   @brief Alias for transmit buffer ready flag
+*
+*   Used with linIsTxReady.
+*/
+#define LIN_TX_READY 0x00000100U
+
+
+/** @def LIN_RX_INT
+*   @brief Alias for receive buffer ready interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_RX_INT 0x00000200U
+
+
+/** @def LIN_ID_INT
+*   @brief Alias for received matching identifier interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_ID_INT 0x00002000U
+
+
+/** @def LIN_PE_INT
+*   @brief Alias for parity error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_PE_INT 0x01000000U
+
+
+/** @def LIN_OE_INT
+*   @brief Alias for overrun error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_OE_INT 0x02000000U
+
+
+/** @def LIN_FE_INT
+*   @brief Alias for framing error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_FE_INT 0x04000000U
+
+
+/** @def LIN_NRE_INT
+*   @brief Alias for no response error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_NRE_INT 0x08000000U
+
+
+/** @def LIN_ISFE_INT
+*   @brief Alias for inconsistent sync field error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_ISFE_INT 0x10000000U
+
+
+/** @def LIN_CE_INT
+*   @brief Alias for checksum error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_CE_INT 0x20000000U
+
+
+/** @def LIN_PBE_INT
+*   @brief Alias for physical bus error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_PBE_INT 0x40000000U
+
+
+/** @def LIN_BE_INT
+*   @brief Alias for bit error interrupt flag
+*
+*   Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_BE_INT 0x80000000U
+
+
+/** @struct linBase
+*   @brief LIN Register Definition
+*
+*   This structure is used to access the LIN module registers.
+*/
+/** @typedef linBASE_t
+*   @brief LIN Register Frame Type Definition
+*
+*   This type is used to access the LIN Registers.
+*/
+
+enum linPinSelect
+{
+    PIN_LIN_TX = 4U,
+    PIN_LIN_RX = 2U
+};
+
+/* Configuration registers */
+typedef struct lin_config_reg
+{
+    uint32 CONFIG_GCR0;
+    uint32 CONFIG_GCR1;
+    uint32 CONFIG_GCR2;
+    uint32 CONFIG_SETINT;
+    uint32 CONFIG_SETINTLVL;
+    uint32 CONFIG_FORMAT;
+    uint32 CONFIG_BRSR;
+    uint32 CONFIG_FUN;
+    uint32 CONFIG_DIR;
+    uint32 CONFIG_ODR;
+    uint32 CONFIG_PD;	
+	uint32 CONFIG_PSL;
+	uint32 CONFIG_COMP;	
+	uint32 CONFIG_MASK;
+	uint32 CONFIG_MBRSR;
+} lin_config_reg_t;
+
+/* Configuration registers initial value for LIN*/
+#define LIN_GCR0_CONFIGVALUE       0x00000001U   
+#define LIN_GCR1_CONFIGVALUE       (0x03000CC0U \
+                                 | (uint32)((uint32)1U << 12U) \
+                                 | (uint32)((uint32)0U << 2U)\
+								 | (uint32)((uint32)1U << 5U))
+#define LIN_GCR2_CONFIGVALUE       0x00000000U       
+#define LIN_SETINTLVL_CONFIGVALUE  (0x00000000U \
+								  |	0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U)
+
+#define LIN_SETINT_CONFIGVALUE     (0x00000000U \
+								  |	0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U \
+                                  | 0x00000000U)
+
+#define LIN_FORMAT_CONFIGVALUE     ((uint32)((uint32)(8U - 1U) << 16U))
+#define LIN_BRSR_CONFIGVALUE       (249U)
+#define LIN_COMP_CONFIGVALUE       ((uint32)((uint32)(1U - 1U) << 8U) | (13U - 13U))
+#define LIN_MASK_CONFIGVALUE       ((uint32)((uint32)0xFFU << 16U) | 0xFFU)
+#define LIN_MBRSR_CONFIGVALUE      (3600U)
+#define LIN_FUN_CONFIGVALUE        (4U | 2U | 0U)
+#define LIN_DIR_CONFIGVALUE        (0U | 0U | 0U)
+#define LIN_ODR_CONFIGVALUE        (0U | 0U | 0U)
+#define LIN_PD_CONFIGVALUE         (0U | 0U | 0U)
+#define LIN_PSL_CONFIGVALUE        (4U | 2U | 1U)
+ 
+/** 
+ *  @defgroup LIN LIN
+ *  @brief Local Interconnect Network Module.
+ *  
+ *  The LIN standard is based on the SCI (UART) serial data link format. The communication concept is
+ *  single-master/multiple-slave with a message identification for multi-cast transmission between any network
+ *  nodes.
+ *
+ *	Related Files
+ *   - reg_lin.h
+ *   - lin.h
+ *   - lin.c
+ *  @addtogroup LIN
+ *  @{
+ */
+ 
+/* LIN Interface Functions */
+void     linInit(void);
+void     linSetFunctional(linBASE_t *lin, uint32 port);
+void     linSendHeader(linBASE_t *lin, uint8 identifier);
+void     linSendWakupSignal(linBASE_t *lin);
+void     linEnterSleep(linBASE_t *lin);
+void     linSoftwareReset(linBASE_t *lin);
+uint32   linIsTxReady(linBASE_t *lin);
+void     linSetLength(linBASE_t *lin, uint32 length);
+void     linSend(linBASE_t *lin, uint8 * data);
+uint32   linIsRxReady(linBASE_t *lin);
+uint32   linTxRxError(linBASE_t *lin);
+uint32   linGetIdentifier(linBASE_t *lin);
+void     linGetData(linBASE_t *lin, uint8 * const data);
+void     linEnableNotification(linBASE_t *lin, uint32 flags);
+void     linDisableNotification(linBASE_t *lin, uint32 flags);
+void     linEnableLoopback(linBASE_t *lin, loopBackType_t Loopbacktype);
+void     linDisableLoopback(linBASE_t *lin);
+void     linGetConfigValue(lin_config_reg_t *config_reg, config_value_type_t type);
+uint32   linGetStatusFlag(linBASE_t *lin);
+void     linClearStatusFlag(linBASE_t *lin, uint32 flags);
+
+/** @fn void linNotification(linBASE_t *lin, uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] lin   - lin module base address
+*   @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt.  The parameter passed to the callback is a copy of the 
+* interrupt flag register.
+*/
+void linNotification(linBASE_t *lin, uint32 flags);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/mdio.h b/include/arch/rm46l8lp/halcogen/mdio.h
new file mode 100644
index 0000000..6a76e6e
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/mdio.h
@@ -0,0 +1,92 @@
+/**
+ *  \file   mdio.h
+ *
+ *  \brief  MDIO APIs and macros.
+ *
+ *   This file contains the driver API prototypes and macro definitions.
+ */
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __MDIO_H__
+#define __MDIO_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_common.h"
+#include "system.h"
+#include "hw_mdio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/* MDIO input and output frequencies in Hz */
+#define MDIO_FREQ_INPUT           ((uint32)(VCLK3_FREQ * 1000000.00F))
+#define MDIO_FREQ_OUTPUT          1000000U
+/*****************************************************************************/
+
+/**
+ *  @addtogroup EMACMDIO
+ *  @{
+ */
+/*
+** Prototypes for the APIs
+*/
+extern uint32 MDIOPhyAliveStatusGet(uint32 baseAddr);
+extern uint32 MDIOPhyLinkStatusGet(uint32 baseAddr);
+extern void MDIOInit(uint32 baseAddr, uint32 mdioInputFreq,
+                     uint32 mdioOutputFreq);
+extern boolean MDIOPhyRegRead(uint32 baseAddr, uint32 phyAddr,
+                                   uint32 regNum, volatile uint16 * dataPtr);
+extern void MDIOPhyRegWrite(uint32 baseAddr, uint32 phyAddr,
+                            uint32 regNum, uint16 RegVal);
+extern void MDIOEnable(uint32 baseAddr);
+extern void MDIODisable(uint32 baseAddr);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* __MDIO_H__ */
diff --git a/include/arch/rm46l8lp/halcogen/mibspi.h b/include/arch/rm46l8lp/halcogen/mibspi.h
new file mode 100644
index 0000000..60c44ae
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/mibspi.h
@@ -0,0 +1,287 @@
+/** @file mibspi.h
+*   @brief MIBSPI Driver Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __MIBSPI_H__
+#define __MIBSPI_H__
+
+#include "reg_mibspi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @enum triggerEvent
+*   @brief Transfer Group Trigger Event
+*/
+enum triggerEvent
+{
+    TRG_NEVER   = 0U,
+    TRG_RISING  = 1U,
+    TRG_FALLING = 2U,
+    TRG_BOTH    = 3U,
+    TRG_HIGH    = 5U,
+    TRG_LOW     = 6U,
+    TRG_ALWAYS  = 7U
+};
+
+/** @enum triggerSource
+*   @brief Transfer Group Trigger Source
+*/
+enum triggerSource
+{
+    TRG_DISABLED,
+    TRG_GIOA0,
+    TRG_GIOA1,
+    TRG_GIOA2,
+    TRG_GIOA3,
+    TRG_GIOA4,
+    TRG_GIOA5,
+    TRG_GIOA6,
+    TRG_GIOA7,
+    TRG_HET1_8,
+    TRG_HET1_10,
+    TRG_HET1_12,
+    TRG_HET1_14,
+    TRG_HET1_16,
+    TRG_HET1_18,
+    TRG_TICK
+};
+
+
+/** @enum mibspiPinSelect
+*   @brief mibspi Pin Select
+*/
+enum mibspiPinSelect
+{
+    PIN_CS0 = 0U,
+    PIN_CS1 = 1U,
+    PIN_CS2 = 2U,
+    PIN_CS3 = 3U,
+    PIN_CS4 = 4U,
+    PIN_CS5 = 5U,
+    PIN_CS6 = 6U,
+    PIN_CS7 = 7U,
+    PIN_ENA = 8U,
+    PIN_CLK = 9U,
+    PIN_SIMO = 10U,
+    PIN_SOMI = 11U,
+   PIN_SIMO_1 = 17U,
+   PIN_SIMO_2 = 18U,
+   PIN_SIMO_3 = 19U,
+   PIN_SIMO_4 = 20U,
+   PIN_SIMO_5 = 21U,
+   PIN_SIMO_6 = 22U,
+   PIN_SIMO_7 = 23U,
+   PIN_SOMI_1 = 25U,
+   PIN_SOMI_2 = 26U,
+   PIN_SOMI_3 = 27U,
+   PIN_SOMI_4 = 28U,
+   PIN_SOMI_5 = 29U,
+   PIN_SOMI_6 = 30U,
+   PIN_SOMI_7 = 31U
+};
+
+
+/** @enum chipSelect
+*   @brief Transfer Group Chip Select
+*/
+enum chipSelect
+{
+    CS_NONE = 0xFFU,
+    CS_0    = 0xFEU,
+    CS_1    = 0xFDU,
+    CS_2    = 0xFBU,
+    CS_3    = 0xF7U,
+    CS_4    = 0xEFU,
+    CS_5    = 0xDFU,
+    CS_6    = 0xBFU,
+    CS_7    = 0x7FU
+};
+
+/** @typedef mibspiPmode_t
+*   @brief Mibspi Parellel mode Type Definition
+*
+*   This type is used to represent Mibspi Parellel mode.
+*/
+typedef enum mibspiPmode
+{
+    PMODE_NORMAL        = 0x0U,
+    PMODE_2_DATALINE    = 0x1U,
+    PMODE_4_DATALINE    = 0x2U,
+    PMODE_8_DATALINE    = 0x3U
+}mibspiPmode_t;
+
+/** @typedef mibspiDFMT_t
+*   @brief Mibspi Data format selection Type Definition
+*
+*   This type is used to represent Mibspi Data format selection.
+*/
+typedef enum mibspiDFMT
+{
+    DATA_FORMAT0    = 0x0U,
+    DATA_FORMAT1    = 0x1U,
+    DATA_FORMAT2    = 0x2U,
+    DATA_FORMAT3    = 0x3U
+}mibspiDFMT_t;
+
+typedef struct mibspi_config_reg
+{
+    uint32 CONFIG_GCR1;
+    uint32 CONFIG_INT0;
+    uint32 CONFIG_LVL;
+    uint32 CONFIG_PCFUN;
+    uint32 CONFIG_PCDIR;
+    uint32 CONFIG_PCPDR;
+    uint32 CONFIG_PCDIS;
+    uint32 CONFIG_PCPSL;
+    uint32 CONFIG_DELAY;
+    uint32 CONFIG_FMT0;
+    uint32 CONFIG_FMT1;
+    uint32 CONFIG_FMT2;
+    uint32 CONFIG_FMT3;
+    uint32 CONFIG_MIBSPIE;
+    uint32 CONFIG_LTGPEND;
+    uint32 CONFIG_TGCTRL[8U];
+    uint32 CONFIG_UERRCTRL;
+}mibspi_config_reg_t;
+
+
+
+#define MIBSPI3_GCR1_CONFIGVALUE     (0x01000000U | (uint32)((uint32)1U << 1U) | 1U)
+#define MIBSPI3_INT0_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U)  | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
+#define MIBSPI3_LVL_CONFIGVALUE      ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
+
+#define MIBSPI3_PCFUN_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U))
+#define MIBSPI3_PCDIR_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
+#define MIBSPI3_PCPDR_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
+#define MIBSPI3_PCDIS_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
+#define MIBSPI3_PCPSL_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U))
+
+#define MIBSPI3_DELAY_CONFIGVALUE    ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U))
+
+#define MIBSPI3_FMT0_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)79U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI3_FMT1_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)79U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI3_FMT2_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)79U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI3_FMT3_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)79U << 8U) | (uint32)((uint32)16U << 0U))
+
+#define MIBSPI3_MIBSPIE_CONFIGVALUE  1U
+#define MIBSPI3_LTGPEND_CONFIGVALUE  ((uint32)((uint32)((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U))
+
+#define MIBSPI3_TGCTRL0_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)0U << 8U)))
+#define MIBSPI3_TGCTRL1_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)8U << 8U)))
+#define MIBSPI3_TGCTRL2_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U) << 8U)))
+#define MIBSPI3_TGCTRL3_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL4_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL5_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL6_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL7_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U)))
+
+#define MIBSPI3_UERRCTRL_CONFIGVALUE (0x00000005U)
+
+
+/**
+ *  @defgroup MIBSPI MIBSPI
+ *  @brief Multi-Buffered Serial Peripheral Interface Module.
+ *
+ *  The MibSPI/MibSPIP is a high-speed synchronous serial input/output port that allows a serial bit stream of
+ *  programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
+ *  The MibSPI has a programmable buffer memory that enables programmed transmission to be completed
+ *  without CPU intervention
+ *
+ *    Related Files
+ *   - reg_mibspi.h
+ *   - mibspi.h
+ *   - mibspi.c
+ *  @addtogroup MIBSPI
+ *  @{
+ */
+
+/* MIBSPI Interface Functions */
+void mibspiInit(void);
+void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port);
+void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data);
+uint32 mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data);
+void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group);
+boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group);
+void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level);
+void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group);
+void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype);
+void mibspiDisableLoopback(mibspiBASE_t *mibspi);
+void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT);
+void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type);
+
+/** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags)
+*   @brief Error interrupt callback
+*   @param[in] mibspi   - mibSpi module base address
+*   @param[in] flags - Copy of error interrupt flags
+*
+* This is a error callback that is provided by the application and is call upon
+* an error interrupt.  The paramer passed to the callback is a copy of the error
+* interrupt flag register.
+*/
+void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags);
+
+
+/** @fn void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group)
+*   @brief Transfer complete notification callback
+*   @param[in] mibspi   - mibSpi module base address
+*   @param[in] group - Transfer group
+*
+* This is a callback function provided by the application.  It is call when
+* a transfer is complete.  The parameter is the transfer group that triggered
+* the interrupt.
+*/
+void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/phy_dp83640.h b/include/arch/rm46l8lp/halcogen/phy_dp83640.h
new file mode 100644
index 0000000..e42aea6
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/phy_dp83640.h
@@ -0,0 +1,132 @@
+/*
+ * DP83640.h
+ */
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _PHY_DP83640_H_
+#define _PHY_DP83640_H_
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @enum PHY_timestamp
+*   @brief Alias names for transmit and receive timestamps
+*   This enumeration is used to provide alias names for getting the transmit and receive timestamps from the Dp83640GetTimeStamp API.
+*/
+typedef enum phyTimeStamp
+{
+	Txtimestamp = 1, /*Transmit Timestamp*/
+	Rxtimestamp = 2 /*Receive Timestamp */
+}phyTimeStamp_t;
+/* PHY register offset definitions */
+#define PHY_BCR                           (0u)
+#define PHY_BSR                           (1u)
+#define PHY_ID1                           (2u)
+#define PHY_ID2                           (3u)
+#define PHY_AUTONEG_ADV                   (4u)
+#define PHY_LINK_PARTNER_ABLTY            (5u)
+#define PHY_LINK_PARTNER_SPD              (16u)
+#define PHY_TXTS						  (28u)
+#define PHY_RXTS						  (29u)
+
+/* PHY status definitions */
+#define PHY_ID_SHIFT                      (16u)
+#define PHY_SOFTRESET                     (0x8000U)
+#define PHY_AUTONEG_ENABLE                (0x1000u)
+#define PHY_AUTONEG_RESTART               (0x0200u)
+#define PHY_AUTONEG_COMPLETE              (0x0020u)
+#define PHY_AUTONEG_INCOMPLETE            (0x0000u)
+#define PHY_AUTONEG_STATUS                (0x0020u)
+#define PHY_AUTONEG_ABLE                  (0x0008u)
+#define PHY_LPBK_ENABLE                   (0x4000u)
+#define PHY_LINK_STATUS                   (0x0004u)
+#define PHY_INVALID_TYPE				  (0x0u)
+
+
+/* PHY ID. The LSB nibble will vary between different phy revisions */
+#define DP83640_PHY_ID                   (0x0007C0F0u)
+#define DP83640_PHY_ID_REV_MASK          (0x0000000Fu)
+
+/* Pause operations */
+#define DP83640_PAUSE_NIL                (0x0000u)
+#define DP83640_PAUSE_SYM                (0x0400u)
+#define DP83640_PAUSE_ASYM               (0x0800u)
+#define DP83640_PAUSE_BOTH_SYM_ASYM      (0x0C00u)
+
+/* 100 Base TX Full Duplex capablity */
+#define DP83640_100BTX_HD                (0x0000u)
+#define DP83640_100BTX_FD                (0x0100u)
+
+/* 100 Base TX capability */
+#define DP83640_NO_100BTX                (0x0000u)
+#define DP83640_100BTX                   (0x0080u)
+
+/* 10 BaseT duplex capabilities */
+#define DP83640_10BT_HD                  (0x0000u)
+#define DP83640_10BT_FD                  (0x0040u)
+
+/* 10 BaseT ability*/
+#define DP83640_NO_10BT                  (0x0000u)
+#define DP83640_10BT                     (0x0020u)
+
+/**************************************************************************
+                        API function Prototypes
+***************************************************************************/
+extern uint32 Dp83640IDGet(uint32 mdioBaseAddr, uint32 phyAddr);
+extern void Dp83640Reset(uint32 mdioBaseAddr, uint32 phyAddr);
+extern boolean Dp83640AutoNegotiate(uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal);
+extern boolean Dp83640PartnerAbilityGet(uint32 mdioBaseAddr, uint32 phyAddr,uint16 *ptnerAblty);
+extern boolean Dp83640LinkStatusGet(uint32 mdioBaseAddr, uint32 phyAddr,volatile uint32 retries);
+extern uint64 Dp83640GetTimeStamp(uint32 mdioBaseAddr, uint32 phyAddr, phyTimeStamp_t type);
+extern void Dp83640EnableLoopback(uint32 mdioBaseAddr, uint32 phyAddr);
+extern void Dp83640DisableLoopback(uint32 mdioBaseAddr, uint32 phyAddr);
+extern boolean Dp83640PartnerSpdGet(uint32 mdioBaseAddr, uint32 phyAddr, uint16 *ptnerAblty);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/pinmux.h b/include/arch/rm46l8lp/halcogen/pinmux.h
new file mode 100644
index 0000000..547acd1
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/pinmux.h
@@ -0,0 +1,575 @@
+/** @file pinmux.h
+*   @brief PINMUX Driver Implementation File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __PINMUX_H__
+#define __PINMUX_H__
+
+#include "reg_pinmux.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define PINMUX_PIN_1_SHIFT                      0U
+#define PINMUX_PIN_2_SHIFT                      8U
+#define PINMUX_PIN_3_SHIFT                      16U
+#define PINMUX_PIN_4_SHIFT                      24U
+#define PINMUX_PIN_5_SHIFT                      0U
+#define PINMUX_PIN_6_SHIFT                      8U
+#define PINMUX_PIN_9_SHIFT                      0U
+#define PINMUX_PIN_14_SHIFT                     24U
+#define PINMUX_PIN_15_SHIFT                     8U
+#define PINMUX_PIN_16_SHIFT                     16U
+#define PINMUX_PIN_22_SHIFT                     0U
+#define PINMUX_PIN_23_SHIFT                     16U
+#define PINMUX_PIN_24_SHIFT                     24U
+#define PINMUX_PIN_25_SHIFT                     0U
+#define PINMUX_PIN_30_SHIFT                     8U
+#define PINMUX_PIN_31_SHIFT                     16U
+#define PINMUX_PIN_32_SHIFT                     0U
+#define PINMUX_PIN_33_SHIFT                     0U
+#define PINMUX_PIN_35_SHIFT                     16U
+#define PINMUX_PIN_36_SHIFT                     0U
+#define PINMUX_PIN_37_SHIFT                     8U
+#define PINMUX_PIN_38_SHIFT                     16U
+#define PINMUX_PIN_39_SHIFT                     0U
+#define PINMUX_PIN_40_SHIFT                     8U
+#define PINMUX_PIN_41_SHIFT                     16U
+#define PINMUX_PIN_51_SHIFT                     8U
+#define PINMUX_PIN_52_SHIFT                     16U
+#define PINMUX_PIN_53_SHIFT                     24U
+#define PINMUX_PIN_54_SHIFT                     8U
+#define PINMUX_PIN_55_SHIFT                     16U
+#define PINMUX_PIN_86_SHIFT                     0U
+#define PINMUX_PIN_91_SHIFT                     24U
+#define PINMUX_PIN_92_SHIFT                     0U
+#define PINMUX_PIN_96_SHIFT                     16U
+#define PINMUX_PIN_97_SHIFT                     24U
+#define PINMUX_PIN_98_SHIFT                     0U
+#define PINMUX_PIN_99_SHIFT                     8U
+#define PINMUX_PIN_100_SHIFT                    16U
+#define PINMUX_PIN_105_SHIFT                    24U
+#define PINMUX_PIN_106_SHIFT                    0U
+#define PINMUX_PIN_107_SHIFT                    8U
+#define PINMUX_PIN_118_SHIFT                    0U
+#define PINMUX_PIN_124_SHIFT                    16U
+#define PINMUX_PIN_125_SHIFT                    8U
+#define PINMUX_PIN_126_SHIFT                    24U
+#define PINMUX_PIN_127_SHIFT                    8U
+#define PINMUX_PIN_130_SHIFT                    16U
+#define PINMUX_PIN_133_SHIFT                    8U
+#define PINMUX_PIN_139_SHIFT                    0U
+#define PINMUX_PIN_140_SHIFT                    8U
+#define PINMUX_PIN_141_SHIFT                    16U
+
+
+#define PINMUX_GATE_EMIF_CLK_SHIFT              8U
+#define PINMUX_GIOB_DISABLE_HET2_SHIFT          16U
+#define PINMUX_ALT_ADC_TRIGGER_SHIFT            0U
+#define PINMUX_ETHERNET_SHIFT                   24U
+#define PINMUX_ETPWM1_SHIFT                     0U
+#define PINMUX_ETPWM2_SHIFT                     8U
+#define PINMUX_ETPWM3_SHIFT                     16U
+#define PINMUX_ETPWM4_SHIFT                     24U
+#define PINMUX_ETPWM5_SHIFT                     0U
+#define PINMUX_ETPWM6_SHIFT                     8U
+#define PINMUX_ETPWM7_SHIFT                     16U
+#define PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT       24U
+#define PINMUX_ETPWM_TBCLK_SYNC_SHIFT           0U
+#define PINMUX_TZ1_SHIFT                        16U
+#define PINMUX_TZ2_SHIFT                        24U
+#define PINMUX_TZ3_SHIFT                        0U
+#define PINMUX_EPWM1SYNCI_SHIFT                 8U
+
+#define PINMUX_PIN_1_MASK                       (~(uint32)((uint32)0xFFU << PINMUX_PIN_1_SHIFT))
+#define PINMUX_PIN_2_MASK                       (~(uint32)((uint32)0xFFU << PINMUX_PIN_2_SHIFT))
+#define PINMUX_PIN_3_MASK                       (~(uint32)((uint32)0xFFU << PINMUX_PIN_3_SHIFT))
+#define PINMUX_PIN_4_MASK                       (~(uint32)((uint32)0xFFU << PINMUX_PIN_4_SHIFT))
+#define PINMUX_PIN_5_MASK                       (~(uint32)((uint32)0xFFU << PINMUX_PIN_5_SHIFT))
+#define PINMUX_PIN_6_MASK                       (~(uint32)((uint32)0xFFU << PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_9_MASK                       (~(uint32)((uint32)0xFFU << PINMUX_PIN_9_SHIFT))
+#define PINMUX_PIN_14_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_14_SHIFT))
+#define PINMUX_PIN_15_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_15_SHIFT))
+#define PINMUX_PIN_16_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_16_SHIFT))
+#define PINMUX_PIN_22_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_22_SHIFT))
+#define PINMUX_PIN_23_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_24_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_25_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_25_SHIFT))
+#define PINMUX_PIN_30_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_30_SHIFT))
+#define PINMUX_PIN_31_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_31_SHIFT))
+#define PINMUX_PIN_32_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_32_SHIFT))
+#define PINMUX_PIN_33_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_33_SHIFT))
+#define PINMUX_PIN_35_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_35_SHIFT))
+#define PINMUX_PIN_36_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_36_SHIFT))
+#define PINMUX_PIN_37_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_37_SHIFT))
+#define PINMUX_PIN_38_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_38_SHIFT))
+#define PINMUX_PIN_39_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_39_SHIFT))
+#define PINMUX_PIN_40_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_40_SHIFT))
+#define PINMUX_PIN_41_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_41_SHIFT))
+#define PINMUX_PIN_51_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_51_SHIFT))
+#define PINMUX_PIN_52_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_52_SHIFT))
+#define PINMUX_PIN_53_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_53_SHIFT))
+#define PINMUX_PIN_54_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_54_SHIFT))
+#define PINMUX_PIN_55_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_55_SHIFT))
+#define PINMUX_PIN_86_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_86_SHIFT))
+#define PINMUX_PIN_91_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_91_SHIFT))
+#define PINMUX_PIN_92_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_92_SHIFT))
+#define PINMUX_PIN_96_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_96_SHIFT))
+#define PINMUX_PIN_97_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_97_SHIFT))
+#define PINMUX_PIN_98_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_98_SHIFT))
+#define PINMUX_PIN_99_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_PIN_99_SHIFT))
+#define PINMUX_PIN_100_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_100_SHIFT))
+#define PINMUX_PIN_105_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_105_SHIFT))
+#define PINMUX_PIN_106_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_106_SHIFT))
+#define PINMUX_PIN_107_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_107_SHIFT))
+#define PINMUX_PIN_118_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_118_SHIFT))
+#define PINMUX_PIN_124_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_124_SHIFT))
+#define PINMUX_PIN_125_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_125_SHIFT))
+#define PINMUX_PIN_126_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_126_SHIFT))
+#define PINMUX_PIN_127_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_127_SHIFT))
+#define PINMUX_PIN_130_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_130_SHIFT))
+#define PINMUX_PIN_133_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_133_SHIFT))
+#define PINMUX_PIN_139_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_139_SHIFT))
+#define PINMUX_PIN_140_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_140_SHIFT))
+#define PINMUX_PIN_141_MASK                     (~(uint32)((uint32)0xFFU << PINMUX_PIN_141_SHIFT))
+
+#define PINMUX_GATE_EMIF_CLK_MASK               (~(uint32)((uint32)0xFFU << PINMUX_GATE_EMIF_CLK_SHIFT))
+#define PINMUX_GIOB_DISABLE_HET2_MASK           (~(uint32)((uint32)0xFFU << PINMUX_GIOB_DISABLE_HET2_SHIFT))
+#define PINMUX_ALT_ADC_TRIGGER_MASK             (~(uint32)((uint32)0xFFU << PINMUX_ALT_ADC_TRIGGER_SHIFT))
+#define PINMUX_ETHERNET_MASK                    (~(uint32)((uint32)0xFFU << PINMUX_ETHERNET_SHIFT))
+
+
+
+#define PINMUX_ETPWM1_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_ETPWM1_SHIFT))
+#define PINMUX_ETPWM2_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_ETPWM2_SHIFT))
+#define PINMUX_ETPWM3_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_ETPWM3_SHIFT))
+#define PINMUX_ETPWM4_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_ETPWM4_SHIFT))
+#define PINMUX_ETPWM5_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_ETPWM5_SHIFT))
+#define PINMUX_ETPWM6_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_ETPWM6_SHIFT))
+#define PINMUX_ETPWM7_MASK                      (~(uint32)((uint32)0xFFU << PINMUX_ETPWM7_SHIFT))
+#define PINMUX_ETPWM_TIME_BASE_SYNC_MASK        (~(uint32)((uint32)0xFFU << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT))
+#define PINMUX_ETPWM_TBCLK_SYNC_MASK            (~(uint32)((uint32)0xFFU << PINMUX_ETPWM_TBCLK_SYNC_SHIFT))
+#define PINMUX_TZ1_MASK                         (~(uint32)((uint32)0xFFU << PINMUX_TZ1_SHIFT))
+#define PINMUX_TZ2_MASK                         (~(uint32)((uint32)0xFFU << PINMUX_TZ2_SHIFT))
+#define PINMUX_TZ3_MASK                         (~(uint32)((uint32)0xFFU << PINMUX_TZ3_SHIFT))
+#define PINMUX_EPWM1SYNCI_MASK                  (~(uint32)((uint32)0xFFU << PINMUX_EPWM1SYNCI_SHIFT))
+
+#define PINMUX_PIN_1_GIOB_3                     ((uint32)((uint32)0x1U <<  PINMUX_PIN_1_SHIFT))
+#define PINMUX_PIN_1_OHCI_PRT_RcvData_1         ((uint32)((uint32)0x2U <<  PINMUX_PIN_1_SHIFT))
+#define PINMUX_PIN_1_W2FC_RXDI                  ((uint32)((uint32)0x4U <<  PINMUX_PIN_1_SHIFT))
+
+#define PINMUX_PIN_2_GIOA_0                     ((uint32)((uint32)0x1U <<  PINMUX_PIN_2_SHIFT))
+#define PINMUX_PIN_2_OHCI_PRT_RcvDpls_1         ((uint32)((uint32)0x2U <<  PINMUX_PIN_2_SHIFT))
+#define PINMUX_PIN_2_W2FC_RXDPI                 ((uint32)((uint32)0x4U <<  PINMUX_PIN_2_SHIFT))
+
+#define PINMUX_PIN_3_MIBSPI3NCS_3               ((uint32)((uint32)0x1U <<  PINMUX_PIN_3_SHIFT))
+#define PINMUX_PIN_3_I2C_SCL                    ((uint32)((uint32)0x2U <<  PINMUX_PIN_3_SHIFT))
+#define PINMUX_PIN_3_HET1_29                    ((uint32)((uint32)0x4U <<  PINMUX_PIN_3_SHIFT))
+#define PINMUX_PIN_3_nTZ1                       ((uint32)((uint32)0x8U <<  PINMUX_PIN_3_SHIFT))
+
+#define PINMUX_PIN_4_MIBSPI3NCS_2               ((uint32)((uint32)0x1U <<  PINMUX_PIN_4_SHIFT))
+#define PINMUX_PIN_4_I2C_SDA                    ((uint32)((uint32)0x2U <<  PINMUX_PIN_4_SHIFT))
+#define PINMUX_PIN_4_HET1_27                    ((uint32)((uint32)0x4U <<  PINMUX_PIN_4_SHIFT))
+#define PINMUX_PIN_4_nTZ2                       ((uint32)((uint32)0x8U <<  PINMUX_PIN_4_SHIFT))
+
+#define PINMUX_PIN_5_GIOA_1                     ((uint32)((uint32)0x1U <<  PINMUX_PIN_5_SHIFT))
+#define PINMUX_PIN_5_OHCI_PRT_RcvDmns_1         ((uint32)((uint32)0x2U <<  PINMUX_PIN_5_SHIFT))
+#define PINMUX_PIN_5_W2FC_RXDMI                 ((uint32)((uint32)0x4U <<  PINMUX_PIN_5_SHIFT))
+
+#define PINMUX_PIN_6_HET1_11                    ((uint32)((uint32)0x1U <<  PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_6_MIBSPI3NCS_4               ((uint32)((uint32)0x2U <<  PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_6_HET2_18                    ((uint32)((uint32)0x4U <<  PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_6_OHCI_PRT_OvrCurrent_1      ((uint32)((uint32)0x8U <<  PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_6_W2FC_VBUSI                 ((uint32)((uint32)0x10U <<  PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_6_ETPWM1SYNCO                ((uint32)((uint32)0x20U <<  PINMUX_PIN_6_SHIFT))
+
+#define PINMUX_PIN_9_GIOA_2                     ((uint32)((uint32)0x1U <<  PINMUX_PIN_9_SHIFT))
+#define PINMUX_PIN_9_OHCI_RCFG_txdPls_1         ((uint32)((uint32)0x2U <<  PINMUX_PIN_9_SHIFT))
+#define PINMUX_PIN_9_W2FC_TXDO                  ((uint32)((uint32)0x4U <<  PINMUX_PIN_9_SHIFT))
+#define PINMUX_PIN_9_HET2_0                     ((uint32)((uint32)0x8U <<  PINMUX_PIN_9_SHIFT))
+#define PINMUX_PIN_9_EQEP2I                     ((uint32)((uint32)0x10U <<  PINMUX_PIN_9_SHIFT))
+
+#define PINMUX_PIN_14_GIOA_5                    ((uint32)((uint32)0x1U <<  PINMUX_PIN_14_SHIFT))
+#define PINMUX_PIN_14_EXTCLKIN                  ((uint32)((uint32)0x2U <<  PINMUX_PIN_14_SHIFT))
+#define PINMUX_PIN_14_ETPWM1A                   ((uint32)((uint32)0x4U <<  PINMUX_PIN_14_SHIFT))
+
+#define PINMUX_PIN_15_HET1_22                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_15_SHIFT))
+#define PINMUX_PIN_15_OHCI_RCFG_txSe0_1         ((uint32)((uint32)0x2U <<  PINMUX_PIN_15_SHIFT))
+#define PINMUX_PIN_15_W2FC_SE0O                 ((uint32)((uint32)0x4U <<  PINMUX_PIN_15_SHIFT))
+
+#define PINMUX_PIN_16_GIOA_6                    ((uint32)((uint32)0x1U <<  PINMUX_PIN_16_SHIFT))
+#define PINMUX_PIN_16_HET2_4                    ((uint32)((uint32)0x2U <<  PINMUX_PIN_16_SHIFT))
+#define PINMUX_PIN_16_ETPWM1B                   ((uint32)((uint32)0x4U <<  PINMUX_PIN_16_SHIFT))
+
+#define PINMUX_PIN_22_GIOA_7                    ((uint32)((uint32)0x1U <<  PINMUX_PIN_22_SHIFT))
+#define PINMUX_PIN_22_HET2_6                    ((uint32)((uint32)0x2U <<  PINMUX_PIN_22_SHIFT))
+#define PINMUX_PIN_22_ETPWM2A                   ((uint32)((uint32)0x4U <<  PINMUX_PIN_22_SHIFT))
+
+#define PINMUX_PIN_23_HET1_01                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_23_SPI4NENA                  ((uint32)((uint32)0x2U <<  PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_23_OHCI_RCFG_txEnL_1         ((uint32)((uint32)0x4U <<  PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_23_W2FC_PUENO                ((uint32)((uint32)0x8U <<  PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_23_HET2_8                    ((uint32)((uint32)0x10U <<  PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_23_EQEP2A                    ((uint32)((uint32)0x20U <<  PINMUX_PIN_23_SHIFT))
+
+#define PINMUX_PIN_24_HET1_03                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_24_SPI4NCS_0                 ((uint32)((uint32)0x2U <<  PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_24_OHCI_RCFG_speed_1         ((uint32)((uint32)0x4U <<  PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_24_W2FC_PUENON               ((uint32)((uint32)0x8U <<  PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_24_HET2_10                   ((uint32)((uint32)0x10U <<  PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_24_EQEP2B                    ((uint32)((uint32)0x20U <<  PINMUX_PIN_24_SHIFT))
+
+#define PINMUX_PIN_25_HET1_0                    ((uint32)((uint32)0x1U <<  PINMUX_PIN_25_SHIFT))
+#define PINMUX_PIN_25_SPI4CLK                   ((uint32)((uint32)0x2U <<  PINMUX_PIN_25_SHIFT))
+#define PINMUX_PIN_25_ETPWM2B                   ((uint32)((uint32)0x4U <<  PINMUX_PIN_25_SHIFT))
+
+#define PINMUX_PIN_30_HET1_02                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_30_SHIFT))
+#define PINMUX_PIN_30_SPI4SIMO                  ((uint32)((uint32)0x2U <<  PINMUX_PIN_30_SHIFT))
+#define PINMUX_PIN_30_ETPWM3A                   ((uint32)((uint32)0x4U <<  PINMUX_PIN_30_SHIFT))
+
+#define PINMUX_PIN_31_HET1_05                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_31_SHIFT))
+#define PINMUX_PIN_31_SPI4SOMI                  ((uint32)((uint32)0x2U <<  PINMUX_PIN_31_SHIFT))
+#define PINMUX_PIN_31_HET2_12                   ((uint32)((uint32)0x4U <<  PINMUX_PIN_31_SHIFT))
+#define PINMUX_PIN_31_ETPWM3B                   ((uint32)((uint32)0x8U <<  PINMUX_PIN_31_SHIFT))
+
+#define PINMUX_PIN_32_MIBSPI5NCS_0              ((uint32)((uint32)0x1U <<  PINMUX_PIN_32_SHIFT))
+#define PINMUX_PIN_32_ETPWM4A                   ((uint32)((uint32)0x4U <<  PINMUX_PIN_32_SHIFT))
+
+#define PINMUX_PIN_33_HET1_07                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_33_SHIFT))
+#define PINMUX_PIN_33_OHCI_RCFG_PrtPower_1      ((uint32)((uint32)0x2U <<  PINMUX_PIN_33_SHIFT))
+#define PINMUX_PIN_33_W2FC_GZO                  ((uint32)((uint32)0x4U <<  PINMUX_PIN_33_SHIFT))
+#define PINMUX_PIN_33_HET2_14                   ((uint32)((uint32)0x8U <<  PINMUX_PIN_33_SHIFT))
+#define PINMUX_PIN_33_ETPWM7B                   ((uint32)((uint32)0x10U <<  PINMUX_PIN_33_SHIFT))
+
+#define PINMUX_PIN_35_HET1_09                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_35_SHIFT))
+#define PINMUX_PIN_35_HET2_16                   ((uint32)((uint32)0x2U <<  PINMUX_PIN_35_SHIFT))
+#define PINMUX_PIN_35_OHCI_RCFG_suspend_1       ((uint32)((uint32)0x4U <<  PINMUX_PIN_35_SHIFT))
+#define PINMUX_PIN_35_W2FC_SUSPENDO             ((uint32)((uint32)0x8U <<  PINMUX_PIN_35_SHIFT))
+#define PINMUX_PIN_35_ETPWM7A                   ((uint32)((uint32)0x10U <<  PINMUX_PIN_35_SHIFT))
+
+#define PINMUX_PIN_36_HET1_04                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_36_SHIFT))
+#define PINMUX_PIN_36_ETPWM4B                   ((uint32)((uint32)0x2U <<  PINMUX_PIN_36_SHIFT))
+
+#define PINMUX_PIN_37_MIBSPI3NCS_1              ((uint32)((uint32)0x1U <<  PINMUX_PIN_37_SHIFT))
+#define PINMUX_PIN_37_HET1_25                   ((uint32)((uint32)0x2U <<  PINMUX_PIN_37_SHIFT))
+#define PINMUX_PIN_37_MDCLK                     ((uint32)((uint32)0x4U <<  PINMUX_PIN_37_SHIFT))
+
+#define PINMUX_PIN_38_HET1_06                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_38_SHIFT))
+#define PINMUX_PIN_38_SCIRX                     ((uint32)((uint32)0x2U <<  PINMUX_PIN_38_SHIFT))
+#define PINMUX_PIN_38_ETPWM5A                   ((uint32)((uint32)0x4U <<  PINMUX_PIN_38_SHIFT))
+
+#define PINMUX_PIN_39_HET1_13                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_39_SHIFT))
+#define PINMUX_PIN_39_SCITX                     ((uint32)((uint32)0x2U <<  PINMUX_PIN_39_SHIFT))
+#define PINMUX_PIN_39_ETPWM5B                   ((uint32)((uint32)0x4U <<  PINMUX_PIN_39_SHIFT))
+
+#define PINMUX_PIN_40_MIBSPI1NCS_2              ((uint32)((uint32)0x1U <<  PINMUX_PIN_40_SHIFT))
+#define PINMUX_PIN_40_HET1_19                   ((uint32)((uint32)0x2U <<  PINMUX_PIN_40_SHIFT))
+#define PINMUX_PIN_40_MDIO                      ((uint32)((uint32)0x4U <<  PINMUX_PIN_40_SHIFT))
+
+#define PINMUX_PIN_41_HET1_15                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_41_SHIFT))
+#define PINMUX_PIN_41_MIBSPI1NCS_4              ((uint32)((uint32)0x2U <<  PINMUX_PIN_41_SHIFT))
+#define PINMUX_PIN_41_ECAP1                     ((uint32)((uint32)0x4U <<  PINMUX_PIN_41_SHIFT))
+
+#define PINMUX_PIN_51_MIBSPI3SOMI               ((uint32)((uint32)0x1U <<  PINMUX_PIN_51_SHIFT))
+#define PINMUX_PIN_51_AWM_EXT_ENA               ((uint32)((uint32)0x2U <<  PINMUX_PIN_51_SHIFT))
+#define PINMUX_PIN_51_ECAP2                     ((uint32)((uint32)0x4U <<  PINMUX_PIN_51_SHIFT))
+
+#define PINMUX_PIN_52_MIBSPI3SIMO               ((uint32)((uint32)0x1U <<  PINMUX_PIN_52_SHIFT))
+#define PINMUX_PIN_52_AWM_EXT_SEL_0             ((uint32)((uint32)0x2U <<  PINMUX_PIN_52_SHIFT))
+#define PINMUX_PIN_52_ECAP3                     ((uint32)((uint32)0x4U <<  PINMUX_PIN_52_SHIFT))
+
+#define PINMUX_PIN_53_MIBSPI3CLK                ((uint32)((uint32)0x1U <<  PINMUX_PIN_53_SHIFT))
+#define PINMUX_PIN_53_AWM_EXT_SEL_1             ((uint32)((uint32)0x2U <<  PINMUX_PIN_53_SHIFT))
+#define PINMUX_PIN_53_EQEP1A                    ((uint32)((uint32)0x4U <<  PINMUX_PIN_53_SHIFT))
+
+#define PINMUX_PIN_54_MIBSPI3NENA               ((uint32)((uint32)0x1U <<  PINMUX_PIN_54_SHIFT))
+#define PINMUX_PIN_54_MIBSPI3NCS_5              ((uint32)((uint32)0x2U <<  PINMUX_PIN_54_SHIFT))
+#define PINMUX_PIN_54_HET1_31                   ((uint32)((uint32)0x4U <<  PINMUX_PIN_54_SHIFT))
+#define PINMUX_PIN_54_EQEP1B                    ((uint32)((uint32)0x8U <<  PINMUX_PIN_54_SHIFT))
+
+#define PINMUX_PIN_55_MIBSPI3NCS_0              ((uint32)((uint32)0x1U <<  PINMUX_PIN_55_SHIFT))
+#define PINMUX_PIN_55_AD2EVT                    ((uint32)((uint32)0x2U <<  PINMUX_PIN_55_SHIFT))
+#define PINMUX_PIN_55_GIOB_2                    ((uint32)((uint32)0x4U <<  PINMUX_PIN_55_SHIFT))
+#define PINMUX_PIN_55_EQEP1I                    ((uint32)((uint32)0x8U <<  PINMUX_PIN_55_SHIFT))
+
+#define PINMUX_PIN_86_AD1EVT                    ((uint32)((uint32)0x1U <<  PINMUX_PIN_86_SHIFT))
+#define PINMUX_PIN_86_MII_RX_ER                 ((uint32)((uint32)0x2U <<  PINMUX_PIN_86_SHIFT))
+#define PINMUX_PIN_86_RMII_RX_ER                ((uint32)((uint32)0x4U <<  PINMUX_PIN_86_SHIFT))
+
+#define PINMUX_PIN_91_HET1_24                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_91_SHIFT))
+#define PINMUX_PIN_91_MIBSPI1NCS_5              ((uint32)((uint32)0x2U <<  PINMUX_PIN_91_SHIFT))
+#define PINMUX_PIN_91_MII_RXD_0                 ((uint32)((uint32)0x4U <<  PINMUX_PIN_91_SHIFT))
+#define PINMUX_PIN_91_RMII_RXD_0                ((uint32)((uint32)0x8U <<  PINMUX_PIN_91_SHIFT))
+
+#define PINMUX_PIN_92_HET1_26                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_92_SHIFT))
+#define PINMUX_PIN_92_MII_RXD_1                 ((uint32)((uint32)0x2U <<  PINMUX_PIN_92_SHIFT))
+#define PINMUX_PIN_92_RMII_RXD_1                ((uint32)((uint32)0x4U <<  PINMUX_PIN_92_SHIFT))
+
+#define PINMUX_PIN_96_MIBSPI1NENA               ((uint32)((uint32)0x1U <<  PINMUX_PIN_96_SHIFT))
+#define PINMUX_PIN_96_HET1_23                   ((uint32)((uint32)0x2U <<  PINMUX_PIN_96_SHIFT))
+#define PINMUX_PIN_96_MII_RXD_2                 ((uint32)((uint32)0x4U <<  PINMUX_PIN_96_SHIFT))
+#define PINMUX_PIN_96_OHCI_PRT_RcvDpls_0        ((uint32)((uint32)0x8U <<  PINMUX_PIN_96_SHIFT))
+#define PINMUX_PIN_96_ECAP4                     ((uint32)((uint32)0x10U <<  PINMUX_PIN_96_SHIFT))
+
+#define PINMUX_PIN_97_MIBSPI5NENA               ((uint32)((uint32)0x1U <<  PINMUX_PIN_97_SHIFT))
+#define PINMUX_PIN_97_MII_RXD_3                 ((uint32)((uint32)0x4U <<  PINMUX_PIN_97_SHIFT))
+#define PINMUX_PIN_97_OHCI_PRT_RcvDmns_0        ((uint32)((uint32)0x8U <<  PINMUX_PIN_97_SHIFT))
+#define PINMUX_PIN_97_MIBSPI5SOMI_1             ((uint32)((uint32)0x10U <<  PINMUX_PIN_97_SHIFT))
+#define PINMUX_PIN_97_ECAP5                     ((uint32)((uint32)0x20U <<  PINMUX_PIN_97_SHIFT))
+
+#define PINMUX_PIN_98_MIBSPI5SOMI_0             ((uint32)((uint32)0x1U <<  PINMUX_PIN_98_SHIFT))
+#define PINMUX_PIN_98_MII_TXD_0                 ((uint32)((uint32)0x4U <<  PINMUX_PIN_98_SHIFT))
+#define PINMUX_PIN_98_RMII_TXD_0                ((uint32)((uint32)0x8U <<  PINMUX_PIN_98_SHIFT))
+
+#define PINMUX_PIN_99_MIBSPI5SIMO_0             ((uint32)((uint32)0x1U <<  PINMUX_PIN_99_SHIFT))
+#define PINMUX_PIN_99_MII_TXD_1                 ((uint32)((uint32)0x4U <<  PINMUX_PIN_99_SHIFT))
+#define PINMUX_PIN_99_RMII_TXD_1                ((uint32)((uint32)0x8U <<  PINMUX_PIN_99_SHIFT))
+#define PINMUX_PIN_99_MIBSPI5SOMI_2             ((uint32)((uint32)0x10U <<  PINMUX_PIN_99_SHIFT))
+
+#define PINMUX_PIN_100_MIBSPI5CLK               ((uint32)((uint32)0x1U <<  PINMUX_PIN_100_SHIFT))
+#define PINMUX_PIN_100_MII_TXEN                 ((uint32)((uint32)0x4U <<  PINMUX_PIN_100_SHIFT))
+#define PINMUX_PIN_100_RMII_TXEN                ((uint32)((uint32)0x8U <<  PINMUX_PIN_100_SHIFT))
+
+#define PINMUX_PIN_105_MIBSPI1NCS_0             ((uint32)((uint32)0x1U <<  PINMUX_PIN_105_SHIFT))
+#define PINMUX_PIN_105_MIBSPI1SOMI_1            ((uint32)((uint32)0x2U <<  PINMUX_PIN_105_SHIFT))
+#define PINMUX_PIN_105_MII_TXD_2                ((uint32)((uint32)0x4U <<  PINMUX_PIN_105_SHIFT))
+#define PINMUX_PIN_105_OHCI_PRT_RcvData_0       ((uint32)((uint32)0x8U <<  PINMUX_PIN_105_SHIFT))
+#define PINMUX_PIN_105_ECAP6                    ((uint32)((uint32)0x10U <<  PINMUX_PIN_105_SHIFT))
+
+#define PINMUX_PIN_106_HET1_08                  ((uint32)((uint32)0x1U <<  PINMUX_PIN_106_SHIFT))
+#define PINMUX_PIN_106_MIBSPI1SIMO_1            ((uint32)((uint32)0x2U <<  PINMUX_PIN_106_SHIFT))
+#define PINMUX_PIN_106_MII_TXD_3                ((uint32)((uint32)0x4U <<  PINMUX_PIN_106_SHIFT))
+#define PINMUX_PIN_106_OHCI_PRT_OvrCurrent_0    ((uint32)((uint32)0x8U <<  PINMUX_PIN_106_SHIFT))
+
+#define PINMUX_PIN_107_HET1_28                  ((uint32)((uint32)0x1U <<  PINMUX_PIN_107_SHIFT))
+#define PINMUX_PIN_107_MII_RXCLK                ((uint32)((uint32)0x2U <<  PINMUX_PIN_107_SHIFT))
+#define PINMUX_PIN_107_RMII_REFCLK              ((uint32)((uint32)0x4U <<  PINMUX_PIN_107_SHIFT))
+#define PINMUX_PIN_107_MII_RX_AVCLK4            ((uint32)((uint32)0x8U <<  PINMUX_PIN_107_SHIFT))
+
+#define PINMUX_PIN_118_HET1_10                  ((uint32)((uint32)0x1U <<  PINMUX_PIN_118_SHIFT))
+#define PINMUX_PIN_118_MII_TX_CLK               ((uint32)((uint32)0x2U <<  PINMUX_PIN_118_SHIFT))
+#define PINMUX_PIN_118_OHCI_RCFG_txEnL_0        ((uint32)((uint32)0x4U <<  PINMUX_PIN_118_SHIFT))
+#define PINMUX_PIN_118_MII_TX_AVCLK4            ((uint32)((uint32)0x8U <<  PINMUX_PIN_118_SHIFT))
+#define PINMUX_PIN_118_nTZ3                     ((uint32)((uint32)0x10U <<  PINMUX_PIN_118_SHIFT))
+
+#define PINMUX_PIN_124_HET1_12                  ((uint32)((uint32)0x1U <<  PINMUX_PIN_124_SHIFT))
+#define PINMUX_PIN_124_MII_CRS                  ((uint32)((uint32)0x2U <<  PINMUX_PIN_124_SHIFT))
+#define PINMUX_PIN_124_RMII_CRS_DV              ((uint32)((uint32)0x4U <<  PINMUX_PIN_124_SHIFT))
+
+#define PINMUX_PIN_125_HET1_14                  ((uint32)((uint32)0x1U <<  PINMUX_PIN_125_SHIFT))
+#define PINMUX_PIN_125_OHCI_RCFG_txSe0_0        ((uint32)((uint32)0x2U <<  PINMUX_PIN_125_SHIFT))
+
+#define PINMUX_PIN_126_GIOB_0                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_126_SHIFT))
+#define PINMUX_PIN_126_OHCI_RCFG_txDpls_0       ((uint32)((uint32)0x2U <<  PINMUX_PIN_126_SHIFT))
+
+#define PINMUX_PIN_127_HET1_30                  ((uint32)((uint32)0x1U <<  PINMUX_PIN_127_SHIFT))
+#define PINMUX_PIN_127_MII_RX_DV                ((uint32)((uint32)0x2U <<  PINMUX_PIN_127_SHIFT))
+#define PINMUX_PIN_127_OHCI_RCFG_speed_0        ((uint32)((uint32)0x4U <<  PINMUX_PIN_127_SHIFT))
+#define PINMUX_PIN_127_EQEP2S                   ((uint32)((uint32)0x8U <<  PINMUX_PIN_127_SHIFT))
+
+#define PINMUX_PIN_130_MIBSPI1NCS_1             ((uint32)((uint32)0x1U <<  PINMUX_PIN_130_SHIFT))
+#define PINMUX_PIN_130_HET1_17                  ((uint32)((uint32)0x2U <<  PINMUX_PIN_130_SHIFT))
+#define PINMUX_PIN_130_MII_COL                  ((uint32)((uint32)0x4U <<  PINMUX_PIN_130_SHIFT))
+#define PINMUX_PIN_130_OHCI_RCFG_suspend_0      ((uint32)((uint32)0x8U <<  PINMUX_PIN_130_SHIFT))
+#define PINMUX_PIN_130_EQEP1S                   ((uint32)((uint32)0x10U <<  PINMUX_PIN_130_SHIFT))
+
+#define PINMUX_PIN_133_GIOB_1                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_133_SHIFT))
+#define PINMUX_PIN_133_OHCI_RCFG_PrtPower_0     ((uint32)((uint32)0x2U <<  PINMUX_PIN_133_SHIFT))
+
+#define PINMUX_PIN_139_HET1_16                  ((uint32)((uint32)0x1U <<  PINMUX_PIN_139_SHIFT))
+#define PINMUX_PIN_139_ETPWM1SYNCI              ((uint32)((uint32)0x2U <<  PINMUX_PIN_139_SHIFT))
+#define PINMUX_PIN_139_ETPWM1SYNCO              ((uint32)((uint32)0x4U <<  PINMUX_PIN_139_SHIFT))
+
+#define PINMUX_PIN_140_HET1_18                  ((uint32)((uint32)0x1U <<  PINMUX_PIN_140_SHIFT))
+#define PINMUX_PIN_140_ETPWM6A                  ((uint32)((uint32)0x2U <<  PINMUX_PIN_140_SHIFT))
+
+#define PINMUX_PIN_141_HET1_20                  ((uint32)((uint32)0x1U <<  PINMUX_PIN_141_SHIFT))
+#define PINMUX_PIN_141_ETPWM6B                  ((uint32)((uint32)0x2U <<  PINMUX_PIN_141_SHIFT))
+
+#define PINMUX_PIN_133_GIOB_1                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_133_SHIFT))
+
+#define PINMUX_PIN_1_GIOB_3                     ((uint32)((uint32)0x1U <<  PINMUX_PIN_1_SHIFT))
+
+#define PINMUX_PIN_2_GIOA_0                     ((uint32)((uint32)0x1U <<  PINMUX_PIN_2_SHIFT))
+
+#define PINMUX_PIN_5_GIOA_1                     ((uint32)((uint32)0x1U <<  PINMUX_PIN_5_SHIFT))
+
+#define PINMUX_PIN_15_HET1_22                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_15_SHIFT))
+
+#define PINMUX_PIN_125_HET1_14                  ((uint32)((uint32)0x1U <<  PINMUX_PIN_125_SHIFT))
+
+#define PINMUX_PIN_126_GIOB_0                   ((uint32)((uint32)0x1U <<  PINMUX_PIN_126_SHIFT))
+
+#define PINMUX_GATE_EMIF_CLK_ON                 ((uint32)((uint32)0x0 <<  PINMUX_GATE_EMIF_CLK_SHIFT))
+#define PINMUX_GIOB_DISABLE_HET2_ON             ((uint32)((uint32)0x1U <<  PINMUX_GIOB_DISABLE_HET2_SHIFT))
+#define PINMUX_GATE_EMIF_CLK_OFF                ((uint32)((uint32)0x1U <<  PINMUX_GATE_EMIF_CLK_SHIFT))
+#define PINMUX_GIOB_DISABLE_HET2_OFF            ((uint32)((uint32)0x0 <<  PINMUX_GIOB_DISABLE_HET2_SHIFT))
+#define PINMUX_ALT_ADC_TRIGGER_1                ((uint32)((uint32)0x1U <<  PINMUX_ALT_ADC_TRIGGER_SHIFT))
+#define PINMUX_ALT_ADC_TRIGGER_2                ((uint32)((uint32)0x2U <<  PINMUX_ALT_ADC_TRIGGER_SHIFT))
+#define PINMUX_ETHERNET_MII                     ((uint32)((uint32)0x0 <<  PINMUX_ETHERNET_SHIFT))
+#define PINMUX_ETHERNET_RMII                    ((uint32)((uint32)0x1U <<  PINMUX_ETHERNET_SHIFT))
+
+#define PINMUX_ETPWM1_EQEPERR12                 ((uint32)((uint32)0x1U <<  PINMUX_ETPWM1_SHIFT))
+#define PINMUX_ETPWM1_EQEPERR1                  ((uint32)((uint32)0x2U <<  PINMUX_ETPWM1_SHIFT))
+#define PINMUX_ETPWM1_EQEPERR2                  ((uint32)((uint32)0x4U <<  PINMUX_ETPWM1_SHIFT))
+#define PINMUX_ETPWM2_EQEPERR12                 ((uint32)((uint32)0x1U <<  PINMUX_ETPWM2_SHIFT))
+#define PINMUX_ETPWM2_EQEPERR1                  ((uint32)((uint32)0x2U <<  PINMUX_ETPWM2_SHIFT))
+#define PINMUX_ETPWM2_EQEPERR2                  ((uint32)((uint32)0x4U <<  PINMUX_ETPWM2_SHIFT))
+#define PINMUX_ETPWM3_EQEPERR12                 ((uint32)((uint32)0x1U <<  PINMUX_ETPWM3_SHIFT))
+#define PINMUX_ETPWM3_EQEPERR1                  ((uint32)((uint32)0x2U <<  PINMUX_ETPWM3_SHIFT))
+#define PINMUX_ETPWM3_EQEPERR2                  ((uint32)((uint32)0x4U <<  PINMUX_ETPWM3_SHIFT))
+#define PINMUX_ETPWM4_EQEPERR12                 ((uint32)((uint32)0x1U <<  PINMUX_ETPWM4_SHIFT))
+#define PINMUX_ETPWM4_EQEPERR1                  ((uint32)((uint32)0x2U <<  PINMUX_ETPWM4_SHIFT))
+#define PINMUX_ETPWM4_EQEPERR2                  ((uint32)((uint32)0x4U <<  PINMUX_ETPWM4_SHIFT))
+#define PINMUX_ETPWM5_EQEPERR12                 ((uint32)((uint32)0x1U <<  PINMUX_ETPWM5_SHIFT))
+#define PINMUX_ETPWM5_EQEPERR1                  ((uint32)((uint32)0x2U <<  PINMUX_ETPWM5_SHIFT))
+#define PINMUX_ETPWM5_EQEPERR2                  ((uint32)((uint32)0x4U <<  PINMUX_ETPWM5_SHIFT))
+#define PINMUX_ETPWM6_EQEPERR12                 ((uint32)((uint32)0x1U <<  PINMUX_ETPWM6_SHIFT))
+#define PINMUX_ETPWM6_EQEPERR1                  ((uint32)((uint32)0x2U <<  PINMUX_ETPWM6_SHIFT))
+#define PINMUX_ETPWM6_EQEPERR2                  ((uint32)((uint32)0x4U <<  PINMUX_ETPWM6_SHIFT))
+#define PINMUX_ETPWM7_EQEPERR12                 ((uint32)((uint32)0x1U <<  PINMUX_ETPWM7_SHIFT))
+#define PINMUX_ETPWM7_EQEPERR1                  ((uint32)((uint32)0x2U <<  PINMUX_ETPWM7_SHIFT))
+#define PINMUX_ETPWM7_EQEPERR2                  ((uint32)((uint32)0x4U <<  PINMUX_ETPWM7_SHIFT))
+#define PINMUX_ETPWM_TIME_BASE_SYNC_ON          ((uint32)((uint32)0x2U <<  PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT))
+#define PINMUX_ETPWM_TBCLK_SYNC_ON              ((uint32)((uint32)0x2U <<  PINMUX_ETPWM_TBCLK_SYNC_SHIFT))
+#define PINMUX_ETPWM_TIME_BASE_SYNC_OFF         ((uint32)((uint32)0x0 <<  PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT))
+#define PINMUX_ETPWM_TBCLK_SYNC_OFF             ((uint32)((uint32)0x0 <<  PINMUX_ETPWM_TBCLK_SYNC_SHIFT))
+#define PINMUX_TZ1_ASYNC                        ((uint32)((uint32)0x1U <<  PINMUX_TZ1_SHIFT))
+#define PINMUX_TZ1_SYNC                         ((uint32)((uint32)0x2U <<  PINMUX_TZ1_SHIFT))
+#define PINMUX_TZ1_FILTERED                     ((uint32)((uint32)0x4U <<  PINMUX_TZ1_SHIFT))
+#define PINMUX_TZ2_ASYNC                        ((uint32)((uint32)0x1U <<  PINMUX_TZ2_SHIFT))
+#define PINMUX_TZ2_SYNC                         ((uint32)((uint32)0x2U <<  PINMUX_TZ2_SHIFT))
+#define PINMUX_TZ2_FILTERED                     ((uint32)((uint32)0x4U <<  PINMUX_TZ2_SHIFT))
+#define PINMUX_TZ3_ASYNC                        ((uint32)((uint32)0x1U <<  PINMUX_TZ3_SHIFT))
+#define PINMUX_TZ3_SYNC                         ((uint32)((uint32)0x2U <<  PINMUX_TZ3_SHIFT))
+#define PINMUX_TZ3_FILTERED                     ((uint32)((uint32)0x4U <<  PINMUX_TZ3_SHIFT))
+#define PINMUX_EPWM1SYNCI_ASYNC                 ((uint32)((uint32)0x1U <<  PINMUX_EPWM1SYNCI_SHIFT))
+#define PINMUX_EPWM1SYNCI_SYNC                  ((uint32)((uint32)0x2U <<  PINMUX_EPWM1SYNCI_SHIFT))
+#define PINMUX_EPWM1SYNCI_FILTERED              ((uint32)((uint32)0x4U <<  PINMUX_EPWM1SYNCI_SHIFT))
+
+typedef struct pinmux_config_reg
+{
+    uint32 CONFIG_PINMMR0;
+    uint32 CONFIG_PINMMR1;
+    uint32 CONFIG_PINMMR2;
+    uint32 CONFIG_PINMMR3;
+    uint32 CONFIG_PINMMR4;
+    uint32 CONFIG_PINMMR5;
+    uint32 CONFIG_PINMMR6;
+    uint32 CONFIG_PINMMR7;
+    uint32 CONFIG_PINMMR8;
+    uint32 CONFIG_PINMMR9;
+    uint32 CONFIG_PINMMR10;
+    uint32 CONFIG_PINMMR11;
+    uint32 CONFIG_PINMMR12;
+    uint32 CONFIG_PINMMR13;
+    uint32 CONFIG_PINMMR14;
+    uint32 CONFIG_PINMMR15;
+    uint32 CONFIG_PINMMR16;
+    uint32 CONFIG_PINMMR17;
+    uint32 CONFIG_PINMMR18;
+    uint32 CONFIG_PINMMR19;
+    uint32 CONFIG_PINMMR20;
+    uint32 CONFIG_PINMMR21;
+    uint32 CONFIG_PINMMR22;
+    uint32 CONFIG_PINMMR23;
+    uint32 CONFIG_PINMMR24;
+    uint32 CONFIG_PINMMR25;
+    uint32 CONFIG_PINMMR26;
+    uint32 CONFIG_PINMMR27;
+    uint32 CONFIG_PINMMR28;
+    uint32 CONFIG_PINMMR29;
+    uint32 CONFIG_PINMMR30;
+    uint32 CONFIG_PINMMR31;
+    uint32 CONFIG_PINMMR32;
+    uint32 CONFIG_PINMMR33;
+    uint32 CONFIG_PINMMR34;
+    uint32 CONFIG_PINMMR35;
+    uint32 CONFIG_PINMMR36;
+    uint32 CONFIG_PINMMR37;
+    uint32 CONFIG_PINMMR38;
+    uint32 CONFIG_PINMMR39;
+    uint32 CONFIG_PINMMR40;
+    uint32 CONFIG_PINMMR41;
+    uint32 CONFIG_PINMMR42;
+    uint32 CONFIG_PINMMR43;
+    uint32 CONFIG_PINMMR44;
+    uint32 CONFIG_PINMMR45;
+    uint32 CONFIG_PINMMR46;
+    uint32 CONFIG_PINMMR47;
+}pinmux_config_reg_t;
+
+/**
+ *  @defgroup IOMM IOMM
+ *  @brief I/O Multiplexing and Control Module.
+ *
+ *  The IOMM contains memory-mapped registers (MMR) that control device-specific multiplexed functions.
+ *  The safety and diagnostic features of the IOMM are:
+ *  - Kicker mechanism to protect the MMRs from accidental writes
+ *  - Master-id checker to only allow the CPU to write to the MMRs
+ *  - Error indication for access violations
+ *
+ *  Related Files
+ *   - reg_pinmux.h
+ *   - pinmux.h
+ *   - pinmux.c
+ *  @addtogroup IOMM
+ *  @{
+ */
+
+/** @fn void muxInit(void)
+*   @brief Initializes the PINMUX Driver
+*
+*   This function initializes the PINMUX module and configures the selected
+*   pinmux settings as per the user selection in the GUI
+*/
+void muxInit(void);
+void pinmuxGetConfigValue(pinmux_config_reg_t *config_reg, config_value_type_t type);
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/pom.h b/include/arch/rm46l8lp/halcogen/pom.h
new file mode 100644
index 0000000..dfd4034
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/pom.h
@@ -0,0 +1,242 @@
+/** @file pom.h
+*   @brief POM Driver Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __POM_H__
+#define __POM_H__
+
+#include "reg_pom.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @enum pom_region_size
+*   @brief Alias names for pom region size
+*   This enumeration is used to provide alias names for POM region size:
+*/
+enum pom_region_size
+{
+        SIZE_32BYTES    = 0U,
+        SIZE_64BYTES    = 1U,
+        SIZE_128BYTES   = 2U,
+        SIZE_256BYTES   = 3U,
+        SIZE_512BYTES   = 4U,
+        SIZE_1KB        = 5U,
+        SIZE_2KB        = 6U,
+        SIZE_4KB        = 7U,
+        SIZE_8KB        = 8U,
+        SIZE_16KB       = 9U,
+        SIZE_32KB       = 10U,
+        SIZE_64KB       = 11U,
+        SIZE_128KB      = 12U,
+        SIZE_256KB      = 13U
+};
+
+/** @def INTERNAL_RAM 
+*   @brief Alias name for Internal RAM
+*/   
+#define INTERNAL_RAM    0x08000000U
+
+/** @def SDRAM 
+*   @brief Alias name for SD RAM
+*/   
+#define SDRAM   0x80000000U
+
+/** @def ASYNC_MEMORY 
+*   @brief Alias name for Async RAM
+*/   
+#define ASYNC_MEMORY   0x60000000U
+
+
+typedef uint32 REGION_t;
+
+/** @struct REGION_CONFIG_ST
+*   @brief POM region configuration
+*/
+typedef struct
+{       
+        uint32 Prog_Reg_Sta_Addr;
+        uint32 Ovly_Reg_Sta_Addr;
+        uint32 Reg_Size;
+}REGION_CONFIG_t;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/* Configuration registers */
+typedef struct pom_config_reg
+{
+    uint32 CONFIG_POMGLBCTRL;
+    uint32 CONFIG_POMPROGSTART0;
+    uint32 CONFIG_POMOVLSTART0;
+    uint32 CONFIG_POMREGSIZE0;        
+    uint32 CONFIG_POMPROGSTART1; 
+    uint32 CONFIG_POMOVLSTART1; 
+    uint32 CONFIG_POMREGSIZE1;
+    uint32 CONFIG_POMPROGSTART2; 
+    uint32 CONFIG_POMOVLSTART2; 
+    uint32 CONFIG_POMREGSIZE2;
+    uint32 CONFIG_POMPROGSTART3; 
+    uint32 CONFIG_POMOVLSTART3; 
+    uint32 CONFIG_POMREGSIZE3;    
+    uint32 CONFIG_POMPROGSTART4; 
+    uint32 CONFIG_POMOVLSTART4; 
+    uint32 CONFIG_POMREGSIZE4;    
+    uint32 CONFIG_POMPROGSTART5; 
+    uint32 CONFIG_POMOVLSTART5; 
+    uint32 CONFIG_POMREGSIZE5;    
+    uint32 CONFIG_POMPROGSTART6; 
+    uint32 CONFIG_POMOVLSTART6; 
+    uint32 CONFIG_POMREGSIZE6;
+    uint32 CONFIG_POMPROGSTART7; 
+    uint32 CONFIG_POMOVLSTART7; 
+    uint32 CONFIG_POMREGSIZE7;
+    uint32 CONFIG_POMPROGSTART8; 
+    uint32 CONFIG_POMOVLSTART8; 
+    uint32 CONFIG_POMREGSIZE8;    
+    uint32 CONFIG_POMPROGSTART9; 
+    uint32 CONFIG_POMOVLSTART9; 
+    uint32 CONFIG_POMREGSIZE9;    
+    uint32 CONFIG_POMPROGSTART10;
+    uint32 CONFIG_POMOVLSTART10;
+    uint32 CONFIG_POMREGSIZE10;
+    uint32 CONFIG_POMPROGSTART11; 
+    uint32 CONFIG_POMOVLSTART11; 
+    uint32 CONFIG_POMREGSIZE11;
+    uint32 CONFIG_POMPROGSTART12; 
+    uint32 CONFIG_POMOVLSTART12; 
+    uint32 CONFIG_POMREGSIZE12;
+    uint32 CONFIG_POMPROGSTART13; 
+    uint32 CONFIG_POMOVLSTART13; 
+    uint32 CONFIG_POMREGSIZE13;    
+    uint32 CONFIG_POMPROGSTART14; 
+    uint32 CONFIG_POMOVLSTART14; 
+    uint32 CONFIG_POMREGSIZE14;    
+    uint32 CONFIG_POMPROGSTART15; 
+    uint32 CONFIG_POMOVLSTART15; 
+    uint32 CONFIG_POMREGSIZE15;    
+    uint32 CONFIG_POMPROGSTART16; 
+    uint32 CONFIG_POMOVLSTART16; 
+    uint32 CONFIG_POMREGSIZE16;
+    uint32 CONFIG_POMPROGSTART17; 
+    uint32 CONFIG_POMOVLSTART17; 
+    uint32 CONFIG_POMREGSIZE17;
+    uint32 CONFIG_POMPROGSTART18; 
+    uint32 CONFIG_POMOVLSTART18; 
+    uint32 CONFIG_POMREGSIZE18;    
+    uint32 CONFIG_POMPROGSTART19; 
+    uint32 CONFIG_POMOVLSTART19; 
+    uint32 CONFIG_POMREGSIZE19;    
+    uint32 CONFIG_POMPROGSTART20;
+    uint32 CONFIG_POMOVLSTART20;
+    uint32 CONFIG_POMREGSIZE20;
+    uint32 CONFIG_POMPROGSTART21; 
+    uint32 CONFIG_POMOVLSTART21; 
+    uint32 CONFIG_POMREGSIZE21;
+    uint32 CONFIG_POMPROGSTART22; 
+    uint32 CONFIG_POMOVLSTART22; 
+    uint32 CONFIG_POMREGSIZE22;
+    uint32 CONFIG_POMPROGSTART23; 
+    uint32 CONFIG_POMOVLSTART23; 
+    uint32 CONFIG_POMREGSIZE23;    
+    uint32 CONFIG_POMPROGSTART24; 
+    uint32 CONFIG_POMOVLSTART24; 
+    uint32 CONFIG_POMREGSIZE24;    
+    uint32 CONFIG_POMPROGSTART25; 
+    uint32 CONFIG_POMOVLSTART25; 
+    uint32 CONFIG_POMREGSIZE25;    
+    uint32 CONFIG_POMPROGSTART26; 
+    uint32 CONFIG_POMOVLSTART26; 
+    uint32 CONFIG_POMREGSIZE26;
+    uint32 CONFIG_POMPROGSTART27; 
+    uint32 CONFIG_POMOVLSTART27; 
+    uint32 CONFIG_POMREGSIZE27;
+    uint32 CONFIG_POMPROGSTART28; 
+    uint32 CONFIG_POMOVLSTART28; 
+    uint32 CONFIG_POMREGSIZE28;    
+    uint32 CONFIG_POMPROGSTART29; 
+    uint32 CONFIG_POMOVLSTART29; 
+    uint32 CONFIG_POMREGSIZE29;    
+    uint32 CONFIG_POMPROGSTART30;
+    uint32 CONFIG_POMOVLSTART30;
+    uint32 CONFIG_POMREGSIZE30;
+    uint32 CONFIG_POMPROGSTART31;
+    uint32 CONFIG_POMOVLSTART31;
+    uint32 CONFIG_POMREGSIZE31;    
+} pom_config_reg_t;
+
+
+/** 
+ *  @defgroup POM POM
+ *  @brief Parameter Overlay Module.
+ *  
+ *  The POM provides a mechanism to redirect accesses to non-volatile memory into a volatile memory
+ *  internal or external to the device. The data requested by the CPU will be fetched from the overlay memory
+ *  instead of the main non-volatile memory.
+ *
+ *    Related Files
+ *   - reg_pom.h
+ *   - pom.h
+ *   - pom.c
+ *  @addtogroup POM
+ *  @{
+ */
+ 
+/* POM Interface Functions */
+void POM_Region_Config(REGION_CONFIG_t *Reg_Config_Ptr,REGION_t Region_Num);
+void POM_Reset(void);
+void POM_Init(void);
+void POM_Enable(void);
+void pomGetConfigValue(pom_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+#endif /* __POM_H_*/
diff --git a/include/arch/rm46l8lp/halcogen/reg_adc.h b/include/arch/rm46l8lp/halcogen/reg_adc.h
new file mode 100644
index 0000000..4919db7
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_adc.h
@@ -0,0 +1,261 @@
+/** @file reg_adc.h
+*   @brief ADC Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the ADC driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_ADC_H__
+#define __REG_ADC_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Adc Register Frame Definition */
+/** @struct adcBase
+*   @brief ADC Register Frame Definition
+*
+*   This type is used to access the ADC Registers.
+*/
+/** @typedef adcBASE_t
+*   @brief ADC Register Frame Type Definition
+*
+*   This type is used to access the ADC Registers.
+*/
+typedef volatile struct adcBase
+{
+    uint32 RSTCR;              /**< 0x0000: Reset control register                              */
+    uint32 OPMODECR;           /**< 0x0004: Operating mode control register                     */
+    uint32 CLOCKCR;            /**< 0x0008: Clock control register                              */
+    uint32 CALCR;              /**< 0x000C: Calibration control register                        */
+    uint32 GxMODECR[3U];       /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register       */
+    uint32 EVSRC;              /**< 0x001C: Group 0 trigger source control register             */
+    uint32 G1SRC;              /**< 0x0020: Group 1 trigger source control register             */
+    uint32 G2SRC;              /**< 0x0024: Group 2 trigger source control register             */
+    uint32 GxINTENA[3U];       /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register   */
+    uint32 GxINTFLG[3U];       /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register     */
+    uint32 GxINTCR[3U];        /**< 0x0040-0x0048: Group 0-2 interrupt threshold register       */
+    uint32 EVDMACR;            /**< 0x004C: Group 0 DMA control register                        */
+    uint32 G1DMACR;            /**< 0x0050: Group 1 DMA control register                        */
+    uint32 G2DMACR;            /**< 0x0054: Group 2 DMA control register                        */
+    uint32 BNDCR;              /**< 0x0058: Buffer boundary control register                    */
+    uint32 BNDEND;             /**< 0x005C: Buffer boundary end register                        */
+    uint32 EVSAMP;             /**< 0x0060: Group 0 sample window register                      */
+    uint32 G1SAMP;             /**< 0x0064: Group 1 sample window register                      */
+    uint32 G2SAMP;             /**< 0x0068: Group 2 sample window register                      */
+    uint32 EVSR;               /**< 0x006C: Group 0 status register                             */
+    uint32 G1SR;               /**< 0x0070: Group 1 status register                             */
+    uint32 G2SR;               /**< 0x0074: Group 2 status register                             */
+    uint32 GxSEL[3U];          /**< 0x0078-0x007C: Group 0-2 channel select register            */
+    uint32 CALR;               /**< 0x0084: Calibration register                                */
+    uint32 SMSTATE;            /**< 0x0088: State machine state register                        */
+    uint32 LASTCONV;           /**< 0x008C: Last conversion register                            */
+    struct
+    {
+        uint32 BUF0;           /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register    */
+        uint32 BUF1;           /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register    */
+        uint32 BUF2;           /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register    */
+        uint32 BUF3;           /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register    */
+        uint32 BUF4;           /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register    */
+        uint32 BUF5;           /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register    */
+        uint32 BUF6;           /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register    */
+        uint32 BUF7;           /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register    */
+    } GxBUF[3U];                                                                               
+    uint32 EVEMUBUFFER;        /**< 0x00F0: Group 0 emulation result buffer                     */
+    uint32 G1EMUBUFFER;        /**< 0x00F4: Group 1 emulation result buffer                     */
+    uint32 G2EMUBUFFER;        /**< 0x00F8: Group 2 emulation result buffer                     */
+    uint32 EVTDIR;             /**< 0x00FC: Event pin direction register                        */
+    uint32 EVTOUT;             /**< 0x0100: Event pin digital output register                   */
+    uint32 EVTIN;              /**< 0x0104: Event pin digital input register                    */
+    uint32 EVTSET;             /**< 0x0108: Event pin set register                              */
+    uint32 EVTCLR;             /**< 0x010C: Event pin clear register                            */
+    uint32 EVTPDR;             /**< 0x0110: Event pin open drain register                       */
+    uint32 EVTDIS;             /**< 0x0114: Event pin pull disable register                     */
+    uint32 EVTPSEL;            /**< 0x0118: Event pin pull select register                      */
+    uint32 EVSAMPDISEN;        /**< 0x011C: Group 0 sample discharge register                   */
+    uint32 G1SAMPDISEN;        /**< 0x0120: Group 1 sample discharge register                   */
+    uint32 G2SAMPDISEN;        /**< 0x0124: Group 2 sample discharge register                   */
+    uint32 MAGINTCR1;          /**< 0x0128: Magnitude interrupt control register 1              */
+    uint32 MAGINT1MASK;        /**< 0x012C: Magnitude interrupt mask register 1                 */
+    uint32 MAGINTCR2;          /**< 0x0130: Magnitude interrupt control register 2              */
+    uint32 MAGINT2MASK;        /**< 0x0134: Magnitude interrupt mask register 2                 */
+    uint32 MAGINTCR3;          /**< 0x0138: Magnitude interrupt control register 3              */
+    uint32 MAGINT3MASK;        /**< 0x013C: Magnitude interrupt mask register 3                 */
+    uint32   rsvd1;            /**< 0x0140: Reserved                                            */
+    uint32   rsvd2;            /**< 0x0144: Reserved                                            */
+    uint32   rsvd3;            /**< 0x0148: Reserved                                            */
+    uint32   rsvd4;            /**< 0x014C: Reserved                                            */
+    uint32   rsvd5;            /**< 0x0150: Reserved                                            */
+    uint32   rsvd6;            /**< 0x0154: Reserved                                            */
+    uint32 MAGTHRINTENASET;    /**< 0x0158: Magnitude interrupt set register                    */
+    uint32 MAGTHRINTENACLR;    /**< 0x015C: Magnitude interrupt clear register                  */
+    uint32 MAGTHRINTFLG;       /**< 0x0160: Magnitude interrupt flag register                   */
+    uint32 MAGTHRINTOFFSET;    /**< 0x0164: Magnitude interrupt offset register                 */
+    uint32 GxFIFORESETCR[3U];  /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register         */
+    uint32 EVRAMADDR;          /**< 0x0174: Group 0 RAM pointer register                        */
+    uint32 G1RAMADDR;          /**< 0x0178: Group 1 RAM pointer register                        */
+    uint32 G2RAMADDR;          /**< 0x017C: Group 2 RAM pointer register                        */
+    uint32 PARCR;              /**< 0x0180: Parity control register                             */
+    uint32 PARADDR;            /**< 0x0184: Parity error address register                       */
+    uint32 PWRUPDLYCTRL;       /**< 0x0188: Power-Up delay control register                     */
+    uint32   rsvd7;            /**< 0x018C: Reserved                                            */
+	uint32 ADEVCHNSELMODECTRL; /**< 0x0190: Event Group Channel Selection Mode Control Register */
+    uint32 ADG1CHNSELMODECTRL; /**< 0x0194: Group1 Channel Selection Mode Control Register      */
+    uint32 ADG2CHNSELMODECTRL; /**< 0x0198: Group2 Channel Selection Mode Control Register      */
+    uint32 ADEVCURRCOUNT;      /**< 0x019C: Event Group Current Count Register                  */
+    uint32 ADEVMAXCOUNT;       /**< 0x01A0: Event Group Max Count Register                      */
+    uint32 ADG1CURRCOUNT;      /**< 0x01A4: Group1 Current Count Register                       */
+    uint32 ADG1MAXCOUNT;       /**< 0x01A8: Group1 Max Count Register                           */
+    uint32 ADG2CURRCOUNT;      /**< 0x01AC: Group2 Current Count Register                       */
+    uint32 ADG2MAXCOUNT;       /**< 0x01B0: Group2 Max Count Register                           */
+} adcBASE_t;
+
+
+/** @struct adcLUTEntry
+*   @brief ADC Look-Up Table Entry
+*
+*   This type is used to access ADC Look-Up Table Entry
+*/
+/** @typedef adcLUTEntry_t
+*   @brief ADC Look-Up Table Entry
+*
+*   This type is used to access the Look-Up Table Entry.
+*/
+typedef struct adcLUTEntry
+{
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+    uint8 EV_INT_CHN_MUX_SEL;
+    uint8 EV_EXT_CHN_MUX_SEL;
+    uint16 rsvd;
+#else
+    uint16 rsvd;
+    uint8 EV_EXT_CHN_MUX_SEL;
+    uint8 EV_INT_CHN_MUX_SEL;
+#endif
+}adcLUTEntry_t;
+
+
+/** @struct adcLUT
+*   @brief ADC Look-Up Table
+*
+*   This type is used to access ADC Look-Up Table
+*/
+/** @typedef adcLUT_t
+*   @brief ADC Look-Up Table
+*
+*   This type is used to access the ADC Look-Up Table.
+*/
+typedef volatile struct adcLUT
+{
+    adcLUTEntry_t eventGroup[32];
+    adcLUTEntry_t Group1[32];
+    adcLUTEntry_t Group2[32];
+} adcLUT_t;
+
+
+/** @def adcREG1
+*   @brief ADC1 Register Frame Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC1 registers.
+*/
+#define adcREG1 ((adcBASE_t *)0xFFF7C000U)
+
+/** @def adcREG2
+*   @brief ADC2 Register Frame Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC2 registers.
+*/
+#define adcREG2 ((adcBASE_t *)0xFFF7C200U)
+
+/** @def adcRAM1
+*   @brief ADC1 RAM Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC1 RAM.
+*/
+#define adcRAM1 (*(volatile uint32 *)0xFF3E0000U)
+
+/** @def adcRAM2
+*   @brief ADC2 RAM Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC2 RAM.
+*/
+#define adcRAM2 (*(volatile uint32 *)0xFF3A0000U)
+
+/** @def adcPARRAM1
+*   @brief ADC1 Parity RAM Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC1 Parity RAM.
+*/
+#define adcPARRAM1 (*(volatile uint32 *)(0xFF3E0000U + 0x1000U))
+
+/** @def adcPARRAM2
+*   @brief ADC2 Parity RAM Pointer
+*
+*   This pointer is used by the ADC driver to access the ADC2 Parity RAM.
+*/
+#define adcPARRAM2 (*(volatile uint32 *)(0xFF3A0000U + 0x1000U))
+
+/** @def adcLUT1
+*   @brief ADC1 Look-Up Table
+*
+*   This pointer is used by the ADC driver to access the ADC1 Look-Up Table.
+*/
+#define adcLUT1 ((adcLUT_t *) 0xFF3E2000U)
+
+/** @def adcLUT2
+*   @brief ADC2 Look-Up Table
+*
+*   This pointer is used by the ADC driver to access the ADC2 Look-Up Table.
+*/
+#define adcLUT2 ((adcLUT_t *) 0xFF3A2000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_can.h b/include/arch/rm46l8lp/halcogen/reg_can.h
new file mode 100644
index 0000000..db6211a
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_can.h
@@ -0,0 +1,208 @@
+/** @file reg_can.h
+*   @brief CAN Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the CAN driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_CAN_H__
+#define __REG_CAN_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Can Register Frame Definition */
+/** @struct canBase
+*   @brief CAN Register Frame Definition
+*
+*   This type is used to access the CAN Registers.
+*/
+/** @typedef canBASE_t
+*   @brief CAN Register Frame Type Definition
+*
+*   This type is used to access the CAN Registers.
+*/
+typedef volatile struct canBase
+{
+    uint32      CTL;          /**< 0x0000: Control Register                       */
+    uint32      ES;           /**< 0x0004: Error and Status Register              */
+    uint32      EERC;         /**< 0x0008: Error Counter Register                 */
+    uint32      BTR;          /**< 0x000C: Bit Timing Register                    */
+    uint32      INT;          /**< 0x0010: Interrupt Register                     */
+    uint32      TEST;         /**< 0x0014: Test Register                          */
+    uint32      rsvd1;        /**< 0x0018: Reserved                               */
+    uint32      PERR;         /**< 0x001C: Parity/SECDED Error Code Register      */
+    uint32      rsvd2[24];    /**< 0x002C - 0x7C: Reserved                        */
+    uint32      ABOTR;        /**< 0x0080: Auto Bus On Time Register              */
+    uint32      TXRQX;        /**< 0x0084: Transmission Request X Register        */
+    uint32      TXRQx[4U];    /**< 0x0088-0x0094: Transmission Request Registers  */
+    uint32      NWDATX;       /**< 0x0098: New Data X Register                    */
+    uint32      NWDATx[4U];   /**< 0x009C-0x00A8: New Data Registers              */
+    uint32      INTPNDX;      /**< 0x00AC: Interrupt Pending X Register           */
+    uint32      INTPNDx[4U];  /**< 0x00B0-0x00BC: Interrupt Pending Registers     */
+    uint32      MSGVALX;      /**< 0x00C0: Message Valid X Register               */
+    uint32      MSGVALx[4U];  /**< 0x00C4-0x00D0: Message Valid Registers         */
+    uint32        rsvd3;      /**< 0x00D4: Reserved                               */
+    uint32      INTMUXx[4U];  /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */
+    uint32        rsvd4[6];   /**< 0x00E8: Reserved                               */
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+    uint8 IF1NO;              /**< 0x0100: IF1 Command Register, Msg Number       */
+    uint8 IF1STAT;            /**< 0x0100: IF1 Command Register, Status           */
+    uint8 IF1CMD;             /**< 0x0100: IF1 Command Register, Command          */
+    uint8   rsvd9;            /**< 0x0100: IF1 Command Register, Reserved         */
+#else
+    uint8   rsvd9;            /**< 0x0100: IF1 Command Register, Reserved         */
+    uint8 IF1CMD;             /**< 0x0100: IF1 Command Register, Command          */
+    uint8 IF1STAT;            /**< 0x0100: IF1 Command Register, Status           */
+    uint8 IF1NO;              /**< 0x0100: IF1 Command Register, Msg Number       */
+#endif
+    uint32      IF1MSK;       /**< 0x0104: IF1 Mask Register                      */
+    uint32      IF1ARB;       /**< 0x0108: IF1 Arbitration Register               */
+    uint32      IF1MCTL;      /**< 0x010C: IF1 Message Control Register           */
+    uint8 IF1DATx[8U];        /**< 0x0110-0x0114: IF1 Data A and B Registers      */
+    uint32        rsvd5[2];   /**< 0x0118: Reserved                               */
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+    uint8 IF2NO;              /**< 0x0120: IF2 Command Register, Msg No           */
+    uint8 IF2STAT;            /**< 0x0120: IF2 Command Register, Status           */
+    uint8 IF2CMD;             /**< 0x0120: IF2 Command Register, Command          */
+    uint8   rsvd10;           /**< 0x0120: IF2 Command Register, Reserved         */
+#else
+    uint8   rsvd10;            /**< 0x0120: IF2 Command Register, Reserved         */
+    uint8 IF2CMD;             /**< 0x0120: IF2 Command Register, Command          */
+    uint8 IF2STAT;            /**< 0x0120: IF2 Command Register, Status           */
+    uint8 IF2NO;              /**< 0x0120: IF2 Command Register, Msg Number       */
+#endif
+    uint32      IF2MSK;       /**< 0x0124: IF2 Mask Register                      */
+    uint32      IF2ARB;       /**< 0x0128: IF2 Arbitration Register               */
+    uint32      IF2MCTL;      /**< 0x012C: IF2 Message Control Register           */
+    uint8 IF2DATx[8U];        /**< 0x0130-0x0134: IF2 Data A and B Registers      */
+    uint32        rsvd6[2];   /**< 0x0138: Reserved                               */
+    uint32      IF3OBS;       /**< 0x0140: IF3 Observation Register               */
+    uint32      IF3MSK;       /**< 0x0144: IF3 Mask Register                      */
+    uint32      IF3ARB;       /**< 0x0148: IF3 Arbitration Register               */
+    uint32      IF3MCTL;      /**< 0x014C: IF3 Message Control Register           */
+    uint8 IF3DATx[8U];        /**< 0x0150-0x0154: IF3 Data A and B Registers      */
+    uint32        rsvd7[2];   /**< 0x0158: Reserved                               */
+    uint32      IF3UEy[4U];   /**< 0x0160-0x016C: IF3 Update Enable Registers     */
+    uint32        rsvd8[28];  /**< 0x0170: Reserved                               */
+    uint32      TIOC;         /**< 0x01E0: TX IO Control Register                 */
+    uint32      RIOC;         /**< 0x01E4: RX IO Control Register                 */
+} canBASE_t;
+
+
+/** @def canREG1
+*   @brief CAN1 Register Frame Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN1 registers.
+*/
+#define canREG1 ((canBASE_t *)0xFFF7DC00U)
+
+/** @def canREG2
+*   @brief CAN2 Register Frame Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN2 registers.
+*/
+#define canREG2 ((canBASE_t *)0xFFF7DE00U)
+
+/** @def canREG3
+*   @brief CAN3 Register Frame Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN3 registers.
+*/
+#define canREG3 ((canBASE_t *)0xFFF7E000U)
+
+/** @def canRAM1
+*   @brief CAN1 Mailbox RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN1 RAM.
+*/
+#define canRAM1 (*(volatile uint32 *)0xFF1E0000U)
+
+/** @def canRAM2
+*   @brief CAN2 Mailbox RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN2 RAM.
+*/
+#define canRAM2 (*(volatile uint32 *)0xFF1C0000U)
+
+/** @def canRAM3
+*   @brief CAN3 Mailbox RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN3 RAM.
+*/
+#define canRAM3 (*(volatile uint32 *)0xFF1A0000U)
+
+/** @def canPARRAM1
+*   @brief CAN1 Mailbox Parity RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN1 Parity RAM
+*   for testing RAM parity error detect logic.
+*/
+#define canPARRAM1 (*(volatile uint32 *)(0xFF1E0000U + 0x10U))
+
+/** @def canPARRAM2
+*   @brief CAN2 Mailbox Parity RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN2 Parity RAM
+*   for testing RAM parity error detect logic.
+*/
+#define canPARRAM2 (*(volatile uint32 *)(0xFF1C0000U + 0x10U))
+
+/** @def canPARRAM3
+*   @brief CAN3 Mailbox Parity RAM Pointer
+*
+*   This pointer is used by the CAN driver to access the CAN3 Parity RAM
+*   for testing RAM parity error detect logic.
+*/
+#define canPARRAM3 (*(volatile uint32 *)(0xFF1A0000U + 0x10U))
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_crc.h b/include/arch/rm46l8lp/halcogen/reg_crc.h
new file mode 100644
index 0000000..7ba7df6
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_crc.h
@@ -0,0 +1,127 @@
+/** @file reg_crc.h
+*   @brief CRC Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the CRC driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_CRC_H__
+#define __REG_CRC_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Crc Register Frame Definition */
+/** @struct crcBase
+*   @brief CRC Register Frame Definition
+*
+*   This type is used to access the CRC Registers.
+*/
+/** @typedef crcBASE_t
+*   @brief CRC Register Frame Type Definition
+*
+*   This type is used to access the CRC Registers.
+*/
+typedef volatile struct crcBase
+{
+    uint32      CTRL0;                /**< 0x0000: Global Control Register 0 >**/
+    uint32      rvd1;                 /**< 0x0004: reserved >**/
+    uint32      CTRL1;                /**< 0x0008: Global Control Register 1 >**/
+    uint32      rvd2;                 /**< 0x000C: reserved >**/    
+    uint32      CTRL2;                /**< 0x0010: Global Control Register 2 >**/
+    uint32      rvd3;                 /**< 0x0014: reserved >**/        
+    uint32      INTS;                 /**< 0x0018: Interrupt Enable Set Register >**/
+    uint32      rvd4;                 /**< 0x001C: reserved >**/        
+    uint32      INTR;                 /**< 0x0020: Interrupt Enable Reset Register >**/
+    uint32      rvd5;                 /**< 0x0024: reserved >**/    
+    uint32      STATUS;               /**< 0x0028: Interrupt Status Register >**/
+    uint32      rvd6;                 /**< 0x002C: reserved >**/    
+    uint32      INT_OFFSET_REG;       /**< 0x0030: Interrupt Offset >**/
+    uint32      rvd7;                 /**< 0x0034: reserved >**/    
+    uint32      BUSY;                 /**< 0x0038: CRC Busy Register >**/
+    uint32      rvd8;                 /**< 0x003C: reserved >**/    
+    uint32      PCOUNT_REG1;          /**< 0x0040: Pattern Counter Preload Register1 >**/
+    uint32      SCOUNT_REG1;          /**< 0x0044: Sector Counter Preload Register1 >**/
+    uint32      CURSEC_REG1;          /**< 0x0048: Current Sector Register 1 >**/
+    uint32      WDTOPLD1;             /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/
+    uint32      BCTOPLD1;             /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/
+    uint32      rvd9[3];              /**< 0x0054: reserved >**/
+    uint32      PSA_SIGREGL1;         /**< 0x0060: Channel 1 PSA signature low register >**/
+    uint32      PSA_SIGREGH1;         /**< 0x0064: Channel 1 PSA signature high register >**/
+    uint32      REGL1;                /**< 0x0068: Channel 1 CRC value low register >**/
+    uint32      REGH1;                /**< 0x006C: Channel 1 CRC value high register >**/
+    uint32      PSA_SECSIGREGL1;      /**< 0x0070: Channel 1 PSA sector signature low register >**/
+    uint32      PSA_SECSIGREGH1;      /**< 0x0074: Channel 1 PSA sector signature high register >**/
+    uint32      RAW_DATAREGL1;        /**< 0x0078: Channel 1 Raw Data Low Register >**/
+    uint32      RAW_DATAREGH1;        /**< 0x007C: Channel 1 Raw Data High Register >**/
+    uint32      PCOUNT_REG2;          /**< 0x0080: CRC Pattern Counter Preload Register2 >**/
+    uint32      SCOUNT_REG2;          /**< 0x0084: Sector Counter Preload Register2 >**/
+    uint32      CURSEC_REG2;          /**< 0x0088: Current Sector Register 2>**/
+    uint32      WDTOPLD2;             /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/
+    uint32      BCTOPLD2;             /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/
+    uint32      rvd10[3];             /**< 0x0094: reserved >**/
+    uint32      PSA_SIGREGL2;         /**< 0x00A0: Channel 2 PSA signature low register >**/
+    uint32      PSA_SIGREGH2;         /**< 0x00A4: Channel 2 PSA signature high register >**/
+    uint32      REGL2;                /**< 0x00A8: Channel 2 CRC value low register >**/
+    uint32      REGH2;                /**< 0x00AC: Channel 2 CRC value high register >**/
+    uint32      PSA_SECSIGREGL2;      /**< 0x00B0: Channel 2 PSA sector signature low register >**/
+    uint32      PSA_SECSIGREGH2;      /**< 0x00B4: Channel 2 PSA sector signature high register >**/
+    uint32      RAW_DATAREGL2;        /**< 0x00B8: Channel 2 Raw Data Low Register >**/
+    uint32      RAW_DATAREGH2;        /**< 0x00BC: Channel 2 Raw Data High Register >**/
+}crcBASE_t;
+ 
+/** @def crcREG
+*   @brief CRC Register Frame Pointer
+*
+*   This pointer is used by the CRC driver to access the CRC registers.
+*/
+#define crcREG ((crcBASE_t *)0xFE000000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_dcc.h b/include/arch/rm46l8lp/halcogen/reg_dcc.h
new file mode 100644
index 0000000..7edde03
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_dcc.h
@@ -0,0 +1,103 @@
+/** @file reg_dcc.h
+*   @brief DCC Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the DCC driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_DCC_H__
+#define __REG_DCC_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Dcc Register Frame Definition */
+/** @struct dccBase
+*   @brief DCC Base Register Definition
+*
+*   This structure is used to access the DCC module registers.
+*/
+/** @typedef dccBASE_t
+*   @brief DCC Register Frame Type Definition
+*
+*   This type is used to access the DCC Registers.
+*/
+typedef volatile struct dccBase
+{
+    uint32 GCTRL;      	    /**< 0x0000: DCC Control Register		*/
+    uint32 REV;      		/**< 0x0004: DCC Revision Id Register 	*/
+    uint32 CNT0SEED;    	/**< 0x0008: DCC Counter0 Seed Register	*/
+    uint32 VALID0SEED;      /**< 0x000C: DCC Valid0 Seed Register 	*/
+    uint32 CNT1SEED;		/**< 0x0010: DCC Counter1 Seed Register 	*/
+    uint32 STAT; 			/**< 0x0014: DCC Status Register 		*/
+    uint32 CNT0;    		/**< 0x0018: DCC Counter0 Value Register 	*/
+    uint32 VALID0;    	    /**< 0x001C: DCC Valid0 Value Register 	*/
+    uint32 CNT1;      	    /**< 0x0020: DCC Counter1 Value Register	*/
+    uint32 CNT1CLKSRC;   	/**< 0x0024: DCC Counter1 Clock Source Selection Register 	*/
+    uint32 CNT0CLKSRC;   	/**< 0x0028: DCC Counter0 Clock Source Selection Register 	*/
+} dccBASE_t;
+
+
+/** @def dccREG1
+*   @brief DCC1 Register Frame Pointer
+*
+*   This pointer is used by the DCC driver to access the dcc2 module registers.
+*/
+#define dccREG1   ((dccBASE_t *)0xFFFFEC00U)
+
+
+/** @def dccREG2
+*   @brief DCC2 Register Frame Pointer
+*
+*   This pointer is used by the DCC driver to access the dcc2 module registers.
+*/
+#define dccREG2   ((dccBASE_t *)0xFFFFF400U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_dma.h b/include/arch/rm46l8lp/halcogen/reg_dma.h
new file mode 100644
index 0000000..60cc45f
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_dma.h
@@ -0,0 +1,185 @@
+/** @file reg_dma.h
+*   @brief DMA Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the DMA driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_DMA_H__
+#define __REG_DMA_H__
+
+#include "sys_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* DMA Register Frame Definition */
+/** @struct dmaBase
+*   @brief DMA Register Frame Definition
+*
+*   This type is used to access the DMA Registers.
+*/
+/** @struct dmaBASE_t
+*   @brief DMA Register Definition
+*
+*   This structure is used to access the DMA module egisters.
+*/
+typedef volatile struct dmaBase
+{
+
+    uint32 GCTRL;       /**<  0x0000: Global Control Register                */
+    uint32 PEND;        /**<  0x0004: Channel Pending Register               */
+    uint32 FBREG;       /**<  0x0008: Fall Back Register                     */
+    uint32 DMASTAT;     /**<  0x000C: Status Register                        */
+    uint32  rsvd1;      /**<  0x0010: Reserved                               */
+    uint32 HWCHENAS;    /**<  0x0014: HW Channel Enable Set                  */
+    uint32  rsvd2;      /**<  0x0018: Reserved                               */
+    uint32 HWCHENAR;    /**<  0x001C: HW Channel Enable Reset                */
+    uint32  rsvd3;      /**<  0x0020: Reserved                               */
+    uint32 SWCHENAS;    /**<  0x0024: SW Channel Enable Set                  */
+    uint32  rsvd4;      /**<  0x0028: Reserved                               */
+    uint32 SWCHENAR;    /**<  0x002C: SW Channel Enable Reset                */
+    uint32  rsvd5;      /**<  0x0030: Reserved                               */
+    uint32 CHPRIOS;     /**<  0x0034: Channel Priority Set                   */
+    uint32  rsvd6;      /**<  0x0038: Reserved                               */
+    uint32 CHPRIOR;     /**<  0x003C: Channel Priority Reset                 */
+    uint32  rsvd7;      /**<  0x0040: Reserved                               */
+    uint32 GCHIENAS;    /**<  0x0044: Global Channel Interrupt Enable Set    */
+    uint32  rsvd8;      /**<  0x0048: Reserved                               */
+    uint32 GCHIENAR;    /**<  0x004C: Global Channel Interrupt Enable Reset  */
+    uint32  rsvd9;      /**<  0x0050: Reserved                               */
+    uint32 DREQASI[8U]; /**<  0x0054 - 0x70: DMA Request Assignment Register */
+    uint32  rsvd10[8U]; /**<  0x0074 - 0x90: Reserved                        */
+    uint32 PAR[4U];     /**<  0x0094 - 0xA0: Port Assignment Register        */
+    uint32  rsvd11[4U]; /**<  0x00A4 - 0xB0: Reserved                        */
+    uint32 FTCMAP;      /**<  0x00B4: FTC Interrupt Mapping Register         */
+    uint32  rsvd12;     /**<  0x00B8: Reserved                               */
+    uint32 LFSMAP;      /**<  0x00BC: LFS Interrupt Mapping Register         */
+    uint32  rsvd13;     /**<  0x00C0: Reserved                               */
+    uint32 HBCMAP;      /**<  0x00C4: HBC Interrupt Mapping Register         */
+    uint32  rsvd14;     /**<  0x00C8: Reserved                               */
+    uint32 BTCMAP;      /**<  0x00CC: BTC Interrupt Mapping Register         */
+    uint32  rsvd15;     /**<  0x00D0: Reserved                               */
+    uint32 BERMAP;      /**<  0x00D4: BER Interrupt Mapping Register         */
+    uint32  rsvd16;     /**<  0x00D8: Reserved                               */
+    uint32 FTCINTENAS;  /**<  0x00DC: FTC Interrupt Enable Set               */
+    uint32  rsvd17;     /**<  0x00E0: Reserved                               */
+    uint32 FTCINTENAR;  /**<  0x00E4: FTC Interrupt Enable Reset             */
+    uint32  rsvd18;     /**<  0x00E8: Reserved                               */
+    uint32 LFSINTENAS;  /**<  0x00EC: LFS Interrupt Enable Set               */
+    uint32  rsvd19;     /**<  0x00F0: Reserved                               */
+    uint32 LFSINTENAR;  /**<  0x00F4: LFS Interrupt Enable Reset             */
+    uint32  rsvd20;     /**<  0x00F8: Reserved                               */
+    uint32 HBCINTENAS;  /**<  0x00FC: HBC Interrupt Enable Set               */
+    uint32  rsvd21;     /**<  0x0100: Reserved                               */
+    uint32 HBCINTENAR;  /**<  0x0104: HBC Interrupt Enable Reset             */
+    uint32  rsvd22;     /**<  0x0108: Reserved                               */
+    uint32 BTCINTENAS;  /**<  0x010C: BTC Interrupt Enable Set               */
+    uint32  rsvd23;     /**<  0x0110: Reserved                               */
+    uint32 BTCINTENAR;  /**<  0x0114: BTC Interrupt Enable Reset             */
+    uint32  rsvd24;     /**<  0x0118: Reserved                               */
+    uint32 GINTFLAG;    /**<  0x011C: Global Interrupt Flag Register         */
+    uint32  rsvd25;     /**<  0x0120: Reserved                               */
+    uint32 FTCFLAG;     /**<  0x0124: FTC Interrupt Flag Register            */
+    uint32  rsvd26;     /**<  0x0128: Reserved                               */
+    uint32 LFSFLAG;     /**<  0x012C: LFS Interrupt Flag Register            */
+    uint32  rsvd27;     /**<  0x0130: Reserved                               */
+    uint32 HBCFLAG;     /**<  0x0134: HBC Interrupt Flag Register            */
+    uint32  rsvd28;     /**<  0x0138: Reserved                               */
+    uint32 BTCFLAG;     /**<  0x013C: BTC Interrupt Flag Register            */
+    uint32  rsvd29;     /**<  0x0140: Reserved                               */
+    uint32 BERFLAG;     /**<  0x0144: BER Interrupt Flag Register            */
+    uint32  rsvd30;     /**<  0x0148: Reserved                               */
+    uint32 FTCAOFFSET;  /**<  0x014C: FTCA Interrupt Channel Offset Register */
+    uint32 LFSAOFFSET;  /**<  0x0150: LFSA Interrupt Channel Offset Register */
+    uint32 HBCAOFFSET;  /**<  0x0154: HBCA Interrupt Channel Offset Register */
+    uint32 BTCAOFFSET;  /**<  0x0158: BTCA Interrupt Channel Offset Register */
+    uint32 BERAOFFSET;  /**<  0x015C: BERA Interrupt Channel Offset Register */
+    uint32 FTCBOFFSET;  /**<  0x0160: FTCB Interrupt Channel Offset Register */
+    uint32 LFSBOFFSET;  /**<  0x0164: LFSB Interrupt Channel Offset Register */
+    uint32 HBCBOFFSET;  /**<  0x0168: HBCB Interrupt Channel Offset Register */
+    uint32 BTCBOFFSET;  /**<  0x016C: BTCB Interrupt Channel Offset Register */
+    uint32 BERBOFFSET;  /**<  0x0170: BERB Interrupt Channel Offset Register */
+    uint32  rsvd31;     /**<  0x0174: Reserved                               */
+    uint32 PTCRL;       /**<  0x0178: Port Control Register                  */
+    uint32 RTCTRL;      /**<  0x017C: RAM Test Control Register              */
+    uint32 DCTRL;       /**<  0x0180: Debug Control                          */
+    uint32 WPR;         /**<  0x0184: Watch Point Register                   */
+    uint32 WMR;         /**<  0x0188: Watch Mask Register                    */
+    uint32 PAACSADDR;   /**<  0x018C:           */
+    uint32 PAACDADDR;   /**<  0x0190:           */
+    uint32 PAACTC;      /**<  0x0194:           */
+    uint32 PBACSADDR;   /**<  0x0198: Port B Active Channel Source Address Register       */
+    uint32 PBACDADDR;   /**<  0x019C: Port B Active Channel Destination Address Register  */
+    uint32 PBACTC;      /**<  0x01A0: Port B Active Channel Transfer Count Register       */
+    uint32  rsvd32;     /**<  0x01A4: Reserved                               */
+    uint32 DMAPCR;      /**<  0x01A8: Parity Control Register                */
+    uint32 DMAPAR;      /**<  0x01AC: DMA Parity Error Address Register      */
+    uint32 DMAMPCTRL;   /**<  0x01B0: DMA Memory Protection Control Register */
+    uint32 DMAMPST;     /**<  0x01B4: DMA Memory Protection Status Register  */
+    struct
+    {
+    	uint32 STARTADD; /**<  0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region Start Address Register  */
+    	uint32 ENDADD;   /**<  0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region Start Address Register  */
+    }DMAMPR[4U];
+} dmaBASE_t;
+
+
+/** @def dmaREG
+*   @brief DMA1 Register Frame Pointer
+*
+*   This pointer is used by the DMA driver to access the DMA module registers.
+*/
+#define dmaREG ((dmaBASE_t *)0xFFFFF000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_ecap.h b/include/arch/rm46l8lp/halcogen/reg_ecap.h
new file mode 100644
index 0000000..9bfb07b
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_ecap.h
@@ -0,0 +1,159 @@
+/** @file reg_ecap.h
+*   @brief ECAP Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the ECAP driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_ECAP_H__
+#define __REG_ECAP_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Ecap Register Frame Definition */
+/** @struct ecapBASE
+*   @brief ECAP Register Frame Definition
+*
+*   This type is used to access the ECAP Registers.
+*/
+/** @typedef ecapBASE_t
+*   @brief ECAP Register Frame Type Definition
+*
+*   This type is used to access the ECAP Registers.
+*/
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) 
+
+typedef volatile struct ecapBASE
+ {
+   uint32 TSCTR;     /**<  0x0000 Time stamp counter Register*/
+   uint32 CTRPHS;    /**<  0x0004 Counter phase Register*/ 
+   uint32 CAP1;      /**<  0x0008 Capture 1 Register*/
+   uint32 CAP2;      /**<  0x000C Capture 2 Register*/
+   uint32 CAP3;      /**<  0x0010 Capture 3 Register*/
+   uint32 CAP4;      /**<  0x0014 Capture 4 Register*/
+   uint16 rsvd1[8U]; /**<  0x0018 Reserved*/
+   uint16 ECCTL1;    /**<  0x0028 Capture Control Reg 1 Register*/
+   uint16 ECCTL2;    /**<  0x002A Capture Control Reg 2 Register*/
+   uint16 ECEINT;    /**<  0x002C Interrupt enable Register*/
+   uint16 ECFLG;     /**<  0x002E Interrupt flags Register*/ 
+   uint16 ECCLR;     /**<  0x0030 Interrupt clear Register*/
+   uint16 ECFRC;     /**<  0x0032 Interrupt force Register*/
+   uint16 rsvd2[6U]; /**<  0x0034 Reserved*/
+
+}ecapBASE_t;
+
+#else
+
+typedef volatile struct ecapBASE
+ {
+   uint32 TSCTR;     /**<  0x0000 Time stamp counter Register*/
+   uint32 CTRPHS;    /**<  0x0004 Counter phase Register*/ 
+   uint32 CAP1;      /**<  0x0008 Capture 1 Register*/
+   uint32 CAP2;      /**<  0x000C Capture 2 Register*/
+   uint32 CAP3;      /**<  0x0010 Capture 3 Register*/
+   uint32 CAP4;      /**<  0x0014 Capture 4 Register*/
+   uint16 rsvd1[8U]; /**<  0x0018 Reserved*/
+   uint16 ECCTL2;    /**<  0x002A Capture Control Reg 2 Register*/
+   uint16 ECCTL1;    /**<  0x0028 Capture Control Reg 1 Register*/
+   uint16 ECFLG;     /**<  0x002E Interrupt flags Register*/ 
+   uint16 ECEINT;    /**<  0x002C Interrupt enable Register*/
+   uint16 ECFRC;     /**<  0x0032 Interrupt force Register*/
+   uint16 ECCLR;     /**<  0x0030 Interrupt clear Register*/
+   uint16 rsvd2[6U]; /**<  0x0034 Reserved*/
+
+}ecapBASE_t;
+
+#endif
+/** @def ecapREG1
+*   @brief ECAP1 Register Frame Pointer
+*
+*   This pointer is used by the ECAP driver to access the ECAP1 registers.
+*/
+#define ecapREG1 ((ecapBASE_t *)0xFCF79300U)
+
+/** @def ecapREG2
+*   @brief ECAP2 Register Frame Pointer
+*
+*   This pointer is used by the ECAP driver to access the ECAP2 registers.
+*/
+#define ecapREG2 ((ecapBASE_t *)0xFCF79400U)
+
+/** @def ecapREG3
+*   @brief ECAP3 Register Frame Pointer
+*
+*   This pointer is used by the ECAP driver to access the ECAP3 registers.
+*/
+#define ecapREG3 ((ecapBASE_t *)0xFCF79500U)
+
+/** @def ecapREG4
+*   @brief ECAP4 Register Frame Pointer
+*
+*   This pointer is used by the ECAP driver to access the ECAP4 registers.
+*/
+#define ecapREG4 ((ecapBASE_t *)0xFCF79600U)
+
+/** @def ecapREG5
+*   @brief ECAP5 Register Frame Pointer
+*
+*   This pointer is used by the ECAP driver to access the ECAP5 registers.
+*/
+#define ecapREG5 ((ecapBASE_t *)0xFCF79700U)
+
+/** @def ecapREG6
+*   @brief ECAP6 Register Frame Pointer
+*
+*   This pointer is used by the ECAP driver to access the ECAP6 registers.
+*/
+#define ecapREG6 ((ecapBASE_t *)0xFCF79800U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_efc.h b/include/arch/rm46l8lp/halcogen/reg_efc.h
new file mode 100644
index 0000000..1890288
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_efc.h
@@ -0,0 +1,96 @@
+/** @file reg_efc.h
+*   @brief EFC Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_EFC_H__
+#define __REG_EFC_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Efc Register Frame Definition */
+/** @struct efcBase
+*   @brief Efc Register Frame Definition
+*
+*   This type is used to access the Efc Registers.
+*/
+/** @typedef efcBASE_t
+*   @brief Efc Register Frame Type Definition
+*
+*   This type is used to access the Efc Registers.
+*/
+typedef volatile struct efcBase
+{
+    uint32 INSTRUCTION;             /* 0x0  INSTRUCTION AN DUMPWORD REGISTER    */
+    uint32 ADDRESS;                 /* 0x4  ADDRESS REGISTER                    */
+    uint32 DATA_UPPER;              /* 0x8  DATA UPPER REGISTER                 */
+    uint32 DATA_LOWER;              /* 0xc  DATA LOWER REGISTER                 */
+    uint32 SYSTEM_CONFIG;           /* 0x10 SYSTEM CONFIG REGISTER              */
+    uint32 SYSTEM_STATUS;           /* 0x14 SYSTEM STATUS REGISTER              */
+    uint32 ACCUMULATOR;             /* 0x18 ACCUMULATOR REGISTER                */
+    uint32 BOUNDARY;                /* 0x1C BOUNDARY REGISTER                   */
+    uint32 KEY_FLAG;                /* 0x20 KEY FLAG REGISTER                   */
+    uint32 KEY;                     /* 0x24 KEY REGISTER                        */
+    uint32   rsvd1;                 /* 0x28 RESERVED                            */
+    uint32 PINS;                    /* 0x2C PINS REGISTER                       */
+    uint32 CRA;                     /* 0x30 CRA                                 */
+    uint32 READ;                    /* 0x34 READ REGISTER                       */
+    uint32 PROGRAMME;               /* 0x38 PROGRAMME REGISTER                  */
+    uint32 ERROR;                   /* 0x3C ERROR STATUS REGISTER               */
+    uint32 SINGLE_BIT;              /* 0x40 SINGLE BIT ERROR                    */
+    uint32 TWO_BIT_ERROR;           /* 0x44 DOUBLE BIT ERROR                    */
+    uint32 SELF_TEST_CYCLES;        /* 0x48 SELF TEST CYCLEX                    */
+    uint32 SELF_TEST_SIGN;          /* 0x4C SELF TEST SIGNATURE                 */
+} efcBASE_t;
+
+#define efcREG   ((efcBASE_t *)0xFFF8C000U)
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_eqep.h b/include/arch/rm46l8lp/halcogen/reg_eqep.h
new file mode 100644
index 0000000..39342c6
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_eqep.h
@@ -0,0 +1,151 @@
+/** @file reg_eqep.h
+*   @brief EQEP Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the EQEP driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_EQEP_H__
+#define __REG_EQEP_H__
+
+#include "sys_common.h"
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Eqep Register Frame Definition */
+/** @struct eqepBASE
+*   @brief EQEP Register Frame Definition
+*
+*   This type is used to access the EQEP Registers.
+*/
+/** @typedef eqepBASE_t
+*   @brief EQEP Register Frame Type Definition
+*
+*   This type is used to access the EQEP Registers.
+*/
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) 
+
+typedef volatile struct eqepBASE
+{
+  uint32      QPOSCNT;       /*< 0x0000 eQEP Position Counter*/
+  uint32      QPOSINIT;      /*< 0x0004 eQEP Initialization Position Count*/
+  uint32      QPOSMAX;       /*< 0x0008 eQEP Maximum Position Count*/
+  uint32      QPOSCMP;       /*< 0x000C eQEP Position Compare*/
+  uint32      QPOSILAT;      /*< 0x0010 eQEP Index Position Latch*/
+  uint32      QPOSSLAT;      /*< 0x0014 eQEP Strobe Position Latch*/
+  uint32      QPOSLAT;       /*< 0x0018 eQEP Position Latch*/
+  uint32      QUTMR;         /*< 0x001C eQEP Unit Timer*/
+  uint32      QUPRD;         /*< 0x0020 eQEP Unit Period*/
+  uint16		QWDTMR;		   /*< 0x0024 eQEP Watchdog Timer*/
+  uint16		QWDPRD;		   /*< 0x0026 eQEP Watchdog Period*/
+  uint16		QDECCTL;	   /*< 0x0028 eQEP Decoder Control*/
+  uint16		QEPCTL;		   /*< 0x002A eQEP Control*/
+  uint16		QCAPCTL;	   /*< 0x002C eQEP Capture Control*/
+  uint16		QPOSCTL;	   /*< 0x002E eQEP Position Compare Control*/
+  uint16		QEINT;		   /*< 0x0030 eQEP Interrupt Enable Register*/
+  uint16		QFLG;		   /*< 0x0032 eQEP Interrupt Flag Register*/
+  uint16		QCLR;		   /*< 0x0034 eQEP Interrupt Clear Register*/
+  uint16		QFRC;		   /*< 0x0036 eQEP Interrupt Force Register*/
+  uint16		QEPSTS;		   /*< 0x0038 eQEP Status Register*/
+  uint16		QCTMR;		   /*< 0x003A eQEP Capture Timer*/
+  uint16		QCPRD;		   /*< 0x003C eQEP Capture Period*/
+  uint16		QCTMRLAT;	   /*< 0x003E eQEP Capture Timer Latch*/
+  uint16		QCPRDLAT;	   /*< 0x0040 eQEP Capture Period Latch*/
+  uint16		rsvd_1;	       /*< 0x0042 Reserved*/
+} eqepBASE_t;
+
+#else
+
+typedef volatile struct eqepBASE
+{
+  uint32      QPOSCNT;       /*< 0x0000 eQEP Position Counter*/
+  uint32      QPOSINIT;      /*< 0x0004 eQEP Initialization Position Count*/
+  uint32      QPOSMAX;       /*< 0x0008 eQEP Maximum Position Count*/
+  uint32      QPOSCMP;       /*< 0x000C eQEP Position Compare*/
+  uint32      QPOSILAT;      /*< 0x0010 eQEP Index Position Latch*/
+  uint32      QPOSSLAT;      /*< 0x0014 eQEP Strobe Position Latch*/
+  uint32      QPOSLAT;       /*< 0x0018 eQEP Position Latch*/
+  uint32      QUTMR;         /*< 0x001C eQEP Unit Timer*/
+  uint32      QUPRD;         /*< 0x0020 eQEP Unit Period*/
+  uint16		QWDPRD;		   /*< 0x0026 eQEP Watchdog Period*/
+  uint16		QWDTMR;		   /*< 0x0024 eQEP Watchdog Timer*/
+  uint16		QEPCTL;		   /*< 0x002A eQEP Control*/
+  uint16		QDECCTL;	   /*< 0x0028 eQEP Decoder Control*/
+  uint16		QPOSCTL;	   /*< 0x002E eQEP Position Compare Control*/
+  uint16		QCAPCTL;	   /*< 0x002C eQEP Capture Control*/
+  uint16		QFLG;		   /*< 0x0032 eQEP Interrupt Flag Register*/
+  uint16		QEINT;		   /*< 0x0030 eQEP Interrupt Enable Register*/
+  uint16		QFRC;		   /*< 0x0036 eQEP Interrupt Force Register*/
+  uint16		QCLR;		   /*< 0x0034 eQEP Interrupt Clear Register*/
+  uint16		QCTMR;		   /*< 0x003A eQEP Capture Timer*/
+  uint16		QEPSTS;		   /*< 0x0038 eQEP Status Register*/
+  uint16		QCTMRLAT;	   /*< 0x003E eQEP Capture Timer Latch*/
+  uint16		QCPRD;		   /*< 0x003C eQEP Capture Period*/
+  uint16		rsvd_1;	       /*< 0x0042 Reserved*/
+  uint16		QCPRDLAT;	   /*< 0x0040 eQEP Capture Period Latch*/
+} eqepBASE_t;
+
+#endif
+
+/** @def eqepREG1
+*   @brief eQEP1 Register Frame Pointer
+*
+*   This pointer is used by the eQEP driver to access the eQEP1 registers.
+*/
+#define eqepREG1 ((eqepBASE_t *)0xFCF79900U)
+
+/** @def eqepREG2
+*   @brief eQEP2 Register Frame Pointer
+*
+*   This pointer is used by the eQEP driver to access the eQEP2 registers.
+*/
+#define eqepREG2 ((eqepBASE_t *)0xFCF79A00U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_esm.h b/include/arch/rm46l8lp/halcogen/reg_esm.h
new file mode 100644
index 0000000..ce5f5ab
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_esm.h
@@ -0,0 +1,106 @@
+/** @file reg_esm.h
+*   @brief ESM Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the ESM driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_ESM_H__
+#define __REG_ESM_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Esm Register Frame Definition */
+/** @struct esmBase
+*   @brief Esm Register Frame Definition
+*
+*   This type is used to access the Esm Registers.
+*/
+/** @typedef esmBASE_t
+*   @brief Esm Register Frame Type Definition
+*
+*   This type is used to access the Esm Registers.
+*/
+typedef volatile struct esmBase
+{
+    uint32 EEPAPR1;           /* 0x0000                 */
+    uint32 DEPAPR1;           /* 0x0004                 */
+    uint32 IESR1;             /* 0x0008                 */
+    uint32 IECR1;             /* 0x000C                 */
+    uint32 ILSR1;             /* 0x0010                 */
+    uint32 ILCR1;             /* 0x0014                 */
+    uint32 SR1[3U];           /* 0x0018, 0x001C, 0x0020 */
+    uint32 EPSR;              /* 0x0024                 */
+    uint32 IOFFHR;            /* 0x0028                 */
+    uint32 IOFFLR;            /* 0x002C                 */
+    uint32 LTCR;              /* 0x0030                 */
+    uint32 LTCPR;             /* 0x0034                 */
+    uint32 EKR;               /* 0x0038                 */
+    uint32 SSR2;              /* 0x003C                 */
+    uint32 IEPSR4;            /* 0x0040                 */
+    uint32 IEPCR4;            /* 0x0044                 */
+    uint32 IESR4;             /* 0x0048                 */
+    uint32 IECR4;             /* 0x004C                 */
+    uint32 ILSR4;             /* 0x0050                 */
+    uint32 ILCR4;             /* 0x0054                 */
+    uint32 SR4[3U];           /* 0x0058, 0x005C, 0x0060 */
+} esmBASE_t;
+
+/** @def esmREG
+*   @brief Esm Register Frame Pointer
+*
+*   This pointer is used by the Esm driver to access the Esm registers.
+*/
+#define esmREG ((esmBASE_t *)0xFFFFF500U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_etpwm.h b/include/arch/rm46l8lp/halcogen/reg_etpwm.h
new file mode 100644
index 0000000..a6b8a8f
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_etpwm.h
@@ -0,0 +1,225 @@
+/** @file reg_etpwm.h
+*   @brief ETPWM Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the ETPWM driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_ETPWM_H__
+#define __REG_ETPWM_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* ETPWM Register Frame Definition */
+/** @struct etpwmBASE
+*   @brief ETPWM Register Frame Definition
+*
+*   This type is used to access the ETPWM Registers.
+*/
+/** @typedef etpwmBASE_t
+*   @brief ETPWM Register Frame Type Definition
+*
+*   This type is used to access the ETPWM Registers.
+*/
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+
+typedef volatile struct etpwmBASE
+{
+    uint16 TBCTL;           /**<  0x0000 Time-Base Control Register*/
+    uint16 TBSTS;           /**<  0x0002 Time-Base Status Register*/
+    uint16   rsvd1;         /**<  0x0004 Reserved*/
+    uint16 TBPHS;           /**<  0x0006 Time-Base Phase Register*/
+    uint16 TBCTR;           /**<  0x0008 Time-Base Counter Register*/
+    uint16 TBPRD;           /**<  0x000A Time-Base Period Register*/
+    uint16   rsvd2;         /**<  0x000C Reserved*/
+    uint16 CMPCTL;          /**<  0x000E Counter-Compare Control Register*/
+    uint16   rsvd3;         /**<  0x0010 Reserved*/
+    uint16 CMPA;            /**<  0x0012 Counter-Compare A Register*/
+    uint16 CMPB;            /**<  0x0014 Counter-Compare B Register*/
+    uint16 AQCTLA;          /**<  0x0016 Action-Qualifier Control Register for Output A (ETPWMxA)*/
+    uint16 AQCTLB;          /**<  0x0018 Action-Qualifier Control Register for Output B (ETPWMxB)*/
+    uint16 AQSFRC;          /**<  0x001A Action-Qualifier Software Force Register*/
+    uint16 AQCSFRC;         /**<  0x001C Action-Qualifier Continuous S/W Force Register Set*/
+    uint16 DBCTL;           /**<  0x001E Dead-Band Generator Control Register*/
+    uint16 DBRED;           /**<  0x0020 Dead-Band Generator Rising Edge Delay Count Register*/
+    uint16 DBFED;           /**<  0x0022 Dead-Band Generator Falling Edge Delay Count Register*/
+    uint16 TZSEL;           /**<  0x0024 Trip-Zone Select Register*/
+    uint16 TZDCSEL;         /**<  0x0026 Trip Zone Digital Compare Select Register*/
+    uint16 TZCTL;           /**<  0x0028 Trip-Zone Control Register*/
+    uint16 TZEINT;          /**<  0x002A Trip-Zone Enable Interrupt Register*/
+    uint16 TZFLG;           /**<  0x002C Trip-Zone Flag Register*/
+    uint16 TZCLR;           /**<  0x002E Trip-Zone Clear Register*/
+    uint16 TZFRC;           /**<  0x0030 Trip-Zone Force Register*/
+    uint16 ETSEL;           /**<  0x0032 Event-Trigger Selection Register*/
+    uint16 ETPS;            /**<  0x0034 Event-Trigger Pre-Scale Register*/
+    uint16 ETFLG;           /**<  0x0036 Event-Trigger Flag Register*/
+    uint16 ETCLR;           /**<  0x0038 Event-Trigger Clear Register*/
+    uint16 ETFRC;           /**<  0x003A Event-Trigger Force Register*/
+    uint16 PCCTL;           /**<  0x003C PWM-Chopper Control Register*/
+    uint16   rsvd4;         /**<  0x003E Reserved*/
+	uint16   rsvd5[16U];    /**<  0x0040 Reserved*/
+    uint16 DCTRIPSEL;       /**<  0x0060 Digital Compare Trip Select Register*/
+    uint16 DCACTL;          /**<  0x0062 Digital Compare A Control Register*/
+    uint16 DCBCTL;          /**<  0x0064 Digital Compare B Control Register*/
+    uint16 DCFCTL;          /**<  0x0066 Digital Compare Filter Control Register*/
+    uint16 DCCAPCTL;        /**<  0x0068 Digital Compare Capture Control Register*/
+    uint16 DCFOFFSET;       /**<  0x006A Digital Compare Filter Offset Register*/
+    uint16 DCFOFFSETCNT;    /**<  0x006C Digital Compare Filter Offset Counter Register*/
+    uint16 DCFWINDOW;       /**<  0x006E Digital Compare Filter Window Register*/
+    uint16 DCFWINDOWCNT;    /**<  0x0070 Digital Compare Filter Window Counter Register*/
+    uint16 DCCAP;           /**<  0x0072 Digital Compare Counter Capture Register*/
+} etpwmBASE_t;
+
+#else
+
+typedef volatile struct etpwmBASE
+{
+    uint16 TBSTS;           /**<  0x0000 Time-Base Status Register*/
+	uint16 TBCTL;           /**<  0x0002 Time-Base Control Register*/
+    uint16 TBPHS;           /**<  0x0004 Time-Base Phase Register*/
+    uint16   rsvd1;         /**<  0x0006 Reserved*/
+    uint16 TBPRD;           /**<  0x0008 Time-Base Period Register*/
+    uint16 TBCTR;           /**<  0x000A Time-Base Counter Register*/
+    uint16 CMPCTL;          /**<  0x000C Counter-Compare Control Register*/
+    uint16   rsvd2;         /**<  0x000E Reserved*/
+    uint16 CMPA;            /**<  0x0010 Counter-Compare A Register*/
+    uint16   rsvd3;         /**<  0x0012 Reserved*/
+    uint16 AQCTLA;          /**<  0x0014 Action-Qualifier Control Register for Output A (ETPWMxA)*/
+    uint16 CMPB;            /**<  0x0016 Counter-Compare B Register*/
+    uint16 AQSFRC;          /**<  0x0018 Action-Qualifier Software Force Register*/
+    uint16 AQCTLB;          /**<  0x001A Action-Qualifier Control Register for Output B (ETPWMxB)*/
+    uint16 DBCTL;           /**<  0x001C Dead-Band Generator Control Register*/
+    uint16 AQCSFRC;         /**<  0x001E Action-Qualifier Continuous S/W Force Register Set*/
+    uint16 DBFED;           /**<  0x0020 Dead-Band Generator Falling Edge Delay Count Register*/
+    uint16 DBRED;           /**<  0x0022 Dead-Band Generator Rising Edge Delay Count Register*/
+    uint16 TZDCSEL;         /**<  0x0024 Trip Zone Digital Compare Select Register*/
+    uint16 TZSEL;           /**<  0x0026 Trip-Zone Select Register*/
+    uint16 TZEINT;          /**<  0x0028 Trip-Zone Enable Interrupt Register*/
+    uint16 TZCTL;           /**<  0x002A Trip-Zone Control Register*/
+    uint16 TZCLR;           /**<  0x002C Trip-Zone Clear Register*/
+    uint16 TZFLG;           /**<  0x002E Trip-Zone Flag Register*/
+    uint16 ETSEL;           /**<  0x0030 Event-Trigger Selection Register*/
+    uint16 TZFRC;           /**<  0x0032 Trip-Zone Force Register*/
+    uint16 ETFLG;           /**<  0x0034 Event-Trigger Flag Register*/
+    uint16 ETPS;            /**<  0x0036 Event-Trigger Pre-Scale Register*/
+    uint16 ETFRC;           /**<  0x0038 Event-Trigger Force Register*/
+    uint16 ETCLR;           /**<  0x003A Event-Trigger Clear Register*/
+    uint16   rsvd4;         /**<  0x003C Reserved*/
+    uint16 PCCTL;           /**<  0x003E PWM-Chopper Control Register*/
+	uint16   rsvd5[16U];    /**<  0x0040 Reserved*/
+    uint16 DCACTL;          /**<  0x0060 Digital Compare A Control Register*/
+    uint16 DCTRIPSEL;       /**<  0x0062 Digital Compare Trip Select Register*/
+    uint16 DCFCTL;          /**<  0x0064 Digital Compare Filter Control Register*/
+    uint16 DCBCTL;          /**<  0x0066 Digital Compare B Control Register*/
+    uint16 DCFOFFSET;       /**<  0x0068 Digital Compare Filter Offset Register*/
+    uint16 DCCAPCTL;        /**<  0x006A Digital Compare Capture Control Register*/
+    uint16 DCFWINDOW;       /**<  0x006C Digital Compare Filter Window Register*/
+    uint16 DCFOFFSETCNT;    /**<  0x006E Digital Compare Filter Offset Counter Register*/
+    uint16 DCCAP;           /**<  0x0070 Digital Compare Counter Capture Register*/
+    uint16 DCFWINDOWCNT;    /**<  0x0072 Digital Compare Filter Window Counter Register*/
+} etpwmBASE_t;
+
+#endif
+
+
+
+/** @def etpwmREG1
+*   @brief ETPWM1 Register Frame Pointer
+*
+*   This pointer is used by the ETPWM driver to access the ETPWM1 registers.
+*/
+#define etpwmREG1 ((etpwmBASE_t *)0xFCF78C00U)
+
+/** @def etpwmREG2
+*   @brief ETPWM2 Register Frame Pointer
+*
+*   This pointer is used by the ETPWM driver to access the ETPWM2 registers.
+*/
+#define etpwmREG2 ((etpwmBASE_t *)0xFCF78D00U)
+
+/** @def etpwmREG3
+*   @brief ETPWM3 Register Frame Pointer
+*
+*   This pointer is used by the ETPWM driver to access the ETPWM3 registers.
+*/
+#define etpwmREG3 ((etpwmBASE_t *)0xFCF78E00U)
+
+/** @def etpwmREG4
+*   @brief ETPWM4 Register Frame Pointer
+*
+*   This pointer is used by the ETPWM driver to access the ETPWM4 registers.
+*/
+#define etpwmREG4 ((etpwmBASE_t *)0xFCF78F00U)
+
+/** @def etpwmREG5
+*   @brief ETPWM5 Register Frame Pointer
+*
+*   This pointer is used by the ETPWM driver to access the ETPWM5 registers.
+*/
+#define etpwmREG5 ((etpwmBASE_t *)0xFCF79000U)
+
+/** @def etpwmREG6
+*   @brief ETPWM6 Register Frame Pointer
+*
+*   This pointer is used by the ETPWM driver to access the ETPWM6 registers.
+*/
+#define etpwmREG6 ((etpwmBASE_t *)0xFCF79100U)
+
+/** @def etpwmREG7
+*   @brief ETPWM7 Register Frame Pointer
+*
+*   This pointer is used by the ETPWM driver to access the ETPWM7 registers.
+*/
+#define etpwmREG7 ((etpwmBASE_t *)0xFCF79200U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_flash.h b/include/arch/rm46l8lp/halcogen/reg_flash.h
new file mode 100644
index 0000000..b50da1e
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_flash.h
@@ -0,0 +1,134 @@
+/** @file reg_flash.h
+*   @brief Flash Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_FLASH_H__
+#define __REG_FLASH_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/* Flash Register Frame Definition */
+/** @struct flashWBase
+*   @brief Flash Wrapper Register Frame Definition
+*
+*   This type is used to access the Flash Wrapper Registers.
+*/
+/** @typedef flashWBASE_t
+*   @brief Flash Wrapper Register Frame Type Definition
+*
+*   This type is used to access the Flash Wrapper Registers.
+*/
+typedef volatile struct flashWBase
+{
+    uint32 FRDCNTL;       /* 0x0000 */
+    uint32   rsvd1;       /* 0x0004 */
+    uint32 FEDACCTRL1;    /* 0x0008 */
+    uint32 FEDACCTRL2;    /* 0x000C */
+    uint32 FCORERRCNT;    /* 0x0010 */
+    uint32 FCORERRADD;    /* 0x0014 */
+    uint32 FCORERRPOS;    /* 0x0018 */
+    uint32 FEDACSTATUS;   /* 0x001C */
+    uint32 FUNCERRADD;    /* 0x0020 */
+    uint32 FEDACSDIS;     /* 0x0024 */
+    uint32 FPRIMADDTAG;   /* 0x0028 */
+    uint32 FREDUADDTAG;   /* 0x002C */
+    uint32 FBPROT;        /* 0x0030 */
+    uint32 FBSE;          /* 0x0034 */
+    uint32 FBBUSY;        /* 0x0038 */
+    uint32 FBAC;          /* 0x003C */
+    uint32 FBFALLBACK;    /* 0x0040 */
+    uint32 FBPRDY;        /* 0x0044 */
+    uint32 FPAC1;         /* 0x0048 */
+    uint32 FPAC2;         /* 0x004C */
+    uint32 FMAC;          /* 0x0050 */
+    uint32 FMSTAT;        /* 0x0054 */
+    uint32 FEMUDMSW;      /* 0x0058 */
+    uint32 FEMUDLSW;      /* 0x005C */
+    uint32 FEMUECC;       /* 0x0060 */
+    uint32 FLOCK;         /* 0x0064 */
+    uint32 FEMUADDR;      /* 0x0068 */
+    uint32 FDIAGCTRL;     /* 0x006C */
+    uint32 FRAWDATAH;     /* 0x0070 */
+    uint32 FRAWDATAL;     /* 0x0074 */
+    uint32 FRAWECC;       /* 0x0078 */
+    uint32 FPAROVR;       /* 0x007C */
+    uint32   rsvd2[16U];  /* 0x009C */
+    uint32 FEDACSDIS2;    /* 0x00C0 */
+    uint32   rsvd3[15U];  /* 0x00C4 */
+    uint32   rsvd4[13U];  /* 0x0100 */
+    uint32   rsvd5[85U];  /* 0x0134 */
+    uint32 FSMWRENA;      /* 0x0288 */
+    uint32   rsvd6[6U];   /* 0x028C */
+    uint32 FSMSECTOR;     /* 0x02A4 */
+    uint32   rsvd7[4U];   /* 0x02A8 */
+    uint32 EEPROMCONFIG;  /* 0x02B8 */
+    uint32   rsvd8[19U];  /* 0x02BC */
+    uint32 EECTRL1;       /* 0x0308 */
+    uint32 EECTRL2;       /* 0x030C */
+    uint32 EECORRERRCNT;  /* 0x0310 */
+    uint32 EECORRERRADD;  /* 0x0314 */
+    uint32 EECORRERRPOS;  /* 0x0318 */
+    uint32 EESTATUS;      /* 0x031C */
+    uint32 EEUNCERRADD;   /* 0x0320 */
+} flashWBASE_t;
+
+/** @def flashWREG
+*   @brief Flash Wrapper Register Frame Pointer
+*
+*   This pointer is used by the system driver to access the flash wrapper registers.
+*/
+#define flashWREG ((flashWBASE_t *)(0xFFF87000U))
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_gio.h b/include/arch/rm46l8lp/halcogen/reg_gio.h
new file mode 100644
index 0000000..d845205
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_gio.h
@@ -0,0 +1,134 @@
+/** @file reg_gio.h
+*   @brief GIO Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the GIO driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_GIO_H__
+#define __REG_GIO_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Gio Register Frame Definition */
+/** @struct gioBase
+*   @brief GIO Base Register Definition
+*
+*   This structure is used to access the GIO module registers.
+*/
+/** @typedef gioBASE_t
+*   @brief GIO Register Frame Type Definition
+*
+*   This type is used to access the GIO Registers.
+*/
+typedef volatile struct gioBase
+{
+    uint32 GCR0;      /**< 0x0000: Global Control Register */
+    uint32   rsvd;    /**< 0x0004: Reserved*/
+    uint32 INTDET;    /**< 0x0008: Interrupt Detect Register*/
+    uint32 POL;       /**< 0x000C: Interrupt Polarity Register */
+    uint32 ENASET;    /**< 0x0010: Interrupt Enable Set Register */
+    uint32 ENACLR;    /**< 0x0014: Interrupt Enable Clear Register */
+    uint32 LVLSET;    /**< 0x0018: Interrupt Priority Set Register */
+    uint32 LVLCLR;    /**< 0x001C: Interrupt Priority Clear Register */
+    uint32 FLG;       /**< 0x0020: Interrupt Flag Register */
+    uint32 OFF1;      /**< 0x0024: Interrupt Offset A Register */
+    uint32 OFF2;      /**< 0x0028: Interrupt Offset B Register */
+    uint32 EMU1;      /**< 0x002C: Emulation 1 Register */
+	uint32 EMU2;      /**< 0x0030: Emulation 2 Register */
+} gioBASE_t;
+
+
+/** @struct gioPort
+*   @brief GIO Port Register Definition
+*/
+/** @typedef gioPORT_t
+*   @brief GIO Port Register Type Definition
+*
+*   This type is used to access the GIO Port Registers.
+*/
+typedef volatile struct gioPort
+{
+    uint32 DIR;    /**< 0x0000: Data Direction Register */
+    uint32 DIN;    /**< 0x0004: Data Input Register */
+    uint32 DOUT;   /**< 0x0008: Data Output Register */
+    uint32 DSET;   /**< 0x000C: Data Output Set Register */
+    uint32 DCLR;   /**< 0x0010: Data Output Clear Register */
+    uint32 PDR;    /**< 0x0014: Open Drain Register */
+    uint32 PULDIS; /**< 0x0018: Pullup Disable Register */
+    uint32 PSL;    /**< 0x001C: Pull Up/Down Selection Register */
+} gioPORT_t;
+
+
+/** @def gioREG
+*   @brief GIO Register Frame Pointer
+*
+*   This pointer is used by the GIO driver to access the gio module registers.
+*/
+#define gioREG   ((gioBASE_t *)0xFFF7BC00U)
+
+/** @def gioPORTA
+*   @brief GIO Port (A) Register Pointer
+*
+*   Pointer used by the GIO driver to access PORTA
+*/
+#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)
+
+/** @def gioPORTB
+*   @brief GIO Port (B) Register Pointer
+*
+*   Pointer used by the GIO driver to access PORTB
+*/
+#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_het.h b/include/arch/rm46l8lp/halcogen/reg_het.h
new file mode 100644
index 0000000..f2d70eb
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_het.h
@@ -0,0 +1,203 @@
+/** @file reg_het.h
+*   @brief HET Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the HET driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_HET_H__
+#define __REG_HET_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Het Register Frame Definition */
+/** @struct hetBase
+*   @brief HET Base Register Definition
+*
+*   This structure is used to access the HET module registers.
+*/
+/** @typedef hetBASE_t
+*   @brief HET Register Frame Type Definition
+*
+*   This type is used to access the HET Registers.
+*/
+
+typedef volatile struct hetBase
+{
+    uint32 GCR;     /**< 0x0000: Global control register              */
+    uint32 PFR;     /**< 0x0004: Prescale factor register             */
+    uint32 ADDR;    /**< 0x0008: Current address register             */
+    uint32 OFF1;    /**< 0x000C: Interrupt offset register 1          */
+    uint32 OFF2;    /**< 0x0010: Interrupt offset register 2          */
+    uint32 INTENAS; /**< 0x0014: Interrupt enable set register        */
+    uint32 INTENAC; /**< 0x0018: Interrupt enable clear register      */
+    uint32 EXC1;    /**< 0x001C: Exception control register 1          */
+    uint32 EXC2;    /**< 0x0020: Exception control register 2          */
+    uint32 PRY;     /**< 0x0024: Interrupt priority register          */
+    uint32 FLG;     /**< 0x0028: Interrupt flag register              */
+    uint32 AND;     /**< 0x002C: AND share control register         */
+    uint32   rsvd1; /**< 0x0030: Reserved                             */
+    uint32 HRSH;    /**< 0x0034: High resolution share register        */
+    uint32 XOR;     /**< 0x0038: XOR share register                   */
+    uint32 REQENS;  /**< 0x003C: Request enable set register          */
+    uint32 REQENC;  /**< 0x0040: Request enable clear register        */
+    uint32 REQDS;   /**< 0x0044: Request destination select register  */
+    uint32   rsvd2; /**< 0x0048: Reserved                             */
+    uint32 DIR;     /**< 0x004C: Direction register                   */
+    uint32 DIN;     /**< 0x0050: Data input register                  */
+    uint32 DOUT;    /**< 0x0054: Data output register                 */
+    uint32 DSET;    /**< 0x0058: Data output set register             */
+    uint32 DCLR;    /**< 0x005C: Data output clear register           */
+    uint32 PDR;     /**< 0x0060: Open drain register                  */
+    uint32 PULDIS;  /**< 0x0064: Pull disable register                */
+    uint32 PSL;     /**< 0x0068: Pull select register                 */
+    uint32   rsvd3; /**< 0x006C: Reserved                             */
+    uint32   rsvd4; /**< 0x0070: Reserved                             */
+    uint32 PCR;   /**< 0x0074: Parity control register              */
+    uint32 PAR;     /**< 0x0078: Parity address register              */
+    uint32 PPR;     /**< 0x007C: Parity pin select register           */
+    uint32 SFPRLD;  /**< 0x0080: Suppression filter preload register  */
+    uint32 SFENA;   /**< 0x0084: Suppression filter enable register   */
+    uint32   rsvd5; /**< 0x0088: Reserved                             */
+    uint32 LBPSEL;  /**< 0x008C: Loop back pair select register       */
+    uint32 LBPDIR;  /**< 0x0090: Loop back pair direction register    */
+    uint32 PINDIS;  /**< 0x0094: Pin disable register                 */
+} hetBASE_t;
+
+
+/** @struct hetInstructionBase
+*   @brief HET Instruction Definition
+*
+*   This structure is used to access the HET RAM.
+*/
+/** @typedef hetINSTRUCTION_t
+*   @brief HET Instruction Type Definition
+*
+*   This type is used to access a HET Instruction.
+*/
+typedef volatile struct hetInstructionBase
+{
+    uint32 Program;
+    uint32 Control;
+    uint32 Data;
+    uint32   rsvd1;
+} hetINSTRUCTION_t;
+
+
+/** @struct hetRamBase
+*   @brief HET RAM Definition
+*
+*   This structure is used to access the HET RAM.
+*/
+/** @typedef hetRAMBASE_t
+*   @brief HET RAM Type Definition
+*
+*   This type is used to access the HET RAM.
+*/
+typedef volatile struct het1RamBase
+{
+    hetINSTRUCTION_t Instruction[160U];
+} hetRAMBASE_t;
+
+
+/** @def hetREG1
+*   @brief HET Register Frame Pointer
+*
+*   This pointer is used by the HET driver to access the het module registers.
+*/
+#define hetREG1 ((hetBASE_t *)0xFFF7B800U)
+
+
+/** @def hetPORT1
+*   @brief HET GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of HET1
+*   (use the GIO drivers to access the port pins).
+*/
+#define hetPORT1 ((gioPORT_t *)0xFFF7B84CU)
+
+/** @def hetRAM1
+*   @brief NHET1 RAM Pointer
+*
+*   This pointer is used by the HET driver to access the NHET1 memory.
+*/
+#define hetRAM1 ((hetRAMBASE_t *)0xFF460000U)
+
+#define NHET1RAMPARLOC	(*(volatile uint32 *)0xFF462000U)
+#define NHET1RAMLOC		(*(volatile uint32 *)0xFF460000U)
+
+/** @def hetREG2
+*   @brief HET2 Register Frame Pointer
+*
+*   This pointer is used by the HET driver to access the het module registers.
+*/
+#define hetREG2 ((hetBASE_t *)0xFFF7B900U)
+
+/** @def hetPORT2
+*   @brief HET2 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of HET2
+*   (use the GIO drivers to access the port pins).
+*/
+#define hetPORT2 ((gioPORT_t *)0xFFF7B94CU)
+
+/** @def hetRAM2
+*   @brief NHET1 RAM Pointer
+*
+*   This pointer is used by the HET driver to access the NHET2 memory.
+*/
+#define hetRAM2 ((hetRAMBASE_t *)0xFF440000U)
+
+#define NHET2RAMPARLOC	(*(volatile uint32 *)0xFF442000U)
+#define NHET2RAMLOC		(*(volatile uint32 *)0xFF440000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_htu.h b/include/arch/rm46l8lp/halcogen/reg_htu.h
new file mode 100644
index 0000000..92e830c
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_htu.h
@@ -0,0 +1,141 @@
+/** @file reg_htu.h
+*   @brief HTU Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the HTU driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_HTU_H__
+#define __REG_HTU_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* htu Register Frame Definition */
+/** @struct htuBase
+*   @brief HTU Base Register Definition
+*
+*   This structure is used to access the HTU module registers.
+*/
+/** @typedef htuBASE_t
+*   @brief HTU Register Frame Type Definition
+*
+*   This type is used to access the HTU Registers.
+*/
+typedef volatile struct htuBase
+{
+    uint32 GC;				/** 0x00 */ 
+    uint32 CPENA;			/** 0x04 */ 
+    uint32 BUSY0;			/** 0x08 */ 
+    uint32 BUSY1;			/** 0x0C */ 
+    uint32 BUSY2;			/** 0x10 */ 
+    uint32 BUSY3;			/** 0x14 */ 
+	uint32 ACPE;			/** 0x18 */ 
+    uint32 rsvd1;    		/** 0x1C */ 
+    uint32 RLBECTRL;		/** 0x20 */ 
+    uint32 BFINTS;			/** 0x24 */ 
+    uint32 BFINTC;			/** 0x28 */ 
+    uint32 INTMAP;			/** 0x2C */ 
+    uint32 rsvd2;  			/** 0x30 */ 
+    uint32 INTOFF0;			/** 0x34 */ 
+    uint32 INTOFF1;			/** 0x38 */ 
+    uint32 BIM;				/** 0x3C */ 
+    uint32 RLOSTFL;			/** 0x40 */ 
+    uint32 BFINTFL;			/** 0x44 */ 
+    uint32 BERINTFL;		/** 0x48 */ 
+    uint32 MP1S;			/** 0x4C */ 
+    uint32 MP1E;			/** 0x50 */ 
+    uint32 DCTRL;			/** 0x54 */ 
+    uint32 WPR;				/** 0x58 */ 
+    uint32 WMR;				/** 0x5C */ 
+    uint32 ID;				/** 0x60 */ 
+    uint32 PCR;				/** 0x64 */ 
+    uint32 PAR;				/** 0x68 */ 
+    uint32 rsvd3; 			/** 0x6C */ 
+    uint32 MPCS;			/** 0x70 */ 
+    uint32 MP0S;			/** 0x74 */ 
+    uint32 MP0E;			/** 0x78 */ 
+} htuBASE_t;                        
+
+typedef volatile struct
+{
+     struct                                     /* 0x00-0x7C */
+     {
+        uint32 IFADDRA;			 
+        uint32 IFADDRB;			
+        uint32 IHADDRCT;		
+        uint32 ITCOUNT; 
+     }DCP[8U];
+
+     struct                                     /* 0x80-0xFC */
+     {
+       uint32 res[32U];
+     } RESERVED;
+
+     struct                                     /* 0x100-0x17C */
+     {
+        uint32 CFADDRA;			
+        uint32 CFADDRB;			
+        uint32 CFCOUNT;			
+        uint32 rsvd4; 	
+     }CDCP[8U];
+
+} htuRAMBASE_t;
+
+#define htuREG1   ((htuBASE_t *)0xFFF7A400U)
+#define htuREG2   ((htuBASE_t *)0xFFF7A500U)
+
+#define htuRAM1   ((htuRAMBASE_t *)0xFF4E0000U)
+#define htuRAM2   ((htuRAMBASE_t *)0xFF4C0000U)
+
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_i2c.h b/include/arch/rm46l8lp/halcogen/reg_i2c.h
new file mode 100644
index 0000000..4e86e4d
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_i2c.h
@@ -0,0 +1,147 @@
+/** @file reg_i2c.h
+*   @brief I2C Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the I2C driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_I2C_H__
+#define __REG_I2C_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* I2c Register Frame Definition */
+/** @struct i2cBase
+*   @brief I2C Base Register Definition
+*
+*   This structure is used to access the I2C module registers.
+*/
+/** @typedef i2cBASE_t
+*   @brief I2C Register Frame Type Definition
+*
+*   This type is used to access the I2C Registers.
+*/
+typedef volatile struct i2cBase
+{
+
+    uint32 OAR;           /**<  0x0000 I2C Own Address register               */
+    uint32 IMR;           /**<  0x0004 I2C Interrupt Mask/Status register     */
+    uint32 STR;           /**<  0x0008 I2C Interrupt Status register          */
+    uint32 CKL;          /**<  0x000C I2C Clock Divider Low register          */
+    uint32 CKH;          /**<  0x0010 I2C Clock Divider High register         */
+    uint32 CNT;           /**<  0x0014 I2C Data Count register                */
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+    uint8 DRR;            /**< 0x0018: I2C Data Receive register,             */
+    uint8 rsvd1;          /**< 0x0018: I2C Data Receive register, Reserved    */
+    uint8 rsvd2;          /**< 0x0018: I2C Data Receive register, Reserved    */
+    uint8 rsvd3;          /**< 0x0018: I2C Data Receive register, Reserved    */
+#else
+    uint8 rsvd3;          /**< 0x0018: I2C Data Receive register, Reserved    */
+    uint8 rsvd2;          /**< 0x0018: I2C Data Receive register, Reserved    */
+    uint8 rsvd1;          /**< 0x0018: I2C Data Receive register, Reserved    */
+    uint8 DRR;            /**< 0x0018: I2C Data Receive register,             */
+#endif	
+    uint32 SAR;           /**<  0x001C I2C Slave Address register             */
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+    uint8 DXR;            /**< 0x0020: I2C Data Transmit register,            */
+    uint8 rsvd4;          /**< 0x0020: I2C Data Transmit register, Reserved   */
+    uint8 rsvd5;          /**< 0x0020: I2C Data Transmit register, Reserved   */
+    uint8 rsvd6;          /**< 0x0020: I2C Data Transmit register, Reserved   */
+#else
+    uint8 rsvd6;          /**< 0x0020: I2C Data Transmit register, Reserved   */
+    uint8 rsvd5;          /**< 0x0020: I2C Data Transmit register, Reserved   */
+    uint8 rsvd4;          /**< 0x0020: I2C Data Transmit register, Reserved   */
+    uint8 DXR;            /**< 0x0020: I2C Data Transmit register,            */
+#endif	
+    uint32 MDR;           /**<  0x0024 I2C Mode register                      */
+    uint32 IVR;           /**<  0x0028 I2C Interrupt Vector register          */
+    uint32 EMDR;          /**<  0x002C I2C Extended Mode register             */
+    uint32 PSC;           /**<  0x0030 I2C Prescaler register                 */
+    uint32 PID11;         /**<  0x0034 I2C Peripheral ID register 1           */
+    uint32 PID12;         /**<  0x0038 I2C Peripheral ID register 2           */
+    uint32 DMACR;         /**<  0x003C I2C DMA Control Register               */
+    uint32 rsvd7;         /**<  0x0040 Reserved                               */
+    uint32 rsvd8;         /**<  0x0044 Reserved                               */
+    uint32 PFNC;          /**<  0x0048 Pin Function Register                  */
+    uint32 DIR;           /**<  0x004C Pin Direction Register                 */
+    uint32 DIN;           /**<  0x0050 Pin Data In Register                   */
+    uint32 DOUT;          /**<  0x0054 Pin Data Out Register                  */
+    uint32 SET;           /**<  0x0058 Pin Data Set Register                  */
+    uint32 CLR;           /**<  0x005C Pin Data Clr Register                  */
+    uint32 PDR;           /**<  0x0060 Pin Open Drain Output Enable Register  */
+    uint32 PDIS;          /**<  0x0064 Pin Pullup/Pulldown Disable Register   */
+    uint32 PSEL;          /**<  0x0068 Pin Pullup/Pulldown Selection Register */
+    uint32 PSRS;          /**<  0x006C Pin Slew Rate Select Register          */	
+} i2cBASE_t;
+
+
+/** @def i2cREG1
+*   @brief I2C Register Frame Pointer
+*
+*   This pointer is used by the I2C driver to access the I2C module registers.
+*/
+#define i2cREG1 ((i2cBASE_t *)0xFFF7D400U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @def i2cPORT1
+*   @brief I2C GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of I2C
+*   (use the GIO drivers to access the port pins).
+*/
+#define i2cPORT1 ((gioPORT_t *)0xFFF7D44CU)
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_lin.h b/include/arch/rm46l8lp/halcogen/reg_lin.h
new file mode 100644
index 0000000..c9c7730
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_lin.h
@@ -0,0 +1,129 @@
+/** @file reg_lin.h
+*   @brief LIN Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the LIN driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_LIN_H__
+#define __REG_LIN_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Lin Register Frame Definition */
+/** @struct linBase
+*   @brief LIN Base Register Definition
+*
+*   This structure is used to access the LIN module registers.
+*/
+/** @typedef linBASE_t
+*   @brief LIN  Register Frame Type Definition
+*
+*   This type is used to access the LIN Registers.
+*/
+
+typedef volatile struct linBase
+{
+    uint32      GCR0;         /**< 0x0000: Global control register 0              */
+    uint32      GCR1;         /**< 0x0004: Global control register 1              */
+    uint32      GCR2;         /**< 0x0008: Global control register 2              */
+    uint32      SETINT;       /**< 0x000C: Set interrupt enable register          */
+    uint32      CLEARINT;     /**< 0x0010: Clear interrupt enable register        */
+    uint32      SETINTLVL;    /**< 0x0014: Set interrupt level register           */
+    uint32      CLEARINTLVL;  /**< 0x0018: Set interrupt level register           */
+    uint32      FLR;          /**< 0x001C: interrupt flag register                */
+    uint32      INTVECT0;     /**< 0x0020: interrupt vector Offset 0              */
+    uint32      INTVECT1;     /**< 0x0024: interrupt vector Offset 1              */
+    uint32      FORMAT;       /**< 0x0028: Format Control Register                */	
+    uint32      BRS;          /**< 0x002C: Baud rate selection register           */
+    uint32      ED;           /**< 0x0030: Emulation register                     */
+    uint32      RD;           /**< 0x0034: Receive data register                  */
+    uint32      TD;           /**< 0x0038: Transmit data register                 */
+    uint32      PIO0;         /**< 0x003C: Pin function register                  */
+    uint32      PIO1;         /**< 0x0040: Pin direction register                 */
+    uint32      PIO2;         /**< 0x0044: Pin data in register                   */
+    uint32      PIO3;         /**< 0x0048: Pin data out register                  */
+    uint32      PIO4;         /**< 0x004C: Pin data set register                  */
+    uint32      PIO5;         /**< 0x0050: Pin data clr register                  */
+    uint32      PIO6;         /**< 0x0054: Pin open drain output enable register  */
+    uint32      PIO7;         /**< 0x0058: Pin pullup/pulldown disable register   */
+    uint32      PIO8;         /**< 0x005C: Pin pullup/pulldown selection register */
+    uint32      COMP;         /**< 0x0060: Compare register                       */
+    uint8       RDx[8U];      /**< 0x0064-0x0068: RX buffer register              */
+    uint32      MASK;         /**< 0x006C: Mask register                          */
+    uint32      ID;           /**< 0x0070: Identification Register                */	
+    uint8       TDx[8U];      /**< 0x0074-0x0078: TX buffer register              */
+    uint32      MBRSR;        /**< 0x007C: Maximum baud rate selection register   */
+    uint32      rsvd1[4U];    /**< 0x0080 - 0x8C: Reserved                               */
+    uint32      IODFTCTRL;    /**< 0x0090: IODFT loopback register                */
+} linBASE_t;
+
+
+/** @def linREG
+*   @brief LIN Register Frame Pointer
+*
+*   This pointer is used by the LIN driver to access the lin module registers.
+*/
+#define linREG ((linBASE_t *)0xFFF7E400U)
+
+
+/** @def linPORT
+*   @brief LIN GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of LIN
+*   (use the GIO drivers to access the port pins).
+*/
+#define linPORT ((gioPORT_t *)0xFFF7E440U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_mibspi.h b/include/arch/rm46l8lp/halcogen/reg_mibspi.h
new file mode 100644
index 0000000..a696f40
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_mibspi.h
@@ -0,0 +1,257 @@
+/** @file reg_mibspi.h
+*   @brief MIBSPI Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the MIBSPI driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_MIBSPI_H__
+#define __REG_MIBSPI_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Mibspi Register Frame Definition */
+/** @struct mibspiBase
+*   @brief MIBSPI Register Definition
+*
+*   This structure is used to access the MIBSPI module registers.
+*/
+/** @typedef mibspiBASE_t
+*   @brief MIBSPI Register Frame Type Definition
+*
+*   This type is used to access the MIBSPI Registers.
+*/
+typedef volatile struct mibspiBase
+{
+    uint32  GCR0;                 /**< 0x0000: Global Control 0 */
+    uint32  GCR1;                 /**< 0x0004: Global Control 1 */	
+    uint32  INT0;                 /**< 0x0008: Interrupt Register */	
+    uint32  LVL;                  /**< 0x000C: Interrupt Level */
+    uint32  FLG;                  /**< 0x0010: Interrupt flags */	
+    uint32  PC0;                /**< 0x0014: Function Pin Enable */
+    uint32  PC1;                /**< 0x0018: Pin Direction */
+    uint32  PC2;                /**< 0x001C: Pin Input Latch */
+    uint32  PC3;               /**< 0x0020: Pin Output Latch */
+    uint32  PC4;                /**< 0x0024: Output Pin Set */
+    uint32  PC5;                /**< 0x0028: Output Pin Clr */
+    uint32  PC6;                /**< 0x002C: Open Drain Output Enable */
+    uint32  PC7;                /**< 0x0030: Pullup/Pulldown Disable */
+    uint32  PC8;                /**< 0x0034: Pullup/Pulldown Selection */
+    uint32  DAT0;                 /**< 0x0038: Transmit Data */
+    uint32  DAT1;                 /**< 0x003C: Transmit Data with Format and Chip Select */
+    uint32  BUF;                  /**< 0x0040: Receive Buffer */
+    uint32  EMU;                  /**< 0x0044: Emulation Receive Buffer */
+    uint32  DELAY;                /**< 0x0048: Delays */
+    uint32  DEF;                /**< 0x004C: Default Chip Select */
+    uint32  FMT0;                 /**< 0x0050: Data Format 0 */
+    uint32  FMT1;                 /**< 0x0054: Data Format 1 */
+    uint32  FMT2;                 /**< 0x0058: Data Format 2 */
+    uint32  FMT3;                 /**< 0x005C: Data Format 3 */
+    uint32  INTVECT0;             /**< 0x0060: Interrupt Vector 0 */
+    uint32  INTVECT1;             /**< 0x0064: Interrupt Vector 1 */
+    uint32  SRSEL;                /**< 0x0068: Slew Rate Select */
+    uint32  PMCTRL;               /**< 0x006C: Parallel Mode Control */
+    uint32  MIBSPIE;              /**< 0x0070: Multi-buffer Mode Enable  */
+    uint32  TGITENST;             /**< 0x0074: TG Interrupt Enable Set */
+    uint32  TGITENCR;             /**< 0x0078: TG Interrupt Enable Clear */
+    uint32  TGITLVST;             /**< 0x007C: Transfer Group Interrupt Level Set */
+    uint32  TGITLVCR;             /**< 0x0080: Transfer Group Interrupt Level Clear */
+    uint32  TGINTFLG;             /**< 0x0084: Transfer Group Interrupt Flag */	
+    uint32    rsvd1[2U];           /**< 0x0088: Reserved */
+    uint32  TICKCNT;              /**< 0x0090: Tick Counter */
+    uint32  LTGPEND;              /**< 0x0090: Last TG End Pointer */	
+    uint32  TGCTRL[16U];          /**< 0x0098 - 0x00D4: Transfer Group Control */
+    uint32  DMACTRL[8U];          /**< 0x00D8 - 0x00F4: DMA Control */
+    uint32  DMACOUNT[8U];         /**< 0x00F8 - 0x0114: DMA Count */
+    uint32  DMACNTLEN;            /**< 0x0118 - 0x0114: DMA Control length */
+    uint32    rsvd2;              /**< 0x011C: Reserved */
+    uint32  UERRCTRL;             /**< 0x0120: Multi-buffer RAM Uncorrectable Parity Error Control */	
+    uint32  UERRSTAT;             /**< 0x0124: Multi-buffer RAM Uncorrectable Parity Error Status */	  
+    uint32  UERRADDRRX;           /**< 0x0128: RXRAM Uncorrectable Parity Error Address */	
+    uint32  UERRADDRTX;           /**< 0x012C: TXRAM Uncorrectable Parity Error Address */	
+    uint32  RXOVRN_BUF_ADDR;      /**< 0x0130: RXRAM Overrun Buffer Address */
+    uint32  IOLPKTSTCR;           /**< 0x0134: IO loopback */
+    uint32  EXT_PRESCALE1;        /**< 0x0138: */
+    uint32  EXT_PRESCALE2;        /**< 0x013C: */
+} mibspiBASE_t;
+
+
+/** @def mibspiREG1
+*   @brief MIBSPI1 Register Frame Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi module registers.
+*/
+#define mibspiREG1 ((mibspiBASE_t *)0xFFF7F400U)
+
+
+/** @def mibspiPORT1
+*   @brief MIBSPI1 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of MIBSPI1
+*   (use the GIO drivers to access the port pins).
+*/
+#define mibspiPORT1 ((gioPORT_t *)0xFFF7F418U)
+
+/** @def mibspiREG3
+*   @brief MIBSPI3 Register Frame Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi module registers.
+*/
+#define mibspiREG3 ((mibspiBASE_t *)0xFFF7F800U)
+
+
+/** @def mibspiPORT3
+*   @brief MIBSPI3 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of MIBSPI3
+*   (use the GIO drivers to access the port pins).
+*/
+#define mibspiPORT3 ((gioPORT_t *)0xFFF7F818U)
+
+/** @def mibspiREG5
+*   @brief MIBSPI5 Register Frame Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi module registers.
+*/
+#define mibspiREG5 ((mibspiBASE_t *)0xFFF7FC00U)
+
+
+/** @def mibspiPORT5
+*   @brief MIBSPI5 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of MIBSPI5
+*   (use the GIO drivers to access the port pins).
+*/
+#define mibspiPORT5 ((gioPORT_t *)0xFFF7FC18U)
+
+
+/** @struct mibspiRamBase
+*   @brief MIBSPI Buffer RAM Definition
+*
+*   This structure is used to access the MIBSPI buffer memory.
+*/
+/** @typedef mibspiRAM_t
+*   @brief MIBSPI RAM Type Definition
+*
+*   This type is used to access the MIBSPI RAM.
+*/
+typedef volatile struct mibspiRamBase
+{
+    struct 
+    {
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+     uint16  data;     /**< tx buffer data    */   
+     uint16  control;  /**< tx buffer control */  
+#else
+     uint16  control;  /**< tx buffer control */
+     uint16  data;     /**< tx buffer data    */
+#endif
+    } tx[128];
+    struct
+    {
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+     uint16 data;     /**< rx buffer data  */
+	 uint16 flags;    /**< rx buffer flags */
+#else
+	 uint16 flags;    /**< rx buffer flags */
+     uint16 data;     /**< rx buffer data  */
+#endif
+    } rx[128];
+} mibspiRAM_t;
+
+
+/** @def mibspiRAM1
+*   @brief MIBSPI1 Buffer RAM Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiRAM1 ((mibspiRAM_t *)0xFF0E0000U)
+
+/** @def mibspiRAM3
+*   @brief MIBSPI3 Buffer RAM Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiRAM3 ((mibspiRAM_t *)0xFF0C0000U)
+
+/** @def mibspiRAM5
+*   @brief MIBSPI5 Buffer RAM Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiRAM5 ((mibspiRAM_t *)0xFF0A0000U)
+
+/** @def mibspiPARRAM1
+*   @brief MIBSPI1 Buffer RAM PARITY Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiPARRAM1 (*(volatile uint32 *)(0xFF0E0000U + 0x00000400U))
+
+/** @def mibspiPARRAM3
+*   @brief MIBSPI3 Buffer RAM PARITY Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiPARRAM3 (*(volatile uint32 *)(0xFF0C0000U + 0x00000400U))
+
+
+/** @def mibspiPARRAM5
+*   @brief MIBSPI5 Buffer RAM PARITY Pointer
+*
+*   This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiPARRAM5 (*(volatile uint32 *)(0xFF0A0000U + 0x00000400U))
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_pbist.h b/include/arch/rm46l8lp/halcogen/reg_pbist.h
new file mode 100644
index 0000000..636e939
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_pbist.h
@@ -0,0 +1,98 @@
+/** @file reg_pbist.h
+*   @brief PBIST Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_PBIST_H__
+#define __REG_PBIST_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* PBIST Register Frame Definition */
+/** @struct pbistBase
+*   @brief PBIST Base Register Definition
+*
+*   This structure is used to access the PBIST module registers.
+*/
+/** @typedef pbistBASE_t
+*   @brief PBIST Register Frame Type Definition
+*
+*   This type is used to access the PBIST Registers.
+*/
+typedef volatile struct pbistBase
+{
+    uint32 RAMT;            /* 0x0160: RAM Configuration Register */
+    uint32 DLR;             /* 0x0164: Datalogger Register */
+    uint32   rsvd1[6U];     /* 0x0168 */
+    uint32 PACT;            /* 0x0180: PBIST Activate Register */
+    uint32 PBISTID;         /* 0x0184: PBIST ID Register */
+    uint32 OVER;            /* 0x0188: Override Register */
+    uint32   rsvd2;         /* 0x018C */
+    uint32 FSRF0;           /* 0x0190: Fail Status Fail Register 0 */
+    uint32 rsvd5;           /* 0x0194 */
+    uint32 FSRC0;           /* 0x0198: Fail Status Count Register 0 */
+    uint32 FSRC1;           /* 0x019C: Fail Status Count Register 1 */
+    uint32 FSRA0;           /* 0x01A0: Fail Status Address 0 Register */
+    uint32 FSRA1;           /* 0x01A4: Fail Status Address 1 Register */
+    uint32 FSRDL0;          /* 0x01A8: Fail Status Data Register 0 */
+    uint32   rsvd3;         /* 0x01AC */
+    uint32 FSRDL1;          /* 0x01B0: Fail Status Data Register 1 */
+    uint32   rsvd4[3U];     /* 0x01B4 */
+    uint32 ROM;             /* 0x01C0: ROM Mask Register */
+    uint32 ALGO;            /* 0x01C4: Algorithm Mask Register */
+    uint32 RINFOL;          /* 0x01C8: RAM Info Mask Lower Register */
+    uint32 RINFOU;          /* 0x01CC: RAM Info Mask Upper Register */
+} pbistBASE_t;
+
+#define pbistREG   ((pbistBASE_t *)0xFFFFE560U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_pcr.h b/include/arch/rm46l8lp/halcogen/reg_pcr.h
new file mode 100644
index 0000000..f3d6f6b
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_pcr.h
@@ -0,0 +1,113 @@
+/** @file reg_pcr.h
+*   @brief PCR Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_PCR_H__
+#define __REG_PCR_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Pcr Register Frame Definition */
+/** @struct pcrBase
+*   @brief Pcr Register Frame Definition
+*
+*   This type is used to access the Pcr Registers.
+*/
+/** @typedef pcrBASE_t
+*   @brief PCR Register Frame Type Definition
+*
+*   This type is used to access the PCR Registers.
+*/
+typedef volatile struct pcrBase
+{
+    uint32 PMPROTSET0;    /* 0x0000 */
+    uint32 PMPROTSET1;    /* 0x0004 */
+    uint32   rsvd1[2U];    /* 0x0008 */
+    uint32 PMPROTCLR0;    /* 0x0010 */
+    uint32 PMPROTCLR1;    /* 0x0014 */
+    uint32   rsvd2[2U];    /* 0x0018 */
+    uint32 PPROTSET0;     /* 0x0020 */
+    uint32 PPROTSET1;     /* 0x0024 */
+    uint32 PPROTSET2;     /* 0x0028 */
+    uint32 PPROTSET3;     /* 0x002C */
+    uint32   rsvd3[4U];    /* 0x0030 */
+    uint32 PPROTCLR0;     /* 0x0040 */
+    uint32 PPROTCLR1;     /* 0x0044 */
+    uint32 PPROTCLR2;     /* 0x0048 */
+    uint32 PPROTCLR3;     /* 0x004C */
+    uint32   rsvd4[4U];    /* 0x0050 */
+    uint32 PCSPWRDWNSET0; /* 0x0060 */
+    uint32 PCSPWRDWNSET1; /* 0x0064 */
+    uint32   rsvd5[2U];    /* 0x0068 */
+    uint32 PCSPWRDWNCLR0; /* 0x0070 */
+    uint32 PCSPWRDWNCLR1; /* 0x0074 */
+    uint32   rsvd6[2U];    /* 0x0078 */
+    uint32 PSPWRDWNSET0;  /* 0x0080 */
+    uint32 PSPWRDWNSET1;  /* 0x0084 */
+    uint32 PSPWRDWNSET2;  /* 0x0088 */
+    uint32 PSPWRDWNSET3;  /* 0x008C */
+    uint32   rsvd7[4U];    /* 0x0090 */
+    uint32 PSPWRDWNCLR0;  /* 0x00A0 */
+    uint32 PSPWRDWNCLR1;  /* 0x00A4 */
+    uint32 PSPWRDWNCLR2;  /* 0x00A8 */
+    uint32 PSPWRDWNCLR3;  /* 0x00AC */
+} pcrBASE_t;
+
+/** @def pcrREG
+*   @brief Pcr Register Frame Pointer
+*
+*   This pointer is used by the system driver to access the Pcr registers.
+*/
+#define pcrREG ((pcrBASE_t *)0xFFFFE000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_pinmux.h b/include/arch/rm46l8lp/halcogen/reg_pinmux.h
new file mode 100644
index 0000000..c70cf31
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_pinmux.h
@@ -0,0 +1,180 @@
+/** @file reg_pinmux.h
+*   @brief PINMUX Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the PINMUX driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_PINMUX_H__
+#define __REG_PINMUX_H__
+
+#include "sys_common.h"
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* IOMM Revision and Boot Register */
+#define REVISION_REG		(*(volatile uint32 *)0xFFFFEA00U)
+#define ENDIAN_REG		(*(volatile uint32 *)0xFFFFEA20U)
+
+/* IOMM Error and Fault Registers */
+/** @struct iommErrFault
+*   @brief IOMM Error and Fault Register Definition
+*
+*   This structure is used to access the IOMM Error and Fault registers.
+*/
+typedef volatile struct iommErrFault
+{
+    uint32 ERR_RAW_STATUS_REG;          /* Error Raw Status / Set Register */
+    uint32 ERR_ENABLED_STATUS_REG;      /* Error Enabled Status / Clear Register */
+    uint32 ERR_ENABLE_REG;              /* Error Signaling Enable Register */
+    uint32 ERR_ENABLE_CLR_REG;          /* Error Signaling Enable Clear Register */
+	uint32  rsvd;                       /* Reserved */
+    uint32 FAULT_ADDRESS_REG;           /* Fault Address Register */
+    uint32 FAULT_STATUS_REG;            /* Fault Status Register */
+    uint32 FAULT_CLEAR_REG;             /* Fault Clear Register */	
+} iommErrFault_t;
+
+/* Pinmux Register Frame Definition */
+/** @struct pinMuxKicker
+*   @brief Pin Muxing Kicker Register Definition
+*
+*   This structure is used to access the Pin Muxing Kicker registers.
+*/
+typedef volatile struct pinMuxKicker
+{
+    uint32 KICKER0;       /* kicker 0 register */
+    uint32 KICKER1;       /* kicker 1 register */
+} pinMuxKICKER_t;
+
+/** @struct pinMuxBase
+*   @brief PINMUX Register Definition
+*
+*   This structure is used to access the PINMUX module egisters.
+*/
+/** @typedef pinMuxBASE_t
+*   @brief PINMUX Register Frame Type Definition
+*
+*   This type is used to access the PINMUX Registers.
+*/
+typedef volatile struct pinMuxBase
+{
+    uint32 PINMMR0;		/**< 0xEB10 Pin Mux 0 register*/
+    uint32 PINMMR1;		/**< 0xEB14 Pin Mux 1 register*/
+    uint32 PINMMR2;		/**< 0xEB18 Pin Mux 2 register*/
+    uint32 PINMMR3;		/**< 0xEB1C Pin Mux 3 register*/
+    uint32 PINMMR4;		/**< 0xEB20 Pin Mux 4 register*/
+    uint32 PINMMR5;		/**< 0xEB24 Pin Mux 5 register*/
+    uint32 PINMMR6;		/**< 0xEB28 Pin Mux 6 register*/
+    uint32 PINMMR7;		/**< 0xEB2C Pin Mux 7 register*/
+    uint32 PINMMR8;		/**< 0xEB30 Pin Mux 8 register*/
+    uint32 PINMMR9;		/**< 0xEB34 Pin Mux 9 register*/
+    uint32 PINMMR10;		/**< 0xEB38 Pin Mux 10 register*/
+    uint32 PINMMR11;		/**< 0xEB3C Pin Mux 11 register*/
+    uint32 PINMMR12;		/**< 0xEB40 Pin Mux 12 register*/
+    uint32 PINMMR13;		/**< 0xEB44 Pin Mux 13 register*/
+    uint32 PINMMR14;		/**< 0xEB48 Pin Mux 14 register*/
+    uint32 PINMMR15;		/**< 0xEB4C Pin Mux 15 register*/
+    uint32 PINMMR16;		/**< 0xEB50 Pin Mux 16 register*/
+    uint32 PINMMR17;		/**< 0xEB54 Pin Mux 17 register*/
+    uint32 PINMMR18;		/**< 0xEB58 Pin Mux 18 register*/
+    uint32 PINMMR19;		/**< 0xEB5C Pin Mux 19 register*/
+    uint32 PINMMR20;		/**< 0xEB60 Pin Mux 20 register*/
+    uint32 PINMMR21;		/**< 0xEB64 Pin Mux 21 register*/
+    uint32 PINMMR22;		/**< 0xEB68 Pin Mux 22 register*/
+    uint32 PINMMR23;		/**< 0xEB6C Pin Mux 23 register*/
+    uint32 PINMMR24;		/**< 0xEB70 Pin Mux 24 register*/
+    uint32 PINMMR25;		/**< 0xEB74 Pin Mux 25 register*/
+    uint32 PINMMR26;		/**< 0xEB78 Pin Mux 26 register*/
+    uint32 PINMMR27;		/**< 0xEB7C Pin Mux 27 register*/
+    uint32 PINMMR28;		/**< 0xEB80 Pin Mux 28 register*/
+    uint32 PINMMR29;		/**< 0xEB84 Pin Mux 29 register*/
+    uint32 PINMMR30;		/**< 0xEB88 Pin Mux 30 register*/
+    uint32 PINMMR31;		/**< 0xEB8C Pin Mux 31 register*/
+    uint32 PINMMR32;		/**< 0xEB90 Pin Mux 32 register*/
+    uint32 PINMMR33;		/**< 0xEB94 Pin Mux 33 register*/
+    uint32 PINMMR34;		/**< 0xEB98 Pin Mux 34 register*/
+    uint32 PINMMR35;		/**< 0xEB9C Pin Mux 35 register*/
+    uint32 PINMMR36;          /**< 0xEBA0 Pin Mux 36 register*/
+    uint32 PINMMR37;          /**< 0xEBA4 Pin Mux 37 register*/
+    uint32 PINMMR38;          /**< 0xEBA8 Pin Mux 38 register*/
+    uint32 PINMMR39;          /**< 0xEBAC Pin Mux 39 register*/
+    uint32 PINMMR40;          /**< 0xEBB0 Pin Mux 40 register*/
+    uint32 PINMMR41;          /**< 0xEBB4 Pin Mux 41 register*/
+    uint32 PINMMR42;          /**< 0xEBB8 Pin Mux 42 register*/
+    uint32 PINMMR43;          /**< 0xEBBC Pin Mux 43 register*/
+    uint32 PINMMR44;          /**< 0xEBC0 Pin Mux 44 register*/
+    uint32 PINMMR45;          /**< 0xEBC4 Pin Mux 45 register*/
+    uint32 PINMMR46;          /**< 0xEBC8 Pin Mux 46 register*/
+    uint32 PINMMR47;          /**< 0xEBCC Pin Mux 47 register*/
+}pinMuxBASE_t;
+
+
+/** @def iommErrFaultReg
+*       @brief IOMM Error Fault Register Frame Pointer
+*
+*               This pointer is used to control IOMM Error and Fault across the device.
+*/      
+#define iommErrFaultReg ((iommErrFault_t *) 0xFFFFEAE0U)
+        
+/** @def kickerReg
+*	@brief Pin Muxing Kicker Register Frame Pointer
+*
+*		This pointer is used to enable and disable muxing accross the device.
+*/	
+#define kickerReg ((pinMuxKICKER_t *) 0xFFFFEA38U)
+
+/** @def pinMuxReg
+*	@brief Pin Muxing Control Register Frame Pointer
+*
+*		This pointer is used to set the muxing registers accross the device.
+*/	
+#define pinMuxReg ((pinMuxBASE_t *) 0xFFFFEB10U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_pmm.h b/include/arch/rm46l8lp/halcogen/reg_pmm.h
new file mode 100644
index 0000000..37e6ac3
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_pmm.h
@@ -0,0 +1,111 @@
+/** @file reg_pmm.h
+*   @brief PMM Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the PMM driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_PMM_H__
+#define __REG_PMM_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Pmm Register Frame Definition */
+/** @struct pmmBase
+*   @brief Pmm Register Frame Definition
+*
+*   This type is used to access the Pmm Registers.
+*/
+/** @typedef pmmBase_t
+*   @brief Pmm Register Frame Type Definition
+*
+*   This type is used to access the Pmm Registers.
+*/
+typedef volatile struct pmmBase
+{
+	uint32 LOGICPDPWRCTRL0;		/**< 0x0000: Logic Power Domain Control Register 0 */	
+    uint32   rsvd1[3U];			/**< 0x0004: Reserved*/
+	uint32 MEMPDPWRCTRL0;		/**< 0x0010: Memory Power Domain Control Register 0 */
+    uint32   rsvd2[3U];			/**< 0x0014: Reserved*/
+    uint32 PDCLKDISREG;			/**< 0x0020: Power Domain Clock Disable Register */
+    uint32 PDCLKDISSETREG;		/**< 0x0024: Power Domain Clock Disable Set Register */
+    uint32 PDCLKDISCLRREG;		/**< 0x0028: Power Domain Clock Disable Clear Register */
+    uint32   rsvd3[5U];			/**< 0x002C: Reserved */
+    uint32 LOGICPDPWRSTAT[4U]; 	/**< 0x0040, 0x0044, 0x0048, 0x004C: Logic Power Domain Power Status Register 
+										- 0: PD2
+										- 1: PD3
+										- 2: PD4
+										- 3: PD5 */
+    uint32   rsvd4[12U];		/**< 0x0050: Reserved*/
+    uint32 MEMPDPWRSTAT[3U];	/**< 0x0080, 0x0084, 0x0088: Memory Power Domain Power Status Register 
+										- 0: RAM_PD1
+										- 1: RAM_PD2
+										- 2: RAM_PD3 */
+    uint32   rsvd5[5U];			/**< 0x008C: Reserved */
+    uint32 GLOBALCTRL1;			/**< 0x00A0: Global Control Register 1 */
+    uint32   rsvd6;				/**< 0x00A4: Reserved */
+    uint32 GLOBALSTAT;			/**< 0x00A8: Global Status Register */
+    uint32 PRCKEYREG;			/**< 0x00AC: PSCON Diagnostic Compare Key Register */
+    uint32 LPDDCSTAT1;			/**< 0x00B0: LogicPD PSCON Diagnostic Compare Status Register 1 */
+    uint32 LPDDCSTAT2;			/**< 0x00B4: LogicPD PSCON Diagnostic Compare Status Register 2 */
+    uint32 MPDDCSTAT1;			/**< 0x00B8: Memory PD PSCON Diagnostic Compare Status Register 1 */
+    uint32 MPDDCSTAT2;			/**< 0x00BC: Memory PD PSCON Diagnostic Compare Status Register 2 */
+    uint32 ISODIAGSTAT;			/**< 0x00C0: Isolation Diagnostic Status Register */
+}pmmBase_t;
+
+
+/** @def pmmREG
+*   @brief Pmm Register Frame Pointer
+*
+*   This pointer is used by the Pmm driver to access the Pmm registers.
+*/
+#define pmmREG ((pmmBase_t *)0xFFFF0000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_pom.h b/include/arch/rm46l8lp/halcogen/reg_pom.h
new file mode 100644
index 0000000..6ee4574
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_pom.h
@@ -0,0 +1,127 @@
+/** @file reg_pom.h
+*   @brief POM Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the POM driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_POM_H__
+#define __REG_POM_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Pom Register Frame Definition */
+/** @struct POMBase
+*   @brief POM Register Frame Definition
+*
+*   This structure is used to access the POM module registers(POM Register Map).
+*/
+typedef struct
+{
+  uint32 POMGLBCTRL;   /* 0x00      */
+  uint32 POMREV;       /* 0x04      */
+  uint32 POMCLKCTRL;   /* 0x08      */
+  uint32 POMFLG;       /* 0x0C      */
+  struct
+  {
+    uint32   rsdv1;
+  }RESERVED_REG[124U];
+  struct                    /* 0x200 ...    */
+  {
+    uint32 POMPROGSTART; 
+    uint32 POMOVLSTART; 
+    uint32 POMREGSIZE; 
+    uint32   rsdv2; 
+  }POMRGNCONF_ST[32U];
+}pomBASE_t;
+
+
+/** @struct POM_CORESIGHT_ST
+*   @brief POM_CORESIGHT_ST Register Definition
+*
+*   This structure is used to access the POM module registers(POM CoreSight Registers ).
+*/
+typedef struct
+{
+    uint32 POMITCTRL;                  /* 0xF00            */
+    struct                                  /* 0xF04 to 0xF9C   */                     
+    {
+        uint32 Reserved_Reg;
+    }Reserved1_ST[39U];
+    uint32 POMCLAIMSET;                /* 0xFA0      */
+    uint32 POMCLAIMCLR;                /* 0xFA4      */
+    uint32   rsvd1[2U];                    /* 0xFA8      */
+    uint32 POMLOCKACCESS;              /* 0xFB0      */
+    uint32 POMLOCKSTATUS;              /* 0xFB4      */
+    uint32 POMAUTHSTATUS;              /* 0xFB8      */
+    uint32   rsvd2[3U];                    /* 0xFBC      */
+    uint32 POMDEVID;                   /* 0xFC8      */
+    uint32 POMDEVTYPE;                 /* 0xFCC      */
+    uint32 POMPERIPHERALID4;           /* 0xFD0      */
+    uint32 POMPERIPHERALID5;           /* 0xFD4      */
+    uint32 POMPERIPHERALID6;           /* 0xFD8      */
+    uint32 POMPERIPHERALID7;           /* 0xFDC      */
+    uint32 POMPERIPHERALID0;           /* 0xFE0      */
+    uint32 POMPERIPHERALID1;           /* 0xFE4      */
+    uint32 POMPERIPHERALID2;           /* 0xFE8      */
+    uint32 POMPERIPHERALID3;           /* 0xFEC      */            
+    uint32 POMCOMPONENTID0;            /* 0xFF0      */
+    uint32 POMCOMPONENTID1;            /* 0xFF4      */
+    uint32 POMCOMPONENTID2;            /* 0xFF8      */
+    uint32 POMCOMPONENTID3;            /* 0xFFC      */
+}POM_CORESIGHT_ST;
+
+
+#define pomREG ((pomBASE_t *)0xFFA04000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_rti.h b/include/arch/rm46l8lp/halcogen/reg_rti.h
new file mode 100644
index 0000000..633c692
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_rti.h
@@ -0,0 +1,129 @@
+/** @file reg_rti.h
+*   @brief RTI Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the RTI driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_RTI_H__
+#define __REG_RTI_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Rti Register Frame Definition */
+/** @struct rtiBase
+*   @brief RTI Register Frame Definition
+*
+*   This type is used to access the RTI Registers.
+*/
+/** @typedef rtiBASE_t
+*   @brief RTI Register Frame Type Definition
+*
+*   This type is used to access the RTI Registers.
+*/
+typedef volatile struct rtiBase
+{
+    uint32 GCTRL;          /**< 0x0000: Global Control Register   */
+    uint32 TBCTRL;         /**< 0x0004: Timebase Control Register */
+    uint32 CAPCTRL;        /**< 0x0008: Capture Control Register  */
+    uint32 COMPCTRL;       /**< 0x000C: Compare Control Register  */
+    struct
+    {
+        uint32 FRCx;       /**< 0x0010,0x0030: Free Running Counter x Register         */
+        uint32 UCx;        /**< 0x0014,0x0034: Up Counter x Register                   */
+        uint32 CPUCx;      /**< 0x0018,0x0038: Compare Up Counter x Register           */
+        uint32   rsvd1;    /**< 0x001C,0x003C: Reserved                                */
+        uint32 CAFRCx;     /**< 0x0020,0x0040: Capture Free Running Counter x Register */
+        uint32 CAUCx;      /**< 0x0024,0x0044: Capture Up Counter x Register           */
+        uint32   rsvd2[2U]; /**< 0x0028,0x0048: Reserved                                */
+    } CNT[2U];               /**< Counter x selection:
+                                    - 0: Counter 0
+                                    - 1: Counter 1                                       */
+    struct
+    {
+        uint32 COMPx;      /**< 0x0050,0x0058,0x0060,0x0068: Compare x Register        */
+        uint32 UDCPx;      /**< 0x0054,0x005C,0x0064,0x006C: Update Compare x Register */
+    } CMP[4U];               /**< Compare x selection:
+                                    - 0: Compare 0 
+                                    - 1: Compare 1
+                                    - 2: Compare 2
+                                    - 3: Compare 3                                       */
+    uint32 TBLCOMP;        /**< 0x0070: External Clock Timebase Low Compare Register   */
+    uint32 TBHCOMP;        /**< 0x0074: External Clock Timebase High Compare Register  */
+    uint32   rsvd3[2U];    /**< 0x0078: Reserved                                       */
+    uint32 SETINTENA;      /**< 0x0080: Set/Status Interrupt Register                  */
+    uint32 CLEARINTENA;    /**< 0x0084: Clear/Status Interrupt Register                */
+    uint32 INTFLAG;        /**< 0x0088: Interrupt Flag Register                        */
+    uint32   rsvd4;        /**< 0x008C: Reserved                                       */
+    uint32 DWDCTRL;        /**< 0x0090: Digital Watchdog Control Register   */
+    uint32 DWDPRLD;        /**< 0x0094: Digital Watchdog Preload Register */
+    uint32 WDSTATUS;       /**< 0x0098: Watchdog Status Register  */
+    uint32 WDKEY;          /**< 0x009C: Watchdog Key Register  */
+    uint32 DWDCNTR;        /**< 0x00A0: Digital Watchdog Down Counter   */
+    uint32 WWDRXNCTRL;     /**< 0x00A4: Digital Windowed Watchdog Reaction Control */
+    uint32 WWDSIZECTRL;    /**< 0x00A8: Digital Windowed Watchdog Window Size Control  */
+    uint32 INTCLRENABLE;   /**< 0x00AC: RTI Compare Interrupt Clear Enable Register  */
+    uint32 COMP0CLR;       /**< 0x00B0: RTI Compare 0 Clear Register   */
+    uint32 COMP1CLR;       /**< 0x00B4: RTI Compare 1 Clear Register */
+    uint32 COMP2CLR;       /**< 0x00B8: RTI Compare 2 Clear Register  */
+    uint32 COMP3CLR;       /**< 0x00BC: RTI Compare 3 Clear Register  */
+} rtiBASE_t;
+
+/** @def rtiREG1
+*   @brief RTI1 Register Frame Pointer
+*
+*   This pointer is used by the RTI driver to access the RTI1 registers.
+*/
+#define rtiREG1 ((rtiBASE_t *)0xFFFFFC00U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_sci.h b/include/arch/rm46l8lp/halcogen/reg_sci.h
new file mode 100644
index 0000000..c0b7f88
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_sci.h
@@ -0,0 +1,139 @@
+/** @file reg_sci.h
+*   @brief SCI Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the SCI driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_SCI_H__
+#define __REG_SCI_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Sci Register Frame Definition */
+/** @struct sciBase
+*   @brief SCI Base Register Definition
+*
+*   This structure is used to access the SCI module registers.
+*/
+/** @typedef sciBASE_t
+*   @brief SCI Register Frame Type Definition
+*
+*   This type is used to access the SCI Registers.
+*/
+typedef volatile struct sciBase
+{
+    uint32 GCR0;          /**< 0x0000 Global Control Register 0 */
+    uint32 GCR1;          /**< 0x0004 Global Control Register 1 */
+    uint32 GCR2;         /**< 0x0008 Global Control Register 2. Note: Applicable only to LIN � SCI Compatibility Mode,Reserved for standalone SCI*/
+    uint32 SETINT;       /**< 0x000C Set Interrupt Enable Register */
+    uint32 CLEARINT;      /**< 0x0010 Clear Interrupt Enable Register */
+    uint32 SETINTLVL;    /**< 0x0014 Set Interrupt Level Register */
+    uint32 CLEARINTLVL;   /**< 0x0018 Set Interrupt Level Register */
+    uint32 FLR;           /**< 0x001C Interrupt Flag Register */
+    uint32 INTVECT0;      /**< 0x0020 Interrupt Vector Offset 0 */
+    uint32 INTVECT1;      /**< 0x0024 Interrupt Vector Offset 1 */
+    uint32 FORMAT;        /**< 0x0028 Format Control Register */
+    uint32 BRS;           /**< 0x002C Baud Rate Selection Register */
+    uint32 ED;            /**< 0x0030 Emulation Register */
+    uint32 RD;            /**< 0x0034 Receive Data Buffer */
+    uint32 TD;            /**< 0x0038 Transmit Data Buffer */
+    uint32 PIO0;          /**< 0x003C Pin Function Register */
+    uint32 PIO1;          /**< 0x0040 Pin Direction Register */
+    uint32 PIO2;          /**< 0x0044 Pin Data In Register */
+    uint32 PIO3;          /**< 0x0048 Pin Data Out Register */
+    uint32 PIO4;          /**< 0x004C Pin Data Set Register */
+    uint32 PIO5;          /**< 0x0050 Pin Data Clr Register */
+    uint32 PIO6;          /**< 0x0054: Pin Open Drain Output Enable Register */
+    uint32 PIO7;          /**< 0x0058: Pin Pullup/Pulldown Disable Register */
+    uint32 PIO8;          /**< 0x005C: Pin Pullup/Pulldown Selection Register */
+    uint32 rsdv2[12U];    /**< 0x0060: Reserved                               */
+    uint32 IODFTCTRL;     /**< 0x0090: I/O Error Enable Register */
+} sciBASE_t;
+
+
+/** @def sciREG
+*   @brief  Register Frame Pointer
+*
+*   This pointer is used by the SCI driver to access the sci module registers.
+*/
+#define sciREG ((sciBASE_t *)0xFFF7E500U)
+
+
+/** @def sciPORT
+*   @brief SCI GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SCI
+*   (use the GIO drivers to access the port pins).
+*/
+#define sciPORT ((gioPORT_t *)0xFFF7E540U)
+
+
+/** @def scilinREG
+*   @brief SCILIN (LIN - Compatibility Mode)  Register Frame Pointer
+*
+*   This pointer is used by the SCI driver to access the sci module registers.
+*/
+#define scilinREG ((sciBASE_t *)0xFFF7E400U)
+
+
+/** @def scilinPORT
+*   @brief SCILIN (LIN - Compatibility Mode)  Register Frame Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of LIN
+*   (use the GIO drivers to access the port pins).
+*/
+#define scilinPORT ((gioPORT_t *)0xFFF7E440U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_spi.h b/include/arch/rm46l8lp/halcogen/reg_spi.h
new file mode 100644
index 0000000..50bd5a8
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_spi.h
@@ -0,0 +1,187 @@
+/** @file reg_spi.h
+*   @brief SPI Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the SPI driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_SPI_H__
+#define __REG_SPI_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Spi Register Frame Definition */
+/** @struct spiBase
+*   @brief SPI Register Definition
+*
+*   This structure is used to access the SPI module registers.
+*/
+/** @typedef spiBASE_t
+*   @brief SPI Register Frame Type Definition
+*
+*   This type is used to access the SPI Registers.
+*/
+typedef volatile struct spiBase
+{
+    uint32  GCR0;                 /**< 0x0000: Global Control 0 */
+    uint32  GCR1;                 /**< 0x0004: Global Control 1 */	
+    uint32  INT0;                 /**< 0x0008: Interrupt Register */	
+    uint32  LVL;                  /**< 0x000C: Interrupt Level */
+    uint32  FLG;                  /**< 0x0010: Interrupt flags */		
+    uint32  PC0;                  /**< 0x0014: Function Pin Enable */
+    uint32  PC1;                  /**< 0x0018: Pin Direction */
+    uint32  PC2;                  /**< 0x001C: Pin Input Latch */
+    uint32  PC3;                  /**< 0x0020: Pin Output Latch */
+    uint32  PC4;                  /**< 0x0024: Output Pin Set */
+    uint32  PC5;                  /**< 0x0028: Output Pin Clr */
+    uint32  PC6;                  /**< 0x002C: Open Drain Output Enable */
+    uint32  PC7;                  /**< 0x0030: Pullup/Pulldown Disable */
+    uint32  PC8;                  /**< 0x0034: Pullup/Pulldown Selection */
+    uint32  DAT0;                 /**< 0x0038: Transmit Data */
+    uint32  DAT1;                 /**< 0x003C: Transmit Data with Format and Chip Select */
+    uint32  BUF;                  /**< 0x0040: Receive Buffer */
+    uint32  EMU;                  /**< 0x0044: Emulation Receive Buffer */
+    uint32  DELAY;                /**< 0x0048: Delays */
+    uint32  DEF;                  /**< 0x004C: Default Chip Select */
+    uint32  FMT0;                 /**< 0x0050: Data Format 0 */
+    uint32  FMT1;                 /**< 0x0054: Data Format 1 */
+    uint32  FMT2;                 /**< 0x0058: Data Format 2 */
+    uint32  FMT3;                 /**< 0x005C: Data Format 3 */
+    uint32  INTVECT0;             /**< 0x0060: Interrupt Vector 0 */
+    uint32  INTVECT1;             /**< 0x0064: Interrupt Vector 1 */
+    uint32  RESERVED[51U];        /**< 0x0068 to 0x0130: Reserved */	
+    uint32  IOLPKTSTCR;           /**< 0x0134: IO loopback */
+} spiBASE_t;
+
+/** @def spiREG1
+*   @brief SPI1 (MIBSPI - Compatibility Mode) Register Frame Pointer
+*
+*   This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG1 ((spiBASE_t *)0xFFF7F400U)
+
+
+/** @def spiPORT1
+*   @brief SPI1 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SPI1
+*   (use the GIO drivers to access the port pins).
+*/
+#define spiPORT1 ((gioPORT_t *)0xFFF7F418U)
+
+/** @def spiREG2
+*   @brief SPI2 Register Frame Pointer
+*
+*   This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG2 ((spiBASE_t *)0xFFF7F600U)
+
+
+/** @def spiPORT2
+*   @brief SPI2 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SPI2
+*   (use the GIO drivers to access the port pins).
+*/
+#define spiPORT2 ((gioPORT_t *)0xFFF7F618U)
+
+/** @def spiREG3
+*   @brief SPI3 (MIBSPI - Compatibility Mode) Register Frame Pointer
+*
+*   This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG3 ((spiBASE_t *)0xFFF7F800U)
+
+
+/** @def spiPORT3
+*   @brief SPI3 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SPI3
+*   (use the GIO drivers to access the port pins).
+*/
+#define spiPORT3 ((gioPORT_t *)0xFFF7F818U)
+
+/** @def spiREG4
+*   @brief SPI4 Register Frame Pointer
+*
+*   This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG4 ((spiBASE_t *)0xFFF7FA00U)
+
+
+/** @def spiPORT4
+*   @brief SPI4 GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SPI4
+*   (use the GIO drivers to access the port pins).
+*/
+#define spiPORT4 ((gioPORT_t *)0xFFF7FA18U)
+
+/** @def spiREG5
+*   @brief SPI5 (MIBSPI - Compatibility Mode) Register Frame Pointer
+*
+*   This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG5 ((spiBASE_t *)0xFFF7FC00U)
+
+
+/** @def spiPORT5
+*   @brief SPI5 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of SPI5
+*   (use the GIO drivers to access the port pins).
+*/
+#define spiPORT5 ((gioPORT_t *)0xFFF7FC18U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_stc.h b/include/arch/rm46l8lp/halcogen/reg_stc.h
new file mode 100644
index 0000000..ab56f8d
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_stc.h
@@ -0,0 +1,93 @@
+/** @file reg_stc.h
+*   @brief STC Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_STC_H__
+#define __REG_STC_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Stc Register Frame Definition */
+/** @struct stcBase
+*   @brief STC Base Register Definition
+*
+*   This structure is used to access the STC module registers.
+*/
+/** @typedef stcBASE_t
+*   @brief STC Register Frame Type Definition
+*
+*   This type is used to access the STC Registers.
+*/
+typedef volatile struct stcBase
+{
+    uint32 STCGCR0;		/**< 0x0000: STC Control Register 0	*/
+    uint32 STCGCR1;		/**< 0x0004: STC Control Register 1 */
+    uint32 STCTPR;		/**< 0x0008: STC Self-Test Run Timeout Counter Preload Register	*/
+    uint32 STCCADDR;		/**< 0x000C: STC Self-Test Current ROM Address Register */
+    uint32 STCCICR;		/**< 0x0010: STC Self-Test Current Interval Count Register */
+    uint32 STCGSTAT;		/**< 0x0014: STC Self-Test Global Status Register */
+	uint32 STCFSTAT;		/**< 0x0018: STC Self-Test Fail Status Register */
+    uint32 CPU1_CURMISR3;	/**< 0x001C: STC CPU1 Current MISR Register */
+    uint32 CPU1_CURMISR2;	/**< 0x0020: STC CPU1 Current MISR Register */
+    uint32 CPU1_CURMISR1;	/**< 0x0024: STC CPU1 Current MISR Register */
+    uint32 CPU1_CURMISR0;	/**< 0x0028: STC CPU1 Current MISR Register */
+    uint32 CPU2_CURMISR3;	/**< 0x002C: STC CPU1 Current MISR Register */
+    uint32 CPU2_CURMISR2;	/**< 0x0030: STC CPU1 Current MISR Register */
+    uint32 CPU2_CURMISR1;	/**< 0x0034: STC CPU1 Current MISR Register */
+    uint32 CPU2_CURMISR0;	/**< 0x0038: STC CPU1 Current MISR Register */
+    uint32 STCSCSCR;		/**< 0x003C: STC Signature Compare Self-Check Register */
+} stcBASE_t;
+
+#define stcREG   ((stcBASE_t *)0xFFFFE600U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_system.h b/include/arch/rm46l8lp/halcogen/reg_system.h
new file mode 100644
index 0000000..772d0ce
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_system.h
@@ -0,0 +1,191 @@
+/** @file reg_system.h
+*   @brief System Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_SYSTEM_H__
+#define __REG_SYSTEM_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+/* System Register Frame 1 Definition */
+/** @struct systemBase1
+*   @brief System Register Frame 1 Definition
+*
+*   This type is used to access the System 1 Registers.
+*/
+/** @typedef systemBASE1_t
+*   @brief System Register Frame 1 Type Definition
+*
+*   This type is used to access the System 1 Registers.
+*/
+typedef volatile struct systemBase1
+{
+    uint32 SYSPC1;                 /* 0x0000 */
+    uint32 SYSPC2;                 /* 0x0004 */
+    uint32 SYSPC3;                 /* 0x0008 */
+    uint32 SYSPC4;                 /* 0x000C */
+    uint32 SYSPC5;                 /* 0x0010 */
+    uint32 SYSPC6;                 /* 0x0014 */
+    uint32 SYSPC7;                 /* 0x0018 */
+    uint32 SYSPC8;                 /* 0x001C */
+    uint32 SYSPC9;                 /* 0x0020 */
+    uint32 SSWPLL1;                /* 0x0024 */
+    uint32 SSWPLL2;                /* 0x0028 */
+    uint32 SSWPLL3;                /* 0x002C */
+    uint32 CSDIS;                  /* 0x0030 */
+    uint32 CSDISSET;               /* 0x0034 */
+    uint32 CSDISCLR;               /* 0x0038 */
+    uint32 CDDIS;                  /* 0x003C */
+    uint32 CDDISSET;               /* 0x0040 */
+    uint32 CDDISCLR;               /* 0x0044 */
+    uint32 GHVSRC;                 /* 0x0048 */
+    uint32 VCLKASRC;               /* 0x004C */
+    uint32 RCLKSRC;                /* 0x0050 */
+    uint32 CSVSTAT;                /* 0x0054 */
+    uint32 MSTGCR;                 /* 0x0058 */
+    uint32 MINITGCR;               /* 0x005C */
+    uint32 MSINENA;                /* 0x0060 */
+    uint32 MSTFAIL;                /* 0x0064 */
+    uint32 MSTCGSTAT;              /* 0x0068 */
+    uint32 MINISTAT;               /* 0x006C */
+    uint32 PLLCTL1;                /* 0x0070 */
+    uint32 PLLCTL2;                /* 0x0074 */
+    uint32 SYSPC10;                /* 0x0078 */
+    uint32 DIEIDL;                 /* 0x007C */
+    uint32 DIEIDH;                 /* 0x0080 */
+    uint32 VRCTL;                  /* 0x0084 */
+    uint32 LPOMONCTL;              /* 0x0088 */
+    uint32 CLKTEST;                /* 0x008C */
+    uint32 DFTCTRLREG1;            /* 0x0090 */
+    uint32 DFTCTRLREG2;            /* 0x0094 */
+    uint32   rsvd1;                /* 0x0098 */
+    uint32   rsvd2;                /* 0x009C */
+    uint32 GPREG1;                 /* 0x00A0 */
+    uint32 BTRMSEL;                /* 0x00A4 */
+    uint32 IMPFASTS;               /* 0x00A8 */
+    uint32 IMPFTADD;               /* 0x00AC */
+    uint32 SSISR1;                 /* 0x00B0 */
+    uint32 SSISR2;                 /* 0x00B4 */
+    uint32 SSISR3;                 /* 0x00B8 */
+    uint32 SSISR4;                 /* 0x00BC */
+    uint32 RAMGCR;                 /* 0x00C0 */
+    uint32 BMMCR1;                 /* 0x00C4 */
+    uint32 BMMCR2;                 /* 0x00C8 */
+    uint32 CPURSTCR;               /* 0x00CC */
+	uint32 CLKCNTL;                /* 0x00D0 */
+    uint32 ECPCNTL;                /* 0x00D4 */
+    uint32 DSPGCR;                 /* 0x00D8 */
+    uint32 DEVCR1;                 /* 0x00DC */
+    uint32 SYSECR;                 /* 0x00E0 */
+    uint32 SYSESR;                 /* 0x00E4 */
+    uint32 SYSTASR;                /* 0x00E8 */
+    uint32 GBLSTAT;                /* 0x00EC */
+    uint32 DEV;                    /* 0x00F0 */
+    uint32 SSIVEC;                 /* 0x00F4 */
+    uint32 SSIF;                   /* 0x00F8 */
+} systemBASE1_t;
+
+
+/** @def systemREG1
+*   @brief System Register Frame 1 Pointer
+*
+*   This pointer is used by the system driver to access the system frame 1 registers.
+*/
+#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)
+
+/** @def systemPORT
+*   @brief ECLK GIO Port Register Pointer
+*
+*   Pointer used by the GIO driver to access I/O PORT of System/Eclk
+*   (use the GIO drivers to access the port pins).
+*/
+#define systemPORT ((gioPORT_t *)0xFFFFFF04U)
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* System Register Frame 2 Definition */
+/** @struct systemBase2
+*   @brief System Register Frame 2 Definition
+*
+*   This type is used to access the System 2 Registers.
+*/
+/** @typedef systemBASE2_t
+*   @brief System Register Frame 2 Type Definition
+*
+*   This type is used to access the System 2 Registers.
+*/
+typedef volatile struct systemBase2
+{
+    uint32 PLLCTL3;        /* 0x0000 */
+    uint32   rsvd1;        /* 0x0004 */
+    uint32 STCCLKDIV;      /* 0x0008 */
+    uint32   rsvd2[6U];     /* 0x000C */
+    uint32 ECPCNTRL0;      /* 0x0024 */
+    uint32   rsvd3[5U];     /* 0x0028 */
+    uint32 CLK2CNTL;       /* 0x003C */	
+    uint32 VCLKACON1;      /* 0x0040 */
+    uint32  rsvd4[11U];     /* 0x0044 */
+    uint32  CLKSLIP;       /* 0x0070 */
+    uint32  rsvd5[30U];   	 /* 0x0074 */
+    uint32  EFC_CTLEN;     /* 0x00EC */
+    uint32  DIEIDL_REG0;   /* 0x00F0 */
+    uint32  DIEIDH_REG1;   /* 0x00F4 */
+    uint32  DIEIDL_REG2;   /* 0x00F8 */
+    uint32  DIEIDH_REG3;   /* 0x00FC */
+} systemBASE2_t;
+
+/** @def systemREG2
+*   @brief System Register Frame 2 Pointer
+*
+*   This pointer is used by the system driver to access the system frame 2 registers.
+*/
+#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_tcram.h b/include/arch/rm46l8lp/halcogen/reg_tcram.h
new file mode 100644
index 0000000..356f35d
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_tcram.h
@@ -0,0 +1,94 @@
+/** @file reg_tcram.h
+*   @brief TCRAM Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_TCRAM_H__
+#define __REG_TCRAM_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/* Tcram Register Frame Definition */
+/** @struct tcramBase
+*   @brief TCRAM Wrapper Register Frame Definition
+*
+*   This type is used to access the TCRAM Wrapper Registers.
+*/
+/** @typedef tcramBASE_t
+*   @brief TCRAM Wrapper Register Frame Type Definition
+*
+*   This type is used to access the TCRAM Wrapper Registers.
+*/
+
+typedef volatile struct tcramBase
+{
+    uint32 RAMCTRL;		    /* 0x0000 */
+    uint32 RAMTHRESHOLD;      /* 0x0004 */
+    uint32 RAMOCCUR;			/* 0x0008 */
+    uint32 RAMINTCTRL;		/* 0x000C */
+    uint32 RAMERRSTATUS;		/* 0x0010 */
+    uint32 RAMSERRADDR;		/* 0x0014 */
+    uint32   rsvd1;			/* 0x0018 */
+    uint32 RAMUERRADDR;		/* 0x001C */
+    uint32   rsvd2[4U];		/* 0x0020 */
+    uint32 RAMTEST;			/* 0x0030 */
+    uint32   rsvd3;			/* 0x0034 */
+    uint32 RAMADDRDECVECT;	/* 0x0038 */
+    uint32 RAMPERADDR;        /* 0x003C */
+} tcramBASE_t;
+
+#define tcram1REG ((tcramBASE_t *)(0xFFFFF800U))
+#define tcram2REG ((tcramBASE_t *)(0xFFFFF900U))
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/reg_vim.h b/include/arch/rm46l8lp/halcogen/reg_vim.h
new file mode 100644
index 0000000..4922efb
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/reg_vim.h
@@ -0,0 +1,110 @@
+/** @file reg_vim.h
+*   @brief VIM Register Layer Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_VIM_H__
+#define __REG_VIM_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Vim Register Frame Definition */
+/** @struct vimBase
+*   @brief Vim Register Frame Definition
+*
+*   This type is used to access the Vim Registers.
+*/
+/** @typedef vimBASE_t
+*   @brief VIM Register Frame Type Definition
+*
+*   This type is used to access the VIM Registers.
+*/
+typedef volatile struct vimBase
+{
+    uint32      IRQINDEX;         /* 0x0000       */
+    uint32      FIQINDEX;         /* 0x0004       */	
+    uint32        rsvd1;          /* 0x0008       */
+    uint32        rsvd2;          /* 0x000C       */
+    uint32      FIRQPR0;          /* 0x0010       */
+    uint32      FIRQPR1;          /* 0x0014       */
+    uint32      FIRQPR2;          /* 0x0018       */
+    uint32      FIRQPR3;          /* 0x001C       */
+    uint32      INTREQ0;          /* 0x0020       */
+    uint32      INTREQ1;          /* 0x0024       */
+    uint32      INTREQ2;          /* 0x0028       */
+    uint32      INTREQ3;          /* 0x002C       */
+    uint32      REQMASKSET0;      /* 0x0030       */
+    uint32      REQMASKSET1;      /* 0x0034       */
+    uint32      REQMASKSET2;      /* 0x0038       */
+    uint32      REQMASKSET3;      /* 0x003C       */
+    uint32      REQMASKCLR0;      /* 0x0040       */
+    uint32      REQMASKCLR1;      /* 0x0044       */
+    uint32      REQMASKCLR2;      /* 0x0048       */
+    uint32      REQMASKCLR3;      /* 0x004C       */
+    uint32      WAKEMASKSET0;     /* 0x0050       */
+    uint32      WAKEMASKSET1;     /* 0x0054       */
+    uint32      WAKEMASKSET2;     /* 0x0058       */
+    uint32      WAKEMASKSET3;     /* 0x005C       */
+    uint32      WAKEMASKCLR0;     /* 0x0060       */
+    uint32      WAKEMASKCLR1;     /* 0x0064       */
+    uint32      WAKEMASKCLR2;     /* 0x0068       */
+    uint32      WAKEMASKCLR3;     /* 0x006C       */
+    uint32      IRQVECREG;        /* 0x0070       */
+    uint32      FIQVECREG;        /* 0x0074       */
+    uint32      CAPEVT;           /* 0x0078       */	
+    uint32        rsvd3;          /* 0x007C       */
+    uint32      CHANCTRL[32U];    /* 0x0080-0x0FC */
+} vimBASE_t;
+
+#define vimREG ((vimBASE_t *)0xFFFFFE00U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/rti.h b/include/arch/rm46l8lp/halcogen/rti.h
new file mode 100644
index 0000000..279a8f8
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/rti.h
@@ -0,0 +1,326 @@
+/** @file rti.h
+*   @brief RTI Driver Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   - Interface Prototypes
+*   .
+*   which are relevant for the RTI driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __RTI_H__
+#define __RTI_H__
+
+#include "reg_rti.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* RTI General Definitions */
+
+/** @def rtiCOUNTER_BLOCK0
+*   @brief Alias name for RTI counter block 0
+*
+*   This is an alias name for the RTI counter block 0.
+*
+*   @note This value should be used for API argument @a counter
+*/
+#define rtiCOUNTER_BLOCK0 0U
+
+/** @def rtiCOUNTER_BLOCK1
+*   @brief Alias name for RTI counter block 1
+*
+*   This is an alias name for the RTI counter block 1.
+*
+*   @note This value should be used for API argument @a counter
+*/
+#define rtiCOUNTER_BLOCK1 1U
+
+/** @def rtiCOMPARE0
+*   @brief Alias name for RTI compare 0
+*
+*   This is an alias name for the RTI compare 0.
+*
+*   @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE0 0U
+
+/** @def rtiCOMPARE1
+*   @brief Alias name for RTI compare 1
+*
+*   This is an alias name for the RTI compare 1.
+*
+*   @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE1 1U
+
+/** @def rtiCOMPARE2
+*   @brief Alias name for RTI compare 2
+*
+*   This is an alias name for the RTI compare 2.
+*
+*   @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE2 2U
+
+/** @def rtiCOMPARE3
+*   @brief Alias name for RTI compare 3
+*
+*   This is an alias name for the RTI compare 3.
+*
+*   @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE3 3U
+
+/** @def rtiNOTIFICATION_COMPARE0
+*   @brief Alias name for RTI compare 0 notification
+*
+*   This is an alias name for the RTI compare 0 notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE0 1U
+
+/** @def rtiNOTIFICATION_COMPARE1
+*   @brief Alias name for RTI compare 1 notification
+*
+*   This is an alias name for the RTI compare 1 notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE1 2U
+
+/** @def rtiNOTIFICATION_COMPARE2
+*   @brief Alias name for RTI compare 2 notification
+*
+*   This is an alias name for the RTI compare 2 notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE2 4U
+
+/** @def rtiNOTIFICATION_COMPARE3
+*   @brief Alias name for RTI compare 3 notification
+*
+*   This is an alias name for the RTI compare 3 notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE3 8U
+
+/** @def rtiNOTIFICATION_TIMEBASE
+*   @brief Alias name for RTI timebase notification
+*
+*   This is an alias name for the RTI timebase notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_TIMEBASE 0x10000U
+
+/** @def rtiNOTIFICATION_COUNTER0
+*   @brief Alias name for RTI counter block 0 overflow notification
+*
+*   This is an alias name for the RTI counter block 0 overflow notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COUNTER0 0x20000U
+
+/** @def rtiNOTIFICATION_COUNTER1
+*   @brief Alias name for RTI counter block 1 overflow notification
+*
+*   This is an alias name for the RTI counter block 1 overflow notification.
+*
+*   @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COUNTER1 0x40000U
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @enum dwdViolationTag
+*   @brief DWD Violations
+*/
+typedef enum dwdViolationTag
+{
+	NoTime_Violation = 0U,
+	Time_Window_Violation = 1U,
+	EndTime_Window_Violation = 2U,
+	StartTime_Window_Violation = 3U,
+	Key_Seq_Violation = 4U
+}dwdViolation_t;
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/** @enum dwdResetStatusTag
+*   @brief DWD Reset status
+*/
+typedef enum dwdResetStatusTag
+{
+	No_Reset_Generated = 0U,
+	Reset_Generated    = 1U
+}dwdResetStatus_t;
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+/** @enum dwwdReactionTag
+*   @brief DWWD Reaction on vioaltion
+*/
+typedef enum dwwdReactionTag
+{
+	Generate_Reset = 0x00000005U,
+	Generate_NMI   = 0x0000000AU
+}dwwdReaction_t;
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+/** @enum dwwdWindowSizeTag
+*   @brief DWWD Window size
+*/
+typedef enum dwwdWindowSizeTag
+{
+	Size_100_Percent   = 0x00000005U,
+	Size_50_Percent    = 0x00000050U,
+	Size_25_Percent    = 0x00000500U,
+	Size_12_5_Percent  = 0x00005000U,
+	Size_6_25_Percent  = 0x00050000U,
+	Size_3_125_Percent = 0x00500000U
+}dwwdWindowSize_t;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+/* Configuration registers */
+typedef struct rti_config_reg
+{
+    uint32 CONFIG_GCTRL;
+    uint32 CONFIG_TBCTRL;
+    uint32 CONFIG_CAPCTRL;
+    uint32 CONFIG_COMPCTRL;
+    uint32 CONFIG_UDCP0;
+    uint32 CONFIG_UDCP1;
+    uint32 CONFIG_UDCP2;
+    uint32 CONFIG_UDCP3;
+} rti_config_reg_t;
+
+
+/* Configuration registers initial value */
+#define RTI_GCTRL_CONFIGVALUE	 ((uint32)((uint32)0x0U << 16U) | 0x00000000U)
+#define RTI_TBCTRL_CONFIGVALUE   0x00000000U
+#define RTI_CAPCTRL_CONFIGVALUE  (0U | 0U)
+#define RTI_COMPCTRL_CONFIGVALUE (0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U)
+#define RTI_UDCP0_CONFIGVALUE    50000U
+#define RTI_UDCP1_CONFIGVALUE    50000000U
+#define RTI_UDCP2_CONFIGVALUE    5000000U
+#define RTI_UDCP3_CONFIGVALUE    50000000U
+
+
+/** 
+ *  @defgroup RTI RTI
+ *  @brief Real Time Interrupt Module.
+ *  
+ *  The real-time interrupt (RTI) module provides timer functionality for operating systems and for
+ *  benchmarking code. The RTI module can incorporate several counters that define the timebases needed
+ *  for scheduling in the operating system.
+ *
+ *	Related Files
+ *   - reg_rti.h
+ *   - rti.h
+ *   - rti.c
+ *  @addtogroup RTI
+ *  @{
+ */
+ 
+/* RTI Interface Functions */
+
+void rtiInit(void);
+void rtiStartCounter(uint32 counter);
+void rtiStopCounter(uint32 counter);
+uint32 rtiResetCounter(uint32 counter);
+void rtiSetPeriod(uint32 compare, uint32 period);
+uint32 rtiGetPeriod(uint32 compare);
+uint32 rtiGetCurrentTick(uint32 compare);
+void rtiEnableNotification(uint32 notification);
+void rtiDisableNotification(uint32 notification);
+void dwdInit(uint16 dwdPreload);
+void dwwdInit(dwwdReaction_t Reaction, uint16 dwdPreload, dwwdWindowSize_t Window_Size);
+uint32 dwwdGetCurrentDownCounter(void);
+void dwdCounterEnable(void);
+void dwdSetPreload(uint16 dwdPreload);
+void dwdReset(void);
+void dwdGenerateSysReset(void);
+boolean IsdwdKeySequenceCorrect(void);
+dwdResetStatus_t dwdGetStatus(void);
+dwdViolation_t dwdGetViolationStatus(void);
+void dwdClearFlag(void);
+void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type);
+/** @fn void rtiNotification(uint32 notification)
+*   @brief Notification of RTI module
+*   @param[in] notification Select notification of RTI module:
+*              - rtiNOTIFICATION_COMPARE0: RTI compare 0 notification
+*              - rtiNOTIFICATION_COMPARE1: RTI compare 1 notification
+*              - rtiNOTIFICATION_COMPARE2: RTI compare 2 notification
+*              - rtiNOTIFICATION_COMPARE3: RTI compare 3 notification
+*              - rtiNOTIFICATION_TIMEBASE: RTI Timebase notification
+*              - rtiNOTIFICATION_COUNTER0: RTI counter 0 overflow notification
+*              - rtiNOTIFICATION_COUNTER1: RTI counter 1 overflow notification
+*
+*   @note This function has to be provide by the user.
+*/
+void rtiNotification(uint32 notification);
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/sci.h b/include/arch/rm46l8lp/halcogen/sci.h
new file mode 100644
index 0000000..6853ec1
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/sci.h
@@ -0,0 +1,203 @@
+/** @file sci.h
+*   @brief SCI Driver Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __SCI_H__
+#define __SCI_H__
+
+#include "reg_sci.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @enum sciIntFlags
+*   @brief Interrupt Flag Definitions
+*
+*   Used with sciEnableNotification, sciDisableNotification
+*/
+enum sciIntFlags
+{
+    SCI_FE_INT    = 0x04000000U,  /* framing error */
+    SCI_OE_INT    = 0x02000000U,  /* overrun error */
+    SCI_PE_INT    = 0x01000000U,  /* parity error */
+    SCI_RX_INT    = 0x00000200U,  /* receive buffer ready */
+    SCI_TX_INT    = 0x00000100U,  /* transmit buffer ready */
+    SCI_WAKE_INT  = 0x00000002U,  /* wakeup */
+    SCI_BREAK_INT = 0x00000001U   /* break detect */
+};
+
+/** @def SCI_IDLE
+*   @brief Alias name for the SCI IDLE Flag
+*
+*   This is an alias name for the SCI IDLE Flag.
+*
+*/
+#define SCI_IDLE 0x00000004U
+
+/** @struct sciBase
+*   @brief SCI Register Definition
+*
+*   This structure is used to access the SCI module registers.
+*/
+/** @typedef sciBASE_t
+*   @brief SCI Register Frame Type Definition
+*
+*   This type is used to access the SCI Registers.
+*/
+
+enum sciPinSelect
+{
+    PIN_SCI_TX = 4U,
+    PIN_SCI_RX = 2U
+};
+
+
+/* Configuration registers */
+typedef struct sci_config_reg
+{
+    uint32 CONFIG_GCR0;
+    uint32 CONFIG_GCR1;
+    uint32 CONFIG_SETINT;
+    uint32 CONFIG_SETINTLVL;
+    uint32 CONFIG_FORMAT;
+    uint32 CONFIG_BRS;
+    uint32 CONFIG_PIO0;
+    uint32 CONFIG_PIO1;
+    uint32 CONFIG_PIO6;
+    uint32 CONFIG_PIO7;	
+	uint32 CONFIG_PIO8;
+} sci_config_reg_t;
+
+
+
+/* Configuration registers initial value for SCI*/
+#define SCILIN_GCR0_CONFIGVALUE       0x00000001U   
+#define SCILIN_GCR1_CONFIGVALUE       ((uint32)((uint32)1U << 5U) \
+                                      |(uint32)((uint32)(2U-1U) << 4U) \
+                                      |(uint32)((uint32)0U << 3U) \
+                                      |(uint32)((uint32)0U << 2U) \
+                                      |(uint32)((uint32)1U << 1U) \
+                                      |(uint32)((uint32)0U << 2U) \
+                                      |(uint32)(0x03000080U))
+									  
+#define SCILIN_SETINTLVL_CONFIGVALUE  ((uint32)((uint32)0U << 26U) \
+                                      |(uint32)((uint32)0U << 25U) \
+                                      |(uint32)((uint32)0U << 24U) \
+                                      |(uint32)((uint32)0U << 9U) \
+                                      |(uint32)((uint32)0U << 8U) \
+                                      |(uint32)((uint32)0U << 1U) \
+                                      |(uint32)((uint32)0U))
+
+#define SCILIN_SETINT_CONFIGVALUE     ((uint32)((uint32)0U << 26U) \
+                                      |(uint32)((uint32)0U << 25U) \
+                                      |(uint32)((uint32)0U << 24U) \
+                                      |(uint32)((uint32)0U << 9U) \
+                                      |(uint32)((uint32)0U << 1U) \
+                                      |(uint32)((uint32)0U << 0U))
+
+#define SCILIN_FORMAT_CONFIGVALUE     (8U - 1U)
+#define SCILIN_BRS_CONFIGVALUE        (259U)
+#define SCILIN_PIO0_CONFIGVALUE       ((uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 1U))
+#define SCILIN_PIO1_CONFIGVALUE       ((uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U))
+#define SCILIN_PIO6_CONFIGVALUE       ((uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U))
+#define SCILIN_PIO7_CONFIGVALUE       ((uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U))
+#define SCILIN_PIO8_CONFIGVALUE       ((uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 1U))
+ 
+
+
+/** 
+ *  @defgroup SCI SCI
+ *  @brief Serial Communication Interface Module.
+ *  
+ *  The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn
+ *  to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-line.
+ *
+ *	Related Files
+ *   - reg_sci.h
+ *   - sci.h
+ *   - sci.c
+ *  @addtogroup SCI
+ *  @{
+ */
+ 
+/* SCI Interface Functions */
+void sciInit(void);
+void sciSetFunctional(sciBASE_t *sci, uint32 port);
+void sciSetBaudrate(sciBASE_t *sci, uint32 baud);
+uint32  sciIsTxReady(sciBASE_t *sci);
+void sciSendByte(sciBASE_t *sci, uint8 byte);
+void sciSend(sciBASE_t *sci, uint32 length, uint8 * data);
+uint32  sciIsRxReady(sciBASE_t *sci);
+uint32  sciIsIdleDetected(sciBASE_t *sci);
+uint32  sciRxError(sciBASE_t *sci);
+uint32  sciReceiveByte(sciBASE_t *sci);
+void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data);
+void sciEnableNotification(sciBASE_t *sci, uint32 flags);
+void sciDisableNotification(sciBASE_t *sci, uint32 flags);
+void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype);
+void sciDisableLoopback(sciBASE_t *sci);
+void sciEnterResetState(sciBASE_t *sci);
+void sciExitResetState(sciBASE_t *sci);
+void scilinGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type);
+/** @fn void sciNotification(sciBASE_t *sci, uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] sci   - sci module base address
+*   @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt.  The parameter passed to the callback is a copy of the 
+* interrupt flag register.
+*/
+void sciNotification(sciBASE_t *sci, uint32 flags);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/spi.h b/include/arch/rm46l8lp/halcogen/spi.h
new file mode 100644
index 0000000..0dc9dab
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/spi.h
@@ -0,0 +1,222 @@
+/** @file spi.h
+*   @brief SPI Driver Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SPI_H__
+#define __SPI_H__
+
+#include "reg_spi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @enum chipSelect
+*   @brief Transfer Group Chip Select
+*/
+enum spiChipSelect
+{
+    SPI_CS_NONE = 0xFFU,
+    SPI_CS_0    = 0xFEU,
+    SPI_CS_1    = 0xFDU,
+    SPI_CS_2    = 0xFBU,
+    SPI_CS_3    = 0xF7U,
+    SPI_CS_4    = 0xEFU,
+    SPI_CS_5    = 0xDFU,
+    SPI_CS_6    = 0xBFU,
+    SPI_CS_7    = 0x7FU
+};
+
+/** @enum spiPinSelect
+*   @brief spi Pin Select
+*/
+enum spiPinSelect
+{
+    SPI_PIN_CS0    = 0U,
+    SPI_PIN_CS1    = 1U,
+    SPI_PIN_CS2    = 2U,
+    SPI_PIN_CS3    = 3U,
+    SPI_PIN_CS4    = 4U,
+    SPI_PIN_CS5    = 5U,
+    SPI_PIN_CS6    = 6U,
+    SPI_PIN_CS7    = 7U,
+    SPI_PIN_ENA    = 8U,
+    SPI_PIN_CLK    = 9U,
+    SPI_PIN_SIMO   = 10U,
+    SPI_PIN_SOMI   = 11U,
+    SPI_PIN_SIMO_1 = 17U,
+    SPI_PIN_SIMO_2 = 18U,
+    SPI_PIN_SIMO_3 = 19U,
+    SPI_PIN_SIMO_4 = 20U,
+    SPI_PIN_SIMO_5 = 21U,
+    SPI_PIN_SIMO_6 = 22U,
+    SPI_PIN_SIMO_7 = 23U,
+    SPI_PIN_SOMI_1 = 25U,
+    SPI_PIN_SOMI_2 = 26U,
+    SPI_PIN_SOMI_3 = 27U,
+    SPI_PIN_SOMI_4 = 28U,
+    SPI_PIN_SOMI_5 = 29U,
+    SPI_PIN_SOMI_6 = 30U,
+    SPI_PIN_SOMI_7 = 31U
+};
+
+/** @enum dataformat
+*   @brief SPI dataformat register select
+*/
+typedef enum dataformat
+{
+    SPI_FMT_0 = 0U,
+    SPI_FMT_1 = 1U,
+    SPI_FMT_2 = 2U,
+    SPI_FMT_3 = 3U
+}SPIDATAFMT_t;
+
+/** @struct spiDAT1RegConfig
+*   @brief SPI data register configuration
+*/
+typedef struct spiDAT1RegConfig
+{
+    boolean CS_HOLD;
+    boolean WDEL;
+    SPIDATAFMT_t DFSEL;
+    uint8 CSNR;
+}spiDAT1_t;
+
+/** @enum SpiTxRxDataStatus
+*   @brief SPI Data Status
+*/
+typedef enum SpiTxRxDataStatus
+{
+    SPI_READY = 0U,
+    SPI_PENDING = 1U,
+    SPI_COMPLETED = 2U
+}SpiDataStatus_t;
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+typedef struct spi_config_reg
+{
+    uint32 CONFIG_GCR1;
+    uint32 CONFIG_INT0;
+    uint32 CONFIG_LVL;
+    uint32 CONFIG_PC0;
+    uint32 CONFIG_PC1;
+    uint32 CONFIG_PC6;
+    uint32 CONFIG_PC7;
+    uint32 CONFIG_PC8;
+    uint32 CONFIG_DELAY;
+    uint32 CONFIG_FMT0;
+    uint32 CONFIG_FMT1;
+    uint32 CONFIG_FMT2;
+    uint32 CONFIG_FMT3;
+}spi_config_reg_t;
+
+
+
+
+
+
+
+
+
+
+/**
+ *  @defgroup SPI SPI
+ *  @brief Serial Peripheral Interface Module.
+ *
+ *  SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
+ *  programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
+ *
+ *    Related Files
+ *   - reg_spi.h
+ *   - spi.h
+ *   - spi.c
+ *  @addtogroup SPI
+ *  @{
+ */
+
+/* SPI Interface Functions */
+void spiInit(void);
+void spiSetFunctional(spiBASE_t *spi, uint32 port);
+void spiEnableNotification(spiBASE_t *spi, uint32 flags);
+void spiDisableNotification(spiBASE_t *spi, uint32 flags);
+uint32 spiTransmitData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff);
+void spiSendData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff);
+uint32 spiReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * destbuff);
+void spiGetData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * destbuff);
+uint32 spiTransmitAndReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff, uint16 * destbuff);
+void spiSendAndGetData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff, uint16 * destbuff);
+void spiEnableLoopback(spiBASE_t *spi, loopBackType_t Loopbacktype);
+void spiDisableLoopback(spiBASE_t *spi);
+SpiDataStatus_t SpiTxStatus(spiBASE_t *spi);
+SpiDataStatus_t SpiRxStatus(spiBASE_t *spi);
+
+/** @fn void spiNotification(spiBASE_t *spi, uint32 flags)
+*   @brief Interrupt callback
+*   @param[in] spi   - Spi module base address
+*   @param[in] flags - Copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt.  The parameter passed to the callback is a copy of the
+* interrupt flag register.
+*/
+void spiNotification(spiBASE_t *spi, uint32 flags);
+
+/** @fn void spiEndNotification(spiBASE_t *spi)
+*   @brief Interrupt callback for End of TX or RX data length.
+*   @param[in] spi   - Spi module base address
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt at the End of TX or RX data length.
+*/
+void spiEndNotification(spiBASE_t *spi);
+
+/**@}*/
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/std_nhet.h b/include/arch/rm46l8lp/halcogen/std_nhet.h
new file mode 100644
index 0000000..3d7ae2d
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/std_nhet.h
@@ -0,0 +1,2499 @@
+/** @file std_nhet.h
+*   @brief NHET Instruction Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef __STD_NHET_H__
+#define __STD_NHET_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifndef HET_v2
+#   define HET_v2 0
+#endif
+
+#if ((__little_endian__ == 0) || (__LITTLE_ENDIAN__ == 0) || defined(_TMS470_BIG) || defined(__big_endian__))
+
+#ifndef HETBYTE
+#   define HETBYTE uint8
+#endif
+
+typedef struct memory_format
+{
+  uint32 program_word  ;
+  uint32 control_word  ;
+  uint32 data_word     ;
+  uint32 reserved_word ;
+} HET_MEMORY  ;
+
+/*---------------------------------------------*/
+/* ACMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct acmp_format
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 9 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 coutprv              : 1 ;
+  uint32                      : 2 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32 ext_reg              : 1 ;
+  uint32                      : 2 ; 
+  uint32 pin_action           : 1 ;
+  uint32                      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  uint32 data                 : 25 ;
+  uint32                      : 7  ;
+ 
+} ACMP_FIELDS;
+ 
+typedef union
+{
+  ACMP_FIELDS  acmp   ;
+  HET_MEMORY   memory ;
+} ACMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct ecmp_format   
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;          
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32 hr_lr                : 1 ;
+  uint32 angle_compare        : 1 ;
+  uint32                      : 7 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 sub_opcode           : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+
+} ECMP_FIELDS;
+
+typedef union 
+{
+  ECMP_FIELDS  ecmp   ;
+  HET_MEMORY   memory ;
+} ECMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct scmp_format     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;          
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32                      : 2 ;
+  uint32                      : 2 ;
+  uint32                      : 5 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 coutprv              : 1 ;
+  uint32                      : 2 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32                      : 2 ;
+  uint32 restart_en           : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} SCMP_FIELDS ;
+
+typedef union 
+{
+  SCMP_FIELDS  scmp   ;
+  HET_MEMORY   memory ;
+} SCMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MCMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct mcmp_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 hr_lr                : 1 ;
+  uint32 angle_compare        : 1 ;
+  uint32                      : 1 ;
+  uint32 save_subtract        : 1 ;
+  uint32                      : 5 ;
+ 
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 sub_opcode           : 1 ; 
+  uint32 order                : 1 ; 
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} MCMP_FIELDS ; 
+
+typedef union 
+{
+  MCMP_FIELDS  mcmp   ;
+  HET_MEMORY   memory ;
+} MCMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MOV64 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct mov64_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+
+} MOV64_FIELDS ; 
+
+typedef union 
+{
+  MOV64_FIELDS  mov64  ;
+  HET_MEMORY    memory ;
+} MOV64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DADM64 INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct dadm64_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} DADM64_FIELDS ; 
+
+typedef union 
+{
+  DADM64_FIELDS  dadm64 ;
+  HET_MEMORY     memory ;
+} DADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* RADM64 INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct RADM64_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} RADM64_FIELDS ; 
+
+
+typedef union 
+{
+  RADM64_FIELDS  radm64 ;
+  HET_MEMORY     memory ;
+} RADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MOV32 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct MOV32_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 z_flag               : 1 ;
+  uint32                      : 15 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode           : 1 ;   
+  uint32 move_type            : 2 ;     
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} MOV32_FIELDS ; 
+
+
+typedef union 
+{
+  MOV32_FIELDS  mov32  ;
+  HET_MEMORY    memory ;
+} MOV32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADM32 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct ADM32_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 19 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode           : 1 ;
+  uint32 move_type            : 2 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} ADM32_FIELDS ; 
+
+
+typedef union 
+{
+  ADM32_FIELDS  adm32  ;
+  HET_MEMORY    memory ;
+} ADM32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADCNST INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct ADCNST_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1 ;  /* pk */
+  uint32                      : 1 ;
+  uint32 constant             : 25 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} ADCNST_FIELDS ;
+
+
+typedef union 
+{
+  ADCNST_FIELDS  adcnst ;
+  HET_MEMORY     memory ;
+} ADCNST_INSTRUCTION;
+
+
+/*----------------------------------------------*/
+/* ADD INSTRUCTION				  	*/
+/*----------------------------------------------*/
+
+typedef struct ADD_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} ADD_FIELDS ;
+
+
+typedef union 
+{
+  ADD_FIELDS  add ;
+  HET_MEMORY  memory ;
+} ADD_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* ADC INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct ADC_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} ADC_FIELDS ;
+
+
+typedef union 
+{
+  ADC_FIELDS  adc ;
+  HET_MEMORY  memory ;
+} ADC_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* SUB INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct SUB_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} SUB_FIELDS ;
+
+
+typedef union 
+{
+  SUB_FIELDS  sub ;
+  HET_MEMORY  memory ;
+} SUB_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* SBB INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct SBB_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} SBB_FIELDS ;
+
+
+typedef union 
+{
+  SBB_FIELDS  sbb ;
+  HET_MEMORY  memory ;
+} SBB_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* AND INSTRUCTION				      */
+/*----------------------------------------------*/
+
+typedef struct AND_format
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} AND_FIELDS ;
+
+
+typedef union 
+{
+#ifdef __cplusplus
+  AND_FIELDS  and_cpp ;
+#else
+  AND_FIELDS  and ;
+#endif
+  HET_MEMORY  memory ;
+} AND_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* OR INSTRUCTION					      */
+/*----------------------------------------------*/
+
+
+typedef struct OR_format
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} OR_FIELDS ;
+
+
+typedef union 
+{
+#ifdef __cplusplus
+  OR_FIELDS  or_cpp ;
+#else
+  OR_FIELDS  or ;
+#endif
+  HET_MEMORY  memory ;
+} OR_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* XOR INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct XOR_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 remote_address       : 9 ;
+ 
+  uint32                      : 5 ;
+  uint32 control              : 1;
+  uint32 sub_opcode3          : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 src_2                : 3 ;
+  uint32 shft_mode            : 3 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 reg_ext              : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 rem_dest             : 2 ;
+  uint32 reg	                : 2 ;
+  uint32                      : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} XOR_FIELDS ;
+
+
+typedef union 
+{
+#ifdef __cplusplus
+  XOR_FIELDS  xor_cpp ;
+#else
+  XOR_FIELDS  xor ;
+#endif
+  HET_MEMORY  memory ;
+} XOR_INSTRUCTION;
+
+
+
+/*---------------------------------------------*/
+/* CNT INSTRUCTION                             */
+/*---------------------------------------------*/
+typedef struct CNT_format                     
+{
+  uint32                      : 9 ;        
+  uint32 brk                  : 1 ;          
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32 angle_cnt            : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32                      : 4 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 1 ;
+  uint32 max                  : 25 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} CNT_FIELDS ; 
+
+typedef union 
+{
+  CNT_FIELDS   cnt    ; 
+  HET_MEMORY   memory ;
+} CNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* APCNT INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct apcnt_format
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 interrupt_enable     : 1 ;
+  uint32 edge_select          : 2 ;
+  uint32                      : 6 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32 count                : 25 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+ 
+} APCNT_FIELDS ;
+ 
+typedef union
+{
+  APCNT_FIELDS  apcnt   ;
+  HET_MEMORY   memory ;
+} APCNT_INSTRUCTION;
+ 
+ 
+
+/*---------------------------------------------*/
+/* PCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct pcnt_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;          
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32 interrupt_enable     : 1 ;
+  uint32 period_pulse_select  : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32 count                : 25 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+
+} PCNT_FIELDS ;      
+
+typedef union 
+{
+  PCNT_FIELDS  pcnt   ; 
+  HET_MEMORY   memory ;
+} PCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct scnt_format                     
+{
+  uint32                      : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 1 ;
+  uint32 count_mode           : 2 ;
+  uint32 step_width           : 2 ;
+  uint32                      : 4 ;
+
+  uint32                      : 5 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 1 ;
+  uint32 gap_start            : 25 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} SCNT_FIELDS ;      
+
+typedef union 
+{
+  SCNT_FIELDS  scnt   ; 
+  HET_MEMORY   memory ;
+} SCNT_INSTRUCTION;
+
+
+
+/*---------------------------------------------*/
+/* ACNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct acnt_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32 edge_select          : 1 ;
+  uint32                      : 7 ;
+  uint32 interrupt_enable     : 1 ; 
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32 gap_end              : 25 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} ACNT_FIELDS ;      
+
+typedef union 
+{
+  ACNT_FIELDS  acnt   ; 
+  HET_MEMORY   memory ;
+} ACNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct ecnt_format
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 1 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 6 ;
+ 
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32                      : 3 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 count_cond           : 3 ;
+  uint32                      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+ 
+} ECNT_FIELDS ;
+ 
+typedef union
+{
+  ECNT_FIELDS  ecnt   ;
+  HET_MEMORY   memory ;
+} ECNT_INSTRUCTION;
+
+
+
+/*---------------------------------------------*/
+/* RCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct rcnt_format
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 1 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 5 ;
+  uint32 count_mode1          : 1 ;
+ 
+  uint32                      : 3 ;
+  uint32                      : 2 ;
+  uint32 control              : 1 ;
+  uint32                      : 1 ;
+  uint32 divisor              : 25 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+ 
+} RCNT_FIELDS ;
+ 
+typedef union
+{
+  RCNT_FIELDS  rcnt   ;
+  HET_MEMORY   memory ;
+} RCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJNZ INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct djnz_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32                      : 1 ;
+  uint32 sub_opcode           : 2 ;
+  uint32                      : 6 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 4 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 10 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} DJNZ_FIELDS ;      
+
+typedef union 
+{
+  DJNZ_FIELDS  djnz   ; 
+  HET_MEMORY   memory ;
+} DJNZ_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJZ INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct djz_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;          
+  uint32 op_code              : 4 ;
+  uint32                      : 1 ;
+  uint32 sub_opcode           : 2 ;
+  uint32                      : 6 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 4 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 10 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} DJZ_FIELDS ;      
+
+typedef union 
+{
+  DJZ_FIELDS  djz   ; 
+  HET_MEMORY   memory ;
+} DJZ_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* PWCNT INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct pwcnt_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 hr_lr                : 1 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 6 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 3 ;
+  uint32 en_pin_action        : 1 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 3 ;
+  uint32 pin_action           : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} PWCNT_FIELDS ;      
+
+typedef union 
+{
+  PWCNT_FIELDS  pwcnt ;
+  HET_MEMORY   memory ;
+} PWCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* WCAP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct wcap_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 hr_lr                : 1 ;
+  uint32                      : 8 ;
+  
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32                      : 3 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 capture_condition    : 2 ;
+  uint32                      : 2 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+
+} WCAP_FIELDS ;      
+
+typedef union 
+{
+  WCAP_FIELDS  wcap   ; 
+  HET_MEMORY   memory ;
+} WCAP_INSTRUCTION;
+ 
+/*----------------------------------------------*/
+/* WCAPE INSTRUCTION                            */
+/*----------------------------------------------*/
+typedef struct wcape_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 9 ;
+  
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32                      : 3 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 capture_condition    : 2 ;
+  uint32                      : 2 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 ts_data              : 25 ;
+  uint32 ec_data              : 7 ;
+
+} WCAPE_FIELDS ;      
+
+typedef union 
+{
+  WCAPE_FIELDS  wcape   ; 
+  HET_MEMORY   memory ;
+} WCAPE_INSTRUCTION;
+ 
+
+/*---------------------------------------------*/
+/* BR   INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct br_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 9 ;
+
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32                      : 3 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+
+#if HET_v2
+  uint32 branch_condition     : 5 ;
+#else 
+  uint32 branch_condition     : 3 ;
+  uint32                      : 1 ;
+  uint32                      : 1 ;
+#endif 
+
+  uint32                      : 2 ;
+  uint32 interrupt_enable     : 1 ;
+ 
+  
+  uint32 data                 : 25 ;
+  uint32 hr_data              : 7 ;
+ 
+} BR_FIELDS ;      
+
+typedef union 
+{
+  BR_FIELDS  br     ; 
+  HET_MEMORY memory ;
+} BR_INSTRUCTION;
+
+ 
+/*---------------------------------------------*/
+/* SHFT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct shft_format                     
+{
+  uint32                      : 6 ;
+  uint32 reqnum               : 3 ;
+  uint32 brk                  : 1 ;
+  uint32 next_program_address : 9 ;
+  uint32 op_code              : 4 ;
+  uint32                      : 5 ;
+  uint32 shift_mode           : 4 ;
+ 
+  uint32                      : 3 ;
+  uint32 request              : 2 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 previous_bit         : 1 ;
+  uint32                      : 3 ;
+  uint32 cond_addr            : 9 ;
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 shift_condition      : 2 ;
+  uint32                      : 2 ;
+  uint32 t_register_select    : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 interrupt_enable     : 1 ;
+
+  
+  uint32 data                 : 25 ;
+  uint32                      : 7 ;
+
+} SHFT_FIELDS ;      
+
+typedef union 
+{
+  SHFT_FIELDS  shft   ; 
+  HET_MEMORY   memory ;
+} SHFT_INSTRUCTION;
+
+/* ---------------------------------------------------------------------------------------------------- */
+
+#else
+
+#ifndef HETBYTE
+#   define HETBYTE uint8
+#endif
+
+typedef struct memory_format
+{
+  uint32 program_word  ;
+  uint32 control_word  ;
+  uint32 data_word     ;
+  uint32 reserved_word ;
+} HET_MEMORY  ;
+ 
+/*---------------------------------------------*/
+/* ACMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct acmp_format
+{
+  uint32                      : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32                      : 3 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ; 
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 2 ;
+  uint32 coutprv              : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+
+  uint32                      : 7  ;
+  uint32 data                 : 25 ;
+ 
+} ACMP_FIELDS;
+ 
+typedef union
+{
+  ACMP_FIELDS  acmp   ;
+  HET_MEMORY   memory ;
+} ACMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct ecmp_format   
+{
+  uint32                      : 7 ;
+  uint32 angle_compare        : 1 ;
+  uint32 hr_lr                : 1 ;         
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ; 
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32 sub_opcode           : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ; 
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+
+} ECMP_FIELDS;
+
+typedef union 
+{
+  ECMP_FIELDS  ecmp   ;
+  HET_MEMORY   memory ;
+} ECMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct scmp_format     
+{
+  uint32                      : 5 ;
+  uint32                      : 2 ;
+  uint32                      : 2 ;         
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ; 
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 restart_en           : 1 ;
+  uint32                      : 2 ;
+  uint32 pin_action           : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 2 ;
+  uint32 coutprv              : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} SCMP_FIELDS ;
+
+typedef union 
+{
+  SCMP_FIELDS  scmp   ;
+  HET_MEMORY   memory ;
+} SCMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MCMP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct mcmp_format                     
+{
+  uint32                      : 5 ;
+  uint32 save_subtract        : 1 ;
+  uint32                      : 1 ;
+  uint32 angle_compare        : 1 ;
+  uint32 hr_lr                : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+ 
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32 order                : 1 ; 
+  uint32 sub_opcode           : 1 ;  
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+ 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ; 
+
+} MCMP_FIELDS ; 
+
+typedef union 
+{
+  MCMP_FIELDS  mcmp   ;
+  HET_MEMORY   memory ;
+} MCMP_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* MOV64 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct mov64_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;          
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+
+} MOV64_FIELDS ; 
+
+typedef union 
+{
+  MOV64_FIELDS  mov64  ;
+  HET_MEMORY    memory ;
+} MOV64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DADM64 INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct dadm64_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ; 
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+ 
+} DADM64_FIELDS ; 
+
+typedef union 
+{
+  DADM64_FIELDS  dadm64 ;
+  HET_MEMORY     memory ;
+} DADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* RADM64 INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct RADM64_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ; 
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32 compare_mode         : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ; 
+
+} RADM64_FIELDS ; 
+
+
+typedef union 
+{
+  RADM64_FIELDS  radm64 ;
+  HET_MEMORY     memory ;
+} RADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MOV32 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct MOV32_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ;
+ 
+  uint32                      : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 move_type            : 2 ;
+  uint32 sub_opcode           : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32                      : 15 ;
+  uint32 z_flag               : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 5 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+ 
+} MOV32_FIELDS ; 
+
+
+typedef union 
+{
+  MOV32_FIELDS  mov32  ;
+  HET_MEMORY    memory ;
+} MOV32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADM32 INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct ADM32_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ; 
+
+  uint32                      : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 move_type            : 2 ;
+  uint32 sub_opcode           : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32                      : 19 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 5 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+   
+} ADM32_FIELDS ; 
+
+
+typedef union 
+{
+  ADM32_FIELDS  adm32  ;
+  HET_MEMORY    memory ;
+} ADM32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADCNST INSTRUCTION                          */
+/*---------------------------------------------*/
+typedef struct ADCNST_format                     
+{
+  uint32 remote_address       : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ;
+ 
+  uint32 constant             : 25 ;
+  uint32                      : 1 ;
+  uint32                      : 5 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ; 
+
+} ADCNST_FIELDS ;
+
+
+typedef union 
+{
+  ADCNST_FIELDS  adcnst ;
+  HET_MEMORY     memory ;
+} ADCNST_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* ADD INSTRUCTION					*/
+/*----------------------------------------------*/
+typedef struct ADD_format                     
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} ADD_FIELDS ;
+
+
+typedef union 
+{
+  ADD_FIELDS  add ;
+  HET_MEMORY  memory ;
+} ADD_INSTRUCTION;
+
+
+
+
+/*----------------------------------------------*/
+/* ADC INSTRUCTION					*/
+/*----------------------------------------------*/
+
+
+typedef struct ADC_format                     
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} ADC_FIELDS ;
+
+
+typedef union 
+{
+  ADC_FIELDS  adc ;
+  HET_MEMORY  memory ;
+} ADC_INSTRUCTION;
+
+
+
+
+/*----------------------------------------------*/
+/* SUB INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct SUB_format                     
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} SUB_FIELDS ;
+
+
+typedef union 
+{
+  SUB_FIELDS  sub ;
+  HET_MEMORY  memory ;
+} SUB_INSTRUCTION;
+
+
+
+
+
+/*----------------------------------------------*/
+/* SBB INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct SBB_format
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} SBB_FIELDS ;
+
+
+typedef union 
+{
+  SBB_FIELDS  sbb ;
+  HET_MEMORY  memory ;
+} SBB_INSTRUCTION;
+
+
+
+
+/*----------------------------------------------*/
+/* AND INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct AND_format
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} AND_FIELDS ;
+
+
+typedef union 
+{
+#ifdef __cplusplus
+  AND_FIELDS  and_cpp ;
+#else
+  AND_FIELDS  and ;
+#endif
+  HET_MEMORY  memory ;
+} AND_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* OR INSTRUCTION						*/
+/*----------------------------------------------*/
+
+typedef struct OR_format
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} OR_FIELDS ;
+
+
+typedef union 
+{
+#ifdef __cplusplus
+  OR_FIELDS  or_cpp ;
+#else
+  OR_FIELDS  or ;
+#endif
+  HET_MEMORY  memory ;
+} OR_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* XOR INSTRUCTION					*/
+/*----------------------------------------------*/
+
+typedef struct XOR_format
+{
+
+  uint32 remote_address       : 9 ;	
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;	
+  uint32                      : 9 ;
+
+  uint32                      : 1 ;  
+  uint32 reg	                : 2 ;
+  uint32 rem_dest             : 2 ;
+  uint32 sub_opcode1          : 1 ;
+  uint32 init_flag            : 1 ;
+  uint32 reg_ext              : 1 ;
+  uint32 shft_cnt             : 5 ;
+  uint32 shft_mode            : 3 ;
+  uint32 src_2                : 3 ;
+  uint32 src_1                : 4 ;
+  uint32 sub_opcode3          : 3 ;
+  uint32 control              : 1 ;
+  uint32                      : 5 ;
+
+  uint32 hr_data              : 7 ; 
+  uint32 data                 : 25 ;
+ 
+ 
+} XOR_FIELDS ;
+
+
+typedef union 
+{
+#ifdef __cplusplus
+  XOR_FIELDS  xor_cpp ;
+#else
+  XOR_FIELDS  xor ;
+#endif
+  HET_MEMORY  memory ;
+} XOR_INSTRUCTION;
+
+
+
+
+/*---------------------------------------------*/
+/* CNT INSTRUCTION                             */
+/*---------------------------------------------*/
+typedef struct CNT_format                     
+{
+  uint32 interrupt_enable     : 1 ;         
+  uint32                      : 4 ;        
+  uint32 ab_register_select   : 1 ;          
+  uint32 t_register_select    : 1 ;
+  uint32 angle_cnt            : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;  
+  uint32                      : 9 ;  
+
+  uint32 max                  : 25 ;
+  uint32                      : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} CNT_FIELDS ; 
+
+typedef union 
+{
+  CNT_FIELDS   cnt    ; 
+  HET_MEMORY   memory ;
+} CNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* APCNT INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct apcnt_format
+{
+  uint32                      : 6 ;
+  uint32 edge_select          : 2 ;
+  uint32 interrupt_enable     : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 count                : 25 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ; 
+
+} APCNT_FIELDS ;
+ 
+typedef union
+{
+  APCNT_FIELDS  apcnt   ;
+  HET_MEMORY   memory ;
+} APCNT_INSTRUCTION;
+ 
+ 
+
+/*---------------------------------------------*/
+/* PCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct pcnt_format                     
+{
+  uint32 pin_select           : 5 ;
+  uint32                      : 1 ;
+  uint32 period_pulse_select  : 2 ;          
+  uint32 interrupt_enable     : 1 ;          
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 count                : 25 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+
+} PCNT_FIELDS ;      
+
+typedef union 
+{
+  PCNT_FIELDS  pcnt   ; 
+  HET_MEMORY   memory ;
+} PCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct scnt_format                     
+{
+  uint32                      : 4 ;
+  uint32 step_width           : 2 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32                      : 9 ;
+
+  uint32 gap_start            : 25 ;
+  uint32                      : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32                      : 5 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} SCNT_FIELDS ;      
+
+typedef union 
+{
+  SCNT_FIELDS  scnt   ; 
+  HET_MEMORY   memory ;
+} SCNT_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* ACNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct acnt_format                     
+{
+  uint32 interrupt_enable     : 1 ; 
+  uint32                      : 7 ;
+  uint32 edge_select          : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 gap_end              : 25 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} ACNT_FIELDS ;      
+
+typedef union 
+{
+  ACNT_FIELDS  acnt   ; 
+  HET_MEMORY   memory ;
+} ACNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct ecnt_format
+{
+  uint32                      : 6 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+ 
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 1 ;
+  uint32 count_cond           : 3 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 3 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ; 
+ 
+
+} ECNT_FIELDS ;
+ 
+typedef union
+{
+  ECNT_FIELDS  ecnt   ;
+  HET_MEMORY   memory ;
+} ECNT_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* RCNT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct rcnt_format
+{
+
+  uint32 count_mode1          : 1 ;
+  uint32                      : 5 ;
+  uint32 count_mode           : 2 ;
+  uint32                      : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+
+  uint32 divisor              : 25 ;  
+  uint32                      : 1 ;
+  uint32 control              : 1 ;
+  uint32                      : 2 ;
+  uint32                      : 3 ;
+
+  uint32                      : 7 ;  
+  uint32 data                 : 25 ;
+
+ 
+} RCNT_FIELDS ;
+ 
+typedef union
+{
+  RCNT_FIELDS  rcnt   ;
+  HET_MEMORY   memory ;
+} RCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJNZ INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct djnz_format                     
+{
+  uint32                      : 6 ;
+  uint32 sub_opcode           : 2 ;
+  uint32                      : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ; 
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 10 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 4 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} DJNZ_FIELDS ;      
+
+typedef union 
+{
+  DJNZ_FIELDS  djnz   ; 
+  HET_MEMORY   memory ;
+} DJNZ_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJZ INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct djz_format                     
+{
+  uint32                      : 6 ;
+  uint32 sub_opcode           : 2 ;
+  uint32                      : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ; 
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 10 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 4 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} DJZ_FIELDS ;      
+
+typedef union 
+{
+  DJZ_FIELDS  djz   ; 
+  HET_MEMORY   memory ;
+} DJZ_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* PWCNT INSTRUCTION                           */
+/*---------------------------------------------*/
+typedef struct pwcnt_format                     
+{
+  uint32                      : 6 ;
+  uint32 count_mode           : 2 ;
+  uint32 hr_lr                : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32 opposite_action      : 1 ;
+  uint32 pin_action           : 1 ;
+  uint32                      : 3 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 en_pin_action        : 1 ;
+  uint32                      : 3 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;  
+ 
+} PWCNT_FIELDS ;      
+
+typedef union 
+{
+  PWCNT_FIELDS  pwcnt ;
+  HET_MEMORY   memory ;
+} PWCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* WCAP INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct wcap_format                     
+{
+  uint32                      : 8 ;
+  uint32 hr_lr                : 1 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ; 
+  
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 2 ;
+  uint32 capture_condition    : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 3 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+
+} WCAP_FIELDS ;      
+
+typedef union 
+{
+  WCAP_FIELDS  wcap   ; 
+  HET_MEMORY   memory ;
+} WCAP_INSTRUCTION;
+ 
+/*----------------------------------------------*/
+/* WCAPE INSTRUCTION                            */
+/*----------------------------------------------*/
+typedef struct wcape_format                     
+{
+  uint32                      : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;  
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 2 ;
+  uint32 capture_condition    : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32 ec_data              : 7 ;
+  uint32 ts_data              : 25 ;
+
+} WCAPE_FIELDS ;      
+
+typedef union 
+{
+  WCAPE_FIELDS  wcape   ; 
+  HET_MEMORY   memory ;
+} WCAPE_INSTRUCTION;
+ 
+
+/*---------------------------------------------*/
+/* BR   INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct br_format                     
+{
+  uint32                      : 9 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ;
+
+  uint32 interrupt_enable     : 1 ;
+  uint32                      : 2 ;
+  uint32                      : 1 ;
+  uint32                      : 1 ;
+  uint32 branch_condition     : 3 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 3 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ; 
+  
+  uint32 hr_data              : 7 ;
+  uint32 data                 : 25 ;
+
+} BR_FIELDS ;      
+
+typedef union 
+{
+  BR_FIELDS  br     ; 
+  HET_MEMORY memory ;
+} BR_INSTRUCTION;
+
+ 
+/*---------------------------------------------*/
+/* SHFT INSTRUCTION                            */
+/*---------------------------------------------*/
+typedef struct shft_format                     
+{
+  uint32 shift_mode           : 4 ;
+  uint32                      : 5 ;
+  uint32 op_code              : 4 ;
+  uint32 next_program_address : 9 ;
+  uint32 brk                  : 1 ;
+  uint32 reqnum               : 3 ;
+  uint32                      : 6 ; 
+
+  uint32 interrupt_enable     : 1 ;
+  uint32 ab_register_select   : 1 ;
+  uint32 t_register_select    : 1 ;
+  uint32                      : 2 ;
+  uint32 shift_condition      : 2 ;
+  uint32                      : 1 ;
+  uint32 pin_select           : 5 ;
+  uint32 cond_addr            : 9 ;
+  uint32                      : 3 ;
+  uint32 previous_bit         : 1 ;
+  uint32 auto_read_clear      : 1 ;
+  uint32 request              : 2 ;
+  uint32                      : 3 ;
+  
+  uint32                      : 7 ;
+  uint32 data                 : 25 ;
+
+} SHFT_FIELDS ;      
+
+typedef union 
+{
+  SHFT_FIELDS  shft   ; 
+  HET_MEMORY   memory ;
+} SHFT_INSTRUCTION;
+
+#endif
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
+/*--------------------------- End Of File ----------------------------------*/
diff --git a/include/arch/rm46l8lp/halcogen/sys_common.h b/include/arch/rm46l8lp/halcogen/sys_common.h
new file mode 100644
index 0000000..2dd8f1d
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/sys_common.h
@@ -0,0 +1,130 @@
+/** @file sys_common.h
+*   @brief Common Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - General Definitions
+*   .
+*   which are relevant for all drivers.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_COMMON_H__
+#define __SYS_COMMON_H__
+
+#include "hal_stdtypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/************************************************************/
+/* Type Definitions                                         */
+/************************************************************/
+
+#ifndef _TBOOLEAN_DECLARED
+typedef boolean tBoolean;
+#define _TBOOLEAN_DECLARED
+#endif
+
+/** @enum loopBackType
+*   @brief Loopback type definition
+*/
+/** @typedef loopBackType_t
+*   @brief Loopback type Type Definition
+*
+*   This type is used to select the module Loopback type Digital or Analog loopback.
+*/
+typedef enum loopBackType 
+{
+    Digital_Lbk = 0U, 
+    Analog_Lbk = 1U
+}loopBackType_t;
+
+/** @enum config_value_type
+*   @brief config type definition
+*/
+/** @typedef config_value_type_t
+*   @brief config type Type Definition
+*
+*   This type is used to specify the Initial and Current value.
+*/
+typedef enum config_value_type
+{
+	InitialValue,
+	CurrentValue
+}config_value_type_t;
+
+#ifndef __little_endian__
+#define __little_endian__  0
+#endif
+#ifndef __LITTLE_ENDIAN__
+#define __LITTLE_ENDIAN__  0
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/********************************************************************************/
+/* The ASSERT macro, which does the actual assertion checking.  Typically, this */
+/* will be for procedure arguments.                                             */
+/********************************************************************************/
+#ifdef DEBUG
+#define ASSERT(expr) {                                      \
+                         if(!(expr))                        \
+                         {                                  \
+                             __error__(__FILE__, __LINE__); \
+                         }                                  \
+                     }
+#else
+#define ASSERT(expr)
+#endif
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/sys_core.h b/include/arch/rm46l8lp/halcogen/sys_core.h
new file mode 100644
index 0000000..33077a7
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/sys_core.h
@@ -0,0 +1,358 @@
+/** @file sys_core.h
+*   @brief System Core Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Core Interface Functions
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_CORE_H__
+#define __SYS_CORE_H__
+
+#include "sys_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @def USER_STACK_LENGTH
+*   @brief USER Mode Stack length (in bytes)
+*
+*   Alias for USER Mode Stack length (in bytes)
+*
+*	@note: Use this macro for USER Mode Stack length (in bytes)
+*/
+#define USER_STACK_LENGTH   0x00001000U
+
+/** @def SVC_STACK_LENGTH
+*   @brief SVC Mode Stack length (in bytes)
+*
+*   Alias for SVC Mode Stack length (in bytes)
+*
+*	@note: Use this macro for SVC Mode Stack length (in bytes)
+*/
+#define SVC_STACK_LENGTH    0x00000100U
+
+/** @def FIQ_STACK_LENGTH
+*   @brief FIQ Mode Stack length (in bytes)
+*
+*   Alias for FIQ Mode Stack length (in bytes)
+*
+*	@note: Use this macro for FIQ Mode Stack length (in bytes)
+*/
+#define FIQ_STACK_LENGTH    0x00000100U
+
+/** @def IRQ_STACK_LENGTH
+*   @brief IRQ Mode Stack length (in bytes)
+*
+*   Alias for IRQ Mode Stack length (in bytes)
+*
+*	@note: Use this macro for IRQ Mode Stack length (in bytes)
+*/
+#define IRQ_STACK_LENGTH    0x00000200U
+
+/** @def ABORT_STACK_LENGTH
+*   @brief ABORT Mode Stack length (in bytes)
+*
+*   Alias for ABORT Mode Stack length (in bytes)
+*
+*	@note: Use this macro for ABORT Mode Stack length (in bytes)
+*/
+#define ABORT_STACK_LENGTH  0x00000100U
+
+/** @def UNDEF_STACK_LENGTH
+*   @brief UNDEF Mode Stack length (in bytes)
+*
+*   Alias for UNDEF Mode Stack length (in bytes)
+*
+*	@note: Use this macro for UNDEF Mode Stack length (in bytes)
+*/
+#define UNDEF_STACK_LENGTH  0x00000100U
+
+/* System Core Interface Functions */
+
+/** @fn void _coreInitRegisters_(void)
+*   @brief Initialize Core register
+*/
+void _coreInitRegisters_(void);
+
+/** @fn void _coreInitStackPointer_(void)
+*   @brief Initialize Core stack pointer
+*/
+void _coreInitStackPointer_(void);
+
+/** @fn void _getCPSRValue_(void)
+*   @brief Get CPSR Value
+*/
+uint32 _getCPSRValue_(void);
+
+/** @fn void _gotoCPUIdle_(void)
+*   @brief Take CPU to Idle state
+*/
+void _gotoCPUIdle_(void);
+
+/** @fn void _coreEnableIrqVicOffset_(void)
+*   @brief Enable Irq offset propagation via Vic controller
+*/
+void _coreEnableIrqVicOffset_(void);
+
+/** @fn void _coreEnableVfp_(void)
+*   @brief Enable vector floating point unit
+*/
+void _coreEnableVfp_(void);
+
+/** @fn void _coreEnableEventBusExport_(void)
+*   @brief Enable event bus export for external monitoring modules
+*   @note It is required to enable event bus export to process ecc issues.
+*
+*   This function enables event bus exports to external monitoring modules
+*   like tightly coupled RAM wrapper, Flash wrapper and error signaling module.
+*/
+void _coreEnableEventBusExport_(void);
+
+/** @fn void _coreDisableEventBusExport_(void)
+*   @brief Disable event bus export for external monitoring modules
+*
+*   This function disables event bus exports to external monitoring modules
+*   like tightly coupled RAM wrapper, Flash wrapper and error signaling module.
+*/
+void _coreDisableEventBusExport_(void);
+
+/** @fn void _coreEnableRamEcc_(void)
+*   @brief Enable external ecc error for RAM odd and even bank
+*   @note It is required to enable event bus export to process ecc issues.
+*/
+void _coreEnableRamEcc_(void);
+
+/** @fn void _coreDisableRamEcc_(void)
+*   @brief Disable external ecc error for RAM odd and even bank
+*/
+void _coreDisableRamEcc_(void);
+
+/** @fn void _coreEnableFlashEcc_(void)
+*   @brief Enable external ecc error for the Flash
+*   @note It is required to enable event bus export to process ecc issues.
+*/
+void _coreEnableFlashEcc_(void);
+
+/** @fn void _coreDisableFlashEcc_(void)
+*   @brief Disable external ecc error for the Flash
+*/
+void _coreDisableFlashEcc_(void);
+
+/** @fn uint32 _coreGetDataFault_(void)
+*   @brief Get core data fault status register
+*   @return The function will return the data fault status register value:
+*           - bit [10,3..0]: 
+*                            - 0b00001: Alignment                -> address is valid
+*                            - 0b00000: Background               -> address is valid
+*                            - 0b01101: Permission               -> address is valid
+*                            - 0b01000: Precise External Abort   -> address is valid
+*                            - 0b10110: Imprecise External Abort -> address is unpredictable
+*                            - 0b11001: Precise ECC Error        -> address is valid
+*                            - 0b11000: Imprecise ECC Error      -> address is unpredictable
+*                            - 0b00010: Debug                    -> address is unchanged
+*           - bit [11]: 
+*                            - 0: Read
+*                            - 1: Write
+*           - bit [12]: 
+*                            - 0: AXI Decode Error (DECERR)
+*                            - 1: AXI Slave Error (SLVERR)
+*/
+uint32 _coreGetDataFault_(void);
+
+/** @fn void _coreClearDataFault_(void)
+*   @brief Clear core data fault status register
+*/
+void _coreClearDataFault_(void);
+
+/** @fn uint32 _coreGetInstructionFault_(void)
+*   @brief Get core instruction fault status register
+*   @return The function will return the instruction fault status register value:
+*           - bit [10,3..0]: 
+*                            - 0b00001: Alignment                -> address is valid
+*                            - 0b00000: Background               -> address is valid
+*                            - 0b01101: Permission               -> address is valid
+*                            - 0b01000: Precise External Abort   -> address is valid
+*                            - 0b10110: Imprecise External Abort -> address is unpredictable
+*                            - 0b11001: Precise ECC Error        -> address is valid
+*                            - 0b11000: Imprecise ECC Error      -> address is unpredictable
+*                            - 0b00010: Debug                    -> address is unchanged
+*           - bit [12]: 
+*                            - 0: AXI Decode Error (DECERR)
+*                            - 1: AXI Slave Error (SLVERR)
+*/
+uint32 _coreGetInstructionFault_(void);
+
+/** @fn void _coreClearInstructionFault_(void)
+*   @brief Clear core instruction fault status register
+*/
+void _coreClearInstructionFault_(void);
+
+/** @fn uint32 _coreGetDataFaultAddress_(void)
+*   @brief Get core data fault address register
+*   @return The function will return the data fault address:
+*/
+uint32 _coreGetDataFaultAddress_(void);
+
+/** @fn void _coreClearDataFaultAddress_(void)
+*   @brief Clear core data fault address register
+*/
+void _coreClearDataFaultAddress_(void);
+
+/** @fn uint32 _coreGetInstructionFaultAddress_(void)
+*   @brief Get core instruction fault address register
+*   @return The function will return the instruction fault address:
+*/
+uint32 _coreGetInstructionFaultAddress_(void);
+
+/** @fn void _coreClearInstructionFaultAddress_(void)
+*   @brief Clear core instruction fault address register
+*/
+void _coreClearInstructionFaultAddress_(void);
+
+/** @fn uint32 _coreGetAuxiliaryDataFault_(void)
+*   @brief Get core auxiliary data fault status register
+*   @return The function will return the auxiliary data fault status register value:
+*           - bit [13..5]:
+*                            - Index value for access giving error
+*           - bit [21]: 
+*                            - 0: Unrecoverable error
+*                            - 1: Recoverable error
+*           - bit [23..22]:
+*                            - 0: Side cache
+*                            - 1: Side ATCM (Flash)
+*                            - 2: Side BTCM (RAM)
+*                            - 3: Reserved
+*           - bit [27..24]: 
+*                            - Cache way or way in which error occurred
+*/
+uint32 _coreGetAuxiliaryDataFault_(void);
+
+/** @fn void _coreClearAuxiliaryDataFault_(void)
+*   @brief Clear core auxiliary data fault status register
+*/
+void _coreClearAuxiliaryDataFault_(void);
+
+/** @fn uint32 _coreGetAuxiliaryInstructionFault_(void)
+*   @brief Get core auxiliary instruction fault status register
+*   @return The function will return the auxiliary instruction fault status register value:
+*           - bit [13..5]:
+*                            - Index value for access giving error
+*           - bit [21]: 
+*                            - 0: Unrecoverable error
+*                            - 1: Recoverable error
+*           - bit [23..22]:
+*                            - 0: Side cache
+*                            - 1: Side ATCM (Flash)
+*                            - 2: Side BTCM (RAM)
+*                            - 3: Reserved
+*           - bit [27..24]: 
+*                            - Cache way or way in which error occurred
+*/
+uint32 _coreGetAuxiliaryInstructionFault_(void);
+
+/** @fn void _coreClearAuxiliaryInstructionFault_(void)
+*   @brief Clear core auxiliary instruction fault status register
+*/
+void _coreClearAuxiliaryInstructionFault_(void);
+
+/** @fn void _disable_interrupt_(void)
+*   @brief Disable IRQ and FIQ Interrupt mode in CPSR register
+*
+*   This function disables IRQ and FIQ Interrupt mode in CPSR register.
+*/
+void _disable_interrupt_(void);
+
+/** @fn void _disable_IRQ_interrupt_(void)
+*   @brief Disable IRQ Interrupt mode in CPSR register
+*
+*   This function disables IRQ Interrupt mode in CPSR register.
+*/
+void _disable_IRQ_interrupt_(void);
+
+/** @fn void _disable_FIQ_interrupt_(void)
+*   @brief Disable FIQ Interrupt mode in CPSR register
+*
+*   This function disables IRQ Interrupt mode in CPSR register.
+*/
+void _disable_FIQ_interrupt_(void);
+
+/** @fn void _enable_interrupt_(void)
+*   @brief Enable IRQ and FIQ Interrupt mode in CPSR register
+*
+*   This function Enables IRQ and FIQ Interrupt mode in CPSR register.
+*   User must call this function to enable Interrupts in non-OS environments.
+*/
+void _enable_interrupt_(void);
+
+/** @fn void _esmCcmErrorsClear_(void)
+*   @brief Clears ESM Error caused due to CCM Errata in RevA Silicon
+*
+*   This function Clears ESM Error caused due to CCM Errata 
+*   in RevA Silicon immediately after powerup.
+*/
+void _esmCcmErrorsClear_(void);
+
+/** @fn void _errata_CORTEXR4_66_(void)
+*   @brief Work Around for Errata CORTEX-R4#66
+*
+*   This function Disable out-of-order completion for divide 
+*   instructions in Auxiliary Control register.
+*/
+void _errata_CORTEXR4_66_(void);
+
+/** @fn void _errata_CORTEXR4_57_(void)
+*   @brief Work Around for Errata CORTEX-R4#57
+*
+*   Disable out-of-order single-precision floating point  
+*   multiply-accumulate instruction completion.
+*/
+void _errata_CORTEXR4_57_(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/sys_dma.h b/include/arch/rm46l8lp/halcogen/sys_dma.h
new file mode 100644
index 0000000..813806a
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/sys_dma.h
@@ -0,0 +1,367 @@
+/** @file dma.h
+*   @brief DMA Driver Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __DMA_H__
+#define __DMA_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "reg_dma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @def BLOCK_TRANSFER
+*   @brief Alias name for DMA Block transfer
+*   @note This value should be used while setting the DMA control packet
+*/
+#define BLOCK_TRANSFER      1U
+
+/** @def FRAME_TRANSFER
+*   @brief Alias name for DMA Frame transfer
+*   @note This value should be used while setting the DMA control packet
+*/
+#define FRAME_TRANSFER      0U
+
+/** @def AUTOINIT_ON
+*   @brief Alias name for Auto Initialization ON
+*   @note This value should be used while setting the DMA control packet
+*/
+#define AUTOINIT_ON         1U
+
+/** @def AUTOINIT_OFF
+*   @brief Alias name for Auto Initialization OFF
+*   @note This value should be used while setting the DMA control packet
+*/
+#define AUTOINIT_OFF        0U
+
+/** @def ADDR_FIXED
+*   @brief Alias name for Fixed Addressing mode
+*   @note This value should be used while setting the DMA control packet
+*/
+#define ADDR_FIXED          0U
+
+/** @def ADDR_INC1
+*   @brief Alias name for Post-increment Addressing mode
+*   @note This value should be used while setting the DMA control packet
+*/
+#define ADDR_INC1           1U
+
+/** @def ADDR_OFFSET
+*   @brief Alias name for Offset Addressing mode
+*   @note This value should be used while setting the DMA control packet
+*/
+#define ADDR_OFFSET         3U
+
+/** @def INTERRUPT_ENABLE
+*   @brief Alias name for Interrupt enable
+*   @note @note This value should be used for API argument @a intenable
+*/
+#define INTERRUPT_ENABLE	1U
+
+/** @def INTERRUPT_DISABLE
+*   @brief Alias name for Interrupt disable
+*   @note @note This value should be used for API argument @a intenable
+*/
+#define INTERRUPT_DISABLE	0U
+
+
+/** @def DMA_GCTRL_BUSBUSY
+*   @brief Bit mask for BUS BUSY in GCTRL Register
+*   @note @note This value should be used for API argument @a intenable
+*/
+#define DMA_GCTRL_BUSBUSY	(0x00004000U)
+
+/** @enum dmaREQTYPE
+*   @brief DMA TRANSFER Type definitions 
+*
+*   Used to define DMA transfer type
+*/
+enum dmaREQTYPE
+{
+    DMA_HW = 0x0U,  /**<  Hardware trigger  */
+    DMA_SW = 0x1U   /**<  Software trigger  */
+};
+
+
+/** @enum dmaCHANNEL
+*   @brief DMA CHANNEL definitions 
+*
+*   Used to define DMA Channel Number
+*/
+enum dmaCHANNEL
+{
+    DMA_CH0  = 0x00U,
+    DMA_CH1  = 0x01U,
+    DMA_CH2  = 0x02U,
+    DMA_CH3  = 0x03U,
+    DMA_CH4  = 0x04U,
+    DMA_CH5  = 0x05U,
+    DMA_CH6  = 0x06U,
+    DMA_CH7  = 0x07U,
+    DMA_CH8  = 0x08U,
+    DMA_CH9  = 0x09U,
+    DMA_CH10 = 0x0AU,
+    DMA_CH11 = 0x0BU,
+    DMA_CH12 = 0x0CU,
+    DMA_CH13 = 0x0DU,
+    DMA_CH14 = 0x0EU,
+    DMA_CH15 = 0x0FU,
+    DMA_CH16 = 0x10U,
+    DMA_CH17 = 0x11U,
+    DMA_CH18 = 0x12U,
+    DMA_CH19 = 0x13U,
+    DMA_CH20 = 0x14U,
+    DMA_CH21 = 0x15U,
+    DMA_CH22 = 0x16U,
+    DMA_CH23 = 0x17U,
+    DMA_CH24 = 0x18U,
+    DMA_CH25 = 0x19U,
+    DMA_CH26 = 0x1AU,
+    DMA_CH27 = 0x1BU,
+    DMA_CH28 = 0x1CU,
+    DMA_CH29 = 0x1DU,
+    DMA_CH30 = 0x1EU,
+    DMA_CH31 = 0x1FU
+};
+
+/** @enum dmaACCESS
+*   @brief DMA ACESS WIDTH definitions 
+*
+*   Used to define DMA access width
+*/
+typedef enum dmaACCESS
+{
+ ACCESS_8_BIT   =  0U,
+ ACCESS_16_BIT  =  1U,
+ ACCESS_32_BIT  =  2U,
+ ACCESS_64_BIT  =  3U
+}dmaACCESS_t;
+
+
+/** @enum dmaPRIORITY
+*   @brief DMA Channel Priority
+*
+*   Used to define to which priority queue a DMA channel is assigned to
+*/
+typedef enum dmaPRIORITY
+{
+	LOWPRIORITY = 0U,
+	HIGHPRIORITY = 1U
+}dmaPRIORITY_t;
+
+
+/** @enum dmaREGION
+*   @brief DMA Memory Protection Region
+*
+*   Used to define DMA Memory Protection Region
+*/
+typedef enum dmaREGION
+{
+	DMA_REGION0 = 0U,
+	DMA_REGION1 = 1U,
+	DMA_REGION2 = 2U,
+	DMA_REGION3 = 3U
+}dmaREGION_t;
+
+
+/** @enum dmaRegionAccess
+*   @brief DMA Memory Protection Region Access
+*
+*   Used to define access permission of DMA memory protection regions
+*/
+typedef enum dmaRegionAccess
+{
+	FULLACCESS = 0U,
+	READONLY   = 1U,
+	WRITEONLY  = 2U,
+	NOACCESS   = 3U
+}dmaRegionAccess_t;
+
+
+/** @enum dmaInterrupt
+*   @brief DMA Interrupt
+*
+*   Used to define DMA interrupts
+*/
+typedef enum dmaInterrupt
+{
+	FTC = 1U,   /**<  Frame transfer complete Interrupt      */
+	LFS = 2U,   /**<  Last frame transfer started Interrupt  */
+	HBC = 3U,   /**<  First half of block complete Interrupt */
+	BTC = 4U    /**<  Block transfer complete Interrupt      */
+}dmaInterrupt_t;
+
+/** @struct g_dmaCTRL
+*   @brief Interrupt mode globals
+*
+*/
+typedef struct  dmaCTRLPKT
+{
+    uint32 SADD;       /* initial source address             */
+    uint32 DADD;       /* initial destination address        */
+    uint32 CHCTRL;     /* next ctrl packet to be trigger + 1 */
+    uint32 FRCNT;      /* frame   count                      */
+    uint32 ELCNT;      /* element count                      */
+    uint32 ELDOFFSET;  /* element destination offset         */
+    uint32 ELSOFFSET;  /* element source offset              */
+    uint32 FRDOFFSET;  /* frame detination offset            */
+    uint32 FRSOFFSET;  /* frame source offset                */
+    uint32 PORTASGN;   /* dma port                           */
+    uint32 RDSIZE;     /* read element size                  */
+    uint32 WRSIZE;     /* write element size                 */
+    uint32 TTYPE;      /* trigger type - frame/block         */
+    uint32 ADDMODERD;  /* addresssing mode for source        */
+    uint32 ADDMODEWR;  /* addresssing mode for destination   */
+    uint32 AUTOINIT;   /* auto-init mode                     */
+    uint32 COMBO;      /* next ctrl packet trigger(Not used) */
+} g_dmaCTRL;
+
+typedef volatile struct
+{
+     
+     struct                                     /* 0x000-0x400 */
+     {
+      uint32 ISADDR;
+      uint32 IDADDR;
+      uint32 ITCOUNT; 
+      uint32  rsvd1;    
+      uint32 CHCTRL;
+      uint32 EIOFF;
+      uint32 FIOFF;
+      uint32  rsvd2;  
+     }PCP[32U];
+
+     struct                                     /* 0x400-0x800   */
+     {
+       uint32 res[256U];
+     } RESERVED;
+
+     struct                                     /* 0x800-0xA00 */
+     {
+      uint32 CSADDR;
+      uint32 CDADDR;
+      uint32 CTCOUNT;
+      uint32  rsvd3; 
+     }WCP[32U];
+
+} dmaRAMBASE_t;
+
+#define dmaRAMREG ((dmaRAMBASE_t *)0xFFF80000U)
+
+typedef struct dma_config_reg
+{
+    uint32 CONFIG_CHPRIOS;
+    uint32 CONFIG_GCHIENAS;
+    uint32 CONFIG_DREQASI[8U];
+    uint32 CONFIG_FTCINTENAS;
+    uint32 CONFIG_LFSINTENAS;
+    uint32 CONFIG_HBCINTENAS;
+    uint32 CONFIG_BTCINTENAS;
+    uint32 CONFIG_DMAPCR;
+    uint32 CONFIG_DMAMPCTRL;
+} dma_config_reg_t;
+
+
+/**
+ * @defgroup DMA DMA
+ * @brief Direct Memory Access Controller
+ *
+ * The DMA controller is used to transfer data between two locations in the memory map in the background
+ * of CPU operations. Typically, the DMA is used to:
+ * - Transfer blocks of data between external and internal data memories
+ * - Restructure portions of internal data memory
+ * - Continually service a peripheral
+ * - Page program sections to internal program memory
+ *
+ * Related files:
+ * - reg_dma.h
+ * - sys_dma.h
+ * - sys_dma.c
+ *
+ * @addtogroup DMA
+ * @{
+ */
+/* DMA Interface Functions */
+void dmaEnable(void);
+void dmaDisable(void);
+void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT);
+void dmaSetChEnable(uint32 channel,uint32 type);
+void dmaReqAssign(uint32 channel,uint32 reqline);
+uint32 dmaGetReq(uint32 channel);
+void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority);
+void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype);
+void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype);
+void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add);
+void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable);
+void dmaDisableRegion(dmaREGION_t region);
+void dmaEnableParityCheck(void);
+void dmaDisableParityCheck(void);
+void dmaGetConfigValue(dma_config_reg_t *config_reg, config_value_type_t type);
+
+/** @fn void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
+*   @brief Interrupt callback
+*   @param[in] inttype  Interrupt type
+*                        - FTC
+*                        - LFS
+*                        - HBC
+*                        - BTC
+*   @param[in] channel  channel number 0..15
+* This is a callback that is provided by the application and is called apon
+* an interrupt.  The parameter passed to the callback is a copy of the 
+* interrupt flag register.
+*/
+void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/sys_mpu.h b/include/arch/rm46l8lp/halcogen/sys_mpu.h
new file mode 100644
index 0000000..d8c7e82
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/sys_mpu.h
@@ -0,0 +1,517 @@
+/** @file sys_mpu.h
+*   @brief System Mpu Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Mpu Interface Functions
+*   .
+*   which are relevant for the memory protection unit driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_MPU_H__
+#define __SYS_MPU_H__
+
+#include "sys_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @def mpuREGION1
+*   @brief Mpu region 1
+*
+*   Alias for Mpu region 1
+*/
+#define mpuREGION1 0U
+
+/** @def mpuREGION2
+*   @brief Mpu region 2
+*
+*   Alias for Mpu region 1
+*/
+#define mpuREGION2 1U
+
+/** @def mpuREGION3
+*   @brief Mpu region 3
+*
+*   Alias for Mpu region 3
+*/
+#define mpuREGION3 2U
+
+/** @def mpuREGION4
+*   @brief Mpu region 4
+*
+*   Alias for Mpu region 4
+*/
+#define mpuREGION4 3U
+
+/** @def mpuREGION5
+*   @brief Mpu region 5
+*
+*   Alias for Mpu region 5
+*/
+#define mpuREGION5 4U
+
+/** @def mpuREGION6
+*   @brief Mpu region 6
+*
+*   Alias for Mpu region 6
+*/
+#define mpuREGION6 5U
+
+/** @def mpuREGION7
+*   @brief Mpu region 7
+*
+*   Alias for Mpu region 7
+*/
+#define mpuREGION7 6U
+
+/** @def mpuREGION8
+*   @brief Mpu region 8
+*
+*   Alias for Mpu region 8
+*/
+#define mpuREGION8 7U
+
+/** @def mpuREGION9
+*   @brief Mpu region 9
+*
+*   Alias for Mpu region 9
+*/
+#define mpuREGION9 8U
+
+/** @def mpuREGION10
+*   @brief Mpu region 10
+*
+*   Alias for Mpu region 10
+*/
+#define mpuREGION10 9U
+
+/** @def mpuREGION11
+*   @brief Mpu region 11
+*
+*   Alias for Mpu region 11
+*/
+#define mpuREGION11 10U
+
+/** @def mpuREGION12
+*   @brief Mpu region 12
+*
+*   Alias for Mpu region 12
+*/
+#define mpuREGION12 11U
+
+/** @def mpuREGION_ENABLE
+*   @brief Enable MPU Region
+*
+*   Alias for MPU region enable.
+*
+*   @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuREGION_ENABLE 1U
+
+/** @def mpuREGION_DISABLE
+*   @brief Disable MPU Region
+*
+*   Alias for MPU region disable.
+*
+*   @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuREGION_DISABLE 0U
+
+/** @def mpuSUBREGION0_DISABLE
+*   @brief Disable MPU Sub Region0
+*
+*   Alias for MPU subregion0 disable.
+*
+*   @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION0_DISABLE 0x100U
+
+/** @def mpuSUBREGION1_DISABLE
+*   @brief Disable MPU Sub Region1
+*
+*   Alias for MPU subregion1 disable.
+*
+*   @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION1_DISABLE 0x200U
+
+/** @def mpuSUBREGION2_DISABLE
+*   @brief Disable MPU Sub Region2
+*
+*   Alias for MPU subregion2 disable.
+*
+*   @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION2_DISABLE 0x400U
+
+/** @def mpuSUBREGION3_DISABLE
+*   @brief Disable MPU Sub Region3
+*
+*   Alias for MPU subregion3 disable.
+*
+*   @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION3_DISABLE 0x800U
+
+/** @def mpuSUBREGION4_DISABLE
+*   @brief Disable MPU Sub Region4
+*
+*   Alias for MPU subregion4 disable.
+*
+*   @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION4_DISABLE 0x1000U
+
+/** @def mpuSUBREGION5_DISABLE
+*   @brief Disable MPU Sub Region5
+*
+*   Alias for MPU subregion5 disable.
+*
+*   @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION5_DISABLE 0x2000U
+
+/** @def mpuSUBREGION6_DISABLE
+*   @brief Disable MPU Sub Region6
+*
+*   Alias for MPU subregion6 disable.
+*
+*   @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION6_DISABLE 0x4000U
+
+/** @def mpuSUBREGION7_DISABLE
+*   @brief Disable MPU Sub Region7
+*
+*   Alias for MPU subregion7 disable.
+*
+*   @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION7_DISABLE 0x8000U
+
+
+
+/** @enum mpuRegionAccessPermission
+*   @brief Alias names for mpu region access permissions
+*
+*   This enumeration is used to provide alias names for the mpu region access permission:
+*     - MPU_PRIV_NA_USER_NA_EXEC no access in privileged mode, no access in user mode and execute
+*     - MPU_PRIV_RW_USER_NA_EXEC read/write in privileged mode, no access in user mode and execute
+*     - MPU_PRIV_RW_USER_RO_EXEC read/write in privileged mode, read only in user mode and execute
+*     - MPU_PRIV_RW_USER_RW_EXEC read/write in privileged mode, read/write in user mode and execute
+*     - MPU_PRIV_RO_USER_NA_EXEC read only in privileged mode, no access in user mode and execute
+*     - MPU_PRIV_RO_USER_RO_EXEC read only in privileged mode, read only in user mode and execute
+*     - MPU_PRIV_NA_USER_NA_NOEXEC no access in privileged mode, no access in user mode and no execution
+*     - MPU_PRIV_RW_USER_NA_NOEXEC read/write in privileged mode, no access in user mode and no execution
+*     - MPU_PRIV_RW_USER_RO_NOEXEC read/write in privileged mode, read only in user mode and no execution
+*     - MPU_PRIV_RW_USER_RW_NOEXEC read/write in privileged mode, read/write in user mode and no execution
+*     - MPU_PRIV_RO_USER_NA_NOEXEC read only in privileged mode, no access in user mode and no execution
+*     - MPU_PRIV_RO_USER_RO_NOEXEC read only in privileged mode, read only in user mode and no execution
+*
+*/
+enum mpuRegionAccessPermission
+{
+    MPU_PRIV_NA_USER_NA_EXEC   = 0x0000U, /**< Alias no access in privileged mode, no access in user mode and execute */
+    MPU_PRIV_RW_USER_NA_EXEC   = 0x0100U, /**< Alias no read/write in privileged mode, no access in user mode and execute */
+    MPU_PRIV_RW_USER_RO_EXEC   = 0x0200U, /**< Alias no read/write in privileged mode, read only in user mode and execute */
+    MPU_PRIV_RW_USER_RW_EXEC   = 0x0300U, /**< Alias no read/write in privileged mode, read/write in user mode and execute */
+    MPU_PRIV_RO_USER_NA_EXEC   = 0x0500U, /**< Alias no read only in privileged mode, no access in user mode and execute */
+    MPU_PRIV_RO_USER_RO_EXEC   = 0x0600U, /**< Alias no read only in privileged mode, read only in user mode and execute */
+    MPU_PRIV_NA_USER_NA_NOEXEC = 0x1000U, /**< Alias no access in privileged mode, no access in user mode and no execution */
+    MPU_PRIV_RW_USER_NA_NOEXEC = 0x1100U, /**< Alias no read/write in privileged mode, no access in user mode and no execution */
+    MPU_PRIV_RW_USER_RO_NOEXEC = 0x1200U, /**< Alias no read/write in privileged mode, read only in user mode and no execution */
+    MPU_PRIV_RW_USER_RW_NOEXEC = 0x1300U, /**< Alias no read/write in privileged mode, read/write in user mode and no execution */
+    MPU_PRIV_RO_USER_NA_NOEXEC = 0x1500U, /**< Alias no read only in privileged mode, no access in user mode and no execution */
+    MPU_PRIV_RO_USER_RO_NOEXEC = 0x1600U  /**< Alias no read only in privileged mode, read only in user mode and no execution */
+};
+
+/** @enum mpuRegionType
+*   @brief Alias names for mpu region type
+*
+*   This enumeration is used to provide alias names for the mpu region type:
+*     - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable
+*     - MPU_DEVICE_SHAREABLE          Memory type device and sharable
+*     - MPU_NORMAL_OIWTNOWA_NONSHARED Memory type normal outer and inner write-through, no write allocate and non shared
+*     - MPU_NORMAL_OIWTNOWA_SHARED    Memory type normal outer and inner write-through, no write allocate and shared
+*     - MPU_NORMAL_OIWBNOWA_NONSHARED Memory type normal outer and inner write-back, no write allocate and non shared
+*     - MPU_NORMAL_OIWBNOWA_SHARED    Memory type normal outer and inner write-back, no write allocate and shared
+*     - MPU_NORMAL_OINC_NONSHARED     Memory type normal outer and inner non-cachable and non shared
+*     - MPU_NORMAL_OINC_SHARED        Memory type normal outer and inner non-cachable and shared
+*     - MPU_NORMAL_OIWBWA_NONSHARED   Memory type normal outer and inner write-back, write allocate and non shared
+*     - MPU_NORMAL_OIWBWA_SHARED      Memory type normal outer and inner write-back, write allocate and shared
+*     - MPU_DEVICE_NONSHAREABLE       Memory type device and non sharable
+*/
+enum mpuRegionType
+{
+    MPU_STRONGLYORDERED_SHAREABLE = 0x0000U, /**< Memory type strongly ordered and sharable */
+    MPU_DEVICE_SHAREABLE          = 0x0001U, /**< Memory type device and sharable */
+    MPU_NORMAL_OIWTNOWA_NONSHARED = 0x0002U, /**< Memory type normal outer and inner write-through, no write allocate and non shared */
+    MPU_NORMAL_OIWBNOWA_NONSHARED = 0x0003U, /**< Memory type normal outer and inner write-back, no write allocate and non shared */
+    MPU_NORMAL_OIWTNOWA_SHARED    = 0x0006U, /**< Memory type normal outer and inner write-through, no write allocate and shared */
+    MPU_NORMAL_OIWBNOWA_SHARED    = 0x0007U, /**< Memory type normal outer and inner write-back, no write allocate and shared */
+    MPU_NORMAL_OINC_NONSHARED     = 0x0008U, /**< Memory type normal outer and inner non-cachable and non shared */
+    MPU_NORMAL_OIWBWA_NONSHARED   = 0x000BU, /**< Memory type normal outer and inner write-back, write allocate and non shared */
+    MPU_NORMAL_OINC_SHARED        = 0x000CU, /**< Memory type normal outer and inner non-cachable and shared */
+    MPU_NORMAL_OIWBWA_SHARED      = 0x000FU, /**< Memory type normal outer and inner write-back, write allocate and shared */
+    MPU_DEVICE_NONSHAREABLE       = 0x0010U  /**< Memory type device and non sharable */
+};
+
+/** @enum mpuRegionSize
+*   @brief Alias names for mpu region type
+*
+*   This enumeration is used to provide alias names for the mpu region type:
+*     - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable
+*     - MPU_32_BYTES Memory size in bytes
+*     - MPU_64_BYTES Memory size in bytes
+*     - MPU_128_BYTES Memory size in bytes
+*     - MPU_256_BYTES Memory size in bytes
+*     - MPU_512_BYTES Memory size in bytes
+*     - MPU_1_KB Memory size in kB
+*     - MPU_2_KB Memory size in kB
+*     - MPU_4_KB Memory size in kB
+*     - MPU_8_KB Memory size in kB
+*     - MPU_16_KB Memory size in kB
+*     - MPU_32_KB Memory size in kB
+*     - MPU_64_KB Memory size in kB
+*     - MPU_128_KB Memory size in kB
+*     - MPU_256_KB  Memory size in kB
+*     - MPU_512_KB Memory size in kB
+*     - MPU_1_MB Memory size in MB
+*     - MPU_2_MB Memory size in MB
+*     - MPU_4_MB Memory size in MB
+*     - MPU_8_MBv Memory size in MB
+*     - MPU_16_MB Memory size in MB
+*     - MPU_32_MB Memory size in MB
+*     - MPU_64_MB Memory size in MB
+*     - MPU_128_MB Memory size in MB
+*     - MPU_256_MB Memory size in MB
+*     - MPU_512_MB Memory size in MB
+*     - MPU_1_GB Memory size in GB
+*     - MPU_2_GB Memory size in GB
+*     - MPU_4_GB Memory size in GB
+*/
+enum mpuRegionSize
+{
+    MPU_32_BYTES  = 0x04U << 1U, /**< Memory size in bytes */
+    MPU_64_BYTES  = 0x05U << 1U, /**< Memory size in bytes */
+    MPU_128_BYTES = 0x06U << 1U, /**< Memory size in bytes */
+    MPU_256_BYTES = 0x07U << 1U, /**< Memory size in bytes */
+    MPU_512_BYTES = 0x08U << 1U, /**< Memory size in bytes */
+    MPU_1_KB      = 0x09U << 1U, /**< Memory size in kB */
+    MPU_2_KB      = 0x0AU << 1U, /**< Memory size in kB */
+    MPU_4_KB      = 0x0BU << 1U, /**< Memory size in kB */
+    MPU_8_KB      = 0x0CU << 1U, /**< Memory size in kB */
+    MPU_16_KB     = 0x0DU << 1U, /**< Memory size in kB */
+    MPU_32_KB     = 0x0EU << 1U, /**< Memory size in kB */
+    MPU_64_KB     = 0x0FU << 1U, /**< Memory size in kB */
+    MPU_128_KB    = 0x10U << 1U, /**< Memory size in kB */
+    MPU_256_KB    = 0x11U << 1U, /**< Memory size in kB */
+    MPU_512_KB    = 0x12U << 1U, /**< Memory size in kB */
+    MPU_1_MB      = 0x13U << 1U, /**< Memory size in MB */
+    MPU_2_MB      = 0x14U << 1U, /**< Memory size in MB */
+    MPU_4_MB      = 0x15U << 1U, /**< Memory size in MB */
+    MPU_8_MB      = 0x16U << 1U, /**< Memory size in MB */
+    MPU_16_MB     = 0x17U << 1U, /**< Memory size in MB */
+    MPU_32_MB     = 0x18U << 1U, /**< Memory size in MB */
+    MPU_64_MB     = 0x19U << 1U, /**< Memory size in MB */
+    MPU_128_MB    = 0x1AU << 1U, /**< Memory size in MB */
+    MPU_256_MB    = 0x1BU << 1U, /**< Memory size in MB */
+    MPU_512_MB    = 0x1CU << 1U, /**< Memory size in MB */
+    MPU_1_GB      = 0x1DU << 1U, /**< Memory size in GB */
+    MPU_2_GB      = 0x1EU << 1U, /**< Memory size in GB */
+    MPU_4_GB      = 0x1FU << 1U  /**< Memory size in GB */
+};
+
+/** @fn void _mpuInit_(void)
+*   @brief Initialize Mpu
+*
+*   This function initializes memory protection unit.
+*/
+void _mpuInit_(void);
+
+/** @fn void _mpuEnable_(void)
+*   @brief Enable Mpu
+*
+*   This function enables memory protection unit.
+*/
+void _mpuEnable_(void);
+
+/** @fn void _mpuDisable_(void)
+*   @brief Disable Mpu
+*
+*   This function disables memory protection unit.
+*/
+void _mpuDisable_(void);
+
+/** @fn void _mpuEnableBackgroundRegion_(void)
+*   @brief Enable Mpu background region
+*
+*   This function enables background region of the memory protection unit.
+*/
+void _mpuEnableBackgroundRegion_(void);
+
+/** @fn void _mpuDisableBackgroundRegion_(void)
+*   @brief Disable Mpu background region
+*
+*   This function disables background region of the memory protection unit.
+*/
+void _mpuDisableBackgroundRegion_(void);
+
+/** @fn uint32 _mpuGetNumberOfRegions_(void)
+*   @brief Returns number of implemented Mpu regions
+*   @return Number of implemented mpu regions
+*
+*   This function returns the number of implemented mpu regions.
+*/
+uint32 _mpuGetNumberOfRegions_(void);
+
+/** @fn uint32 _mpuAreRegionsSeparate_(void)
+*   @brief Returns the type of the implemented mpu regions
+*   @return Mpu type of regions
+*
+*   This function returns 0 when mpu regions are of type unified otherwise regions are of type separate.
+*/
+uint32 _mpuAreRegionsSeparate_(void);
+
+/** @fn void _mpuSetRegion_(uint32 region)
+*   @brief Set mpu region number
+*   @param[in] region Region number: mpuREGION1..mpuREGION12
+*
+*   This function selects one of the implemented mpu regions.
+*/
+void _mpuSetRegion_(uint32 region);
+
+/** @fn uint32 _mpuGetRegion_(void)
+*   @brief Returns the currently selected mpu region
+*   @return Mpu region number
+*
+*   This function returns currently selected mpu region number.
+*/
+uint32 _mpuGetRegion_(void);
+
+/** @fn void _mpuSetRegionBaseAddress_(uint32 address)
+*   @brief Set base address of currently selected mpu region
+*   @param[in] address Base address of the MPU region
+*   @note The base address must always aligned with region size
+*
+*   This function sets the base address of currently selected mpu region.
+*/
+void _mpuSetRegionBaseAddress_(uint32 address);
+
+/** @fn uint32 _mpuGetRegionBaseAddress_(void)
+*   @brief Returns base address of currently selected mpu region
+*   @return Current base address of selected mpu region
+*
+*   This function returns the base address of currently selected mpu region.
+*/
+uint32 _mpuGetRegionBaseAddress_(void);
+
+/** @fn void _mpuSetRegionTypeAndPermission_(uint32 type, uint32 permission)
+*   @brief Set type of currently selected mpu region
+*   @param[in] type Region Type
+*                     - MPU_STRONGLYORDERED_SHAREABLE : Memory type strongly ordered and sharable
+*                     - MPU_DEVICE_SHAREABLE          : Memory type device and sharable
+*                     - MPU_NORMAL_OIWTNOWA_NONSHARED : Memory type normal outer and inner write-through, no write allocate and non shared
+*                     - MPU_NORMAL_OIWBNOWA_NONSHARED : Memory type normal outer and inner write-back, no write allocate and non shared
+*                     - MPU_NORMAL_OIWTNOWA_SHARED    : Memory type normal outer and inner write-through, no write allocate and shared
+*                     - MPU_NORMAL_OIWBNOWA_SHARED    : Memory type normal outer and inner write-back, no write allocate and shared
+*                     - MPU_NORMAL_OINC_NONSHARED     : Memory type normal outer and inner non-cachable and non shared
+*                     - MPU_NORMAL_OIWBWA_NONSHARED   : Memory type normal outer and inner write-back, write allocate and non shared
+*                     - MPU_NORMAL_OINC_SHARED        : Memory type normal outer and inner non-cachable and shared
+*                     - MPU_NORMAL_OIWBWA_SHARED      : Memory type normal outer and inner write-back, write allocate and shared
+*                     - MPU_DEVICE_NONSHAREABLE       : Memory type device and non sharable
+*
+*   @param[in] permission Region Access permission
+*                           - MPU_PRIV_NA_USER_NA_EXEC   : Alias no access in privileged mode, no access in user mode and execute
+*                           - MPU_PRIV_RW_USER_NA_EXEC   : Alias no read/write in privileged mode, no access in user mode and execute
+*                           - MPU_PRIV_RW_USER_RO_EXEC   : Alias no read/write in privileged mode, read only in user mode and execute
+*                           - MPU_PRIV_RW_USER_RW_EXEC   : Alias no read/write in privileged mode, read/write in user mode and execute
+*                           - MPU_PRIV_RO_USER_NA_EXEC   : Alias no read only in privileged mode, no access in user mode and execute
+*                           - MPU_PRIV_RO_USER_RO_EXEC   : Alias no read only in privileged mode, read only in user mode and execute
+*                           - MPU_PRIV_NA_USER_NA_NOEXEC : Alias no access in privileged mode, no access in user mode and no execution
+*                           - MPU_PRIV_RW_USER_NA_NOEXEC : Alias no read/write in privileged mode, no access in user mode and no execution
+*                           - MPU_PRIV_RW_USER_RO_NOEXEC : Alias no read/write in privileged mode, read only in user mode and no execution
+*                           - MPU_PRIV_RW_USER_RW_NOEXEC : Alias no read/write in privileged mode, read/write in user mode and no execution
+*                           - MPU_PRIV_RO_USER_NA_NOEXEC : Alias no read only in privileged mode, no access in user mode and no execution
+*                           - MPU_PRIV_RO_USER_RO_NOEXEC : Alias no read only in privileged mode, read only in user mode and no execution
+*
+*   This function sets the type of currently selected mpu region.
+*/
+void _mpuSetRegionTypeAndPermission_(uint32 type, uint32 permission);
+
+/** @fn uint32 _mpuGetRegionType_(void)
+*   @brief Returns the type of currently selected mpu region
+*   @return Current type of selected mpu region
+*
+*   This function returns the type of currently selected mpu region.
+*/
+uint32 _mpuGetRegionType_(void);
+
+/** @fn uint32 _mpuGetRegionPermission_(void)
+*   @brief Returns permission of currently selected mpu region
+*   @return Current type of selected mpu region
+*
+*   This function returns permission of currently selected mpu region.
+*/
+uint32 _mpuGetRegionPermission_(void);
+
+/** @fn void _mpuSetRegionSizeRegister_(uint32 value)
+*   @brief Set mpu region size register value
+*   @param[in] value Value to be written in the MPU Region Size and Enable register
+*
+*   This function sets mpu region size register value.
+*
+*   Sample usuage: 
+*     _mpuSetRegion_(mpuREGION5);
+*     _mpuSetRegionSizeRegister_(mpuREGION_ENABLE | MPU_16_KB | mpuSUBREGION3_DISABLE | mpuSUBREGION4_DISABLE);
+*/
+void _mpuSetRegionSizeRegister_(uint32 value);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/sys_pcr.h b/include/arch/rm46l8lp/halcogen/sys_pcr.h
new file mode 100644
index 0000000..387e021
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/sys_pcr.h
@@ -0,0 +1,297 @@
+/** @file sys_pcr.h
+*   @brief PCR Driver Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_PCR_H__
+#define __SYS_PCR_H__
+
+#include "reg_pcr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* PCR General Definitions */
+
+typedef uint32 peripheralFrame_CS_t;
+
+#define PeripheralFrame_CS0 0U
+#define PeripheralFrame_CS1 1U
+#define PeripheralFrame_CS2 2U
+#define PeripheralFrame_CS3 3U
+#define PeripheralFrame_CS4 4U
+#define PeripheralFrame_CS5 5U
+#define PeripheralFrame_CS6 6U
+#define PeripheralFrame_CS7 7U
+#define PeripheralFrame_CS8 8U
+#define PeripheralFrame_CS9 9U
+#define PeripheralFrame_CS10 10U
+#define PeripheralFrame_CS11 11U
+#define PeripheralFrame_CS12 12U
+#define PeripheralFrame_CS13 13U
+#define PeripheralFrame_CS14 14U
+#define PeripheralFrame_CS15 15U
+#define PeripheralFrame_CS16 16U
+#define PeripheralFrame_CS17 17U
+#define PeripheralFrame_CS18 18U
+#define PeripheralFrame_CS19 19U
+#define PeripheralFrame_CS20 20U
+#define PeripheralFrame_CS21 21U
+#define PeripheralFrame_CS22 22U
+#define PeripheralFrame_CS23 23U
+#define PeripheralFrame_CS24 24U
+#define PeripheralFrame_CS25 25U
+#define PeripheralFrame_CS26 26U
+#define PeripheralFrame_CS27 27U
+#define PeripheralFrame_CS28 28U
+#define PeripheralFrame_CS29 29U
+#define PeripheralFrame_CS30 30U
+#define PeripheralFrame_CS31 31U
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+typedef uint32 quadrant_Select_t;
+#define Quadrant0 1U
+#define Quadrant1 2U
+#define Quadrant2 4U
+#define Quadrant3 8U
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/** @typedef peripheral_Frame_Select_t
+*   @brief PCR Peripheral Frame Type Definition
+*
+*   This type is used to access the PCR peripheral Frame configuration register.
+*/
+typedef struct peripheral_Frame_Select
+{
+	peripheralFrame_CS_t Peripheral_CS;
+	quadrant_Select_t Peripheral_Quadrant;
+}peripheral_Frame_Select_t;
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+/** @typedef peripheral_Quad_ChipSelect_t
+*   @brief PCR Peripheral Frame registers Type Definition
+*
+*   This type is used to access all the PCR peripheral Frame configuration registers.
+*/
+typedef struct peripheral_Quad_ChipSelect
+{
+	uint32 Peripheral_Quad0_3_CS0_7;
+	uint32 Peripheral_Quad4_7_CS8_15;
+	uint32 Peripheral_Quad8_11_CS16_23;
+	uint32 Peripheral_Quad12_15_CS24_31;
+}peripheral_Quad_ChipSelect_t;
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+/** @typedef peripheral_Memory_ChipSelect_t
+*   @brief PCR Peripheral Memory Frame registers Type Definition
+*
+*   This type is used to access all the PCR peripheral Memory Frame configuration registers.
+*/
+typedef struct peripheral_Memory_ChipSelect
+{
+	uint32 Peripheral_Mem_CS0_31;
+	uint32 Peripheral_Mem_CS32_63;
+}peripheral_Memory_ChipSelect_t;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+typedef uint32 peripheral_MemoryFrame_CS_t;
+
+#define PeripheralMemoryFrame_CS0 0U
+#define PeripheralMemoryFrame_CS1 1U
+#define PeripheralMemoryFrame_CS2 2U
+#define PeripheralMemoryFrame_CS3 3U
+#define PeripheralMemoryFrame_CS4 4U
+#define PeripheralMemoryFrame_CS5 5U
+#define PeripheralMemoryFrame_CS6 6U
+#define PeripheralMemoryFrame_CS7 7U
+#define PeripheralMemoryFrame_CS8 8U
+#define PeripheralMemoryFrame_CS9 9U
+#define PeripheralMemoryFrame_CS10 10U
+#define PeripheralMemoryFrame_CS11 11U
+#define PeripheralMemoryFrame_CS12 12U
+#define PeripheralMemoryFrame_CS13 13U
+#define PeripheralMemoryFrame_CS14 14U
+#define PeripheralMemoryFrame_CS15 15U
+#define PeripheralMemoryFrame_CS16 16U
+#define PeripheralMemoryFrame_CS17 17U
+#define PeripheralMemoryFrame_CS18 18U
+#define PeripheralMemoryFrame_CS19 19U
+#define PeripheralMemoryFrame_CS20 20U
+#define PeripheralMemoryFrame_CS21 21U
+#define PeripheralMemoryFrame_CS22 22U
+#define PeripheralMemoryFrame_CS23 23U
+#define PeripheralMemoryFrame_CS24 24U
+#define PeripheralMemoryFrame_CS25 25U
+#define PeripheralMemoryFrame_CS26 26U
+#define PeripheralMemoryFrame_CS27 27U
+#define PeripheralMemoryFrame_CS28 28U
+#define PeripheralMemoryFrame_CS29 29U
+#define PeripheralMemoryFrame_CS30 30U
+#define PeripheralMemoryFrame_CS31 31U
+#define PeripheralMemoryFrame_CS32 32U
+#define PeripheralMemoryFrame_CS33 33U
+#define PeripheralMemoryFrame_CS34 34U
+#define PeripheralMemoryFrame_CS35 35U
+#define PeripheralMemoryFrame_CS36 36U
+#define PeripheralMemoryFrame_CS37 37U
+#define PeripheralMemoryFrame_CS38 38U
+#define PeripheralMemoryFrame_CS39 39U
+#define PeripheralMemoryFrame_CS40 40U
+#define PeripheralMemoryFrame_CS41 41U
+#define PeripheralMemoryFrame_CS42 42U
+#define PeripheralMemoryFrame_CS43 43U
+#define PeripheralMemoryFrame_CS44 44U
+#define PeripheralMemoryFrame_CS45 45U
+#define PeripheralMemoryFrame_CS46 46U
+#define PeripheralMemoryFrame_CS47 47U
+#define PeripheralMemoryFrame_CS48 48U
+#define PeripheralMemoryFrame_CS49 49U
+#define PeripheralMemoryFrame_CS50 50U
+#define PeripheralMemoryFrame_CS51 51U
+#define PeripheralMemoryFrame_CS52 52U
+#define PeripheralMemoryFrame_CS53 53U
+#define PeripheralMemoryFrame_CS54 54U
+#define PeripheralMemoryFrame_CS55 55U
+#define PeripheralMemoryFrame_CS56 56U
+#define PeripheralMemoryFrame_CS57 57U
+#define PeripheralMemoryFrame_CS58 58U
+#define PeripheralMemoryFrame_CS59 59U
+#define PeripheralMemoryFrame_CS60 60U
+#define PeripheralMemoryFrame_CS61 61U
+#define PeripheralMemoryFrame_CS62 62U
+#define PeripheralMemoryFrame_CS63 63U
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+typedef struct pcr_config_reg
+{
+    uint32 CONFIG_PMPROTSET0;
+    uint32 CONFIG_PMPROTSET1;
+    uint32 CONFIG_PPROTSET0;
+    uint32 CONFIG_PPROTSET1;
+    uint32 CONFIG_PPROTSET2;
+    uint32 CONFIG_PPROTSET3;
+    uint32 CONFIG_PCSPWRDWNSET0;
+    uint32 CONFIG_PCSPWRDWNSET1;
+    uint32 CONFIG_PSPWRDWNSET0;
+    uint32 CONFIG_PSPWRDWNSET1;
+    uint32 CONFIG_PSPWRDWNSET2;
+    uint32 CONFIG_PSPWRDWNSET3;
+} pcr_config_reg_t;
+
+/**
+ * @defgroup PCR PCR
+ * @brief Peripheral Central Resource Controller
+ *
+ * The PCR manages the accesses to the peripheral registers and peripheral
+ * memories. It provides a global reset for all the peripherals. It also supports the
+ * capability to selectively enable or disable the clock for each peripheral
+ * individually. The PCR also manages the accesses to the system module
+ * registers required to configure the device�s clocks, interrupts, and so on. The
+ * system module registers also include status flags for indicating exception
+ * conditions � resets, aborts, errors, interrupts.
+ *
+ * Related files:
+ * - reg_pcr.h
+ * - sys_pcr.h
+ * - sys_pcr.c
+ *
+ * @addtogroup PCR
+ * @{
+ */
+ 
+/* PCR Interface Functions */
+
+void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame);
+void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame);
+void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame);
+void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame);
+
+void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+void peripheral_Protection_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS);
+void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+void peripheral_Powerdown_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS);
+
+void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+void peripheral_Memory_Protection_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS);
+void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+void peripheral_Memory_Powerdown_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS);
+
+void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+
+void pcrGetConfigValue(pcr_config_reg_t *config_reg, config_value_type_t type);
+
+/**@}*/
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/sys_pmm.h b/include/arch/rm46l8lp/halcogen/sys_pmm.h
new file mode 100644
index 0000000..f2c049e
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/sys_pmm.h
@@ -0,0 +1,182 @@
+/** @file sys_pmm.h
+*   @brief PMM Driver Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_PMM_H__
+#define __SYS_PMM_H__
+
+#include "reg_pmm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Bit Masks */
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON0      0x0F000000U     /*PD2*/
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON1      0x000F0000U     /*PD3*/
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON2      0x00000F00U     /*PD4*/
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON3      0x0000000FU     /*PD5*/
+
+#define PMM_MEMPDPWRCTRL0_MEMPDON0          0x0F000000U     /*RAM_PD1*/
+#define PMM_MEMPDPWRCTRL0_MEMPDON1          0x000F0000U     /*RAM_PD2*/
+#define PMM_MEMPDPWRCTRL0_MEMPDON2          0x00000F00U     /*RAM_PD3*/
+
+#define PMM_LOGICPDPWRSTAT_DOMAINON	        0x00000100U
+#define PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT	0x00000003U
+#define PMM_MEMPDPWRSTAT_DOMAINON	        0x00000100U
+#define PMM_MEMPDPWRSTAT_MEMPDPWRSTAT    	0x00000003U
+#define PMM_GLOBALCTRL1_AUTOCLKWAKEENA	    0x00000001U
+
+/* Configuration registers initial value */
+#define PMM_LOGICPDPWRCTRL0_CONFIGVALUE ( (uint32)((uint32)0x5U << 24U) \
+										| (uint32)((uint32)0x5U << 16U) \
+										| (uint32)((uint32)0x5U << 8U)  \
+										| (uint32)((uint32)0x5U << 0U)  )
+#define PMM_MEMPDPWRCTRL0_CONFIGVALUE 	( (uint32)((uint32)0x5U << 24U) \
+										| (uint32)((uint32)0x5U << 16U) \
+										)
+
+#define PMM_PDCLKDISREG_CONFIGVALUE		( (uint32)((uint32)(1U-1U) << 0U) \
+										| (uint32)((uint32)(1U-1U) << 1U) \
+										| (uint32)((uint32)(1U-1U) << 2U) \
+										| (uint32)((uint32)(1U-1U) << 3U) )
+
+#define PMM_GLOBALCTRL1_CONFIGVALUE		( (uint32)((uint32)0U << 8U) \
+                                        | (uint32)((uint32)0U << 0U))
+
+
+/** @enum pmmLogicPDTag
+*   @brief PMM Logic Power Domain 
+*
+*   Used to define PMM Logic Power Domain
+*/
+typedef enum pmmLogicPDTag
+{
+	PMM_LOGICPD1	= 4U,	/*-- NOT USED*/
+	PMM_LOGICPD2	= 0U,
+	PMM_LOGICPD3	= 1U,
+	PMM_LOGICPD4	= 2U,
+	PMM_LOGICPD5	= 3U
+}pmm_LogicPD_t;
+
+
+/** @enum pmmMemPDTag
+*   @brief PMM Memory-Only Power Domain 
+*
+*   Used to define PMM Memory-Only Power Domain
+*/
+typedef enum pmmMemPDTag
+{
+	PMM_MEMPD1 = 0U,
+	PMM_MEMPD2 = 1U,
+	PMM_MEMPD3 = 2U
+}pmm_MemPD_t;
+
+
+/** @enum pmmModeTag
+*   @brief PSCON operating mode 
+*
+*   Used to define the operating mode of PSCON Compare Block
+*/
+typedef enum pmmModeTag
+{
+	LockStep				= 0x0U,
+	SelfTest				= 0x6U,
+	ErrorForcing			= 0x9U,
+	SelfTestErrorForcing	= 0xFU
+}pmm_Mode_t;
+
+
+typedef struct pmm_config_reg
+{
+	uint32 CONFIG_LOGICPDPWRCTRL0;
+	uint32 CONFIG_MEMPDPWRCTRL0;
+	uint32 CONFIG_PDCLKDISREG;
+	uint32 CONFIG_GLOBALCTRL1;
+}pmm_config_reg_t;
+
+/**
+ * @defgroup PMM PMM
+ * @brief Power Management Module
+ *
+ * The PMM provides memory-mapped registers that control the states of the supported power domains. 
+ * The PMM includes interfaces to the Power Mode Controller (PMC) and the Power State Controller (PSCON). 
+ * The PMC and PSCON control the power up/down sequence of each power domain.
+ *
+ * Related files:
+ * - reg_pmm.h
+ * - sys_pmm.h
+ * - sys_pmm.c
+ *
+ * @addtogroup PMM
+ * @{
+ */
+ 
+/* Pmm Interface Functions */
+void pmmInit(void);
+void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD);
+void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD);
+void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD);
+void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD);
+boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD);
+boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD);
+void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type);
+void pmmSetMode(pmm_Mode_t mode);
+boolean pmmPerformSelfTest(void);
+
+/**@}*/
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
+
diff --git a/include/arch/rm46l8lp/halcogen/sys_pmu.h b/include/arch/rm46l8lp/halcogen/sys_pmu.h
new file mode 100644
index 0000000..c2f4e5c
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/sys_pmu.h
@@ -0,0 +1,241 @@
+/** @file sys_pmu.h
+*   @brief System Pmu Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Pmu Interface Functions
+*   .
+*   which are relevant for the performance monitor unit driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_PMU_H__
+#define __SYS_PMU_H__
+
+#include "sys_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @def pmuCOUNTER0
+*   @brief pmu event counter 0 mask
+*
+*   Alias for pmu event counter 0 mask
+*
+*	@note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and _pmuStopCounters_
+*/
+#define pmuCOUNTER0 0x00000001U
+
+/** @def pmuCOUNTER1
+*   @brief pmu event counter 1 mask
+*
+*   Alias for pmu event counter 1 mask
+*
+*	@note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and _pmuStopCounters_
+*/
+#define pmuCOUNTER1 0x00000002U
+
+/** @def pmuCOUNTER2
+*   @brief pmu event counter 2 mask
+*
+*   Alias for pmu event counter 2 mask
+*
+*	@note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and _pmuStopCounters_
+*/
+#define pmuCOUNTER2 0x00000004U
+
+/** @def pmuCYCLE_COUNTER
+*   @brief pmu cycle counter mask
+*
+*   Alias for pmu event counter mask
+*
+*	@note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and _pmuStopCounters_
+*/
+#define pmuCYCLE_COUNTER 0x80000000U
+
+/** @enum pmuEvent
+*   @brief pmu event
+*
+*   Alias for pmu event counter increment source
+*/
+enum pmuEvent
+{
+    PMU_INST_CACHE_MISS                     = 0x01U,
+    PMU_DATA_CACHE_MISS                     = 0x03U,
+    PMU_DATA_CACHE_ACCESS                   = 0x04U,
+    PMU_DATA_READ_ARCH_EXECUTED             = 0x06U,
+    PMU_DATA_WRITE_ARCH_EXECUTED            = 0x07U,
+    PMU_INST_ARCH_EXECUTED                  = 0x08U,
+    PMU_EXCEPTION_TAKEN                     = 0x09U,
+    PMU_EXCEPTION_RETURN_ARCH_EXECUTED      = 0x0AU,
+    PMU_CHANGE_TO_CONTEXT_ID_EXECUTED       = 0x0BU,
+    PMU_SW_CHANGE_OF_PC_ARCH_EXECUTED       = 0x0CU,
+    PMU_BRANCH_IMM_INST_ARCH_EXECUTED       = 0x0DU,
+    PMU_PROC_RETURN_ARCH_EXECUTED           = 0x0EU,
+    PMU_UNALIGNED_ACCESS_ARCH_EXECUTED      = 0x0FU,
+    PMU_BRANCH_MISSPREDICTED                = 0x10U,
+    PMU_CYCLE_COUNT                         = 0x11U,
+    PMU_PREDICTABLE_BRANCHES                = 0x12U,
+    PMU_INST_BUFFER_STALL                   = 0x40U,
+    PMU_DATA_DEPENDENCY_INST_STALL          = 0x41U,
+    PMU_DATA_CACHE_WRITE_BACK               = 0x42U,
+    PMU_EXT_MEMORY_REQUEST                  = 0x43U,
+    PMU_LSU_BUSY_STALL                      = 0x44U,
+    PMU_FORCED_DRAIN_OFSTORE_BUFFER         = 0x45U,
+    PMU_FIQ_DISABLED_CYCLE_COUNT            = 0x46U,
+    PMU_IRQ_DISABLED_CYCLE_COUNT            = 0x47U,
+    PMU_ETMEXTOUT_0                         = 0x48U,
+    PMU_ETMEXTOUT_1                         = 0x49U,
+    PMU_INST_CACHE_TAG_ECC_ERROR            = 0x4AU,
+    PMU_INST_CACHE_DATA_ECC_ERROR           = 0x4BU,
+    PMU_DATA_CACHE_TAG_ECC_ERROR            = 0x4CU,
+    PMU_DATA_CACHE_DATA_ECC_ERROR           = 0x4DU,
+    PMU_TCM_FATAL_ECC_ERROR_PREFETCH        = 0x4EU,
+    PMU_TCM_FATAL_ECC_ERROR_LOAD_STORE      = 0x4FU,
+    PMU_STORE_BUFFER_MERGE                  = 0x50U,
+    PMU_LSU_STALL_STORE_BUFFER_FULL         = 0x51U,
+    PMU_LSU_STALL_STORE_QUEUE_FULL          = 0x52U,
+    PMU_INTEGER_DIV_EXECUTED                = 0x53U,
+    PMU_STALL_INTEGER_DIV                   = 0x54U,
+    PMU_PLD_INST_LINE_FILL                  = 0x55U,
+    PMU_PLD_INST_NO_LINE_FILL               = 0x56U,
+    PMU_NON_CACHEABLE_ACCESS_AXI_MASTER     = 0x57U,
+    PMU_INST_CACHE_ACCESS                   = 0x58U,
+    PMU_DOUBLE_DATA_CACHE_ISSUE             = 0x59U,
+    PMU_DUAL_ISSUE_CASE_A                   = 0x5AU,
+    PMU_DUAL_ISSUE_CASE_B1_B2_F2_F2D        = 0x5BU,
+    PMU_DUAL_ISSUE_OTHER                    = 0x5CU,
+    PMU_DP_FLOAT_INST_EXCECUTED             = 0x5DU,
+    PMU_DUAL_ISSUED_PAIR_INST_ARCH_EXECUTED = 0x5EU,
+    PMU_DATA_CACHE_DATA_FATAL_ECC_ERROR     = 0x60U,
+    PMU_DATA_CACHE_TAG_FATAL_ECC_ERROR      = 0x61U,
+    PMU_PROCESSOR_LIVE_LOCK                 = 0x62U,
+    PMU_ATCM_MULTI_BIT_ECC_ERROR            = 0x64U,
+    PMU_B0TCM_MULTI_BIT_ECC_ERROR           = 0x65U,
+    PMU_B1TCM_MULTI_BIT_ECC_ERROR           = 0x66U,
+    PMU_ATCM_SINGLE_BIT_ECC_ERROR           = 0x67U,
+    PMU_B0TCM_SINGLE_BIT_ECC_ERROR          = 0x68U,
+    PMU_B1TCM_SINGLE_BIT_ECC_ERROR          = 0x69U,
+    PMU_TCM_COR_ECC_ERROR_LOAD_STORE        = 0x6AU,
+    PMU_TCM_COR_ECC_ERROR_PREFETCH          = 0x6BU,
+    PMU_TCM_FATAL_ECC_ERROR_AXI_SLAVE       = 0x6CU,
+    PMU_TCM_COR_ECC_ERROR_AXI_SLAVE         = 0x6DU
+};
+
+/** @fn void _pmuInit_(void)
+*   @brief Initialize Performance Monitor Unit
+*/
+void _pmuInit_(void);
+
+/** @fn void _pmuEnableCountersGlobal_(void)
+*   @brief Enable and reset cycle counter and all 3 event counters
+*/
+void _pmuEnableCountersGlobal_(void);
+
+/** @fn void _pmuDisableCountersGlobal_(void)
+*   @brief Disable cycle counter and all 3 event counters
+*/
+void _pmuDisableCountersGlobal_(void);
+
+/** @fn void _pmuResetCycleCounter_(void)
+*   @brief Reset cycle counter
+*/
+void _pmuResetCycleCounter_(void);
+
+/** @fn void _pmuResetEventCounters_(void)
+*   @brief Reset event counters 0-2
+*/
+void _pmuResetEventCounters_(void);
+
+/** @fn void _pmuResetCounters_(void)
+*   @brief Reset cycle counter and event counters 0-2
+*/
+void _pmuResetCounters_(void);
+
+/** @fn void _pmuStartCounters_(uint32 counters)
+*   @brief Starts selected counters
+*   @param[in] counters - Counter mask
+*/
+void _pmuStartCounters_(uint32 counters);
+
+/** @fn void _pmuStopCounters_(uint32 counters)
+*   @brief Stops selected counters
+*   @param[in] counters - Counter mask
+*/
+void _pmuStopCounters_(uint32 counters);
+
+/** @fn void _pmuSetCountEvent_(uint32 counter, uint32 event)
+*   @brief Set event counter count event
+*   @param[in] counter - Counter select 0..2
+*   @param[in] event   - Count event
+*/
+void _pmuSetCountEvent_(uint32 counter, uint32 event);
+
+/** @fn uint32 _pmuGetCycleCount_(void)
+*   @brief Returns current cycle counter value
+*
+*   @return cycle count.
+*/
+uint32 _pmuGetCycleCount_(void);
+
+/** @fn uint32 _pmuGetEventCount_(uint32 counter)
+*   @brief Returns current event counter value
+*   @param[in] counter - Counter select 0..2
+*
+*   @return event counter count.
+*/
+uint32 _pmuGetEventCount_(uint32 counter);
+
+/** @fn uint32 _pmuGetOverflow_(void)
+*   @brief Returns current overflow register and clear flags
+*
+*   @return overflow flags.
+*/
+uint32 _pmuGetOverflow_(void);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/sys_selftest.h b/include/arch/rm46l8lp/halcogen/sys_selftest.h
new file mode 100644
index 0000000..fcdcfac
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/sys_selftest.h
@@ -0,0 +1,471 @@
+/** @file sys_selftest.h
+*   @brief System Memory Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Efuse Self Test Functions
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __sys_selftest_H__
+#define __sys_selftest_H__
+
+#include "reg_pbist.h"
+#include "reg_stc.h"
+#include "reg_efc.h"
+#include "sys_core.h"
+#include "system.h"
+#include "sys_vim.h"
+#include "adc.h"
+#include "can.h"
+#include "mibspi.h"
+#include "het.h"
+#include "htu.h"
+#include "esm.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#define flash1bitError	(*(volatile uint32 *)(0xF00803F0U))
+#define flash2bitError	(*(volatile uint32 *)(0xF00803F8U))
+
+#define tcramA1bitError	(*(volatile uint32 *)(0x08400000U))
+#define tcramA2bitError (*(volatile uint32 *)(0x08400010U))
+
+#define tcramB1bitError	(*(volatile uint32 *)(0x08400008U))
+#define tcramB2bitError (*(volatile uint32 *)(0x08400018U))
+
+#define tcramA1bit		(*(volatile uint64 *)(0x08000000U))
+#define tcramA2bit		(*(volatile uint64 *)(0x08000010U))
+
+#define tcramB1bit		(*(volatile uint64 *)(0x08000008U))
+#define tcramB2bit		(*(volatile uint64 *)(0x08000018U))
+
+#define flashBadECC1	(*(volatile uint32 *)(0x20000000U))
+#define flashBadECC2	(*(volatile uint32 *)(0x20000010U))
+
+#define CCMSR 			(*(volatile uint32 *)(0xFFFFF600U))
+#define CCMKEYR			(*(volatile uint32 *)(0xFFFFF604U))
+
+#define DMA_PARCR		(*(volatile uint32 *)(0xFFFFF1A8U))
+#define DMA_PARADDR		(*(volatile uint32 *)(0xFFFFF1ACU))
+#define DMARAMLOC		(*(volatile uint32 *)(0xFFF80000U))
+#define DMARAMPARLOC	(*(volatile uint32 *)(0xFFF80A00U))
+
+#define MIBSPI1RAMLOC	(*(volatile uint32 *)(0xFF0E0000U))
+#define MIBSPI3RAMLOC	(*(volatile uint32 *)(0xFF0C0000U))
+#define MIBSPI5RAMLOC	(*(volatile uint32 *)(0xFF0A0000U))
+
+
+#ifndef __PBIST_H__
+#define __PBIST_H__
+
+/** @enum pbistPort
+*   @brief Alias names for pbist Port number
+*
+*   This enumeration is used to provide alias names for the pbist Port number
+*     - PBIST_PORT0
+*     - PBIST_PORT1
+*
+*   @note Check the datasheet for the port avaiability
+*/
+enum pbistPort
+{
+    PBIST_PORT0 = 0U, /**< Alias for PBIST Port 0 */
+    PBIST_PORT1 = 1U  /**< Alias for PBIST Port 1 < Check datasheet for Port 1 availability > */
+};
+/** @enum pbistAlgo
+*   @brief Alias names for pbist Algorithm
+*
+*   This enumeration is used to provide alias names for the pbist Algorithm
+*/
+enum pbistAlgo
+{
+    PBIST_TripleReadSlow     = 0x00000001U,  /**<TRIPLE_READ_SLOW_READ  for PBIST and STC ROM*/
+    PBIST_TripleReadFast     = 0x00000002U,  /**<TRIPLE_READ_SLOW_READ  for PBIST and STC ROM*/
+    PBIST_March13N_DP        = 0x00000004U,  /**< March13 N Algo for 2 Port mem */
+	PBIST_March13N_SP        = 0x00000008U,  /**< March13 N Algo for 1 Port mem */
+    PBIST_DOWN1a_DP          = 0x00000010U,  /**< Down1a Algor forces the switching fo all data bits & most addr bits on consecutive read cycles */
+	PBIST_DOWN1a_SP          = 0x00000020U,  /**< Down1a Algor forces the switching fo all data bits & most addr bits on consecutive read cycles */
+    PBIST_MapColumn_DP       = 0x00000040U,  /**< Map Column algo (to identify bit line senstivities) for 2 Port memory */
+	PBIST_MapColumn_SP       = 0x00000080U,  /**< Map Column algo (to identify bit line senstivities) for 1 Port memory */
+    PBIST_Precharge_DP       = 0x00000100U,  /**< Pre-Charge algo to exercise pre-charge capability for 2 port memory */
+	PBIST_Precharge_SP       = 0x00000200U,  /**< Pre-Charge algo to exercise pre-charge capability for 1 port memory */
+    PBIST_DTXN2a_DP          = 0x00000400U,  /**< Global column decode logic algo for 2 Port memories*/
+	PBIST_DTXN2a_SP          = 0x00000800U,  /**< Global column decode logic algo for 1 Port memories*/
+	PBIST_PMOSOpen_DP        = 0x00001000U,  /**<pmos oper algo for 2 port memories*/
+    PBIST_PMOSOpen_SP        = 0x00002000U,  /**<pmos oper algo for 1 port memories*/
+	PBIST_PPMOSOpenSlice1_DP = 0x00004000U,  /**<pmos open slice1 for 2port memories*/
+	PBIST_PPMOSOpenSlice2_DP = 0x00008000U,  /**<pmos open slice2 for 2port memories*/
+	PBIST_Flip10_DP          = 0x00010000U,  /**<flip10 algo for 2 port memories*/
+	PBIST_Flip10_SP          = 0x00020000U,  /**<flip10  algo for 1 port memories*/
+	PBIST_IDDQ_DP            = 0x00040000U,  /**<iddq  algo for 2 port memories*/
+	PBIST_IDDQ_SP            = 0x00080000U,  /**<iddq  algo for 1 port memories*/
+	PBIST_Retention_DP       = 0x00100000U,  /**<retention  algo for 2 port memories*/
+	PBIST_Retention_SP       = 0x00200000U,  /**<retention  algo for 1 port memories*/
+	PBIST_IDDQ2_DP           = 0x00400000U,  /**<iddq2  algo for 2 port memories*/
+	PBIST_IDDQ2_SP           = 0x00800000U,  /**<iddq2  algo for 1 port memories*/
+	PBIST_Retention2_DP      = 0x01000000U,  /**<retention2  algo for 2 port memories*/
+	PBIST_Retention2_SP      = 0x02000000U,  /**<retention2  algo for 1 port memories*/
+	PBIST_IDDQRowStripe_DP   = 0x04000000U,  /**<iddqwstripe  algo for 2 port memories*/
+	PBIST_IDDQRowStripe_SP   = 0x08000000U,  /**<iddqwstripe  algo for 1 port memories*/
+	PBIST_IDDQRowStripe2_DP  = 0x10000000U,  /**<iddqwstripe2  algo for 2 port memories*/
+	PBIST_IDDQRowStripe2_SP  = 0x20000000U   /**<iddqwstripe2  algo for 1 port memories*/
+};
+/* PBIST configuration registers */
+typedef struct pbist_config_reg
+{
+    uint32 CONFIG_RAMT;
+    uint32 CONFIG_DLR;
+    uint32 CONFIG_PACT;
+    uint32 CONFIG_PBISTID;
+    uint32 CONFIG_OVER;
+    uint32 CONFIG_FSRDL1;
+    uint32 CONFIG_ROM;
+    uint32 CONFIG_ALGO;
+    uint32 CONFIG_RINFOL;
+    uint32 CONFIG_RINFOU;
+} pbist_config_reg_t;
+
+/* PBIST and STC ROM - PBIST RAM GROUPING */
+#define PBIST_ROM_PBIST_RAM_GROUP   1U
+#define STC_ROM_PBIST_RAM_GROUP     2U
+
+/* PBIST congiruration registers initial value */
+#define PBIST_RAMT_CONFIGVALUE 0U
+#define PBIST_DLR_CONFIGVALUE 0U
+#define PBIST_PACT_CONFIGVALUE 0U
+#define PBIST_PBISTID_CONFIGVALUE 0U
+#define PBIST_OVER_CONFIGVALUE 0U
+#define PBIST_FSRDL1_CONFIGVALUE 0U
+#define PBIST_ROM_CONFIGVALUE 0U
+#define PBIST_ALGO_CONFIGVALUE 0U
+#define PBIST_RINFOL_CONFIGVALUE 0U
+#define PBIST_RINFOU_CONFIGVALUE 0U
+
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
+*   @brief Memory Port 0 test fail notification
+*   @param[in] groupSelect Failing Ram group select:
+*   @param[in] dataSelect Failing Ram data select:
+*   @param[in] address Failing Ram offset:
+*   @param[in] data Failing data at address:
+*
+*   @note This function has to be provide by the user.
+*/
+void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data);
+
+/** @fn void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
+*   @brief Memory Port 1 test fail notification
+*   @param[in] groupSelect Failing Ram group select:
+*   @param[in] dataSelect Failing Ram data select:
+*   @param[in] address Failing Ram offset:
+*   @param[in] data Failing data at address:
+*
+*   @note This function has to be provide by the user.
+*/
+void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data);
+
+void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type);
+#endif
+
+#ifndef __STC_H__
+#define __STC_H__
+
+/* STC General Definitions */
+
+/* STC Test Intervals supported in the Device */
+#define STC_INTERVAL 24U
+#define STC_MAX_TIMEOUT 0xFFFFFFFFU
+
+
+
+/* Configuration registers */
+typedef struct stc_config_reg
+{
+	uint32 CONFIG_STCGCR0;
+    uint32 CONFIG_STCGCR1;
+    uint32 CONFIG_STCTPR;
+    uint32 CONFIG_STCSCSCR;
+} stc_config_reg_t;
+
+/* Configuration registers initial value */
+#define STC_STCGCR0_CONFIGVALUE	0xFFFF0000U
+#define STC_STCGCR1_CONFIGVALUE	0x5U
+#define STC_STCTPR_CONFIGVALUE	0xFFFFFFFFU
+#define STC_STCSCSCR_CONFIGVALUE 0x5U
+
+void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type);
+
+#endif
+
+#ifndef __EFC_H__
+#define __EFC_H__
+
+#define INPUT_ENABLE         0x0000000FU
+#define INPUT_DISABLE        0x00000000U
+
+#define SYS_WS_READ_STATES   0x00000000U
+
+
+#define SYS_REPAIR_EN_0      0x00000000U
+#define SYS_REPAIR_EN_3      0x00000100U
+#define SYS_REPAIR_EN_5      0x00000200U
+
+#define SYS_DEID_AUTOLOAD_EN 0x00000400U
+
+#define EFC_FDI_EN            0x00000800U
+#define EFC_FDI_DIS           0x00000000U
+
+#define SYS_ECC_OVERRIDE_EN   0x00001000U
+#define SYS_ECC_OVERRIDE_DIS  0x00000000U
+
+#define SYS_ECC_SELF_TEST_EN  0x00002000U
+#define SYS_ECC_SELF_TEST_DIS 0x00000000U
+
+#define OUTPUT_ENABLE         0x0003C000U
+#define OUTPUT_DISABLE        0x00000000U
+
+/*********** OUTPUT **************/
+
+#define EFC_AUTOLOAD_ERROR_EN    0x00040000U
+#define EFC_INSTRUCTION_ERROR_EN 0x00080000U
+#define EFC_INSTRUCTION_INFO_EN  0x00100000U
+#define EFC_SELF_TEST_ERROR_EN   0x00200000U
+
+
+#define EFC_AUTOLOAD_ERROR_DIS    0x00000000U
+#define EFC_INSTRUCTION_ERROR_DIS 0x00000000U
+#define EFC_INSTRUCTION_INFO_DIS  0x00000000U
+#define EFC_SELF_TEST_ERROR_DIS   0x00000000U
+
+#define DISABLE_READ_ROW0         0x00800000U
+
+/********************************************************************/
+
+#define SYS_REPAIR_0         0x00000010U
+#define SYS_REPAIR_3         0x00000010U
+#define SYS_REPAIR_5         0x00000020U
+
+#define SYS_DEID_AUTOLOAD    0x00000040U
+#define SYS_FCLRZ            0x00000080U
+#define EFC_READY            0x00000100U
+#define SYS_ECC_OVERRIDE     0x00000200U
+#define EFC_AUTOLOAD_ERROR   0x00000400U
+#define EFC_INSTRUCTION_ERROR 0x00000800U
+#define EFC_INSTRUCTION_INFO  0x00001000U
+#define SYS_ECC_SELF_TEST    0x00002000U
+#define EFC_SELF_TEST_ERROR  0x00004000U
+#define EFC_SELF_TEST_DONE   0x00008000U
+
+/**************   0x3C error status register ******************************************************/
+
+#define TIME_OUT 0x01
+#define AUTOLOAD_NO_FUSEROM_DATA      0x02U 
+#define AUTOLOAD_SIGN_FAIL            0x03U
+#define AUTOLOAD_PROG_INTERRUPT       0x04U
+#define AUTOLOAD_TWO_BIT_ERR          0x05U
+#define PROGRAME_WR_P_SET             0x06U
+#define PROGRAME_MNY_DATA_ITERTN      0x07U
+#define PROGRAME_MNY_CNTR_ITERTN      0x08U
+#define UN_PROGRAME_BIT_SET           0x09U
+#define REDUNDANT_REPAIR_ROW          0x0AU
+#define PROGRAME_MNY_CRA_ITERTN       0x0BU
+#define PROGRAME_SAME_DATA            0x0CU
+#define PROGRAME_CMP_SKIP			  0x0DU
+#define PROGRAME_ABORT                0x0EU
+#define PROGRAME_INCORRECT_KEY		  0x0FU
+#define FUSEROM_LASTROW_STUCK		  0x10U
+#define AUTOLOAD_SINGLE_BIT_ERR		  0x15U
+#define DUMPWORD_TWO_BIT_ERR	      0x16U
+#define DUMPWORD_ONE_BIT_ERR          0x17U
+#define SELF_TEST_ERROR               0x18U
+
+#define INSTRUCTION_DONE              0x20U
+
+/**************   Efuse Instruction set ******************************************************/
+
+#define TEST_UNPROGRAME_ROM  0x01000000U
+#define PROGRAME_CRA         0x02000000U 
+#define DUMP_WORD            0x04000000U
+#define LOAD_FUSE_SCAN_CHAIN 0x05000000U
+#define PROGRAME_DATA        0x07000000U
+#define RUN_AUTOLOAD_8       0x08000000U
+#define RUN_AUTOLOAD_A       0x0A000000U
+
+/* Configuration registers */
+typedef struct efc_config_reg
+{
+	uint32 CONFIG_BOUNDARY;
+	uint32 CONFIG_PINS;
+	uint32 CONFIG_SELFTESTCYCLES;
+	uint32 CONFIG_SELFTESTSIGN;
+}efc_config_reg_t;
+
+/* Configuration registers initial value */
+#define EFC_BOUNDARY_CONFIGVALUE	0x0000200FU
+#define EFC_PINS_CONFIGVALUE		0x000082E0U
+#define EFC_SELFTESTCYCLES_CONFIGVALUE	0x00000258U
+#define EFC_SELFTESTSIGN_CONFIGVALUE	0x5362F97FU
+
+void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type);
+#endif
+
+#define CCMSELFCHECK_FAIL1           1U
+#define CCMSELFCHECK_FAIL2           2U
+#define CCMSELFCHECK_FAIL3           3U
+#define CCMSELFCHECK_FAIL4           4U
+#define PBISTSELFCHECK_FAIL1         5U
+#define EFCCHECK_FAIL1               6U
+#define EFCCHECK_FAIL2               7U
+#define FMCECCCHECK_FAIL1            8U
+#define CHECKB0RAMECC_FAIL1          9U
+#define CHECKB1RAMECC_FAIL1         10U
+#define CHECKFLASHECC_FAIL1         11U
+#define VIMPARITYCHECK_FAIL1        12U
+#define DMAPARITYCHECK_FAIL1        13U
+#define HET1PARITYCHECK_FAIL1       14U
+#define HTU1PARITYCHECK_FAIL1       15U
+#define HET2PARITYCHECK_FAIL1       16U
+#define HTU2PARITYCHECK_FAIL1       17U
+#define ADC1PARITYCHECK_FAIL1       18U
+#define ADC2PARITYCHECK_FAIL1       19U
+#define CAN1PARITYCHECK_FAIL1       20U
+#define CAN2PARITYCHECK_FAIL1       21U
+#define CAN3PARITYCHECK_FAIL1       22U
+#define MIBSPI1PARITYCHECK_FAIL1    23U
+#define MIBSPI3PARITYCHECK_FAIL1    24U
+#define MIBSPI5PARITYCHECK_FAIL1    25U
+#define CHECKRAMECC_FAIL1           26U
+#define CHECKRAMECC_FAIL2           27U
+#define CHECKCLOCKMONITOR_FAIL1     28U
+#define CHECKFLASHEEPROMECC_FAIL1   29U 
+#define CHECKFLASHEEPROMECC_FAIL2   31U
+#define CHECKFLASHEEPROMECC_FAIL3   32U
+#define CHECKFLASHEEPROMECC_FAIL4   33U
+#define CHECKPLL1SLIP_FAIL1         34U
+#define CHECKRAMADDRPARITY_FAIL1    35U
+#define CHECKRAMADDRPARITY_FAIL2    36U
+#define CHECKRAMUERRTEST_FAIL1      37U
+#define CHECKRAMUERRTEST_FAIL2      38U
+#define FMCBUS1PARITYCHECK_FAIL1    39U
+#define FMCBUS1PARITYCHECK_FAIL2    40U
+#define PBISTSELFCHECK_FAIL2         41U
+#define PBISTSELFCHECK_FAIL3         42U
+
+/* safety Init Interface Functions */
+void ccmSelfCheck(void);
+
+void stcSelfCheck(void);
+void stcSelfCheckFail(void);
+void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test);
+void cpuSelfTestFail(void);
+
+void memoryInit(uint32 ram);
+
+void pbistSelfCheck(void);
+void pbistRun(uint32 raminfoL, uint32 algomask);
+void pbistStop(void);
+boolean pbistIsTestCompleted(void);
+boolean pbistIsTestPassed(void);
+boolean pbistPortTestStatus(uint32 port);
+void pbistFail(void);
+
+uint32 efcCheck(void);
+void efcSelfTest(void);
+boolean efcStuckZeroTest(void);
+boolean checkefcSelfTest(void);
+
+void fmcBus2Check(void);
+void fmcECCcheck(void);
+void fmcBus1ParityCheck(void);
+
+void checkB0RAMECC(void);
+void checkB1RAMECC(void);
+
+void checkFlashECC(void);
+
+void vimParityCheck(void);
+void dmaParityCheck(void);
+void adc1ParityCheck(void);
+void adc2ParityCheck(void);
+void het1ParityCheck(void);
+void htu1ParityCheck(void);
+void het2ParityCheck(void);
+void htu2ParityCheck(void);
+void can1ParityCheck(void);
+void can2ParityCheck(void);
+void can3ParityCheck(void);
+void mibspi1ParityCheck(void);
+void mibspi3ParityCheck(void);
+void mibspi5ParityCheck(void);
+
+void checkRAMECC(void);
+void checkClockMonitor(void);
+void checkFlashEEPROMECC(void);
+void checkPLL1Slip(void);
+void checkPLL2Slip(void);
+void checkRAMAddrParity(void);
+void checkRAMUERRTest(void);
+
+void enableParity(void);
+void disableParity(void);
+
+void custom_dabort(void);
+void selftestFailNotification(uint32 flag);
+void errata_PBIST_4(void);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/* Configuration registers */
+typedef struct ccmr4_config_reg
+{
+	uint32 CONFIG_CCMKEYR;
+}ccmr4_config_reg_t;
+
+/* Configuration registers initial value */
+#define CCMR4_CCMKEYR_CONFIGVALUE	0U
+
+void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type);
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/sys_vim.h b/include/arch/rm46l8lp/halcogen/sys_vim.h
new file mode 100644
index 0000000..6e1273e
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/sys_vim.h
@@ -0,0 +1,457 @@
+/** @file sys_vim.h
+*   @brief Vectored Interrupt Module Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - VIM Type Definitions
+*   - VIM General Definitions
+*   .
+*   which are relevant for Vectored Interrupt Controller.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_VIM_H__
+#define __SYS_VIM_H__
+
+#include "reg_vim.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* VIM Type Definitions */
+
+/** @typedef t_isrFuncPTR
+*   @brief ISR Function Pointer Type Definition
+*
+*   This type is used to access the ISR handler.
+*/
+typedef void (*t_isrFuncPTR)(void);
+
+/** @enum systemInterrupt
+*   @brief Alias names for clock sources
+*
+*   This enumeration is used to provide alias names for the clock sources:
+*     - IRQ
+*     - FIQ
+*/
+typedef enum systemInterrupt
+{
+    SYS_IRQ = 0U, /**< Alias for IRQ interrupt */
+    SYS_FIQ = 1U  /**< Alias for FIQ interrupt */
+}systemInterrupt_t;
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/* VIM General Configuration */
+
+#define VIM_CHANNELS 128U
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/* Interrupt Handlers */
+
+extern void esmHighInterrupt(void);
+extern void phantomInterrupt(void);
+extern void rtiCompare0Interrupt(void);
+extern void rtiCompare1Interrupt(void);
+extern void rtiCompare2Interrupt(void);
+extern void rtiCompare3Interrupt(void);
+extern void esmLowInterrupt(void);
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+#define VIM_PARFLG		(*(volatile uint32 *)0xFFFFFDECU)
+#define VIM_PARCTL		(*(volatile uint32 *)0xFFFFFDF0U)
+#define VIM_ADDERR		(*(volatile uint32 *)0xFFFFFDF4U)
+#define VIM_FBPARERR	(*(volatile uint32 *)0xFFFFFDF8U)
+
+#define VIMRAMPARLOC	(*(volatile uint32 *)0xFFF82400U)
+#define VIMRAMLOC		(*(volatile uint32 *)0xFFF82000U)
+
+/* Configuration registers */
+typedef struct vim_config_reg
+{
+    uint32 CONFIG_FIRQPR0;
+    uint32 CONFIG_FIRQPR1;
+    uint32 CONFIG_FIRQPR2;
+    uint32 CONFIG_FIRQPR3;
+    uint32 CONFIG_REQMASKSET0;
+    uint32 CONFIG_REQMASKSET1;
+    uint32 CONFIG_REQMASKSET2;
+    uint32 CONFIG_REQMASKSET3;
+    uint32 CONFIG_WAKEMASKSET0;
+    uint32 CONFIG_WAKEMASKSET1;
+    uint32 CONFIG_WAKEMASKSET2;
+    uint32 CONFIG_WAKEMASKSET3;
+    uint32 CONFIG_CAPEVT;
+    uint32 CONFIG_CHANCTRL[32U];
+} vim_config_reg_t;
+
+/* Configuration registers initial value */
+#define VIM_FIRQPR0_CONFIGVALUE	( (uint32)((uint32)SYS_FIQ << 0U)\
+                                | (uint32)((uint32)SYS_FIQ << 1U)\
+                                | (uint32)((uint32)SYS_IRQ << 2U)\
+                                | (uint32)((uint32)SYS_IRQ << 3U)\
+                                | (uint32)((uint32)SYS_IRQ << 4U)\
+                                | (uint32)((uint32)SYS_IRQ << 5U)\
+                                | (uint32)((uint32)SYS_IRQ << 6U)\
+                                | (uint32)((uint32)SYS_IRQ << 7U)\
+                                | (uint32)((uint32)SYS_IRQ << 8U)\
+                                | (uint32)((uint32)SYS_IRQ << 9U)\
+                                | (uint32)((uint32)SYS_IRQ << 10U)\
+                                | (uint32)((uint32)SYS_IRQ << 11U)\
+                                | (uint32)((uint32)SYS_IRQ << 12U)\
+                                | (uint32)((uint32)SYS_IRQ << 13U)\
+                                | (uint32)((uint32)SYS_IRQ << 14U)\
+                                | (uint32)((uint32)SYS_IRQ << 15U)\
+                                | (uint32)((uint32)SYS_IRQ << 16U)\
+                                | (uint32)((uint32)SYS_IRQ << 17U)\
+                                | (uint32)((uint32)SYS_IRQ << 18U)\
+                                | (uint32)((uint32)SYS_IRQ << 19U)\
+                                | (uint32)((uint32)SYS_IRQ << 20U)\
+                                | (uint32)((uint32)SYS_IRQ << 21U)\
+                                | (uint32)((uint32)SYS_IRQ << 22U)\
+                                | (uint32)((uint32)SYS_IRQ << 23U)\
+                                | (uint32)((uint32)SYS_IRQ << 24U)\
+                                | (uint32)((uint32)SYS_IRQ << 25U)\
+                                | (uint32)((uint32)SYS_IRQ << 26U)\
+                                | (uint32)((uint32)SYS_IRQ << 27U)\
+                                | (uint32)((uint32)SYS_IRQ << 28U)\
+                                | (uint32)((uint32)SYS_IRQ << 29U)\
+                                | (uint32)((uint32)SYS_IRQ << 30U)\
+                                | (uint32)((uint32)SYS_IRQ << 31U))
+					
+#define VIM_FIRQPR1_CONFIGVALUE	( (uint32)((uint32)SYS_IRQ << 0U)\
+                                | (uint32)((uint32)SYS_IRQ << 1U)\
+                                | (uint32)((uint32)SYS_IRQ << 2U)\
+                                | (uint32)((uint32)SYS_IRQ << 3U)\
+                                | (uint32)((uint32)SYS_IRQ << 4U)\
+                                | (uint32)((uint32)SYS_IRQ << 5U)\
+                                | (uint32)((uint32)SYS_IRQ << 6U)\
+                                | (uint32)((uint32)SYS_IRQ << 7U)\
+                                | (uint32)((uint32)SYS_IRQ << 8U)\
+                                | (uint32)((uint32)SYS_IRQ << 9U)\
+                                | (uint32)((uint32)SYS_IRQ << 10U)\
+                                | (uint32)((uint32)SYS_IRQ << 11U)\
+                                | (uint32)((uint32)SYS_IRQ << 12U)\
+                                | (uint32)((uint32)SYS_IRQ << 13U)\
+                                | (uint32)((uint32)SYS_IRQ << 14U)\
+                                | (uint32)((uint32)SYS_IRQ << 15U)\
+                                | (uint32)((uint32)SYS_IRQ << 16U)\
+                                | (uint32)((uint32)SYS_IRQ << 17U)\
+                                | (uint32)((uint32)SYS_IRQ << 18U)\
+                                | (uint32)((uint32)SYS_IRQ << 19U)\
+                                | (uint32)((uint32)SYS_IRQ << 20U)\
+                                | (uint32)((uint32)SYS_IRQ << 21U)\
+                                | (uint32)((uint32)SYS_IRQ << 22U)\
+                                | (uint32)((uint32)SYS_IRQ << 23U)\
+                                | (uint32)((uint32)SYS_IRQ << 24U)\
+                                | (uint32)((uint32)SYS_IRQ << 25U)\
+                                | (uint32)((uint32)SYS_IRQ << 26U)\
+                                | (uint32)((uint32)SYS_IRQ << 27U)\
+                                | (uint32)((uint32)SYS_IRQ << 28U)\
+                                | (uint32)((uint32)SYS_IRQ << 29U)\
+                                | (uint32)((uint32)SYS_IRQ << 30U)\
+                                | (uint32)((uint32)SYS_IRQ << 31U))
+					
+#define VIM_FIRQPR2_CONFIGVALUE	( (uint32)((uint32)SYS_IRQ << 0U)\
+                                | (uint32)((uint32)SYS_IRQ << 1U)\
+                                | (uint32)((uint32)SYS_IRQ << 2U)\
+                                | (uint32)((uint32)SYS_IRQ << 3U)\
+                                | (uint32)((uint32)SYS_IRQ << 4U)\
+                                | (uint32)((uint32)SYS_IRQ << 5U)\
+                                | (uint32)((uint32)SYS_IRQ << 6U)\
+                                | (uint32)((uint32)SYS_IRQ << 7U)\
+                                | (uint32)((uint32)SYS_IRQ << 8U)\
+                                | (uint32)((uint32)SYS_IRQ << 9U)\
+                                | (uint32)((uint32)SYS_IRQ << 10U)\
+                                | (uint32)((uint32)SYS_IRQ << 11U)\
+                                | (uint32)((uint32)SYS_IRQ << 12U)\
+                                | (uint32)((uint32)SYS_IRQ << 13U)\
+                                | (uint32)((uint32)SYS_IRQ << 14U)\
+                                | (uint32)((uint32)SYS_IRQ << 15U)\
+                                | (uint32)((uint32)SYS_IRQ << 16U)\
+                                | (uint32)((uint32)SYS_IRQ << 17U)\
+                                | (uint32)((uint32)SYS_IRQ << 18U)\
+                                | (uint32)((uint32)SYS_IRQ << 19U)\
+                                | (uint32)((uint32)SYS_IRQ << 20U)\
+                                | (uint32)((uint32)SYS_IRQ << 21U)\
+                                | (uint32)((uint32)SYS_IRQ << 22U)\
+                                | (uint32)((uint32)SYS_IRQ << 23U)\
+                                | (uint32)((uint32)SYS_IRQ << 24U)\
+                                | (uint32)((uint32)SYS_IRQ << 25U)\
+					            | (uint32)((uint32)SYS_IRQ << 26U)\
+                                | (uint32)((uint32)SYS_IRQ << 27U)\
+                                | (uint32)((uint32)SYS_IRQ << 28U)\
+                                | (uint32)((uint32)SYS_IRQ << 29U)\
+                                | (uint32)((uint32)SYS_IRQ << 30U)\
+                                | (uint32)((uint32)SYS_IRQ << 31U))
+					
+#define VIM_FIRQPR3_CONFIGVALUE	( (uint32)((uint32)SYS_IRQ << 0U)\
+                                | (uint32)((uint32)SYS_IRQ << 1U)\
+                                | (uint32)((uint32)SYS_IRQ << 2U)\
+                                | (uint32)((uint32)SYS_IRQ << 3U)\
+                                | (uint32)((uint32)SYS_IRQ << 4U)\
+                                | (uint32)((uint32)SYS_IRQ << 5U)\
+                                | (uint32)((uint32)SYS_IRQ << 6U)\
+                                | (uint32)((uint32)SYS_IRQ << 7U)\
+                                | (uint32)((uint32)SYS_IRQ << 8U)\
+                                | (uint32)((uint32)SYS_IRQ << 9U)\
+                                | (uint32)((uint32)SYS_IRQ << 10U)\
+                                | (uint32)((uint32)SYS_IRQ << 11U)\
+                                | (uint32)((uint32)SYS_IRQ << 12U)\
+                                | (uint32)((uint32)SYS_IRQ << 13U)\
+                                | (uint32)((uint32)SYS_IRQ << 14U)\
+                                | (uint32)((uint32)SYS_IRQ << 15U)\
+                                | (uint32)((uint32)SYS_IRQ << 16U)\
+                                | (uint32)((uint32)SYS_IRQ << 17U)\
+                                | (uint32)((uint32)SYS_IRQ << 18U)\
+                                | (uint32)((uint32)SYS_IRQ << 19U)\
+                                | (uint32)((uint32)SYS_IRQ << 20U)\
+                                | (uint32)((uint32)SYS_IRQ << 21U)\
+                                | (uint32)((uint32)SYS_IRQ << 22U)\
+                                | (uint32)((uint32)SYS_IRQ << 23U)\
+                                | (uint32)((uint32)SYS_IRQ << 24U)\
+                                | (uint32)((uint32)SYS_IRQ << 25U)\
+					            | (uint32)((uint32)SYS_IRQ << 26U)\
+                                | (uint32)((uint32)SYS_IRQ << 27U)\
+                                | (uint32)((uint32)SYS_IRQ << 28U)\
+                                | (uint32)((uint32)SYS_IRQ << 29U)\
+                                | (uint32)((uint32)SYS_IRQ << 30U)\
+                                | (uint32)((uint32)SYS_IRQ << 31U))
+					
+#define VIM_REQMASKSET0_CONFIGVALUE	( (uint32)((uint32)1U << 0U)\
+                                    | (uint32)((uint32)1U << 1U)\
+                                    | (uint32)((uint32)1U << 2U)\
+                                    | (uint32)((uint32)1U << 3U)\
+                                    | (uint32)((uint32)1U << 4U)\
+                                    | (uint32)((uint32)1U << 5U)\
+                                    | (uint32)((uint32)0U << 6U)\
+                                    | (uint32)((uint32)0U << 7U)\
+                                    | (uint32)((uint32)0U << 8U)\
+                                    | (uint32)((uint32)0U << 9U)\
+                                    | (uint32)((uint32)0U << 10U)\
+                                    | (uint32)((uint32)0U << 11U)\
+                                    | (uint32)((uint32)0U << 12U)\
+                                    | (uint32)((uint32)0U << 13U)\
+                                    | (uint32)((uint32)0U << 14U)\
+                                    | (uint32)((uint32)0U << 15U)\
+                                    | (uint32)((uint32)0U << 16U)\
+                                    | (uint32)((uint32)0U << 17U)\
+                                    | (uint32)((uint32)0U << 18U)\
+                                    | (uint32)((uint32)0U << 19U)\
+                                    | (uint32)((uint32)1U << 20U)\
+                                    | (uint32)((uint32)0U << 21U)\
+                                    | (uint32)((uint32)0U << 22U)\
+                                    | (uint32)((uint32)0U << 23U)\
+                                    | (uint32)((uint32)0U << 24U)\
+                                    | (uint32)((uint32)0U << 25U)\
+                                    | (uint32)((uint32)0U << 26U)\
+                                    | (uint32)((uint32)0U << 27U)\
+                                    | (uint32)((uint32)0U << 28U)\
+                                    | (uint32)((uint32)0U << 29U)\
+                                    | (uint32)((uint32)0U << 30U)\
+                                    | (uint32)((uint32)0U << 31U))
+						
+#define VIM_REQMASKSET1_CONFIGVALUE	( (uint32)((uint32)0U << 0U)\
+                                    | (uint32)((uint32)0U << 1U)\
+                                    | (uint32)((uint32)0U << 2U)\
+                                    | (uint32)((uint32)0U << 3U)\
+                                    | (uint32)((uint32)0U << 4U)\
+                                    | (uint32)((uint32)0U << 5U)\
+                                    | (uint32)((uint32)0U << 6U)\
+                                    | (uint32)((uint32)0U << 7U)\
+                                    | (uint32)((uint32)0U << 8U)\
+                                    | (uint32)((uint32)0U << 9U)\
+                                    | (uint32)((uint32)0U << 10U)\
+                                    | (uint32)((uint32)0U << 11U)\
+                                    | (uint32)((uint32)0U << 12U)\
+                                    | (uint32)((uint32)0U << 13U)\
+                                    | (uint32)((uint32)0U << 14U)\
+                                    | (uint32)((uint32)0U << 15U)\
+                                    | (uint32)((uint32)0U << 16U)\
+                                    | (uint32)((uint32)0U << 17U)\
+                                    | (uint32)((uint32)0U << 18U)\
+                                    | (uint32)((uint32)0U << 19U)\
+                                    | (uint32)((uint32)0U << 20U)\
+                                    | (uint32)((uint32)0U << 21U)\
+                                    | (uint32)((uint32)0U << 22U)\
+                                    | (uint32)((uint32)0U << 23U)\
+                                    | (uint32)((uint32)0U << 24U)\
+                                    | (uint32)((uint32)0U << 25U)\
+                                    | (uint32)((uint32)0U << 26U)\
+                                    | (uint32)((uint32)0U << 27U)\
+                                    | (uint32)((uint32)0U << 28U)\
+                                    | (uint32)((uint32)0U << 29U)\
+                                    | (uint32)((uint32)0U << 30U)\
+                                    | (uint32)((uint32)0U << 31U))
+						
+#define VIM_REQMASKSET2_CONFIGVALUE	( (uint32)((uint32)0U << 0U)\
+                                    | (uint32)((uint32)0U << 1U)\
+                                    | (uint32)((uint32)0U << 2U)\
+                                    | (uint32)((uint32)0U << 3U)\
+                                    | (uint32)((uint32)0U << 4U)\
+                                    | (uint32)((uint32)0U << 5U)\
+                                    | (uint32)((uint32)0U << 6U)\
+                                    | (uint32)((uint32)0U << 7U)\
+                                    | (uint32)((uint32)0U << 8U)\
+                                    | (uint32)((uint32)0U << 9U)\
+                                    | (uint32)((uint32)0U << 10U)\
+                                    | (uint32)((uint32)0U << 11U)\
+                                    | (uint32)((uint32)0U << 12U)\
+                                    | (uint32)((uint32)0U << 13U)\
+                                    | (uint32)((uint32)0U << 14U)\
+                                    | (uint32)((uint32)0U << 15U)\
+                                    | (uint32)((uint32)0U << 16U)\
+                                    | (uint32)((uint32)0U << 17U)\
+                                    | (uint32)((uint32)0U << 18U)\
+                                    | (uint32)((uint32)0U << 19U)\
+                                    | (uint32)((uint32)0U << 20U)\
+                                    | (uint32)((uint32)0U << 21U)\
+                                    | (uint32)((uint32)0U << 22U)\
+                                    | (uint32)((uint32)0U << 23U)\
+                                    | (uint32)((uint32)0U << 24U)\
+                                    | (uint32)((uint32)0U << 25U)\
+					                | (uint32)((uint32)0U << 26U)\
+                                    | (uint32)((uint32)0U << 27U)\
+                                    | (uint32)((uint32)0U << 28U)\
+                                    | (uint32)((uint32)0U << 29U)\
+                                    | (uint32)((uint32)0U << 30U)\
+                                    | (uint32)((uint32)0U << 31U))
+						
+#define VIM_REQMASKSET3_CONFIGVALUE	( (uint32)((uint32)0U << 0U)\
+                                    | (uint32)((uint32)0U << 1U)\
+                                    | (uint32)((uint32)0U << 2U)\
+                                    | (uint32)((uint32)0U << 3U)\
+                                    | (uint32)((uint32)0U << 4U)\
+                                    | (uint32)((uint32)0U << 5U)\
+                                    | (uint32)((uint32)0U << 6U)\
+                                    | (uint32)((uint32)0U << 7U)\
+                                    | (uint32)((uint32)0U << 8U)\
+                                    | (uint32)((uint32)0U << 9U)\
+                                    | (uint32)((uint32)0U << 10U)\
+                                    | (uint32)((uint32)0U << 11U)\
+                                    | (uint32)((uint32)0U << 12U)\
+                                    | (uint32)((uint32)0U << 13U)\
+                                    | (uint32)((uint32)0U << 14U)\
+                                    | (uint32)((uint32)0U << 15U)\
+                                    | (uint32)((uint32)0U << 16U)\
+                                    | (uint32)((uint32)0U << 17U)\
+                                    | (uint32)((uint32)0U << 18U)\
+                                    | (uint32)((uint32)0U << 19U)\
+                                    | (uint32)((uint32)0U << 20U)\
+                                    | (uint32)((uint32)0U << 21U)\
+                                    | (uint32)((uint32)0U << 22U)\
+                                    | (uint32)((uint32)0U << 23U)\
+                                    | (uint32)((uint32)0U << 24U)\
+                                    | (uint32)((uint32)0U << 25U)\
+						            | (uint32)((uint32)0U << 26U)\
+                                    | (uint32)((uint32)0U << 27U)\
+                                    | (uint32)((uint32)0U << 28U)\
+                                    | (uint32)((uint32)0U << 29U)\
+                                    | (uint32)((uint32)0U << 30U)\
+                                    | (uint32)((uint32)0U << 31U))
+						
+#define VIM_WAKEMASKSET0_CONFIGVALUE	0xFFFFFFFFU
+#define VIM_WAKEMASKSET1_CONFIGVALUE	0xFFFFFFFFU
+#define VIM_WAKEMASKSET2_CONFIGVALUE	0xFFFFFFFFU
+#define VIM_WAKEMASKSET3_CONFIGVALUE	0xFFFFFFFFU
+#define VIM_CAPEVT_CONFIGVALUE	    	((uint32)((uint32)0U << 0U)|(uint32)((uint32)0U << 16U))
+
+#define VIM_CHANCTRL0_CONFIGVALUE		0x00010203U
+#define VIM_CHANCTRL1_CONFIGVALUE		0x04050607U
+#define VIM_CHANCTRL2_CONFIGVALUE		0x08090A0BU
+#define VIM_CHANCTRL3_CONFIGVALUE		0x0C0D0E0FU
+#define VIM_CHANCTRL4_CONFIGVALUE		0x10111213U
+#define VIM_CHANCTRL5_CONFIGVALUE		0x14151617U
+#define VIM_CHANCTRL6_CONFIGVALUE		0x18191A1BU
+#define VIM_CHANCTRL7_CONFIGVALUE		0x1C1D1E1FU
+#define VIM_CHANCTRL8_CONFIGVALUE		0x20212223U
+#define VIM_CHANCTRL9_CONFIGVALUE		0x24252627U
+#define VIM_CHANCTRL10_CONFIGVALUE		0x28292A2BU
+#define VIM_CHANCTRL11_CONFIGVALUE		0x2C2D2E2FU
+#define VIM_CHANCTRL12_CONFIGVALUE		0x30313233U
+#define VIM_CHANCTRL13_CONFIGVALUE		0x34353637U
+#define VIM_CHANCTRL14_CONFIGVALUE		0x38393A3BU
+#define VIM_CHANCTRL15_CONFIGVALUE		0x3C3D3E3FU
+#define VIM_CHANCTRL16_CONFIGVALUE		0x40414243U
+#define VIM_CHANCTRL17_CONFIGVALUE		0x44454647U
+#define VIM_CHANCTRL18_CONFIGVALUE		0x48494A4BU
+#define VIM_CHANCTRL19_CONFIGVALUE		0x4C4D4E4FU
+#define VIM_CHANCTRL20_CONFIGVALUE		0x50515253U
+#define VIM_CHANCTRL21_CONFIGVALUE		0x54555657U
+#define VIM_CHANCTRL22_CONFIGVALUE		0x58595A5BU
+#define VIM_CHANCTRL23_CONFIGVALUE		0x5C5D5E5FU
+#define VIM_CHANCTRL24_CONFIGVALUE      0x60616263U
+#define VIM_CHANCTRL25_CONFIGVALUE      0x64656667U
+#define VIM_CHANCTRL26_CONFIGVALUE      0x68696A6BU
+#define VIM_CHANCTRL27_CONFIGVALUE      0x6C6D6E6FU
+#define VIM_CHANCTRL28_CONFIGVALUE      0x70717273U
+#define VIM_CHANCTRL29_CONFIGVALUE      0x74757677U
+#define VIM_CHANCTRL30_CONFIGVALUE      0x78797A7BU
+#define VIM_CHANCTRL31_CONFIGVALUE      0x7C7D7E7FU
+
+
+/**
+ * @defgroup VIM VIM
+ * @brief Vectored Interrupt Manager
+ *
+ * The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the
+ * many interrupt sources present on a device. Interrupts are caused by events outside of the normal flow of
+ * program execution.
+ *
+ * Related files:
+ * - reg_vim.h
+ * - sys_vim.h
+ * - sys_vim.c
+ *
+ * @addtogroup VIM
+ * @{
+ */
+/*VIM Interface functions*/
+void vimInit(void);
+void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler);
+void vimEnableInterrupt(uint32 channel, systemInterrupt_t inttype);
+void vimDisableInterrupt(uint32 channel);
+void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type);
+/*@}*/
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/system.h b/include/arch/rm46l8lp/halcogen/system.h
new file mode 100644
index 0000000..2b27c67
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/system.h
@@ -0,0 +1,510 @@
+/** @file system.h
+*   @brief System Driver Header File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*   
+*   This file contains:
+*   - Definitions
+*   - Types
+*   .
+*   which are relevant for the System driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_SYSTEM_H__
+#define __SYS_SYSTEM_H__
+
+#include "reg_system.h"
+#include "reg_flash.h"
+#include "reg_tcram.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* System General Definitions */
+
+/** @enum systemClockSource
+*   @brief Alias names for clock sources
+*
+*   This enumeration is used to provide alias names for the clock sources:
+*     - Oscillator
+*     - Pll1
+*     - External1
+*     - Low Power Oscillator Low
+*     - Low Power Oscillator High
+*     - PLL2
+*     - External2
+*     - Synchronous VCLK1
+*/
+enum systemClockSource
+{
+    SYS_OSC             = 0U,  /**< Alias for oscillator clock Source                */
+    SYS_PLL1            = 1U,  /**< Alias for Pll1 clock Source                      */
+    SYS_EXTERNAL1       = 3U,  /**< Alias for external clock Source                  */
+    SYS_LPO_LOW         = 4U,  /**< Alias for low power oscillator low clock Source  */
+    SYS_LPO_HIGH        = 5U,  /**< Alias for low power oscillator high clock Source */
+    SYS_PLL2            = 6U,  /**< Alias for Pll2 clock Source                      */
+    SYS_EXTERNAL2       = 7U,  /**< Alias for external 2 clock Source                */
+    SYS_VCLK            = 9U   /**< Alias for synchronous VCLK1 clock Source         */
+};
+
+#define SYS_DOZE_MODE        0x000F3F02U
+#define SYS_SNOOZE_MODE      0x000F3F03U
+#define SYS_SLEEP_MODE       0x000FFFFFU
+#define LPO_TRIM_VALUE       (((*(volatile uint32 *)0xF00801B4U) & 0xFFFF0000U)>>16U)
+#define SYS_EXCEPTION        (*(volatile uint32 *)0xFFFFFFE4U)
+
+#define POWERON_RESET        0x8000U
+#define OSC_FAILURE_RESET    0x4000U
+#define WATCHDOG_RESET       0x2000U
+#define ICEPICK_RESET        0x2000U
+#define CPU_RESET            0x0020U
+#define SW_RESET             0x0010U
+
+#define WATCHDOG_STATUS     (*(volatile uint32 *)0xFFFFFC98U)
+#define DEVICE_ID_REV       (*(volatile uint32 *)0xFFFFFFF0U)
+
+/** @def OSC_FREQ
+*   @brief Oscillator clock source exported from HALCoGen GUI
+*
+*   Oscillator clock source exported from HALCoGen GUI
+*/
+#define OSC_FREQ     16.0F
+
+/** @def PLL1_FREQ
+*   @brief PLL 1 clock source exported from HALCoGen GUI
+*
+*   PLL 1 clock source exported from HALCoGen GUI
+*/
+#define PLL1_FREQ    160.00F
+
+/** @def LPO_LF_FREQ
+*   @brief LPO Low Freq Oscillator source exported from HALCoGen GUI
+*
+*   LPO Low Freq Oscillator source exported from HALCoGen GUI
+*/
+#define LPO_LF_FREQ  0.080F
+
+/** @def LPO_HF_FREQ
+*   @brief LPO High Freq Oscillator source exported from HALCoGen GUI
+*
+*   LPO High Freq Oscillator source exported from HALCoGen GUI
+*/
+#define LPO_HF_FREQ  10.000F
+
+/** @def PLL1_FREQ
+*   @brief PLL 2 clock source exported from HALCoGen GUI
+*
+*   PLL 2 clock source exported from HALCoGen GUI
+*/
+#define PLL2_FREQ    160.00F
+
+/** @def GCLK_FREQ
+*   @brief GCLK domain frequency exported from HALCoGen GUI
+*
+*   GCLK domain frequency exported from HALCoGen GUI
+*/
+#define GCLK_FREQ    160.000F
+
+/** @def HCLK_FREQ
+*   @brief HCLK domain frequency exported from HALCoGen GUI
+*
+*   HCLK domain frequency exported from HALCoGen GUI
+*/
+#define HCLK_FREQ    160.000F
+
+/** @def RTI_FREQ
+*   @brief RTI Clock frequency exported from HALCoGen GUI
+*
+*   RTI Clock frequency exported from HALCoGen GUI
+*/
+#define RTI_FREQ     80.000F
+
+/** @def AVCLK1_FREQ
+*   @brief AVCLK1 Domain frequency exported from HALCoGen GUI
+*
+*   AVCLK Domain frequency exported from HALCoGen GUI
+*/
+#define AVCLK1_FREQ  80.000F
+
+/** @def AVCLK2_FREQ
+*   @brief AVCLK2 Domain frequency exported from HALCoGen GUI
+*
+*   AVCLK2 Domain frequency exported from HALCoGen GUI
+*/
+#define AVCLK2_FREQ  80.000F
+
+/** @def AVCLK3_FREQ
+*   @brief AVCLK3 Domain frequency exported from HALCoGen GUI
+*
+*   AVCLK3 Domain frequency exported from HALCoGen GUI
+*/
+#define AVCLK3_FREQ  0.000F
+
+/** @def AVCLK4_FREQ
+*   @brief AVCLK4 Domain frequency exported from HALCoGen GUI
+*
+*   AVCLK4 Domain frequency exported from HALCoGen GUI
+*/
+#define AVCLK4_FREQ  80.000F
+
+/** @def VCLK1_FREQ
+*   @brief VCLK1 Domain frequency exported from HALCoGen GUI
+*
+*   VCLK1 Domain frequency exported from HALCoGen GUI
+*/
+#define VCLK1_FREQ   80.000F
+
+/** @def VCLK2_FREQ
+*   @brief VCLK2 Domain frequency exported from HALCoGen GUI
+*
+*   VCLK2 Domain frequency exported from HALCoGen GUI
+*/
+#define VCLK2_FREQ   80.000F
+
+/** @def VCLK3_FREQ
+*   @brief VCLK3 Domain frequency exported from HALCoGen GUI
+*
+*   VCLK3 Domain frequency exported from HALCoGen GUI
+*/
+#define VCLK3_FREQ   80.000F
+
+/** @def VCLK4_FREQ
+*   @brief VCLK4 Domain frequency exported from HALCoGen GUI
+*
+*   VCLK4 Domain frequency exported from HALCoGen GUI
+*/
+#define VCLK4_FREQ   80.000F
+
+
+/** @def SYS_PRE1
+*   @brief Alias name for RTI1CLK PRE clock source
+*
+*   This is an alias name for the RTI1CLK pre clock source.
+*   This can be either:
+*     - Oscillator
+*     - Pll
+*     - 32 kHz Oscillator
+*     - External
+*     - Low Power Oscillator Low
+*     - Low Power Oscillator High
+*     - Flexray Pll
+*/
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> " Value comes from GUI drop down option " */
+#define SYS_PRE1 (SYS_PLL1)
+
+/** @def SYS_PRE2
+*   @brief Alias name for RTI2CLK pre clock source
+*
+*   This is an alias name for the RTI2CLK pre clock source.
+*   This can be either:
+*     - Oscillator
+*     - Pll
+*     - 32 kHz Oscillator
+*     - External
+*     - Low Power Oscillator Low
+*     - Low Power Oscillator High
+*     - Flexray Pll
+*/
+/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> " Value comes from GUI drop down option " */
+#define SYS_PRE2 (SYS_PLL1)
+
+/* Configuration registers */
+typedef struct system_config_reg
+{
+    uint32 CONFIG_SYSPC1;
+    uint32 CONFIG_SYSPC2;
+    uint32 CONFIG_SYSPC7;
+    uint32 CONFIG_SYSPC8;
+    uint32 CONFIG_SYSPC9;
+    uint32 CONFIG_CSDIS;
+    uint32 CONFIG_CDDIS;
+    uint32 CONFIG_GHVSRC;
+    uint32 CONFIG_VCLKASRC;
+    uint32 CONFIG_RCLKSRC;
+    uint32 CONFIG_MSTGCR;
+    uint32 CONFIG_MINITGCR;
+    uint32 CONFIG_MSINENA;
+    uint32 CONFIG_PLLCTL1;
+    uint32 CONFIG_PLLCTL2;
+    uint32 CONFIG_UERFLAG;
+    uint32 CONFIG_LPOMONCTL;
+    uint32 CONFIG_CLKTEST;
+    uint32 CONFIG_DFTCTRLREG1;
+    uint32 CONFIG_DFTCTRLREG2;
+    uint32 CONFIG_GPREG1;
+    uint32 CONFIG_RAMGCR;
+    uint32 CONFIG_BMMCR1;
+    uint32 CONFIG_MMUGCR;
+    uint32 CONFIG_CLKCNTL;
+    uint32 CONFIG_ECPCNTL;
+    uint32 CONFIG_DEVCR1;
+    uint32 CONFIG_SYSECR;
+    uint32 CONFIG_PLLCTL3;
+    uint32 CONFIG_STCCLKDIV;
+    uint32 CONFIG_CLK2CNTL;
+    uint32 CONFIG_VCLKACON1;
+    uint32 CONFIG_CLKSLIP;
+    uint32 CONFIG_EFC_CTLEN;
+} system_config_reg_t;
+
+/* Configuration registers initial value */
+#define SYS_SYSPC1_CONFIGVALUE  0U
+
+#define SYS_SYSPC2_CONFIGVALUE  1U
+
+#define SYS_SYSPC7_CONFIGVALUE  0U
+
+#define SYS_SYSPC8_CONFIGVALUE  0U
+
+#define SYS_SYSPC9_CONFIGVALUE  1U
+
+#define SYS_CSDIS_CONFIGVALUE   ( 0x00000000U\
+                                | 0x00000000U \
+                                | 0x00000008U \
+                                | 0x00000080U \
+                                | 0x00000000U \
+                                | 0x00000000U \
+                                | 0x00000000U\
+                                | 0x4U )
+                      
+#define SYS_CDDIS_CONFIGVALUE   ( (uint32)((uint32)0U << 4U )\
+                                | (uint32)((uint32)0U << 5U )\
+                                | (uint32)((uint32)0U << 8U )\
+								| (uint32)((uint32)0U << 9U )\
+                                | (uint32)((uint32)1U << 10U)\
+                                | (uint32)((uint32)0U << 11U) )
+                      
+#define SYS_GHVSRC_CONFIGVALUE  ( (uint32)((uint32)SYS_OSC << 24U) \
+                                | (uint32)((uint32)SYS_OSC << 16U) \
+                                | (uint32)((uint32)SYS_PLL1 << 0U) )
+                                
+#define SYS_VCLKASRC_CONFIGVALUE    ( (uint32)((uint32)SYS_VCLK << 8U)\
+                                    | (uint32)((uint32)SYS_VCLK << 0U) )
+                                    
+#define SYS_RCLKSRC_CONFIGVALUE     ( (uint32)((uint32)1U << 24U)\
+                                    | (uint32)((uint32)SYS_VCLK << 16U)\
+                                    | (uint32)((uint32)1U << 8U)\
+                                    | (uint32)((uint32)SYS_VCLK << 0U) )
+                                    
+#define SYS_MSTGCR_CONFIGVALUE      0x00000105U
+
+#define SYS_MINITGCR_CONFIGVALUE    0x5U
+
+#define SYS_MSINENA_CONFIGVALUE     0U
+
+#define SYS_PLLCTL1_CONFIGVALUE_1   ( (uint32)0x00000000U \
+                                    | (uint32)0x20000000U \
+                                    | (uint32)((uint32)0x1FU << 24U) \
+                                    | (uint32)0x00000000U \
+                                    | (uint32)((uint32)(6U - 1U)<< 16U)\
+                                    | (uint32)(0x7700U))
+                                    
+#define SYS_PLLCTL1_CONFIGVALUE_2   (((SYS_PLLCTL1_CONFIGVALUE_1) & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U))
+                                    
+#define SYS_PLLCTL2_CONFIGVALUE     ( (uint32)0x00000000U\
+                                    | (uint32)((uint32)255U << 22U)\
+                                    | (uint32)((uint32)7U << 12U)\
+                                    | (uint32)((uint32)(2U - 1U)<< 9U)\
+                                    | (uint32)61U)
+                                    
+#define SYS_UERFLAG_CONFIGVALUE     0U
+
+#define SYS_LPOMONCTL_CONFIGVALUE_1 ((uint32)((uint32)1U << 24U) | LPO_TRIM_VALUE)
+#define SYS_LPOMONCTL_CONFIGVALUE_2 ((uint32)((uint32)1U << 24U) | (uint32)((uint32)16U << 8U) | 16U)
+
+#define SYS_CLKTEST_CONFIGVALUE     0x000A0000U
+
+#define SYS_DFTCTRLREG1_CONFIGVALUE 0x00002205U
+
+#define SYS_DFTCTRLREG2_CONFIGVALUE 0x5U
+
+#define SYS_GPREG1_CONFIGVALUE      0x0005FFFFU
+                                    
+#define SYS_RAMGCR_CONFIGVALUE      0x00050000U
+                                    
+#define SYS_BMMCR1_CONFIGVALUE      0xAU
+                                    
+#define SYS_MMUGCR_CONFIGVALUE      0U
+
+#define SYS_CLKCNTL_CONFIGVALUE     ( 0x00000100U \
+                                    | (uint32)((uint32)1U << 16U) \
+                                    | (uint32)((uint32)1U << 24U) ) 
+                                    
+#define SYS_ECPCNTL_CONFIGVALUE     ( (uint32)((uint32)0U << 24U)\
+                                    | (uint32)((uint32)0U << 23U)\
+                                    | (uint32)((uint32)(8U - 1U) & 0xFFFFU) )
+                                    
+#define SYS_DEVCR1_CONFIGVALUE      0xAU
+                                    
+#define SYS_SYSECR_CONFIGVALUE      0x00004000U
+#define SYS2_PLLCTL3_CONFIGVALUE_1  ( (uint32)((uint32)(2U - 1U) << 29U)\
+                                    | (uint32)((uint32)0x1FU << 24U) \
+                                    | (uint32)((uint32)(6U - 1U)<< 16U) \
+                                    | (uint32)(0x7700U))
+                                    
+#define SYS2_PLLCTL3_CONFIGVALUE_2  (((SYS2_PLLCTL3_CONFIGVALUE_1) & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U))
+#define SYS2_STCCLKDIV_CONFIGVALUE  0U
+#define SYS2_CLK2CNTL_CONFIGVALUE   (1U | 0x00000100U)
+#define SYS2_VCLKACON1_CONFIGVALUE  ( (uint32)((uint32)1U << 24U) \
+                                    | (uint32)((uint32)1U << 20U) \
+                                    | (uint32)((uint32)SYS_VCLK << 16U)\
+                                    | (uint32)((uint32)1U << 8U)\
+                                    | (uint32)((uint32)1U << 4U) \
+                                    | (uint32)((uint32)SYS_VCLK << 0U) )
+#define SYS2_CLKSLIP_CONFIGVALUE    0x5U
+#define SYS2_EFC_CTLEN_CONFIGVALUE  0x5U
+    
+void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/* FlashW General Definitions */
+
+
+/** @enum flashWPowerModes
+*   @brief Alias names for flash bank power modes
+*
+*   This enumeration is used to provide alias names for the flash bank power modes:
+*     - sleep
+*     - standby
+*     - active
+*/
+enum flashWPowerModes
+{
+    SYS_SLEEP   = 0U, /**< Alias for flash bank power mode sleep   */
+    SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */
+    SYS_ACTIVE  = 3U  /**< Alias for flash bank power mode active  */
+};
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+#define FSM_WR_ENA_HL       (*(volatile uint32 *)0xFFF87288U)
+#define EEPROM_CONFIG_HL    (*(volatile uint32 *)0xFFF872B8U)
+
+/* Configuration registers */
+typedef struct tcmflash_config_reg
+{
+    uint32 CONFIG_FRDCNTL;
+    uint32 CONFIG_FEDACCTRL1;
+    uint32 CONFIG_FEDACCTRL2;
+    uint32 CONFIG_FEDACSDIS;
+    uint32 CONFIG_FBPROT;
+    uint32 CONFIG_FBSE;
+    uint32 CONFIG_FBAC;
+    uint32 CONFIG_FBFALLBACK;
+    uint32 CONFIG_FPAC1;
+    uint32 CONFIG_FPAC2;
+    uint32 CONFIG_FMAC;
+    uint32 CONFIG_FLOCK;
+    uint32 CONFIG_FDIAGCTRL;
+    uint32 CONFIG_FEDACSDIS2;
+} tcmflash_config_reg_t;
+
+/* Configuration registers initial value */
+#define TCMFLASH_FRDCNTL_CONFIGVALUE        (0x00000000U | (uint32)((uint32)3U << 8U) | (uint32)((uint32)1U << 4U) |  1U)
+#define TCMFLASH_FEDACCTRL1_CONFIGVALUE     0x000A0005U
+#define TCMFLASH_FEDACCTRL2_CONFIGVALUE     0U
+#define TCMFLASH_FEDACSDIS_CONFIGVALUE      0U
+#define TCMFLASH_FBPROT_CONFIGVALUE         0U
+#define TCMFLASH_FBSE_CONFIGVALUE           0U
+#define TCMFLASH_FBAC_CONFIGVALUE           0xFU
+#define TCMFLASH_FBFALLBACK_CONFIGVALUE     ( (uint32)((uint32)SYS_ACTIVE << 14U) \
+                                            | (uint32)((uint32)3U << 12U) \
+                                            | (uint32)((uint32)3U << 10U) \
+                                            | (uint32)((uint32)3U << 8U) \
+                                            | (uint32)((uint32)3U << 6U) \
+                                            | (uint32)((uint32)3U << 4U) \
+                                            | (uint32)((uint32)SYS_ACTIVE << 2U) \
+                                            | (uint32)((uint32)SYS_ACTIVE << 0U) )
+                          
+#define TCMFLASH_FPAC1_CONFIGVALUE          0x00C80001U
+#define TCMFLASH_FPAC2_CONFIGVALUE          0U
+#define TCMFLASH_FMAC_CONFIGVALUE           0U
+#define TCMFLASH_FLOCK_CONFIGVALUE          0x55AAU
+#define TCMFLASH_FDIAGCTRL_CONFIGVALUE      0x000A0000U
+#define TCMFLASH_FEDACSDIS2_CONFIGVALUE     0U
+
+void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+
+/* System Interface Functions */
+void setupPLL(void);
+void trimLPO(void);
+void customTrimLPO(void);
+void setupFlash(void);
+void periphInit(void);
+void mapClocks(void);
+void systemInit(void);
+void systemPowerDown(uint32 mode);
+
+/*Configuration registers
+* index 0: Even RAM
+* index 1: Odd RAM
+*/
+typedef struct sram_config_reg
+{
+    uint32 CONFIG_RAMCTRL[2U];
+    uint32 CONFIG_RAMTHRESHOLD[2U];
+    uint32 CONFIG_RAMINTCTRL[2U];
+    uint32 CONFIG_RAMTEST[2U];
+    uint32 CONFIG_RAMADDRDECVECT[2U];
+} sram_config_reg_t;
+
+/* Configuration registers initial value */
+#define SRAM_RAMCTRL_CONFIGVALUE        0x0005000AU
+#define SRAM_RAMTHRESHOLD_CONFIGVALUE   1U
+#define SRAM_RAMINTCTRL_CONFIGVALUE 1U
+#define SRAM_RAMTEST_CONFIGVALUE        0x5U
+#define SRAM_RAMADDRDECVECT_CONFIGVALUE 0U
+
+void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type);
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/ti_fee.h b/include/arch/rm46l8lp/halcogen/ti_fee.h
new file mode 100644
index 0000000..40800ef
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/ti_fee.h
@@ -0,0 +1,504 @@
+/**********************************************************************************************************************
+ *  FILE DESCRIPTION
+ *  -------------------------------------------------------------------------------------------------------------------
+ *         File:  ti_fee.h
+ *      Project:  Tms570_TIFEEDriver
+ *       Module:  TIFEEDriver
+ *    Generator:  None
+ *
+ *  Description:  This file implements the TI FEE Api.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author:  Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version        Date         Author               Change ID        Description
+ *---------------------------------------------------------------------------------------------------------------------
+ * 00.01.00       31Aug2012    Vishwanath Reddy     0000000000000    Initial Version 
+ * 00.01.01       29Oct2012    Vishwanath Reddy     0000000000000    Changes for implementing Error Recovery
+ * 00.01.02       30Nov2012    Vishwanath Reddy     SDOCM00097786    Misra Fixes, Memory segmentation changes.
+ * 00.01.03       14Jan2013    Vishwanath Reddy     SDOCM00098510    Changes as requested by Vector.
+ * 00.01.04		  12Feb2012	   Vishwanath Reddy     SDOCM00099152    Integration issues fix. 
+ * 00.01.05		  04Mar2013	   Vishwanath Reddy     SDOCM00099152    Added Deleting a block feature, bug fixes. 
+ * 00.01.06		  11Mar2013	   Vishwanath Reddy     SDOCM00099152    Added feature : copying of unconfigured blocks. 
+ * 00.01.07		  15Mar2013	   Vishwanath Reddy     SDOCM00099152    Added feature : Number of 8 bytes writes, fixed 
+																	 issue with copy blocks. 
+ * 00.01.08		  05Apr2013	   Vishwanath Reddy     SDOCM00099152    Added feature : CRC check for unconfigured  blocks,
+																	 Main function modified to complete writes as fast 
+																	 as possible, Added Non polling mode support.
+ * 00.01.09		  19Apr2013	   Vishwanath Reddy     SDOCM00099152    Warning removal, Added feature comparision of data  
+																	 during write.	
+ * 00.01.10       11Jun2013	   Vishwanath Reddy     SDOCM00101845	 Updated version information.																	 
+ * 00.01.11       05Jul2013	   Vishwanath Reddy     SDOCM00101643	 Updated version information.	
+ * 01.12.00		  13Dec2013    Vishwanath Reddy     SDOCM00105412    Traceability tags added. 
+ *                                                                   MISRA C fixes.	Version info corrected. 
+ * 01.13.00       30Dec2013	   Vishwanath Reddy     0000000000000	 Undated version info for  SDOCM00107976
+ *                                                                   and SDOCM00105795.     
+ * 01.13.01       19May2014	   Vishwanath Reddy     0000000000000	 Updated version info for  SDOCM00107913
+ *                                                                   and SDOCM00107622.     
+ * 01.13.02       12Jun2014	   Vishwanath Reddy     0000000000000	 Updated version info for SDOCM00108238
+ * 01.14.00		  26Mar2014    Vishwanath Reddy 	                 Update version info for SDOCM00107161. 
+ * 01.15.00		  06Jun2014    Vishwanath Reddy 	                 Support for Conqueror.
+ * 01.16.00		  15Jul2014    Vishwanath Reddy 	SDOCM00112141    Remove  MISRA warnings.
+ * 01.16.01		  12Sep2014	   Vishwanath Reddy     SDOCM00112930    Prototype for TI_Fee_SuspendResumeErase added.
+ *                                                                   TI_Fee_EraseCommandType enum added.    
+ *                                                                   extern added for TI_Fee_bEraseSuspended.     
+ * 01.17.00		  15Oct2014    Vishwanath Reddy     SDOCM00113379    RAM Optimization changes.
+ * 01.17.01		  30Oct2014    Vishwanath Reddy     SDOCM00113536    Support for TMS570LS07xx,TMS570LS09xx,
+ *                                                                   TMS570LS05xx, RM44Lx. 
+ * 01.17.02		  26Dec2014    Vishwanath Reddy     SDOCM00114102    FLEE Errata Fix.
+ *                                                  SDOCM00114104    Change ALL 1's OK check condition.
+ *                                                                   Updated version info. Added new macros.
+ *                                                  SDOCM00114423	 Add new enum TI_Fee_DeviceType.
+ *                                                                   Add new variable TI_Fee_MaxSectors and 
+ *                                                                   prototype TI_FeeInternal_PopulateStructures. 
+ * 01.18.00		  12Oct2015    Vishwanath Reddy     SDOCM00119455    Update version history.
+ *                                                                   Update ti_fee_util.c file for the
+ *                                                                   bugfix "If morethan one data set is config-
+ *                                                                   ured, then a valid block may get invalidated if
+ *                                                                   multiple valid blocks are present in FEE memory. 
+ * 01.18.01		  17Nov2015    Vishwanath Reddy     SDOCM00120161    Update version history.
+ *                                                                   In TI_FeeInternal_FeeManager, do not change the 
+ *                                                                   state to IDLE,after completing the copy operation. 
+ * 01.18.02		  05Feb2016    Vishwanath Reddy     SDOCM00121158    Update version history.
+ *                                                                   Add a call of TI_FeeInternal_PollFlashStatus()
+ *                                                                   before reading data from FEE bank in
+ *                                                                   TI_FeeInternal_UpdateBlockOffsetArray(),
+ *                                                                   TI_Fee_WriteAsync(),TI_Fee_WriteSync(),
+ *                                                                   TI_Fee_ReadSync(), TI_Fee_Read()
+ * 01.18.03       30June2016   Vishwanath Reddy     SDOCM00122388    Update patch version TI_FEE_SW_PATCH_VERSION.
+ *                                                                   TI_FEE_FLASH_CRC_ENABLE is renamed to 
+ *                                                                   TI_FEE_FLASH_CHECKSUM_ENABLE.  
+ *                                                  SDOCM00122429    In ti_fee_types.h, add error when endianess 
+ *                                                                   is not defined.
+ * 01.19.00       08Augu2016   Vishwanath Reddy     SDOCM00122592    Update patch version TI_FEE_MINOR_VERSION.
+ *                                                                   Code for using partially ersed sector is now 
+ *                                                                   removed. 
+ *                                                                   Bugfix for FEE reading from unimplemented memory
+ *                                                                   space.
+ * 01.19.01       12Augu2016   Vishwanath Reddy     SDOCM00122543    Update patch version TI_FEE_MINOR_VERSION.
+ *                                                                   Synchronous write API modified to avoid copy of 
+ *                                                                   already copied block.
+ * 01.19.02       25Janu2017   Vishwanath Reddy     SDOCM00122832    Update patch version TI_FEE_MINOR_VERSION.
+ *                                                                   Format API modified to erase all configured VS. 
+ *                                                  SDOCM00122833    In API TI_Fee_ErrorRecovery, added polling for
+ *                                                                   flash status before calling TI_Fee_Init.
+ * 01.19.03       15May2017    Prathap Srinivasan   SDOCM00122917    Added TI_Fee_bIsMainFunctionCalled Global Variable. 
+ * 01.19.04		  05Dec2017    Prathap Srinivasan   HERCULES_SW-5082 Update version history.
+ *********************************************************************************************************************/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef TI_FEE_H
+#define TI_FEE_H
+
+/**********************************************************************************************************************
+ * INCLUDES
+ *********************************************************************************************************************/
+#include "hal_stdtypes.h"
+#include "fee_interface.h"
+#include "ti_fee_types.h"
+#include "ti_fee_cfg.h"
+/**********************************************************************************************************************
+ *  GLOBAL CONSTANT MACROS
+ *********************************************************************************************************************/
+/* Fee Published Information */
+#define TI_FEE_MAJOR_VERSION    3U
+#define TI_FEE_MINOR_VERSION    0U
+#define TI_FEE_PATCH_VERSION    2U
+#define TI_FEE_SW_MAJOR_VERSION 1U
+#define TI_FEE_SW_MINOR_VERSION 19U
+#define TI_FEE_SW_PATCH_VERSION 4U
+
+#define TI_FEE_VIRTUAL_SECTOR_VERSION 1U
+
+/* Virtual sector states */
+#define ActiveVSHi			0x0000FFFFU
+#define ActiveVSLo			0x00000000U			
+#define CopyVSHi			0xFFFFFFFFU
+#define CopyVSLo			0x00000000U
+#define EmptyVSHi			0xFFFFFFFFU
+#define EmptyVSLo			0x0000FFFFU
+#define InvalidVSHi			0xFFFFFFFFU
+#define InvalidVSLo			0xFFFFFFFFU
+#define ReadyforEraseVSHi	0x00000000U
+#define ReadyforEraseVSLo	0x00000000U
+
+/* Data Block states*/
+#define EmptyBlockHi         0xFFFFFFFFU
+#define EmptyBlockLo         0xFFFFFFFFU
+#define StartProgramBlockHi	 0xFFFF0000U
+#define StartProgramBlockLo	 0xFFFFFFFFU
+#define ValidBlockHi		 0x00000000U
+#define ValidBlockLo		 0xFFFFFFFFU
+#define InvalidBlockHi		 0x00000000U
+#define InvalidBlockLo		 0xFFFF0000U
+#define CorruptBlockHi		 0x00000000U
+#define CorruptBlockLo		 0x00000000U
+
+#define FEE_BANK 0U
+
+/* Enable/Disable FEE sectors */
+#define FEE_DISABLE_SECTORS_31_00 0x00000000U
+#define FEE_DISABLE_SECTORS_63_32 0x00000000U
+#define FEE_ENABLE_SECTORS_31_00  0xFFFFFFFFU 
+#define FEE_ENABLE_SECTORS_63_32  0xFFFFFFFFU 
+
+/**********************************************************************************************************************
+ *  GLOBAL DATA TYPES AND STRUCTURES
+ *********************************************************************************************************************/
+/* Structures used */
+/* Enum to describe the Fee Status types */
+typedef enum
+{
+   TI_FEE_OK = 0U,               /* Function returned no error */
+   TI_FEE_ERROR = 1U             /* Function returned an error */
+} TI_Fee_StatusType;
+
+/* Enum to describe the Virtual Sector State */
+typedef enum
+{
+   VsState_Invalid=1U,
+   VsState_Empty=2U,
+   VsState_Copy=3U,
+   VsState_Active=4U,
+   VsState_ReadyForErase=5U
+}VirtualSectorStatesType;
+
+/* Enum to describe the Block State */
+typedef enum
+{   
+   Block_StartProg=1U,
+   Block_Valid=2U,   
+   Block_Invalid=3U   
+}BlockStatesType;
+
+/* Enum for error trpes */
+typedef enum
+{
+ 	Error_Nil=0U,
+ 	Error_TwoActiveVS=1U,
+	Error_TwoCopyVS=2U,	
+	Error_SetupStateMachine=3U,
+	Error_CopyButNoActiveVS=4U,
+	Error_NoActiveVS=5U,
+	Error_BlockInvalid=6U,
+	Error_NullDataPtr=7U,
+	Error_NoFreeVS=8U,
+	Error_InvalidVirtualSectorParameter=9U,
+	Error_ExceedSectorOnBank=10U,		
+	Error_EraseVS=11U,
+	Error_BlockOffsetGtBlockSize=12U,
+	Error_LengthParam=13U,
+	Error_FeeUninit=14U,
+	Error_Suspend=15U,
+	Error_InvalidBlockIndex=16U,
+	Error_NoErase=17U,
+	Error_CurrentAddress=18U,
+	Error_Exceed_No_Of_DataSets=19U
+}TI_Fee_ErrorCodeType;
+
+typedef enum
+{
+	Suspend_Erase=0U,
+	Resume_Erase
+}TI_Fee_EraseCommandType;
+
+/* Enum to describe the Device types */
+typedef enum
+{
+   CHAMPION = 0U,               /* Function returned no error */
+   ARCHER = 1U             /* Function returned an error */
+} TI_Fee_DeviceType;
+
+typedef uint32 TI_Fee_AddressType;                     /* Used for defining variables to indicate number of 
+                                                          bytes for address offset */
+typedef uint32 TI_Fee_LengthType;                      /* Used for defining variables to indicate number of 
+                                                          bytes per read/write/erase */
+typedef TI_Fee_ErrorCodeType Fee_ErrorCodeType;
+
+/* Structure used when defining virtual sectors */
+/* The following error checks need to be performed: */
+/* Virtual Sector definitions are not allowed to overlap */
+/* Virtual Sector definition is at least twice the size in bytes of the total size of all defined blocks */
+/* We will need to define a formula to indicate if the number of write cycles indicated in the block definitions */
+/* is possible in the defined Virtual Sector. */
+/* Ending sector cannot be less than Starting sector */
+typedef struct
+{
+   uint16  FeeVirtualSectorNumber;                   /* Virtual Sector's Number - 0 and 0xFFFF values are not allowed*/
+                                                     /* Minimum 1, Maximum 4 */
+   uint16  FeeFlashBank;                             /* Flash Bank to use for virtual sector. */
+                                                     /* As we do not allow Flash EEPROM Emulation in Bank 0, 
+													    0 is not a valid option */
+                                                     /* Defaultvalue 1, Minimum 1, Maxiumum 7 */   
+   Fapi_FlashSectorType FeeStartSector;              /* Defines the Starting Sector inthe Bank for this VirtualSector*/
+   Fapi_FlashSectorType FeeEndSector;                /* Defines the Ending Sector inthe Bank for this Virtual Sector */
+                                                     /* Start and End sectors can be the same, which indicates only 
+													    one sector */
+                                                     /* is the entire virtual sector. */
+                                                     /* Values are based on the FLASH_SECT enum */
+                                                     /* Defaultvalue and Min is the same sector defined as the starting
+                                                        sector */
+                                                     /* Max values are based onthe device definition file being used.*/
+} Fee_VirtualSectorConfigType;
+
+/* Structure used when defining blocks */
+typedef struct
+{
+   uint16  FeeBlockNumber;                           /* Block's Number - 0 and 0xFFFF values are not allowed */
+                                                     /* Start 1, Next: Number of Blocks + 1, Min 1, Max 0xFFFE */
+   uint16  FeeBlockSize;                             /* Block's Size - Actual number of bits used is reduced */
+                                                     /* by number of bits used for dataset. */
+                                                     /* Default 8, Min 1, Max (2^(16-# of Dataset Bits))-1 */
+   boolean FeeImmediateData;                         /* Indicates if the block is used for immediate data */
+                                                     /* Default: False */
+   uint32  FeeNumberOfWriteCycles;                   /* Number of write cycles this block requires */
+                                                     /* Default: 0, but this will not be a valid number.  
+													    Force customer to select a value */
+                                                     /* Min 1, Max (2^32)-1 */
+   uint8   FeeDeviceIndex;                           /* Device Index - This will always be 0 */
+                                                     /* Fixed value: 0 */
+   uint8   FeeNumberOfDataSets;						 /* Number of DataSets for the Block */
+                                                     /* Default value: 1 */   
+   uint8   FeeEEPNumber; 
+} Fee_BlockConfigType;
+
+
+/* Structure used for Global variables */
+typedef struct
+{
+ 	TI_Fee_AddressType Fee_oFlashNextAddress;			 	/* The next Flash Address to write to */
+	TI_Fee_AddressType Fee_oCopyCurrentAddress;        		/* Indicates the Address within the Active VS 
+	                                                           which will be copied to Copy VS */
+	TI_Fee_AddressType Fee_oCopyNextAddress;			 	/* Indicates the Address within the Copy VS to 
+	                                                           which the data from Active VS will be copied to */
+	TI_Fee_AddressType Fee_u32nextwriteaddress;				/* Indicates the next free Address within the curent 
+	                                                           VS to which the data will be written */	
+	TI_Fee_AddressType Fee_oVirtualSectorStartAddress; 		/* Start Address of the current Virtual Sector */
+	TI_Fee_AddressType Fee_oVirtualSectorEndAddress;    	/* End Address of the current Virtual Sector */ 
+	TI_Fee_AddressType Fee_oCopyVirtualSectorAddress;   	/* Start Address of the Copy Virtual Address */
+	TI_Fee_AddressType Fee_oCurrentStartAddress;		 	/* Start Address of the Previous Block	 */
+	TI_Fee_AddressType Fee_oCurrentBlockHeader;		 		/* Start Address of the Block which is being currently 
+	                                                           written*/
+	TI_Fee_AddressType Fee_oWriteAddress;				 	/* Address within the VS where data is to be written */
+	TI_Fee_AddressType Fee_oCopyWriteAddress;				/* Address within the VS where data is to be copied */
+	TI_Fee_AddressType Fee_oActiveVirtualSectorAddress; 	/* Start Address of the Active VS */
+	TI_Fee_AddressType Fee_oBlankFailAddress;				/* Address of first non-blank location */
+	TI_Fee_AddressType Fee_oActiveVirtualSectorStartAddress;/* Start Address of the active VS */
+	TI_Fee_AddressType Fee_oActiveVirtualSectorEndAddress;	/* End Address of the active VS */	
+	TI_Fee_AddressType Fee_oCopyVirtualSectorStartAddress;	/* Start Address of the Copy VS */	
+	TI_Fee_AddressType Fee_oCopyVirtualSectorEndAddress;	/* End Address of the Copy VS */
+	TI_Fee_AddressType Fee_u32nextActiveVSwriteaddress;		/* Next write address in Active VS */
+	TI_Fee_AddressType Fee_u32nextCopyVSwriteaddress;		/* Next write address in Copy VS */
+	uint16 Fee_u16CopyBlockSize;					 		/* Indicates the size of current block in bytes which is 
+	                                                           been copied from Active to Copy VS */
+	uint8 Fee_u8VirtualSectorStart;							/* Index of the Start Sector of the VS */
+	uint8 Fee_u8VirtualSectorEnd;							/* Index of the End Sector of the VS */
+	uint32 Fee_au32VirtualSectorStateValue[TI_FEE_VIRTUAL_SECTOR_OVERHEAD >> 2U];  		/* Array to store the Virtual 
+	                                                                                       Sector Header and 
+																						   Information record */
+	uint8 Fee_au8VirtualSectorState[TI_FEE_NUMBER_OF_VIRTUAL_SECTORS]; 					/* Stores the state of each 
+	                                                                                       Virtual sector */
+	uint32 Fee_au32VirtualSectorEraseCount[TI_FEE_NUMBER_OF_VIRTUAL_SECTORS]; 	 		/* Array to store the erase 
+	                                                                                       count of each Virtual 
+																						   Sector*/
+	uint16 Fee_au16BlockOffset[TI_FEE_TOTAL_BLOCKS_DATASETS]; 		/* Array to store within the VS */
+	uint32 Fee_au32BlockHeader[TI_FEE_BLOCK_OVERHEAD >> 2U];		/* Array to store the Block Header value */
+	uint8  Fee_au8BlockCopyStatus[TI_FEE_TOTAL_BLOCKS_DATASETS]; 	/* Array to storeblock copy status */
+	uint8 Fee_u8InternalVirtualSectorStart;			/* Indicates internal VS start index */
+    uint8 Fee_u8InternalVirtualSectorEnd;			/* Indicates internal VS end index */
+	TI_FeeModuleStatusType Fee_ModuleState;			/* Indicates the state of the FEE module */	
+	TI_FeeJobResultType Fee_u16JobResult;			/* Stores the Job Result of the current command */	
+	TI_Fee_StatusType Fee_oStatus;					/* Indicates the status of FEE */
+	TI_Fee_ErrorCodeType Fee_Error;					/* Indicates the Error code */	
+	uint16 Fee_u16CopyBlockNumber;					/* Block number which is currently being copied */   	
+	uint16 Fee_u16BlockIndex;						/* Index of the Current Block */			
+	uint16 Fee_u16BlockCopyIndex;					/* Index of the Block being copied from Copy to Active VS */
+	uint16 Fee_u16DataSetIndex;						/* Index of the Current DataSet */
+	uint16 Fee_u16ArrayIndex;						/* Index of the Current DataSet */
+	uint16 Fee_u16BlockSize;						/* Size of the current block in bytes */ 	
+	uint16 Fee_u16BlockSizeinBlockHeader;			/* Size of the current block. Used to write into Block Header */
+	uint16 Fee_u16BlockNumberinBlockHeader;			/* Number of the current block. Used to write into Block Header */
+	uint8  Fee_u8ActiveVirtualSector;				/* Indicates the FeeVirtualSectorNumber for the Active VS */
+	uint8  Fee_u8CopyVirtualSector;					/* Indicates the FeeVirtualSectorNumber for the Copy VS */
+	uint32 Fee_u32InternalEraseQueue;				/* Indicates which VS can be erased when the FEE is in
+	                                                   BusyInternal State*/		
+	uint8 Fee_u8WriteCopyVSHeader;					/* Indicates the number of bytes of the Copy VS Header being 
+	                                                   written */
+	uint8 Fee_u8WriteCount;							/* Indicates the number of bytes of the Block Header being 
+	                                                   written */		
+	uint8 * Fee_pu8ReadDataBuffer;					/* Pointer to read data */
+	uint8 * Fee_pu8ReadAddress;						/* Pointer to read address */
+	uint8 * Fee_pu8Data;							/* Pointer to the next data to be written to the VS */			
+	uint8 * Fee_pu8CopyData;						/* Pointer to the next data to be copied to the VS */			
+	uint8 * Fee_pu8DataStart;						/* Pointer to the first data to be written to the VS */			
+	boolean Fee_bInvalidWriteBit;					/* Indicates whether the block is written/invalidated/erased 
+	                                                   for the first time */
+	boolean Fee_bWriteData;							/* Indicates that there is data which is pending to be written 
+	                                                   to the Block */	
+	boolean Fee_bWriteBlockHeader;					/* Indicates whether the Block Header has been written or not */	
+	boolean bWriteFirstTime;						/* Indicates if the block is being written first time */
+	boolean Fee_bFindNextVirtualSector;				/* Indicates if there is aneed to find next free VS */
+	boolean Fee_bWriteVSHeader;						/* Indicates if block header needs to be written */	
+	boolean Fee_bWriteStartProgram;					/* Indicates if start program block header needs to be written */
+	boolean Fee_bWritePartialBlockHeader;			/* Indicates if start program block header needs to be written */
+	#if (TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U)
+	uint16 Fee_au16UnConfiguredBlockAddress[TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY];		/* Indicates 
+	                                                                          number of unconfigured blocks to copy */
+	uint8  Fee_au8UnConfiguredBlockCopyStatus[TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY]; 	/* Array to store block 
+	                                                                                           copy status */
+	#endif
+}TI_Fee_GlobalVarsType;
+
+/**********************************************************************************************************************
+ * EXTERN Declarations
+ *********************************************************************************************************************/
+/*  Fee Global Variables */
+extern const Fee_BlockConfigType Fee_BlockConfiguration[TI_FEE_NUMBER_OF_BLOCKS];
+#if (TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_OFF)
+extern const Fee_VirtualSectorConfigType Fee_VirtualSectorConfiguration[TI_FEE_NUMBER_OF_VIRTUAL_SECTORS];
+extern const Device_FlashType Device_FlashDevice;
+#endif
+#if (TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON)
+extern Fee_VirtualSectorConfigType Fee_VirtualSectorConfiguration[TI_FEE_NUMBER_OF_VIRTUAL_SECTORS];
+extern Device_FlashType Device_FlashDevice;
+extern uint8 TI_Fee_MaxSectors;
+#endif
+extern TI_Fee_GlobalVarsType TI_Fee_GlobalVariables[TI_FEE_NUMBER_OF_EEPS];
+extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord[TI_FEE_NUMBER_OF_EEPS];
+#if(TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON)
+extern uint32 TI_Fee_u32FletcherChecksum;
+#endif
+extern uint32 TI_Fee_u32BlockEraseCount;
+extern uint8 TI_Fee_u8DataSets;
+extern uint8 TI_Fee_u8DeviceIndex;
+extern uint32 TI_Fee_u32ActCpyVS;
+extern uint8 TI_Fee_u8ErrEraseVS;
+#if (TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U)
+extern uint16 TI_Fee_u16NumberOfUnconfiguredBlocks[TI_FEE_NUMBER_OF_EEPS];
+#endif
+#if(TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix)	
+extern boolean Fee_bDoubleBitError;
+extern boolean Fee_bSingleBitError;
+#endif
+#if(TI_FEE_NUMBER_OF_EEPS==2U)
+extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord_Global;
+#endif
+extern boolean TI_Fee_FapiInitCalled; 
+extern boolean TI_Fee_bEraseSuspended;
+extern boolean TI_Fee_bIsMainFunctionCalled;
+
+
+/**********************************************************************************************************************
+ *  GLOBAL FUNCTION PROTOTYPES
+ *********************************************************************************************************************/
+/*  Interface Functions */
+extern void TI_Fee_Cancel(uint8 u8EEPIndex);
+extern Std_ReturnType TI_Fee_EraseImmediateBlock(uint16 BlockNumber);
+extern TI_FeeModuleStatusType TI_Fee_GetStatus(uint8 u8EEPIndex);
+extern void TI_Fee_GetVersionInfo(Std_VersionInfoType* VersionInfoPtr);
+extern void TI_Fee_Init(void);
+extern Std_ReturnType TI_Fee_InvalidateBlock(uint16 BlockNumber);
+extern Std_ReturnType TI_Fee_Read(uint16 BlockNumber,
+                               uint16 BlockOffset,
+                               uint8* DataBufferPtr,
+                               uint16 Length);
+extern Std_ReturnType TI_Fee_WriteAsync(uint16 BlockNumber, uint8* DataBufferPtr);
+extern void TI_Fee_MainFunction(void);
+extern TI_Fee_ErrorCodeType TI_FeeErrorCode(uint8 u8EEPIndex);
+extern void TI_Fee_ErrorRecovery(TI_Fee_ErrorCodeType ErrorCode, uint8 u8VirtualSector);
+extern TI_FeeJobResultType TI_Fee_GetJobResult(uint8 u8EEPIndex);
+extern void TI_Fee_SuspendResumeErase(TI_Fee_EraseCommandType Command);
+
+#if(TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix)
+extern void TI_Fee_ErrorHookSingleBitError(void);
+extern void TI_Fee_ErrorHookDoubleBitError(void);
+#endif
+
+#if(TI_FEE_DRIVER == 1U)
+extern Std_ReturnType TI_Fee_WriteSync(uint16 BlockNumber, uint8* DataBufferPtr);
+extern Std_ReturnType TI_Fee_Shutdown(void);
+extern boolean TI_Fee_Format(uint32 u32FormatKey);
+extern Std_ReturnType TI_Fee_ReadSync(uint16 BlockNumber,uint16 BlockOffset,uint8* DataBufferPtr,uint16 Length);
+#endif
+
+/*  TI Fee Internal Functions */
+TI_Fee_AddressType TI_FeeInternal_GetNextFlashAddress(uint8 u8EEPIndex);
+TI_Fee_AddressType TI_FeeInternal_AlignAddressForECC(TI_Fee_AddressType oAddress); 
+TI_Fee_AddressType TI_FeeInternal_GetCurrentBlockAddress(uint16 BlockNumber,uint16 DataSetNumber, uint8 u8EEPIndex);
+/*SAFETYMCUSW 61 X MR:1.4,5.1 <APPROVED> "Reason -  TI_FeeInternal_GetVirtualSectorParameter name is required here."*/
+uint32 TI_FeeInternal_GetVirtualSectorParameter(Fapi_FlashSectorType oSector, uint16 u16Bank, boolean VirtualSectorInfo, 
+                                                uint8 u8EEPIndex);
+uint32 TI_FeeInternal_PollFlashStatus(void);
+uint16 TI_FeeInternal_GetBlockSize(uint16 BlockIndex);
+uint16 TI_FeeInternal_GetBlockIndex(uint16 BlockNumber);
+uint16 TI_FeeInternal_GetDataSetIndex(uint16 BlockNumber);
+uint16 TI_FeeInternal_GetBlockNumber(uint16 BlockNumber);
+uint8 TI_FeeInternal_FindNextVirtualSector(uint8 u8EEPIndex);
+uint8 TI_FeeInternal_WriteDataF021(boolean bCopy,uint16 u16WriteSize, uint8 u8EEPIndex);
+boolean TI_FeeInternal_BlankCheck(uint32 u32StartAddress, uint32 u32EndAddress, uint16 u16Bank, uint8 u8EEPIndex);
+Std_ReturnType TI_FeeInternal_CheckReadParameters(uint32 u32BlockSize,uint16 BlockOffset, const uint8* DataBufferPtr,
+                                                  uint16 Length, uint8 u8EEPIndex);
+Std_ReturnType TI_FeeInternal_CheckModuleState(uint8 u8EEPIndex);
+Std_ReturnType TI_FeeInternal_InvalidateErase(uint16 BlockNumber);
+TI_Fee_StatusType TI_FeeInternal_FeeManager(uint8 u8EEPIndex);
+void TI_FeeInternal_WriteVirtualSectorHeader(uint8 FeeVirtualSectorNumber, VirtualSectorStatesType VsState, 
+                                             uint8 u8EEPIndex) ;
+/*SAFETYMCUSW 61 X MR:1.4,5.1 <APPROVED> "Reason -  TI_FeeInternal_GetVirtualSectorIndex name is required here."*/
+void TI_FeeInternal_GetVirtualSectorIndex(Fapi_FlashSectorType oSectorStart, Fapi_FlashSectorType oSectorEnd, 
+                                          uint16 u16Bank, boolean bOperation,  uint8 u8EEPIndex);
+void TI_FeeInternal_WritePreviousBlockHeader(boolean bWrite, uint8 u8EEPIndex);
+void TI_FeeInternal_WriteBlockHeader(boolean bWrite, uint8 u8EEPIndex,uint16 Fee_BlockSize_u16,uint16 u16BlockNumber);
+void TI_FeeInternal_SetClearCopyBlockState(uint8 u8EEPIndex, boolean bSetClear);
+void TI_FeeInternal_SanityCheck(uint16 BlockSize, uint8 u8EEPIndex);
+void TI_FeeInternal_StartProgramBlock(uint8 u8EEPIndex);
+void TI_FeeInternal_UpdateBlockOffsetArray(uint8 u8EEPIndex, boolean bActCpyVS,uint8 u8VirtualSector);
+void TI_FeeInternal_WriteInitialize(TI_Fee_AddressType oFlashNextAddress, uint8* DataBufferPtr, uint8 u8EEPIndex);
+void TI_FeeInternal_CheckForError(uint8 u8EEPIndex);
+void TI_FeeInternal_EnableRequiredFlashSector(uint32 u32VirtualSectorStartAddress);
+uint16 TI_FeeInternal_GetArrayIndex(uint16 BlockNumber, uint16 DataSetNumber, uint8 u8EEPIndex, boolean bCallContext);
+#if(TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON)
+uint32 TI_FeeInternal_Fletcher16( uint8 const *pu8data, uint16 u16Length);
+#endif
+#if (TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON)
+void TI_FeeInternal_PopulateStructures(TI_Fee_DeviceType DeviceType);
+#endif
+#endif /* TI_FEE_H */
+/**********************************************************************************************************************
+ *  END OF FILE: ti_fee.h
+ *********************************************************************************************************************/
+
+
diff --git a/include/arch/rm46l8lp/halcogen/ti_fee_cfg.h b/include/arch/rm46l8lp/halcogen/ti_fee_cfg.h
new file mode 100644
index 0000000..f2d0a16
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/ti_fee_cfg.h
@@ -0,0 +1,55 @@
+/**********************************************************************************************************************
+ *  FILE DESCRIPTION
+ *  -------------------------------------------------------------------------------------------------------------------
+ *         File:  ti_fee_cfg.h
+ *      Project:  Tms570_TIFEEDriver
+ *       Module:  TIFEEDriver
+ *    Generator:  HALCoGen
+ *
+ *  Description:  This file implements the TI FEE Api.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author:  Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version        Date         Author               Change ID        Description
+ *---------------------------------------------------------------------------------------------------------------------
+ * 00.00.01       31Aug2012    Vishwanath Reddy     0000000000000    Initial Version
+ * 01.19.04		  05Dec2017    Prathap Srinivasan   HERCULES_SW-5082 Update version history.
+ *
+ *********************************************************************************************************************/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
diff --git a/include/arch/rm46l8lp/halcogen/ti_fee_types.h b/include/arch/rm46l8lp/halcogen/ti_fee_types.h
new file mode 100644
index 0000000..5f889b2
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/ti_fee_types.h
@@ -0,0 +1,203 @@
+/**********************************************************************************************************************
+ *  FILE DESCRIPTION
+ *  -------------------------------------------------------------------------------------------------------------------
+ *         File:  ti_fee_types.h
+ *      Project:  Tms570_TIFEEDriver
+ *       Module:  TIFEEDriver
+ *    Generator:  None
+ *
+ *  Description:  This file implements the TI FEE Api.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author:  Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version        Date         Author               Change ID        Description
+ *---------------------------------------------------------------------------------------------------------------------
+ * 03.00.00       31Aug2012    Vishwanath Reddy     0000000000000    Initial Version
+ * 00.01.00       31Aug2012    Vishwanath Reddy     0000000000000    Initial Version
+ * 00.01.02       30Nov2012    Vishwanath Reddy     SDOCM00097786    Misra Fixes, Memory segmentation changes.
+ * 01.12.00		  13Dec2013    Vishwanath Reddy     SDOCM00105412    MISRA C fixes.
+ * 01.15.00		  06Jun2014    Vishwanath Reddy 	                 Support for LC Varients.
+ * 01.16.00		  15Jul2014    Vishwanath Reddy 	SDOCM00112141    Remove  MISRA warnings.
+ * 01.18.00		  12Oct2015    Vishwanath Reddy     SDOCM00119455    Update version history.
+ * 01.18.01		  17Nov2015    Vishwanath Reddy     SDOCM00120161    Update version history.
+ * 01.18.02		  05Feb2016    Vishwanath Reddy     SDOCM00121158    Update version history.
+ * 01.18.03       30June2016   Vishwanath Reddy     SDOCM00122388    Update version history.
+ *                                                  SDOCM00122429    Added error when endianess is not defined.
+ * 01.19.00       08Augu2016   Vishwanath Reddy     SDOCM00122592    Update version history.
+ * 01.19.01       12Augu2016   Vishwanath Reddy     SDOCM00122543    Update version history.
+ * 01.19.03       15May2017    Prathap Srinivasan   SDOCM00122917    Update version history.
+ * 01.19.04		  05Dec2017    Prathap Srinivasan   HERCULES_SW-5082 Update version history.
+ *********************************************************************************************************************/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef TI_FEE_TYPES_H
+#define TI_FEE_TYPES_H
+
+/**********************************************************************************************************************
+ * INCLUDES
+ *********************************************************************************************************************/
+#include "Device_header.h"
+
+#ifndef TI_Fee_None
+#define TI_Fee_None 0x00U	/*Take no action on single bit errors, (respond with corrected data), */
+							/*return error for uncorrectable error reads (multibit errors for ECC or parity failures)*/
+							/*For devices with no ECC (they may have parity or not) the only valid option is none. */
+#endif
+
+#ifndef TI_Fee_Fix
+#define TI_Fee_Fix 0x01U	/* single bit error will be fixed by reprogramming */
+							/* return previous valid data for uncorrectable error reads (multi bit errors for ECC 
+							   or parity failures). */
+#endif
+
+#if !defined(_LITTLE_ENDIAN) && !defined(_BIG_ENDIAN)
+#error "Target Endianess is not defined. Include F021 header files and library."
+#endif
+
+/*SAFETYMCUSW 74 S MR:18.4 <APPROVED> "Reason - union declaration is necessary here."*/
+typedef	union 
+{	
+	uint16 Fee_u16StatusWord;	
+	#ifdef _BIG_ENDIAN
+	struct
+	{		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 Reserved: 5U;	
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 Erase:1U;
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 ReadSync:1U;
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 ProgramFailed:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 Read:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 WriteSync:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 WriteAsync:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 EraseImmediate:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 InvalidateBlock:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 Copy:1U;				
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 Initialized:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 SingleBitError:1U;
+	}Fee_StatusWordType_ST;
+	#endif
+	#ifdef _LITTLE_ENDIAN
+	struct
+	{		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 SingleBitError:1U;
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 Initialized:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 Copy:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 InvalidateBlock:1U;			
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 EraseImmediate:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 WriteAsync:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 WriteSync:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 Read:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 ProgramFailed:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 ReadSync:1U;
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 Erase:1U;		
+		/*SAFETYMCUSW 42 S MR:3.5 <APPROVED> "Reason - Bit field declaration is necessary here."*/
+		/*SAFETYMCUSW 73 S MR:6.4 <APPROVED> "Reason - Bit field is declared as unsigned."*/
+		uint16 Reserved: 5U;
+	}Fee_StatusWordType_ST;
+	#endif
+}TI_Fee_StatusWordType_UN;
+
+typedef enum
+{
+   UNINIT,
+   IDLE,
+   /*SAFETYMCUSW 91 S MR:5.2,5.6,5.7 <APPROVED> "Reason - BUSY in F021 is a member of structure."*/
+   BUSY,
+   BUSY_INTERNAL
+}TI_FeeModuleStatusType;
+
+typedef enum
+{
+    JOB_OK,
+    JOB_FAILED,
+    JOB_PENDING,
+    JOB_CANCELLED,
+    BLOCK_INCONSISTENT,
+    BLOCK_INVALID
+}TI_FeeJobResultType;
+
+#endif /* TI_FEE_TYPES_H */
+
+/**********************************************************************************************************************
+ *  END OF FILE: ti_fee_types.h
+ *********************************************************************************************************************/
diff --git a/include/arch/rm46l8lp/halcogen/usb-ids.h b/include/arch/rm46l8lp/halcogen/usb-ids.h
new file mode 100644
index 0000000..6490ece
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/usb-ids.h
@@ -0,0 +1,71 @@
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/**
+ *  @file       usb-ids.h
+ *
+ *  @brief      Definitions of VIDs and PIDs used by Stellaris USB examples.
+ * 
+ */
+
+#ifndef __USBIDS_H__
+#define __USBIDS_H__
+
+/** ***************************************************************************
+ *
+ * TI Vendor ID.
+ *
+ *****************************************************************************/
+#define USB_VID_TI       0x0000
+
+/** ***************************************************************************
+ *
+ * Product IDs.
+ *
+ *****************************************************************************/
+#define USB_PID_MOUSE           0x0000
+#define USB_PID_KEYBOARD        0x0001
+#define USB_PID_SERIAL          0x0000
+#define USB_PID_BULK            0x0003
+#define USB_PID_SCOPE           0x0004
+#define USB_PID_MSC             0x0005
+#define USB_PID_AUDIO           0x0006
+#define USB_PID_COMP_SERIAL     0x0007
+#define USB_PID_COMP_AUDIO_HID  0x0008
+#define USB_PID_COMP_HID_SER    0x0009
+#define USB_PID_DFU             0x00FF
+
+
+#endif /* __USBIDS_H__ */
diff --git a/include/arch/rm46l8lp/halcogen/usb.h b/include/arch/rm46l8lp/halcogen/usb.h
new file mode 100644
index 0000000..d08df05
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/usb.h
@@ -0,0 +1,694 @@
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef USB_H_
+#define USB_H_
+
+/******************************************************************************
+ *
+ * These macros allow conversion between 0-based endpoint indices and the
+ * USB_EP_x values required when calling various USB APIs.
+ *
+ *****************************************************************************/
+#define INDEX_TO_USB_EP(x)      ((x) << 4u)
+#define USB_EP_TO_INDEX(x)      ((x) >> 4u)
+
+/******************************************************************************
+ *
+ * The following are values that can be passed to USBFIFOConfigSet() as the
+ * uFIFOSize parameter.
+ *
+ *****************************************************************************/
+#define USB_FIFO_SZ_8           0x00U  /* 8 byte FIFO */
+#define USB_FIFO_SZ_16          0x01U  /* 16 byte FIFO */
+#define USB_FIFO_SZ_32          0x02U  /* 32 byte FIFO */
+#define USB_FIFO_SZ_64          0x03U  /* 64 byte FIFO */
+#define USB_FIFO_SZ_128         0x04U  /* 128 byte FIFO */
+#define USB_FIFO_SZ_256         0x05U  /* 256 byte FIFO */
+#define USB_FIFO_SZ_512         0x06U  /* 512 byte FIFO */
+#define USB_FIFO_SZ_1024        0x07U  /* 1024 byte FIFO */
+
+
+/******************************************************************************
+ *
+ * This macro allow conversion from a FIFO size label as defined above to
+ * a number of bytes
+ *
+ *****************************************************************************/
+#define USB_FIFO_SIZE_DB_FLAG  0x10U
+#define USB_FIFO_SZ_TO_BYTES(x) (uint16_t)((uint8_t)8U << (((uint8_t)(x) & (uint8_t)(~(uint8_t)USB_FIFO_SIZE_DB_FLAG)) + \
+                                           (uint8_t)(((uint8_t)(x) & (uint8_t)USB_FIFO_SIZE_DB_FLAG) >> 4U)))
+
+                                 
+/******************************************************************************
+ *
+ * The maximum number of independent interfaces that any single device
+ * implementation can support.  Independent interfaces means interface
+ * descriptors with different bInterfaceNumber values - several interface
+ * descriptors offering different alternative settings but the same interface
+ * number count as a single interface.
+ *
+ *****************************************************************************/
+#define USB_MAX_INTERFACES_PER_DEVICE 8u
+
+
+/******************************************************************************
+ *
+ * Following macro directives can be used for the configuring the USB device.
+ * Note that these directives map directly to the hardware bit definitions and
+ * cannot be modified to any other value.
+ *
+ *****************************************************************************/
+#define USBD_PWR_BUS_PWR                (0x0000u)   /* Device is bus powered */
+#define USBD_PWR_SELF_PWR               (0x0004u)   /* Device is self powered */
+#define USBD_DATA_ENDIAN_LITTLE         (0x0000u)   /* Little Endian Data (RM48x) */
+#define USBD_DATA_ENDIAN_BIG            (0x0080u)   /* Bit Endian Data */
+#define USBD_DMA_ENDIAN_LITTLE          (0x0000u)   /* DMA is Little Endian */
+#define USBD_DMA_ENDIAN_BIG             (0x0040u)   /* DMA is Big Endian */
+
+/******************************************************************************
+ *
+ *  Following macro directives can be used for the configuring the Endpoints
+ *  Note that these directives map directly to the hardware bit definitions and
+ *  cannot be modified to any other value.
+ *
+ *****************************************************************************/
+
+#define USBD_EP_DIR_IN                  (0x0010u)        /* IN Endpoint */
+#define USBD_EP_DIR_OUT                 (0x0000u)        /* OUT Endpoint */  
+#define USB_EP_DEV_IN                   (USBD_EP_DIR_IN) /* IN Endpoint */   
+#define USB_EP_DEV_OUT                  (USBD_EP_DIR_OUT)/* OUT Endpoint */
+#define USB_TRANS_IN                    (USBD_EP_DIR_IN) /* IN Endpoint */
+#define USB_TRANS_OUT                   (USBD_EP_DIR_OUT)/* OUT Endpoint */
+#define USB_EP_DIR_IN                   (USBD_EP_DIR_IN)
+#define USB_EP_DIR_OUT                  (USBD_EP_DIR_OUT)
+#define USB_TRANS_IN_LAST               0u               /* Used to indicate the last transaction
+                                                           (NOT USED in this port of USB) */
+
+#define USBD_TXRX_EP_VALID_VALID        (0x8000u)       /* EP is valid & configured */
+#define USBD_TXRX_EP_VALID_NOTVALID     (0x0000u)       /* EP is not valid & not configured */
+#define USBD_TXRX_EP_ISO_ISO            (0x0800u)       /* EP is of ISO type */
+#define USBD_TXRX_EP_ISO_NONISO         (0x0000u)       /* EP is either Bulk/Interrup/Control */
+#define USBD_TXRX_EP_DB_ENABLED         (0x4000u)       /* EP has double buffering enabled */
+                                                        /* For IN EPs DB should be enabled only in DMA mode */
+#define USBD_TXRX_EP_DB_DISABLED        (0x0000u)       /* EP has double buffering disabled */
+
+/******************************************************************************
+ *
+ *  Following macro directives are to be used for enabling/disabling interrupts
+ *  Note that these directives map directly to the hardware bit definitions and
+ *  cannot be modified to any other value.
+ *
+ *****************************************************************************/
+#define USBD_INT_EN_SOF_IE                      (0x0080u)   /* Start-of-Frame Interrupt */
+#define USBD_INT_EN_EPN_RX_IE                   (0x0020u)   /* Non-EP0 RX Interrupt */
+#define USBD_INT_EN_EPN_TX_IE                   (0x0010u)   /* Non-EP0 TX Interrupt */
+#define USBD_INT_EN_DS_CHG_IE                   (0x0008u)   /* Device State change interrupt */
+#define USBD_INT_EN_EP0_IE                      (0x0001u)   /* EP0 Interrupt */
+#define USBD_INT_EN_ALL                         (USBD_IRQ_EN_SOF_IE | \
+                                                 USBD_IRQ_EN_EPN_RX_IE | \
+                                                 USBD_IRQ_EN_EPN_TX_IE | \
+                                                 USBD_IRQ_EN_DS_CHG_IE | \
+                                                 USBD_IRQ_EN_EP0_IE)
+
+
+/******************************************************************************
+ *
+ *  Following macro directives are to be used for decoding the interrupt source
+ *  Note that these directives map directly to the hardware bit definitions and
+ *  cannot be modified to any other value.
+ *
+ *****************************************************************************/
+#define USBD_INT_SRC_TXN_DONE                   (0x0400u)   /* non-EP0 TX done interrupt */
+#define USBD_INT_SRC_RXN_CNT                    (0x0200u)   /* non-EP0 RX Count */
+#define USBD_INT_SRC_RXN_EOT                    (0x0100u)   /* non-EP0 RX end of transfer */
+#define USBD_INT_SRC_SOF                        (0x0080u)   /* Start-of-frame interrupt */
+#define USBD_INT_SRC_EPN_RX                     (0x0020u)   /* non-EP0 RX interrupt */
+#define USBD_INT_SRC_EPN_TX                     (0x0010u)   /* non-EP0 TX interrupt */
+#define USBD_INT_SRC_DS_CHG                     (0x0008u)   /* Device State change interrupt */
+#define USBD_INT_SRC_SETUP                      (0x0004u)   /* Setup interrupt */
+#define USBD_INT_SRC_EP0_RX                     (0x0002u)   /* EP0 RX Interrupt */
+#define USBD_INT_SRC_EP0_TX                     (0x0001u)   /* EP0 TX Interrupt */
+
+
+/******************************************************************************
+ *
+ * These values are used to indicate which endpoint to access.
+ *
+ *****************************************************************************/
+#define USB_EP_0                0x00000000u  /*  Endpoint 0 */
+#define USB_EP_1                0x00000010u  /*  Endpoint 1 */
+#define USB_EP_2                0x00000020u  /*  Endpoint 2 */
+#define USB_EP_3                0x00000030u  /*  Endpoint 3 */
+#define USB_EP_4                0x00000040u  /*  Endpoint 4 */
+#define USB_EP_5                0x00000050u  /*  Endpoint 5 */
+#define USB_EP_6                0x00000060u  /*  Endpoint 6 */
+#define USB_EP_7                0x00000070u  /*  Endpoint 7 */
+#define USB_EP_8                0x00000080u  /*  Endpoint 8 */
+#define USB_EP_9                0x00000090u  /*  Endpoint 9 */
+#define USB_EP_10               0x000000A0u  /*  Endpoint 10 */
+#define USB_EP_11               0x000000B0u  /*  Endpoint 11 */
+#define USB_EP_12               0x000000C0u  /*  Endpoint 12 */
+#define USB_EP_13               0x000000D0u  /*  Endpoint 13 */
+#define USB_EP_14               0x000000E0u  /*  Endpoint 14 */
+#define USB_EP_15               0x000000F0u  /*  Endpoint 15 */
+#define NUM_USB_EP              16u          /*  Number of supported endpoints */
+
+
+/******************************************************************************
+ *
+ * The following are values that can be passed to USBHostEndpointConfig() and
+ * USBDevEndpointConfigSet() as the ulFlags parameter.
+ *
+ *****************************************************************************/
+#define USB_EP_AUTO_SET         0x00000001u  /* Auto set feature enabled */
+#define USB_EP_AUTO_REQUEST     0x00000002u  /* Auto request feature enabled */
+#define USB_EP_AUTO_CLEAR       0x00000004u  /* Auto clear feature enabled */
+#define USB_EP_DMA_MODE_0       0x00000008u  /* Enable DMA access using mode 0 */
+#define USB_EP_DMA_MODE_1       0x00000010u  /* Enable DMA access using mode 1 */
+#define USB_EP_MODE_ISOC        0x00000000u  /* Isochronous endpoint */
+#define USB_EP_MODE_BULK        0x00000100u  /* Bulk endpoint */
+#define USB_EP_MODE_INT         0x00000200u  /* Interrupt endpoint */
+#define USB_EP_MODE_CTRL        0x00000300u  /* Control endpoint */
+#define USB_EP_MODE_MASK        0x00000300u  /* Mode Mask */
+#define USB_EP_SPEED_LOW        0x00000000u  /* Low Speed */
+#define USB_EP_SPEED_FULL       0x00001000u  /* Full Speed */
+
+
+/******************************************************************************
+ *
+ * The following are values that are returned from USBEndpointStatus().  The
+ * USB_HOST_* values are used when the USB controller is in host mode and the
+ * USB_DEV_* values are used when the USB controller is in device mode.
+ *
+ *****************************************************************************/
+#define USB_DEV_EP0_OUT_PKTRDY 0x00000001u  /* Receive data packet ready */
+#define USB_DEV_RX_PKT_RDY      0x00010000u  /* Data packet ready */
+#define USB_DEV_TX_TXPKTRDY     0x00000001u
+#define USB_DEV_TX_FIFO_NE      0x00000002u
+
+
+/******************************************************************************
+ *
+ * This value specifies the maximum size of transfers on endpoint 0 as 64
+ * bytes.  This value is fixed in hardware as the FIFO size for endpoint 0.
+ *
+ *****************************************************************************/
+#define MAX_PACKET_SIZE_EP0     64u
+
+
+/******************************************************************************
+ *
+ * Macros for hardware access, both direct and via the bit-band region.
+ *
+ *****************************************************************************/
+#define HWREG(x)                (*((volatile uint32_t *)(x)))
+
+
+
+
+/******************************************************************************
+ *
+ *  Initialize the USB Device
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usFlags specifies the bus/self powered and endianness for data & dma.
+ *          Should be a combination of the following flags
+ *              USBD_PWR_BUS_PWR or USBD_PWR_SELF_PWR
+ *              USBD_DATA_ENDIAN_LITTLE or USBD_DATA_ENDIAN_BIG
+ *              USBD_DMA_ENDIAN_LITTLE or USBD_DMA_ENDIAN_BIG
+ *  \param usFifoPtr specifies the start of the EP0 FIFO.
+ * 
+ *  This function will initialize the USB Device controller specified by the
+ *  \e ulBase parameter.
+ * 
+ *  \return None
+ * 
+ *  Note This function does not intiate a device connect (pull ups are
+ *  not enabled). Also the EP0 is intialized with FIFO size of 64Bytes.
+ * 
+ *
+ *****************************************************************************/
+void USBDevInit(uint32 ulBase, uint16 usFlags, uint16 usFifoPtr);
+
+
+/******************************************************************************
+ *
+ *  Initialize the USB Device's EP0
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usSize FIFO size. Supported values are USB_FIFO_SZ_8/USB_FIFO_SZ_16/
+ *          USB_FIFO_SZ_32/USB_FIFO_SZ_64.
+ *  \param usFifoPtr specifies the start of the EP0 FIFO.
+ * 
+ *  This function will initialize the USB Device controller specified by the
+ *  \e ulBase parameter.  The \e uFlags parameter is not used by this
+ *  implementation.
+ * 
+ *  \return None
+ * 
+ *
+ *****************************************************************************/
+void USBDevEp0Config(uint32 ulBase, uint16 usSize, uint16 usFifoPtr);
+
+
+/******************************************************************************
+ *
+ *  Disable control interrupts on a given USB device controller.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usFlags specifies which control interrupts to disable.
+ * 
+ *  This function will disable the interrupts for the USB device controller
+ *  specified by the \e ulBase parameter.  The \e usFlags parameter specifies
+ *  which control interrupts to disable.  The flags passed in the \e usFlags
+ *  parameters should be the definitions that start with \b USBD_INT_EN_*
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBIntDisable(uint32 ulBase, uint16 usFlags);
+
+
+/******************************************************************************
+ *
+ *  Enable control interrupts on a given USB device controller.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usFlags specifies which control interrupts to enable.
+ * 
+ *  This function will enable the control interrupts for the USB device controller
+ *  specified by the \e ulBase parameter.  The \e usFlags parameter specifies
+ *  which control interrupts to enable.  The flags passed in the \e usFlags
+ *  parameters should be the definitions that start with \b USBD_INT_EN_* and
+ *  not any other \b USB_INT flags.
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBIntEnable(uint32 ulBase, uint16 usFlags);
+
+
+/******************************************************************************
+ *
+ *  Returns the control interrupt status on a given USB device controller.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ * 
+ *  This function will read interrupt status for a USB device controller.
+ *  The bit values returned should be compared against the \b USBD_INT_SRC_*
+ *  values.
+ * 
+ *  \return Returns the status of the control interrupts for a USB device controller.
+ *
+ *****************************************************************************/
+uint16 USBIntStatus(uint32 ulBase);
+
+
+/******************************************************************************
+ *
+ *  Stalls the specified endpoint in device mode.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usEndpoint specifies the endpoint to stall.
+ *  \param usFlags specifies whether to stall the IN or OUT endpoint.
+ * 
+ *  This function will cause to endpoint number passed in to go into a stall
+ *  condition.  If the \e usFlags parameter is \b USB_EP_DEV_IN then the stall
+ *  will be issued on the IN portion of this endpoint.  If the \e usFlags
+ *  parameter is \b USB_EP_DEV_OUT then the stall will be issued on the OUT
+ *  portion of this endpoint.
+ * 
+ *  \note This function should only be called in device mode.
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBDevEndpointStall(uint32 ulBase, uint16 usEndpoint, uint16 usFlags);
+
+
+/******************************************************************************
+ *
+ *  Clears the stall condition on the specified endpoint in device mode.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usEndpoint specifies which endpoint to remove the stall condition.
+ *  \param usFlags specifies whether to remove the stall condition from the IN
+ *  or the OUT portion of this endpoint.
+ * 
+ *  This function will cause the endpoint number passed in to exit the stall
+ *  condition.  If the \e usFlags parameter is \b USB_EP_DEV_IN then the stall
+ *  will be cleared on the IN portion of this endpoint.  If the \e usFlags
+ *  parameter is \b USB_EP_DEV_OUT then the stall will be cleared on the OUT
+ *  portion of this endpoint.
+ * 
+ *  \note This function should only be called in device mode.
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBDevEndpointStallClear(uint32 ulBase, uint16 usEndpoint, uint16 usFlags);
+
+
+/******************************************************************************
+ *
+ *  Connects the USB device controller to the bus in device mode.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ * 
+ *  This function will cause the soft connect feature of the USB device controller to
+ *  be enabled.  Call USBDisconnect() to remove the USB device from the bus.
+ * 
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBDevConnect(uint32 ulBase);
+
+
+/******************************************************************************
+ *
+ *  Removes the USB device controller from the bus in device mode.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ * 
+ *  This function will cause the soft disconnect feature of the USB device controller to
+ *  remove the device from the USB bus.  A call to USBDevConnect() is needed to
+ *  reconnect to the bus.
+ * 
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBDevDisconnect(uint32 ulBase);
+
+
+/******************************************************************************
+ *
+ *  Sets the address in device mode.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param ulAddress is the address to use for a device.
+ * 
+ *  This function will set the device address on the USB bus.  This address was
+ *  likely received via a SET ADDRESS command from the host controller.
+ * 
+ *  \note This function is not available on this controller. This is maintained
+ *          for compatibility.
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBDevAddrSet(uint32 ulBase, uint32 ulAddress);
+
+
+/******************************************************************************
+ *
+ *  Determine the number of bytes of data available in a given endpoint's FIFO.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usEndpoint is the endpoint to access.
+ * 
+ *  This function will return the number of bytes of data currently available
+ *  in the FIFO for the given receive (OUT) endpoint.  It may be used prior to
+ *  calling USBEndpointDataGet() to determine the size of buffer required to
+ *  hold the newly-received packet.
+ * 
+ *  \return This call will return the number of bytes available in a given
+ *  endpoint FIFO.
+ *
+ *****************************************************************************/
+uint16 USBEndpointDataAvail(uint32 ulBase, uint16 usEndpoint);
+
+
+/******************************************************************************
+ *
+ *  Retrieves data from the given endpoint's FIFO.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usEndpoint is the endpoint to access.
+ *  \param pucData is a pointer to the data area used to return the data from
+ *  the FIFO.
+ *  \param pulSize is initially the size of the buffer passed into this call
+ *  via the \e pucData parameter.  It will be set to the amount of data
+ *  returned in the buffer.
+ * 
+ *  This function will return the data from the FIFO for the given endpoint.
+ *  The \e pulSize parameter should indicate the size of the buffer passed in
+ *  the \e pulData parameter.  The data in the \e pulSize parameter will be
+ *  changed to match the amount of data returned in the \e pucData parameter.
+ *  If a zero byte packet was received this call will not return a error but
+ *  will instead just return a zero in the \e pulSize parameter.  The only
+ *  error case occurs when there is no data packet available.
+ * 
+ *  \return This call will return 0, or -1 if no packet was received.
+ *
+ *****************************************************************************/
+sint32 USBEndpointDataGet(
+    uint32                     ulBase, 
+    uint16                     usEndpoint, 
+    uint8 *                    pucData, 
+    uint32 *                   pulSize);
+
+
+/******************************************************************************
+ *
+ *  Retrieves the setup packet from EP0 Setup FIFO
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param sPkt Pointer to the data area for storing the setup packet.
+ *          Atleast 8 bytes should be available.
+ *  \param pusPktSize On return this contains the size of the setup packet (8Bytes)
+ * 
+ *  This function will retrieves the 8Byte long setup packet from the EP0 setup
+ *  FIFO.
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBDevGetSetupPacket (uint32 ulBase, uint8 * sPkt, uint16 * pusPktSize);
+
+
+/******************************************************************************
+ *
+ *  Acknowledge that data was read from the given endpoint's FIFO in device
+ *  mode.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usEndpoint is the endpoint to access.
+ *  \param bIsLastPacket This parameter is not used.
+ * 
+ *  This function acknowledges that the data was read from the endpoint's FIFO.
+ *  The \e bIsLastPacket parameter is set to a \b true value if this is the
+ *  last in a series of data packets on endpoint zero.  The \e bIsLastPacket
+ *  parameter is not used for endpoints other than endpoint zero.  This call
+ *  can be used if processing is required between reading the data and
+ *  acknowledging that the data has been read.
+ * 
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBDevEndpointDataAck(uint32 ulBase, uint16 usEndpoint, tBoolean bIsLastPacket);
+
+
+/******************************************************************************
+ *
+ *  Puts data into the given endpoint's FIFO.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usEndpoint is the endpoint to access.
+ *  \param pucData is a pointer to the data area used as the source for the
+ *  data to put into the FIFO.
+ *  \param ulSize is the amount of data to put into the FIFO.
+ * 
+ *  This function will put the data from the \e pucData parameter into the FIFO
+ *  for this endpoint.  If a packet is already pending for transmission then
+ *  this call will not put any of the data into the FIFO and will return -1.
+ *  Care should be taken to not write more data than can fit into the FIFO
+ *  allocated by the call to USBFIFOConfig().
+ * 
+ *  \return This call will return 0 on success, or -1 to indicate that the FIFO
+ *  is in use and cannot be written.
+ *
+ *****************************************************************************/
+uint32 USBEndpointDataPut(
+    uint32                     ulBase, 
+    uint16                     usEndpoint,
+    uint8 *                    pucData, 
+    uint32                     ulSize);
+
+/******************************************************************************
+ *
+ *  Starts the transfer of data from an endpoint's FIFO.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usEndpoint is the endpoint to access.
+ *  \param ulTransType Not used.
+ * 
+ *  This function will start the transfer of data from the FIFO for a given
+ *  endpoint.
+ * 
+ *  \return This call will return 0 on success, or -1 if a transmission is
+ *  already in progress.
+ *
+ *****************************************************************************/
+uint32 USBEndpointDataSend(uint32 ulBase, uint16 usEndpoint, uint32 ulTransType);
+
+
+/******************************************************************************
+ *
+ *  Resets the USB Device Controller
+ * 
+ *  \param void
+ * 
+ *  \return None.
+ *
+ *  \note Since the USB Device reset is handled by the host, this is a dummy
+ *  function & maintained for compatibility purpose.
+ *
+ *****************************************************************************/
+void USBReset(void);
+
+
+/******************************************************************************
+ *
+ *  Sets the FIFO configuration for an endpoint.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usEndpoint is the endpoint to access.
+ *  \param uFIFOAddress is the starting address for the FIFO.
+ *  \param uFIFOSize is the size of the FIFO in bytes.
+ *  \param uFlags specifies what information to set in the FIFO configuration.
+ * 
+ *  This function will set the starting FIFO RAM address and size of the FIFO
+ *  for a given endpoint.  Endpoint zero does not have a dynamically
+ *  configurable FIFO so this function should not be called for endpoint zero.
+ *  The \e uFIFOSize parameter should be one of the values in the
+ *  \b USB_FIFO_SZ_ values.  If the endpoint is going to use double buffering
+ *  it should use the values with the \b _DB at the end of the value.  For
+ *  example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16
+ *  byte double buffered FIFO.  If a double buffered FIFO is used, then the
+ *  actual size of the FIFO will be twice the size indicated by the
+ *  \e uFIFOSize parameter.  This means that the \b USB_FIFO_SZ_16_DB value
+ *  will use 32 bytes of the USB controller's FIFO memory.
+ * 
+ *  The \e uFIFOAddress value should be a multiple of 8 bytes and directly
+ *  indicates the starting address in the USB controller's FIFO RAM.  For
+ *  example, a value of 64 indicates that the FIFO should start 64 bytes into
+ *  the USB controller's FIFO memory.  The \e uFlags value specifies whether
+ *  the endpoint's OUT or IN FIFO should be configured.  If in host mode, use
+ *  \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode use
+ *  \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN.
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBFIFOConfigSet(uint32 ulBase, uint32 usEndpoint, uint32 uFIFOAddress, uint32 uFIFOSize, uint16 uFlags);
+
+
+/******************************************************************************
+ *
+ *  Gets the current configuration for an endpoint.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usEndpoint is the endpoint to access.
+ *  \param pulMaxPacketSize is a pointer which will be written with the
+ *  maximum packet size for this endpoint.
+ *  \param puFlags is a pointer which will be written with the current
+ *  endpoint settings. On entry to the function, this pointer must contain
+ *  either \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or
+ *  OUT endpoint is to be queried.
+ * 
+ *  This function will return the basic configuration for an endpoint in device
+ *  mode. The values returned in \e *pulMaxPacketSize and \e *puFlags are
+ *  equivalent to the \e ulMaxPacketSize and \e uFlags previously passed to
+ *  USBDevEndpointConfigSet() for this endpoint.
+ * 
+ *  \note This function should only be called in device mode.
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBDevEndpointConfigGet(
+    uint32                     ulBase, 
+    uint16                     usEndpoint, 
+    uint32 *                   pulMaxPacketSize, 
+    uint32 *                   puFlags);
+
+
+/******************************************************************************
+ *
+ *  Sets the configuration for an endpoint.
+ * 
+ *  \param ulBase specifies the USB module base address.
+ *  \param usEndpoint is the endpoint to access.
+ *  \param ulMaxPacketSize is the maximum packet size for this endpoint.
+ *  \param uFlags are used to configure other endpoint settings.
+ * 
+ *  This function will set the basic configuration for an endpoint in device
+ *  mode.  Endpoint zero does not have a dynamic configuration, so this
+ *  function should not be called for endpoint zero.  The \e uFlags parameter
+ *  determines some of the configuration while the other parameters provide the
+ *  rest.
+ * 
+ *  The \b USB_EP_MODE_ flags define what the type is for the given endpoint.
+ * 
+ *  - \b USB_EP_MODE_CTRL is a control endpoint.
+ *  - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+ *  - \b USB_EP_MODE_BULK is a bulk endpoint.
+ *  - \b USB_EP_MODE_INT is an interrupt endpoint.
+ * 
+ * 
+ *  \note This function should only be called in device mode.
+ * 
+ *  \return None.
+ *
+ *****************************************************************************/
+void USBDevEndpointConfigSet(uint32 ulBase, uint16 usEndpoint, uint32 ulMaxPacketSize, uint32 uFlags);
+
+void USBDevSetDevCfg(uint32 ulBase);
+void USBDevClearDevCfg(uint32 ulBase);
+uint16 USBDevGetEPnStat(uint32 ulBase);
+void USBDevPullEnableDisable(uint32 ulBase, uint32 ulSet);
+void USBIntStatusClear (uint16 uFlag);
+uint16 USBDevGetDevStat(uint32 ulBase);
+void USBDevCfgUnlock(uint32 ulBase);
+void USBDevCfgLock(uint32 ulBase);
+
+#endif /*USB_H_*/
+ 
+ 
+ 
+ 
diff --git a/include/arch/rm46l8lp/halcogen/usb_serial_structs.h b/include/arch/rm46l8lp/halcogen/usb_serial_structs.h
new file mode 100644
index 0000000..f970698
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/usb_serial_structs.h
@@ -0,0 +1,74 @@
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/**
+ *  @file       usb_serial_structs.h
+ *
+ *  @brief      Data structures defining this USB CDC device.
+ * 
+ */
+ 
+#ifndef _USB_SERIAL_STRUCTS_H_
+#define _USB_SERIAL_STRUCTS_H_
+
+/******************************************************************************
+ *
+ * The size of the transmit and receive buffers used for the redirected UART.
+ * This number should be a power of 2 for best performance.  256 is chosen
+ * pretty much at random though the buffer should be at least twice the size of
+ * a maxmum-sized USB packet.
+ *
+ *****************************************************************************/
+#define UART_BUFFER_SIZE 0x0001
+
+/** ***************************************************************************
+ *
+ * CDC device callback function prototypes.
+ *
+ *****************************************************************************/
+uint32 RxHandler(void *pvCBData, uint32 ulEvent,
+                        uint32 ulMsgValue, void *pvMsgData);
+uint32 TxHandler(void *pvCBData, uint32 ulEvent,
+                        uint32 ulMsgValue, void *pvMsgData);
+uint32 ControlHandler(void *pvCBData, uint32 ulEvent,
+                             uint32 ulMsgValue, void *pvMsgData);
+
+extern const tUSBBuffer g_sTxBuffer;
+extern const tUSBBuffer g_sRxBuffer;
+extern const tUSBDCDCDevice g_sCDCDevice;
+extern uint8 g_pucUSBTxBuffer[];
+extern uint8 g_pucUSBRxBuffer[];
+
+#endif
diff --git a/include/arch/rm46l8lp/halcogen/usbcdc.h b/include/arch/rm46l8lp/halcogen/usbcdc.h
new file mode 100644
index 0000000..4e71e94
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/usbcdc.h
@@ -0,0 +1,742 @@
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/******************************************************************************
+ *
+ * Note: This header contains definitions related to the USB Communication
+ *       Device Class specification.  The header is complete for ACM model
+ *       devices but request and notification definitions specific to other
+ *       modem types, ISDN, ATM and Ethernet are currently incomplete or
+ *       omitted.
+ *
+ *****************************************************************************/
+
+#ifndef __USBCDC_H__
+#define __USBCDC_H__
+
+/******************************************************************************
+ *
+ * If building with a C++ compiler, make all of the definitions in this header
+ * have a C binding.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/******************************************************************************
+ *
+ * \ingroup cdc_device_class_api
+ * @{
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Generic macros to read a byte, word or long from a character pointer.
+ *
+ *****************************************************************************/
+/* #define BYTE(pucData)           (*(uint8 *)(pucData))
+#define SHORT(pucData)          (*(uint16 *)(pucData))
+#define LONG(pucData)           (*(uint32 *)(pucData)) */
+
+/******************************************************************************
+ *
+ * USB CDC subclass codes.  Used in interface descriptor, bInterfaceClass
+ *
+ *****************************************************************************/
+#define USB_CDC_SUBCLASS_DIRECT_LINE_MODEL          0x01
+#define USB_CDC_SUBCLASS_ABSTRACT_MODEL             0x02
+#define USB_CDC_SUBCLASS_TELEPHONE_MODEL            0x03
+#define USB_CDC_SUBCLASS_MULTI_CHANNEL_MODEL        0x04
+#define USB_CDC_SUBCLASS_CAPI_MODEL                 0x05
+#define USB_CDC_SUBCLASS_ETHERNET_MODEL             0x06
+#define USB_CDC_SUBCLASS_ATM_MODEL                  0x07
+
+/******************************************************************************
+ *
+ * USB CDC control interface protocols.  Used in control interface descriptor,
+ * bInterfaceProtocol
+ *
+ *****************************************************************************/
+#define USB_CDC_PROTOCOL_NONE                       0x00
+#define USB_CDC_PROTOCOL_V25TER                     0x01
+#define USB_CDC_PROTOCOL_VENDOR                     0xFF
+
+/******************************************************************************
+ *
+ * USB CDC data interface protocols.  Used in data interface descriptor,
+ * bInterfaceProtocol
+ *
+ *****************************************************************************/
+/*      USB_CDC_PROTOCOL_NONE                       0x00 */
+#define USB_CDC_PROTOCOL_I420                       0x30
+#define USB_CDC_PROTOCOL_TRANSPARENT                0x32
+#define USB_CDC_PROTOCOL_Q921M                      0x50
+#define USB_CDC_PROTOCOL_Q921                       0x51
+#define USB_CDC_PROTOCOL_Q921TM                     0x52
+#define USB_CDC_PROTOCOL_V42BIS                     0x90
+#define USB_CDC_PROTOCOL_Q921EURO                   0x91
+#define USB_CDC_PROTOCOL_V120                       0x92
+#define USB_CDC_PROTOCOL_CAPI20                     0x93
+#define USB_CDC_PROTOCOL_HOST_DRIVER                0xFD
+#define USB_CDC_PROTOCOL_CDC_SPEC                   0xFE
+/*      USB_CDC_PROTOCOL_VENDOR                     0xFF */
+
+/******************************************************************************
+ *
+ * Functional descriptor definitions
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Functional descriptor types
+ *
+ *****************************************************************************/
+#define USB_CDC_CS_INTERFACE                    0x24
+#define USB_CDC_CS_ENDPOINT                     0x25
+
+/******************************************************************************
+ *
+ * Functional descriptor subtypes
+ *
+ *****************************************************************************/
+#define USB_CDC_FD_SUBTYPE_HEADER               0x00
+#define USB_CDC_FD_SUBTYPE_CALL_MGMT            0x01
+#define USB_CDC_FD_SUBTYPE_ABSTRACT_CTL_MGMT    0x02
+#define USB_CDC_FD_SUBTYPE_DIRECT_LINE_MGMT     0x03
+#define USB_CDC_FD_SUBTYPE_TELEPHONE_RINGER     0x04
+#define USB_CDC_FD_SUBTYPE_LINE_STATE_CAPS      0x05
+#define USB_CDC_FD_SUBTYPE_UNION                0x06
+#define USB_CDC_FD_SUBTYPE_COUNTRY              0x07
+#define USB_CDC_FD_SUBTYPE_TELEPHONE_MODES      0x08
+#define USB_CDC_FD_SUBTYPE_USB_TERMINAL         0x09
+#define USB_CDC_FD_SUBTYPE_NETWORK_TERMINAL     0x0A
+#define USB_CDC_FD_SUBTYPE_PROTOCOL_UNIT        0x0B
+#define USB_CDC_FD_SUBTYPE_EXTENSION_UNIT       0x0C
+#define USB_CDC_FD_SUBTYPE_MULTI_CHANNEL_MGMT   0x0D
+#define USB_CDC_FD_SUBTYPE_CAPI_MGMT            0x0E
+#define USB_CDC_FD_SUBTYPE_ETHERNET             0x0F
+#define USB_CDC_FD_SUBTYPE_ATM                  0x10
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_CALL_MGMT, Header functional descriptor, bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_CALL_MGMT_VIA_DATA              0x02
+#define USB_CDC_CALL_MGMT_HANDLED               0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_ABSTRACT_CTL_MGMT, Abstract Control Management functional
+ * descriptor, bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_ACM_SUPPORTS_NETWORK_CONNECTION 0x08
+#define USB_CDC_ACM_SUPPORTS_SEND_BREAK         0x04
+#define USB_CDC_ACM_SUPPORTS_LINE_PARAMS        0x02
+#define USB_CDC_ACM_SUPPORTS_COMM_FEATURE       0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_DIRECT_LINE_MGMT, Direct Line Management functional
+ * descriptor, bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_DLM_NEEDS_EXTRA_PULSE_SETUP     0x04
+#define USB_CDC_DLM_SUPPORTS_AUX                0x02
+#define USB_CDC_DLM_SUPPORTS_PULSE              0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_TELEPHONE_MODES, Telephone Operational Modes functional
+ * descriptor, bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_TELEPHONE_SUPPORTS_COMPUTER     0x04
+#define USB_CDC_TELEPHONE_SUPPORTS_STANDALONE   0x02
+#define USB_CDC_TELEPHONE_SUPPORTS_SIMPLE       0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_LINE_STATE_CAPS, Telephone Call and Line State Reporting
+ * Capabilities descriptor
+ *
+ *****************************************************************************/
+#define USB_CDC_LINE_STATE_CHANGES_NOTIFIED     0x20
+#define USB_CDC_LINE_STATE_REPORTS_DTMF         0x10
+#define USB_CDC_LINE_STATE_REPORTS_DIST_RING    0x08
+#define USB_CDC_LINE_STATE_REPORTS_CALLERID     0x04
+#define USB_CDC_LINE_STATE_REPORTS_BUSY         0x02
+#define USB_CDC_LINE_STATE_REPORTS_INT_DIALTONE 0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_USB_TERMINAL, USB Terminal functional descriptor,
+ * bmOptions
+ *
+ *****************************************************************************/
+#define USB_CDC_TERMINAL_NO_WRAPPER_USED        0x00
+#define USB_CDC_TERMINAL_WRAPPER_USED           0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_MULTI_CHANNEL_MGMT, Multi-Channel Management functional
+ * descriptor, bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_MCM_SUPPORTS_SET_UNIT_PARAM     0x04
+#define USB_CDC_MCM_SUPPORTS_CLEAR_UNIT_PARAM   0x02
+#define USB_CDC_MCM_UNIT_PARAMS_NON_VOLATILE    0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_CAPI_MGMT, CAPI Control Management functional descriptor,
+ * bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_CAPI_INTELLIGENT                0x01
+#define USB_CDC_CAPI_SIMPLE                     0x00
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_ETHERNET, Ethernet Networking functional descriptor,
+ * bmEthernetStatistics
+ *
+ *****************************************************************************/
+#define USB_CDC_ENET_XMIT_OK                0x01000000U
+#define USB_CDC_ENET_RCV_OK                 0x02000000U
+#define USB_CDC_ENET_XMIT_ERROR             0x04000000U
+#define USB_CDC_ENET_RCV_ERROR              0x08000000U
+#define USB_CDC_ENET_RCV_NO_BUFFER          0x10000000U
+#define USB_CDC_ENET_DIRECTED_BYTES_XMIT    0x20000000U
+#define USB_CDC_ENET_DIRECTED_FRAMES_XMIT   0x40000000U
+#define USB_CDC_ENET_MULTICAST_BYTES_XMIT   0x80000000U
+#define USB_CDC_ENET_MULTICAST_FRAMES_XMIT  0x00010000U
+#define USB_CDC_ENET_BROADCAST_BYTES_XMIT   0x00020000U
+#define USB_CDC_ENET_BROADCAST_FRAMES_XMIT  0x00040000U
+#define USB_CDC_ENET_DIRECTED_BYTES_RCV     0x00080000U
+#define USB_CDC_ENET_DIRECTED_FRAMES_RCV    0x00100000U
+#define USB_CDC_ENET_MULTICAST_BYTES_RCV    0x00200000U
+#define USB_CDC_ENET_MULTICAST_FRAMES_RCV   0x00400000U
+#define USB_CDC_ENET_BROADCAST_BYTES_RCV    0x00800000U
+#define USB_CDC_ENET_BROADCAST_FRAMES_RCV   0x00000100U
+#define USB_CDC_ENET_RCV_CRC_ERROR          0x00000200U
+#define USB_CDC_ENET_TRANSMIT_QUEUE_LENGTH  0x00000400U
+#define USB_CDC_ENET_RCV_ERROR_ALIGNMENT    0x00000800U
+#define USB_CDC_ENET_XMIT_ONE_COLLISION     0x00001000U
+#define USB_CDC_ENET_XMIT_MORE_COLLISIONS   0x00002000U
+#define USB_CDC_ENET_XMIT_DEFERRED          0x00004000U
+#define USB_CDC_ENET_XMIT_MAX_COLLISIONS    0x00008000U
+#define USB_CDC_ENET_RCV_OVERRUN            0x00000001U
+#define USB_CDC_ENET_XMIT_UNDERRUN          0x00000002U
+#define USB_CDC_ENET_XMIT_HEARTBEAT_FAILURE 0x00000004U
+#define USB_CDC_ENET_XMIT_TIMES_CRS_LOST    0x00000008U
+#define USB_CDC_ENET_XMIT_LATE_COLLISIONS   0x00000010U
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_ATM, ATM Networking functional descriptor,
+ * bmDataCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_ATM_TYPE_3                      0x08
+#define USB_CDC_ATM_TYPE_2                      0x04
+#define USB_CDC_ATM_TYPE_1                      0x02
+
+/******************************************************************************
+ *
+ * bmATMDeviceStatistics
+ *
+ *****************************************************************************/
+#define USB_CDC_ATM_VC_US_CELLS_SENT            0x10
+#define USB_CDC_ATM_VC_US_CELLS_RECEIVED        0x08
+#define USB_CDC_ATM_DS_CELLS_HEC_ERR_CORRECTED  0x04
+#define USB_CDC_ATM_US_CELLS_SENT               0x02
+#define USB_CDC_ATM_US_CELLS_RECEIVED           0x01
+
+/******************************************************************************
+ *
+ * Management Element Requests (provided in tUSBRequest.ucRequest)
+ *
+ *****************************************************************************/
+#define USB_CDC_SEND_ENCAPSULATED_COMMAND                       0x00u
+#define USB_CDC_GET_ENCAPSULATED_RESPONSE                       0x01u
+#define USB_CDC_SET_COMM_FEATURE                                0x02u
+#define USB_CDC_GET_COMM_FEATURE                                0x03u
+#define USB_CDC_CLEAR_COMM_FEATURE                              0x04u
+#define USB_CDC_SET_AUX_LINE_STATE                              0x10u
+#define USB_CDC_SET_HOOK_STATE                                  0x11u
+#define USB_CDC_PULSE_SETUP                                     0x12u
+#define USB_CDC_SEND_PULSE                                      0x13u
+#define USB_CDC_SET_PULSE_TIME                                  0x14u
+#define USB_CDC_RING_AUX_JACK                                   0x15u
+#define USB_CDC_SET_LINE_CODING                                 0x20u
+#define USB_CDC_GET_LINE_CODING                                 0x21u
+#define USB_CDC_SET_CONTROL_LINE_STATE                          0x22u
+#define USB_CDC_SEND_BREAK                                      0x23u
+#define USB_CDC_SET_RINGER_PARMS                                0x30u
+#define USB_CDC_GET_RINGER_PARMS                                0x31u
+#define USB_CDC_SET_OPERATION_PARMS                             0x32u
+#define USB_CDC_GET_OPERATION_PARMS                             0x33u
+#define USB_CDC_SET_LINE_PARMS                                  0x34u
+#define USB_CDC_GET_LINE_PARMS                                  0x35u
+#define USB_CDC_DIAL_DIGITS                                     0x36u
+#define USB_CDC_SET_UNIT_PARAMETER                              0x37u
+#define USB_CDC_GET_UNIT_PARAMETER                              0x38u
+#define USB_CDC_CLEAR_UNIT_PARAMETER                            0x39u
+#define USB_CDC_GET_PROFILE                                     0x3Au
+#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS                  0x40u
+#define USB_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER    0x41u
+#define USB_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER    0x42u
+#define USB_CDC_SET_ETHERNET_PACKET_FILTER                      0x43u
+#define USB_CDC_GET_ETHERNET_STATISTIC                          0x44u
+#define USB_CDC_SET_ATM_DATA_FORMAT                             0x50u
+#define USB_CDC_GET_ATM_DEVICE_STATISTICS                       0x51u
+#define USB_CDC_SET_ATM_DEFAULT_VC                              0x52u
+#define USB_CDC_GET_ATM_VC_STATISTICS                           0x53u
+
+/******************************************************************************
+ *
+ * In cases where a request defined above results in the return of a fixed size
+ * data block, the following group of labels define the size of that block.  In
+ * each of these cases, an access macro is also provided to write the response
+ * data into an appropriately-sized array of uint8acters.
+ *
+ *****************************************************************************/
+#define USB_CDC_SIZE_COMM_FEATURE                                2
+#define USB_CDC_SIZE_LINE_CODING                                 7
+#define USB_CDC_SIZE_RINGER_PARMS                                4
+#define USB_CDC_SIZE_OPERATION_PARMS                             2
+#define USB_CDC_SIZE_UNIT_PARAMETER                              2
+#define USB_CDC_SIZE_PROFILE                                     64
+#define USB_CDC_SIZE_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER    2
+#define USB_CDC_SIZE_ETHERNET_STATISTIC                          4
+#define USB_CDC_SIZE_ATM_DEVICE_STATISTICS                       4
+#define USB_CDC_SIZE_ATM_VC_STATISTICS                           4
+#define USB_CDC_SIZE_LINE_PARMS                                  10
+
+/******************************************************************************
+ *
+ * NB: USB_CDC_SIZE_LINE_PARAMS assumes only a single call.  For multiple
+ * calls, add 4 bytes per additional call.
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * USB_CDC_GET_COMM_FEATURE & USB_CDC_SET_COMM_FEATURE
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * wValue (Feature Selector)
+ *
+ *****************************************************************************/
+#define USB_CDC_ABSTRACT_STATE                  0x0001
+#define USB_CDC_COUNTRY_SETTING                 0x0002
+
+/******************************************************************************
+ *
+ * Data when feature selector is USB_DCD_ABSTRACT_STATE
+ *
+ *****************************************************************************/
+#define USB_CDC_ABSTRACT_CALL_DATA_MULTIPLEXED  0x0002
+#define USB_CDC_ABSTRACT_ENDPOINTS_IDLE         0x0001
+
+/******************************************************************************
+ *
+ * Macros to populate the response data buffer (whose size in bytes is defined
+ * by USB_CDC_SIZE_COMM_FEATURE).
+ *
+ *****************************************************************************/
+/* 
+ * Add code for macro SetResponseCommFeature.
+ */
+/******************************************************************************
+ *
+ * USB_CDC_SET_AUX_LINE_STATE, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_AUX_DISCONNECT                  0x0000
+#define USB_CDC_AUX_CONNECT                     0x0001
+
+/******************************************************************************
+ *
+ * USB_CDC_SET_HOOK_STATE, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_ON_HOOK                         0x0000
+#define USB_CDC_OFF_HOOK                        0x0001
+#define USB_CDC_SNOOPING                        0x0002
+
+/******************************************************************************
+ *
+ * USB_CDC_GET_LINE_CODING
+ *
+ *****************************************************************************/
+#define USB_CDC_STOP_BITS_1                     0x00
+#define USB_CDC_STOP_BITS_1_5                   0x01
+#define USB_CDC_STOP_BITS_2                     0x02
+
+#define USB_CDC_PARITY_NONE                     0x00
+#define USB_CDC_PARITY_ODD                      0x01
+#define USB_CDC_PARITY_EVEN                     0x02
+#define USB_CDC_PARITY_MARK                     0x03
+#define USB_CDC_PARITY_SPACE                    0x04
+
+/******************************************************************************
+ *
+ * Macro to populate the response data buffer (whose size in bytes is defined
+ * by USB_CDC_SIZE_LINE_CODING).
+ *
+ *****************************************************************************/
+/* 
+ * Add code for macro SetResponseLineCoding.
+ */
+/******************************************************************************
+ *
+ * USB_CDC_SET_CONTROL_LINE_STATE, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_DEACTIVATE_CARRIER              0x00
+#define USB_CDC_ACTIVATE_CARRIER                0x02
+#define USB_CDC_DTE_NOT_PRESENT                 0x00
+#define USB_CDC_DTE_PRESENT                     0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_SET_RINGER_PARMS, USB_CDC_GET_RINGER_PARMS and
+ * USB_CDC_GET_LINE_PARMS (ulRingerBmp)
+ *
+ *****************************************************************************/
+#define USB_CDC_RINGER_EXISTS                   0x80000000U
+#define USB_CDC_RINGER_DOES_NOT_EXIST           0x00000000
+
+/******************************************************************************
+ *
+ * Macro to populate the response data buffer to USB_CDC_GET_RINGER_PARMS.
+ * Parameter buf points to a buffer of size USB_CDC_SIZE_RINGER_PARMS bytes.
+ *
+ *****************************************************************************/
+/* 
+ * Add code for macro SetResponseRingerParms.
+ */
+/******************************************************************************
+ *
+ * Macros to extract fields from the USB_CDC_SET_RINGER_PARMS data
+ *
+ *****************************************************************************/
+/* #define GetRingerVolume(pcData)  (BYTE((pcData)+1)) */
+/* #define GetRingerPattern(pcData) (BYTE(pcData)) */
+/* #define GetRingerExists(pcData)  ((LONG(pcData)) & USB_CDC_RINGER_EXISTS) */
+
+/******************************************************************************
+ *
+ * USB_CDC_SET_OPERATION_PARMS, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_SIMPLE_MODE                     0x0000
+#define USB_CDC_STANDALONE_MODE                 0x0001
+#define USB_CDC_HOST_CENTRIC_MODE               0x0002
+
+/******************************************************************************
+ *
+ * Macro to populate the response data buffer to USB_CDC_GET_OPERATION_PARMS.
+ * Parameter buf points to a buffer of size USB_CDC_SIZE_OPERATION_PARMS
+ * bytes.
+ *
+ *****************************************************************************/
+/* 
+ * Add code for macro SetResponseOperationParms.
+ */
+/******************************************************************************
+ *
+ * USB_CDC_SET_LINE_PARMS, wParam - Line State Change
+ *
+ *****************************************************************************/
+#define USB_CDC_DROP_ACTIVE_CALL                0x0000
+#define USB_CDC_START_NEW_CALL                  0x0001
+#define USB_CDC_APPLY_RINGING                   0x0002
+#define USB_CDC_REMOVE_RINGING                  0x0003
+#define USB_CDC_SWITCH_CALL                     0x0004
+
+/******************************************************************************
+ *
+ * Line state bitmap in USB_CDC_GET_LINE_PARMS response
+ *
+ *****************************************************************************/
+#define USB_CDC_LINE_IS_ACTIVE                  0x80000000U
+#define USB_CDC_LINE_IS_IDLE                    0x00000000U
+#define USB_CDC_LINE_NO_ACTIVE_CALL             0x000000FFU
+
+#define USB_CDC_CALL_ACTIVE                     0x80000000U
+
+/******************************************************************************
+ *
+ * Call state value definitions
+ *
+ *****************************************************************************/
+#define USB_CDC_CALL_IDLE                       0x00000000
+#define USB_CDC_CALL_TYPICAL_DIALTONE           0x00000001
+#define USB_CDC_CALL_INTERRUPTED_DIALTONE       0x00000002
+#define USB_CDC_CALL_DIALING                    0x00000003
+#define USB_CDC_CALL_RINGBACK                   0x00000004
+#define USB_CDC_CALL_CONNECTED                  0x00000005
+#define USB_CDC_CALL_INCOMING                   0x00000006
+
+/******************************************************************************
+ *
+ * Call state change value definitions
+ *
+ *****************************************************************************/
+#define USB_CDC_CALL_STATE_IDLE                 0x01
+#define USB_CDC_CALL_STATE_DIALING              0x02
+#define USB_CDC_CALL_STATE_RINGBACK             0x03
+#define USB_CDC_CALL_STATE_CONNECTED            0x04
+#define USB_CDC_CALL_STATE_INCOMING             0x05
+
+/******************************************************************************
+ *
+ * Extra byte of data describing the connection type for
+ * USB_CDC_CALL_STATE_CONNECTED.
+ *
+ *****************************************************************************/
+#define USB_CDC_VOICE                           0x00
+#define USB_CDC_ANSWERING_MACHINE               0x01
+#define USB_CDC_FAX                             0x02
+#define USB_CDC_MODEM                           0x03
+#define USB_CDC_UNKNOWN                         0xFF
+
+/******************************************************************************
+ *
+ * Macro to extract call index from request in cases where wParam is
+ * USB_CDC_SWITCH_CALL.
+ *
+ *****************************************************************************/
+/* #define GetCallIndex(pcData) (BYTE(pcData)) */
+
+/******************************************************************************
+ *
+ * Macro to populate the CallState entries in response to request
+ * USB_CDC_GET_LINE_PARMS.  The ucIndex parameter is a zero based index
+ * indicating which call entry in the pcBuf response buffer to fill in.  Note
+ * that pcBuf points to the first byte of the buffer (the wLength field).
+ *
+ *****************************************************************************/
+/* 
+ * Add code for macro SetResponseCallState.
+ */
+/******************************************************************************
+ *
+ * Macro to populate the response data buffer (whose size in bytes is defined
+ * by USB_CDC_SIZE_LINE_PARMS).  Note that this macro only populates fields for
+ * a single call.  If multiple calls are being managed, additional 4 byte
+ * fields must be appended to provide call state for each call after the first.
+ * This may be done using the SetResponseCallState macro with the appropriate
+ * call index supplied.
+ *
+ *****************************************************************************/
+/* 
+ * Add code for macro  SetResponseLineParms.
+ */
+/******************************************************************************
+ *
+ * Notification Element definitions
+ *
+ *****************************************************************************/
+#define USB_CDC_NOTIFY_NETWORK_CONNECTION               0x00
+#define USB_CDC_NOTIFY_RESPONSE_AVAILABLE               0x01
+#define USB_CDC_NOTIFY_AUX_JACK_HOOK_STATE              0x08
+#define USB_CDC_NOTIFY_RING_DETECT                      0x09
+#define USB_CDC_NOTIFY_SERIAL_STATE                     0x20
+#define USB_CDC_NOTIFY_CALL_STATE_CHANGE                0x28
+#define USB_CDC_NOTIFY_LINE_STATE_CHANGE                0x29
+#define USB_CDC_NOTIFY_CONNECTION_SPEED_CHANGE          0x2A
+
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_NETWORK_CONNECTION, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_NETWORK_DISCONNECTED                    0x0000
+#define USB_CDC_NETWORK_CONNECTED                       0x0001
+
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_AUX_JACK_HOOK_STATE, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_AUX_JACK_ON_HOOK                        0x0000
+#define USB_CDC_AUX_JACK_OFF_HOOK                       0x0001
+
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_SERIAL_STATE, Data
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Number of bytes of data returned alongside this notification.
+ *
+ *****************************************************************************/
+#define USB_CDC_NOTIFY_SERIAL_STATE_SIZE                2u
+
+#define USB_CDC_SERIAL_STATE_OVERRUN                    0x0040U
+#define USB_CDC_SERIAL_STATE_PARITY                     0x0020U
+#define USB_CDC_SERIAL_STATE_FRAMING                    0x0010U
+#define USB_CDC_SERIAL_STATE_RING_SIGNAL                0x0008U
+#define USB_CDC_SERIAL_STATE_BREAK                      0x0004U
+#define USB_CDC_SERIAL_STATE_TXCARRIER                  0x0002U
+#define USB_CDC_SERIAL_STATE_RXCARRIER                  0x0001U
+
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_CALL_STATE_CHANGE, wValue
+ *
+ * Call state values are defined above in the group beginning
+ * USB_CDC_CALL_STATE_IDLE.  Note that the data returned alongside this
+ * notification are heavily dependent upon the call state being reported so no
+ * specific lengths or access macros are provided here.
+ *
+ * Macro to construct the correct wValue for this notification given a state
+ * and call index.
+ *
+ *****************************************************************************/
+/* 
+ * Add code for macro SetNotifyCallStatewValue.
+ */
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_LINE_STATE_CHANGE, wValue
+ *
+ * Note that the data returned alongside this notification are heavily
+ * dependent upon the call state being reported so no specific lengths or
+ * access macros are provided here.
+ *
+ *****************************************************************************/
+#define USB_CDC_LINE_STATE_IDLE                         0x0000
+#define USB_CDC_LINE_STATE_HOLD                         0x0001
+#define USB_CDC_LINE_STATE_OFF_HOOK                     0x0002
+#define USB_CDC_LINE_STATE_ON_HOOK                      0x0003
+
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_CONNECTION_SPEED_CHANGE, Data
+ *
+ * Macro to populate the 8 byte data structure returned alongside this
+ * notification.
+ *
+ *****************************************************************************/
+/* 
+ * Add code for macro SetNotifyConnectionSpeedChange.
+ */
+/******************************************************************************
+ *
+ * Packed structure definitions for request/response data blocks
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * All structures defined in this section of the header require byte packing of
+ * fields.  This is usually accomplished using the PACKED macro but, for IAR
+ * Embedded Workbench, this requires a pragma.
+ *
+ *****************************************************************************/
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack(1)
+#endif
+
+/**
+ *  @brief      USB_CDC_GET/SET_LINE_CODING request-specific data.
+ */
+typedef struct
+{
+    /**
+     *  @brief  The data terminal rate in bits per second.
+     */
+    uint32 ulRate;
+
+    /**
+     *  @brief  The number of stop bits.  Valid values are USB_CDC_STOP_BITS_1,
+     *          USB_CDC_STOP_BITS_1_5 or USB_CDC_STOP_BITS_2
+     */
+    uint8 ucStop;
+
+    /**
+     *  @brief  The parity setting.  Valid values are USB_CDC_PARITY_NONE,
+     *          USB_CDC_PARITY_ODD, USB_CDC_PARITY_EVEN, USB_CDC_PARITY_MARK 
+     *          and USB_CDC_PARITY_SPACE.
+     */
+    uint8 ucParity;
+
+    /**
+     *  @brief  The number of data bits per character.  Valid values are 
+     *          5, 6, 7 and 8 in this implementation.
+     */
+    uint8 ucDatabits;
+}
+PACKED tLineCoding;
+
+/******************************************************************************
+ *
+ * Return to default packing when using the IAR Embedded Workbench compiler.
+ *
+ *****************************************************************************/
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack()
+#endif
+
+/**
+ *  Close the Doxygen group.
+ *  @}
+ */
+
+/******************************************************************************
+ *
+ * Mark the end of the C bindings section for C++ compilers.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBCDC_H__ */
diff --git a/include/arch/rm46l8lp/halcogen/usbdcdc.h b/include/arch/rm46l8lp/halcogen/usbdcdc.h
new file mode 100644
index 0000000..0fd7494
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/usbdcdc.h
@@ -0,0 +1,383 @@
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/**
+ *  @file       usbdcdc.h
+ *
+ *  @brief      USBLib support for generic CDC ACM (serial) device.
+ * 
+ */
+
+#ifndef __USBDCDC_H__
+#define __USBDCDC_H__
+
+/******************************************************************************
+ *
+ * If building with a C++ compiler, make all of the definitions in this header
+ * have a C binding.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** ***************************************************************************
+ *
+ *  \ingroup cdc_device_class_api
+ *  @{
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * PRIVATE
+ *
+ * The first few sections of this header are private defines that are used by
+ * the USB CDC Serial code and are here only to help with the application
+ * allocating the correct amount of memory for the CDC Serial device code.
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * PRIVATE
+ *
+ * This enumeration holds the various states that the device can be in during
+ * normal operation.
+ *
+ *****************************************************************************/
+typedef enum
+{
+    /**
+     *  @brief  Unconfigured.
+     */
+    CDC_STATE_UNCONFIGURED,
+
+    /**
+     *  @brief  No outstanding transaction remains to be completed.
+     */
+    CDC_STATE_IDLE,
+
+    /**
+     *  @brief  Waiting on completion of a send or receive transaction.
+     */
+    CDC_STATE_WAIT_DATA,
+
+    /**
+     *  @brief  Waiting for client to process data.
+     */
+    CDC_STATE_WAIT_CLIENT
+}
+tCDCState;
+
+/******************************************************************************
+ *
+ * PRIVATE
+ *
+ * This structure defines the private instance data and state variables for the
+ * CDC Serial device.  The memory for this structure is pointed to by the
+ * psPrivateCDCSerData field in the tUSBDCDCDevice structure passed on
+ * USBDCDCInit().
+ *
+ *****************************************************************************/
+typedef struct
+{
+    uint32 ulUSBBase;
+    tDeviceInfo *psDevInfo;
+    tConfigDescriptor *psConfDescriptor;
+    volatile tCDCState eCDCRxState;
+    volatile tCDCState eCDCTxState;
+    volatile tCDCState eCDCRequestState;
+    volatile tCDCState eCDCInterruptState;
+    volatile uint8 ucPendingRequest;
+    uint16 usBreakDuration;
+    uint16 usControlLineState;
+    uint16 usSerialState;
+    volatile uint32 usDeferredOpFlags;
+    uint16 usLastTxSize;
+    tLineCoding sLineCoding;
+    volatile tBoolean bRxBlocked;
+    volatile tBoolean bControlBlocked;
+    volatile tBoolean bConnected;
+    uint8 ucControlEndpoint;
+    uint8 ucBulkINEndpoint;
+    uint8 ucBulkOUTEndpoint;
+    uint8 ucInterfaceControl;
+    uint8 ucInterfaceData;
+}
+tCDCSerInstance;
+
+
+#ifndef DEPRECATED
+/** ***************************************************************************
+ *
+ *  @brief  The number of bytes of workspace required by the CDC device class 
+ *          driver. The client must provide a block of RAM of at least this 
+ *          size in the psPrivateCDCSerData field of the tUSBCDCDevice 
+ *          structure passed on USBDCDCInit().
+ *
+ *          This value is deprecated and should not be used, any new code 
+ *          should just pass in a tUSBCDCDevice structure in the 
+ *          psPrivateCDCSerData field.
+ *
+ *****************************************************************************/
+#define USB_CDCSER_WORKSPACE_SIZE (sizeof(tCDCSerInstance))
+#endif
+
+/** ***************************************************************************
+ *
+ * The following defines are used when working with composite devices.
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ *  @brief  The size of the memory that should be allocated to create a 
+ *          configuration descriptor for a single instance of the USB Serial 
+ *          CDC Device. This does not include the configuration descriptor 
+ *          which is automatically ignored by the composite device class.
+ *
+ *          For reference this is sizeof(g_pIADSerDescriptor) +
+ *          sizeof(g_pCDCSerCommInterface) + sizeof(g_pCDCSerDataInterface)
+ *
+ *****************************************************************************/
+#define COMPOSITE_DCDC_SIZE     (8u + 35u + 23u)
+
+/** ***************************************************************************
+ *
+ * CDC-specific events These events are provided to the application in the
+ * \e ulMsg parameter of the tUSBCallback function.
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ *  @brief  The host requests that the device send a BREAK condition on its
+ *          serial communication channel.  The BREAK should remain active until
+ *          a USBD_CDC_EVENT_CLEAR_BREAK event is received.
+ */
+#define USBD_CDC_EVENT_SEND_BREAK (USBD_CDC_EVENT_BASE + 0u)
+
+/** ***************************************************************************
+ *
+ *  @brief  The host requests that the device stop sending a BREAK condition on
+ *          its serial communication channel.
+ */
+#define USBD_CDC_EVENT_CLEAR_BREAK (USBD_CDC_EVENT_BASE + 1u)
+
+/** ***************************************************************************
+ *
+ *  @brief  The host requests that the device set the RS232 signaling lines to
+ *          a particular state.  The ulMsgValue parameter contains the RTS and
+ *          DTR control line states as defined in table 51 of the USB CDC class
+ *          definition and is a combination of the following values:
+ *
+ *         (RTS) USB_CDC_DEACTIVATE_CARRIER or USB_CDC_ACTIVATE_CARRIER
+ *         (DTR) USB_CDC_DTE_NOT_PRESENT or USB_CDC_DTE_PRESENT
+ */
+#define USBD_CDC_EVENT_SET_CONTROL_LINE_STATE (USBD_CDC_EVENT_BASE + 2u)
+
+/** ***************************************************************************
+ *
+ *  @brief  The host requests that the device set the RS232 communication
+ *          parameters.  The pvMsgData parameter points to a tLineCoding 
+ *          structure defining the required number of bits per character, 
+ *          parity mode, number of stop bits and the baud rate.
+ */
+#define USBD_CDC_EVENT_SET_LINE_CODING (USBD_CDC_EVENT_BASE + 3u)
+
+/** ***************************************************************************
+ *
+ *  @brief  The host is querying the current RS232 communication parameters.  
+ *          The pvMsgData parameter points to a tLineCoding structure that the
+ *          application must fill with the current settings prior to returning
+ *          from the callback.
+ */
+#define USBD_CDC_EVENT_GET_LINE_CODING (USBD_CDC_EVENT_BASE + 4u)
+
+/** ***************************************************************************
+ *
+ *  @brief  The structure used by the application to define operating 
+ *          parameters for the CDC device.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The vendor ID that this device is to present in the device 
+     *          descriptor.
+     */
+    uint16 usVID;
+
+    /**
+     *  @brief  The product ID that this device is to present in the device 
+     *          descriptor.
+     */
+    uint16 usPID;
+
+    /**
+     *  @brief  The maximum power consumption of the device, expressed in 
+     *          milliamps.
+     */
+    uint16 usMaxPowermA;
+
+    /**
+     *  @brief  Indicates whether the device is self- or bus-powered and 
+     *          whether or not it supports remote wakeup.  Valid values are 
+     *          USB_CONF_ATTR_SELF_PWR or USB_CONF_ATTR_BUS_PWR, optionally 
+     *          ORed with USB_CONF_ATTR_RWAKE.
+     */
+    uint8 ucPwrAttributes;
+
+    /**
+     *  @brief  A pointer to the callback function which will be called to 
+     *          notify the application of all asynchronous control events 
+     *          related to the operation of the device.
+     */
+    tUSBCallback pfnControlCallback;
+
+    /**
+     *  @brief  A client-supplied pointer which will be sent as the first
+     *          parameter in all calls made to the control channel callback,
+     *          pfnControlCallback.
+     */
+    void *pvControlCBData;
+
+    /**
+     *  @brief  A pointer to the callback function which will be called to 
+     *          notify the application of events related to the device's data 
+     *          receive channel.
+     */
+    tUSBCallback pfnRxCallback;
+
+    /**
+     *  @brief  A client-supplied pointer which will be sent as the first
+     *          parameter in all calls made to the receive channel callback,
+     *          pfnRxCallback.
+     */
+    void *pvRxCBData;
+
+    /**
+     *  @brief  A pointer to the callback function which will be called to 
+     *          notify the application of events related to the device's data 
+     *          transmit channel.
+     */
+    tUSBCallback pfnTxCallback;
+
+    /**
+     *  @brief  A client-supplied pointer which will be sent as the first
+     *          parameter in all calls made to the transmit channel callback,
+     *          pfnTxCallback.
+     */
+    void *pvTxCBData;
+
+    /**
+     *  @brief  A pointer to the string descriptor array for this device.  This
+     *          array must contain the following string descriptor pointers in
+     *          this order. Language descriptor, Manufacturer name string 
+     *          (language 1), Product name string (language 1), Serial number 
+     *          Control interface description string (language 1), 
+     *          Configuration description string (language 1).
+     * 
+     *          If supporting more than 1 language, the strings for indices 
+     *          1 through 5 must be repeated for each of the other languages 
+     *          defined in the language descriptor.
+     */
+    const uint8 * const *ppStringDescriptors;
+
+    /**
+     *  @brief  The number of descriptors provided in the ppStringDescriptors
+     *          array.  This must be 1 + (5 * number of supported languages).
+     */
+    uint32 ulNumStringDescriptors;
+
+    /**
+     *  @brief  A pointer to the private instance data for this device.  This 
+     *          memory must remain accessible for as long as the CDC device is
+     *          in use and must not be modified by any code outside the CDC 
+     *          class driver.
+     */
+    tCDCSerInstance *psPrivateCDCSerData;
+}
+tUSBDCDCDevice;
+
+extern tDeviceInfo g_sCDCSerDeviceInfo;
+
+/** ***************************************************************************
+ *
+ * API Function Prototypes
+ *
+ *****************************************************************************/
+extern void * USBDCDCCompositeInit(uint32 ulIndex,
+                                   const tUSBDCDCDevice *psCDCDevice);
+extern void *USBDCDCInit(uint32 ulIndex,
+                         const tUSBDCDCDevice *psCDCDevice);
+extern void USBDCDCTerm(void *pvInstance);
+extern void *USBDCDCSetControlCBData(tUSBDCDCDevice *pvInstance, void *pvCBData);
+extern void *USBDCDCSetRxCBData(void *pvInstance, void *pvCBData);
+extern void *USBDCDCSetTxCBData(void *pvInstance, void *pvCBData);
+extern uint32 USBDCDCPacketWrite(void *pvInstance,
+                                        uint8 *pcData,
+                                        uint32 ulLength,
+                                        tBoolean bLast);
+extern uint32 USBDCDCPacketRead(void *pvInstance,
+                                       uint8 *pcData,
+                                       uint32 ulLength,
+                                       tBoolean bLast);
+extern uint32 USBDCDCTxPacketAvailable(void *pvInstance);
+extern uint32 USBDCDCRxPacketAvailable(void *pvInstance);
+extern void USBDCDCSerialStateChange(void *pvInstance,
+                                     uint16 usState);
+extern void USBDCDCPowerStatusSet(void *pvInstance, uint8 ucPower);
+extern tBoolean USBDCDCRemoteWakeupRequest(void *pvInstance);
+
+/** ***************************************************************************
+ *
+ *  Close the Doxygen group.
+ *  @}
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Mark the end of the C bindings section for C++ compilers.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBDCDC_H__ */
diff --git a/include/arch/rm46l8lp/halcogen/usbdevice.h b/include/arch/rm46l8lp/halcogen/usbdevice.h
new file mode 100644
index 0000000..67c3484
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/usbdevice.h
@@ -0,0 +1,153 @@
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/**
+ *  @file       usbdevice.h
+ *
+ *  @brief      Types and definitions used during USB enumeration.
+ * 
+ */
+
+#ifndef __USBDEVICE_H__
+#define __USBDEVICE_H__
+
+/******************************************************************************
+ *
+ * If building with a C++ compiler, make all of the definitions in this header
+ * have a C binding.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** ***************************************************************************
+ *
+ * \ingroup device_api
+ * @{
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ *  @brief  The maximum number of independent interfaces that any single device
+ *          implementation can support.  Independent interfaces means interface
+ *          descriptors with different bInterfaceNumber values - several 
+ *          interface descriptors offering different alternative settings but 
+ *          the same interface number count as a single interface.
+ *
+ *****************************************************************************/
+/*#define USB_MAX_INTERFACES_PER_DEVICE 8u*/
+
+/** ***************************************************************************
+ *
+ * Close the Doxygen group.
+ * @}
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ *  @brief  The default USB endpoint FIFO configuration structure.  This 
+ *          structure contains definitions to set all USB FIFOs into single 
+ *          buffered mode with no DMA use.  Each endpoint's FIFO is sized to 
+ *          hold the largest maximum packet size for any interface alternate 
+ *          setting in the current config descriptor.  A pointer to this 
+ *          structure may be passed in the psFIFOConfig field of the 
+ *          tDeviceInfo structure passed to USBCDCInit if the application does 
+ *          not require any special handling of the USB controller FIFO.
+ *
+ *****************************************************************************/
+extern const tFIFOConfig g_sUSBDefaultFIFOConfig;
+
+/** ***************************************************************************
+ *
+ * Public APIs offered by the USB library device control driver.
+ *
+ *****************************************************************************/
+extern void USBDCDInit(uint32 ulIndex, tDeviceInfo *psDevice);
+extern void USBDCDTerm(uint32 ulIndex);
+extern void USBDCDStallEP0(uint32 ulIndex);
+extern void USBDCDRequestDataEP0(uint32 ulIndex, uint8 *pucData,
+                                 uint32 ulSize);
+extern void USBDCDSendDataEP0(uint32 ulIndex, uint8 *pucData,
+                              uint32 ulSize);
+extern void USBDCDSetDefaultConfiguration(uint32 ulIndex,
+                                          uint32 ulDefaultConfig);
+extern uint32 USBDCDConfigDescGetSize(const tConfigHeader *psConfig);
+extern uint32 USBDCDConfigDescGetNum(const tConfigHeader *psConfig,
+                                            uint32 ulType);
+extern tDescriptorHeader *USBDCDConfigDescGet(const tConfigHeader *psConfig,
+                                              uint32 ulType,
+                                              uint32 ulIndex,
+                                              uint32 *pulSection);
+extern uint32
+       USBDCDConfigGetNumAlternateInterfaces(const tConfigHeader *psConfig,
+                                             uint8 ucInterfaceNumber);
+extern tInterfaceDescriptor *
+       USBDCDConfigGetInterface(const tConfigHeader *psConfig,
+                                uint32 ulIndex, uint32 ulAltCfg,
+                                uint32 *pulSection);
+extern tEndpointDescriptor *
+       USBDCDConfigGetInterfaceEndpoint(const tConfigHeader *psConfig,
+                                        uint32 ulInterfaceNumber,
+                                        uint32 ulAltCfg,
+                                        uint32 ulIndex);
+extern void USBDCDPowerStatusSet(uint32 ulIndex, uint8 ucPower);
+extern tBoolean USBDCDRemoteWakeupRequest(uint32 ulIndex);
+
+/** ***************************************************************************
+ *
+ * Early releases of the USB library had the following function named
+ * incorrectly.  This macro ensures that any code which used the previous name
+ * will still operate as expected.
+ *
+ *****************************************************************************/
+#ifndef DEPRECATED
+#define USBCDCConfigGetInterfaceEndpoint(a, b, c, d)                          \
+            USBDCDConfigGetInterfaceEndpoint((a), (b), (c), (d))
+#endif
+
+/** ***************************************************************************
+ *
+ * Mark the end of the C bindings section for C++ compilers.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBENUM_H__ */
diff --git a/include/arch/rm46l8lp/halcogen/usbdevicepriv.h b/include/arch/rm46l8lp/halcogen/usbdevicepriv.h
new file mode 100644
index 0000000..2617b76
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/usbdevicepriv.h
@@ -0,0 +1,90 @@
+/******************************************************************************
+ *  FILE DESCRIPTION
+ *  ---------------------------------------------------------------------------
+ *         File:  usbdevicepriv.h
+ *    Component:  
+ *       Module:  usb
+ *    Generator:  -
+ *
+ *  Description:  Private header file used to share internal variables and
+ *                function prototypes between the various device-related
+ *                modules in the USB library.  This header MUST NOT be
+ *                used by application code.
+ * 
+ *****************************************************************************/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __USBDEVICEPRIV_H__
+#define __USBDEVICEPRIV_H__
+
+/******************************************************************************
+ *
+ * If building with a C++ compiler, make all of the definitions in this header
+ * have a C binding.
+ *
+ *****************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/******************************************************************************
+ *
+ * Device enumeration functions provided by device/usbenum.c and called from
+ * the interrupt handler in device/usbhandler.c
+ *
+ *****************************************************************************/
+extern tBoolean USBDeviceConfig(uint32 ulIndex,
+                                const tConfigHeader *psConfig,
+                                const tFIFOConfig *psFIFOConfig);
+extern tBoolean USBDeviceConfigAlternate(uint32 ulIndex,
+                                         const tConfigHeader *psConfig,
+                                         uint8 ucInterfaceNum,
+                                         uint8 ucAlternateSetting);
+extern void USBDeviceResumeTickHandler(uint32 ulIndex);
+
+/******************************************************************************
+ *
+ * Mark the end of the C bindings section for C++ compilers.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBDEVICEPRIV_H__ */
diff --git a/include/arch/rm46l8lp/halcogen/usblib.h b/include/arch/rm46l8lp/halcogen/usblib.h
new file mode 100644
index 0000000..88e7fa5
--- /dev/null
+++ b/include/arch/rm46l8lp/halcogen/usblib.h
@@ -0,0 +1,1899 @@
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/**
+ *  @file       usblib.h
+ *
+ *  @brief      Main header file for the USB Library.
+ * 
+ */
+
+#ifndef __USBLIB_H__
+#define __USBLIB_H__
+
+/******************************************************************************
+ *
+ * If building with a C++ compiler, make all of the definitions in this header
+ * have a C binding.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+
+/* standard device requests -- USB_SetupDataPacket::bRequest */
+#define USB_REQUEST_GETSTATUS           (0u)
+#define USB_REQUEST_CLEARFEATURE        (1u)
+#define USB_REQUEST_SETFEATURE          (3u)
+#define USB_REQUEST_SETADDRESS          (5u)
+#define USB_REQUEST_GETDESCRIPTOR       (6u)
+#define USB_REQUEST_SETDESCRIPTOR       (7u)
+#define USB_REQUEST_GETCONFIGURATION    (8u)
+#define USB_REQUEST_SETCONFIGURATION    (9u)
+#define USB_REQUEST_GETINTERFACE        (10u)
+#define USB_REQUEST_SETINTERFACE        (11u)
+#define USB_REQUEST_SYNCHFRAME          (12u)
+
+
+/** ***************************************************************************
+ *
+ * This is the maximum number of endpoints supported by the usblib.
+ *
+ *****************************************************************************/
+#define USBLIB_NUM_EP           16u   /* Number of supported endpoints. */
+
+/******************************************************************************
+ *
+ * The following macro allows compiler-independent syntax to be used to
+ * define packed structures.  A typical structure definition using these
+ * macros will look similar to the following example:
+ *
+ *   #ifdef ewarm
+ *   #pragma pack(1)
+ *   #endif
+ *
+ *   typedef struct _PackedStructName
+ *   {
+ *      uint32 ulFirstField;
+ *      char cCharMember;
+ *      uint16 usShort;
+ *   }
+ *   PACKED tPackedStructName;
+ *
+ *   #ifdef ewarm
+ *   #pragma pack()
+ *   #endif
+ *
+ * The conditional blocks related to ewarm include the #pragma pack() lines
+ * only if the IAR Embedded Workbench compiler is being used.  Unfortunately,
+ * it is not possible to emit a #pragma from within a macro definition so this
+ * must be done explicitly.
+ *
+ *****************************************************************************/
+#if defined(ccs) ||             \
+    defined(codered) ||         \
+    defined(gcc) ||             \
+    defined(rvmdk) ||           \
+    defined(__ARMCC_VERSION) || \
+    defined(sourcerygxx)
+#define PACKED __attribute__ ((packed))
+#elif defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#define PACKED
+#elif (__TMS470__)
+#define PACKED __attribute__ ((packed))
+#else
+#error Unrecognized COMPILER!
+#endif
+
+/******************************************************************************
+ *
+ * Assorted language IDs from the document "USB_LANGIDs.pdf" provided by the
+ * USB Implementers' Forum (Version 1.0).
+ *
+ *****************************************************************************/
+#define USB_LANG_CHINESE_PRC    0x0804u      /**< Chinese (PRC) */
+#define USB_LANG_CHINESE_TAIWAN 0x0404u      /**< Chinese (Taiwan) */
+#define USB_LANG_EN_US          0x0409u      /**< English (United States) */
+#define USB_LANG_EN_UK          0x0809u      /**< English (United Kingdom) */
+#define USB_LANG_EN_AUS         0x0C09u      /**< English (Australia) */
+#define USB_LANG_EN_CA          0x1009u      /**< English (Canada) */
+#define USB_LANG_EN_NZ          0x1409u      /**< English (New Zealand) */
+#define USB_LANG_FRENCH         0x040Cu      /**< French (Standard) */
+#define USB_LANG_GERMAN         0x0407u      /**< German (Standard) */
+#define USB_LANG_HINDI          0x0439u      /**< Hindi */
+#define USB_LANG_ITALIAN        0x0410u      /**< Italian (Standard) */
+#define USB_LANG_JAPANESE       0x0411u      /**< Japanese */
+#define USB_LANG_KOREAN         0x0412u      /**< Korean */
+#define USB_LANG_ES_TRAD        0x040Au      /**< Spanish (Traditional) */
+#define USB_LANG_ES_MODERN      0x0C0Au      /**< Spanish (Modern) */
+#define USB_LANG_SWAHILI        0x0441u      /**< Swahili (Kenya) */
+#define USB_LANG_URDU_IN        0x0820u      /**< Urdu (India) */
+#define USB_LANG_URDU_PK        0x0420u      /**< Urdu (Pakistan) */
+/** ***************************************************************************
+ *
+ *  @ingroup usbchap9_src
+ *  @{
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Note:
+ *
+ * Structure definitions which are derived directly from the USB specification
+ * use field names from the specification.  Since a somewhat different version
+ * of Hungarian prefix notation is used from the Stellaris standard, beware of
+ * making assumptions about field sizes based on the field prefix when using
+ * these structures.  Of particular note is the difference in the meaning of
+ * the 'i' prefix.  In USB structures, this indicates a single byte index
+ * whereas in Stellaris code, this is a 32 bit integer.
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * All structures defined in this section of the header require byte packing of
+ * fields.  This is usually accomplished using the PACKED macro but, for IAR
+ * Embedded Workbench, this requires a pragma.
+ *
+ *****************************************************************************/
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack(1)
+#endif
+
+/******************************************************************************
+ *
+ * Definitions related to standard USB device requests (sections 9.3 & 9.4)
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ *  @brief  The standard USB request header as defined in section 9.3 of the 
+ *          USB 2.0 specification.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  Determines the type and direction of the request.
+     */
+    uint8 bmRequestType;
+
+    /**
+     *  @brief  Identifies the specific request being made.
+     */
+    uint8 bRequest;
+
+    /**
+     *  @brief  Word-sized field that varies according to the request.
+     */
+    uint16 wValue;
+
+    /**
+     *  @brief  Word-sized field that varies according to the request; typically used
+     *          to pass an index or offset.
+     */
+    uint16 wIndex;
+
+    /**
+     *  @brief  The number of bytes to transfer if there is a data stage to the
+     *          request.
+     */
+    uint16 wLength;
+
+}
+PACKED tUSBRequest;
+
+/******************************************************************************
+ *
+ * The following defines are used with the bmRequestType member of tUSBRequest.
+ *
+ * Request types have 3 bit fields:
+ * 4:0 - Is the recipient type.
+ * 6:5 - Is the request type.
+ * 7 - Is the direction of the request.
+ *
+ *****************************************************************************/
+#define USB_RTYPE_DIR_IN        0x80u
+#define USB_RTYPE_DIR_OUT       0x00u
+
+#define USB_RTYPE_TYPE_M        0x60u
+#define USB_RTYPE_VENDOR        0x40u
+#define USB_RTYPE_CLASS         0x20u
+#define USB_RTYPE_STANDARD      0x00u
+
+#define USB_RTYPE_RECIPIENT_M   0x1fu
+#define USB_RTYPE_OTHER         0x03u
+#define USB_RTYPE_ENDPOINT      0x02u
+#define USB_RTYPE_INTERFACE     0x01u
+#define USB_RTYPE_DEVICE        0x00u
+
+/******************************************************************************
+ *
+ * Standard USB requests IDs used in the bRequest field of tUSBRequest.
+ *
+ *****************************************************************************/
+#define USBREQ_GET_STATUS       0x00u
+#define USBREQ_CLEAR_FEATURE    0x01u
+#define USBREQ_SET_FEATURE      0x03u
+#define USBREQ_SET_ADDRESS      0x05u
+#define USBREQ_GET_DESCRIPTOR   0x06u
+#define USBREQ_SET_DESCRIPTOR   0x07u
+#define USBREQ_GET_CONFIG       0x08u
+#define USBREQ_SET_CONFIG       0x09u
+#define USBREQ_GET_INTERFACE    0x0au
+#define USBREQ_SET_INTERFACE    0x0bu
+#define USBREQ_SYNC_FRAME       0x0cu
+
+#define USBREQ_COUNT            (USBREQ_SYNC_FRAME + 1u)
+
+/******************************************************************************
+ *
+ * Data returned from a USBREQ_GET_STATUS request to a device.
+ *
+ *****************************************************************************/
+#define USB_STATUS_SELF_PWR     0x0001u  /**< Currently self powered. */
+#define USB_STATUS_BUS_PWR      0x0000u  /**< Currently bus-powered. */
+#define USB_STATUS_PWR_M        0x0001u  /**< Mask for power mode. */
+#define USB_STATUS_REMOTE_WAKE  0x0002u  /**< Remote wake-up is currently 
+                                             enabled. */
+
+/******************************************************************************
+ *
+ * Feature Selectors (tUSBRequest.wValue) passed on USBREQ_CLEAR_FEATURE and
+ * USBREQ_SET_FEATURE.
+ *
+ *****************************************************************************/
+#define USB_FEATURE_EP_HALT     0x0000u  /**< Endpoint halt feature. */
+#define USB_FEATURE_REMOTE_WAKE 0x0001u  /**< Remote wake feature, device only. */
+#define USB_FEATURE_TEST_MODE   0x0002u  /**< Test mode */
+
+/******************************************************************************
+ *
+ * Endpoint Selectors (tUSBRequest.wIndex) passed on USBREQ_CLEAR_FEATURE,
+ * USBREQ_SET_FEATURE and USBREQ_GET_STATUS.
+ *
+ *****************************************************************************/
+#define USB_REQ_EP_NUM_M   0x007Fu
+#define USB_REQ_EP_DIR_M   0x0080u
+#define USB_REQ_EP_DIR_IN  0x0080u
+#define USB_REQ_EP_DIR_OUT 0x0000u
+
+/******************************************************************************
+ *
+ * Standard USB descriptor types.  These values are passed in the upper bytes
+ * of tUSBRequest.wValue on USBREQ_GET_DESCRIPTOR and also appear in the
+ * bDescriptorType field of standard USB descriptors.
+ *
+ *****************************************************************************/
+#define USB_DTYPE_DEVICE        1u
+#define USB_DTYPE_CONFIGURATION 2u
+#define USB_DTYPE_STRING        3u
+#define USB_DTYPE_INTERFACE     4u
+#define USB_DTYPE_ENDPOINT      5u
+#define USB_DTYPE_DEVICE_QUAL   6u
+#define USB_DTYPE_OSPEED_CONF   7u
+#define USB_DTYPE_INTERFACE_PWR 8u
+#define USB_DTYPE_OTG           9u
+#define USB_DTYPE_INTERFACE_ASC 11u
+#define USB_DTYPE_CS_INTERFACE  36u
+
+/******************************************************************************
+ *
+ * Definitions related to USB descriptors (sections 9.5 & 9.6)
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ *  @brief      This structure describes a generic descriptor header.  These 
+ *              fields are to be found at the beginning of all valid USB 
+ *              descriptors.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The length of this descriptor (including this length byte) expressed
+     *          in bytes.
+     */
+    uint8 bLength;
+
+    /**
+     *  @brief  The type identifier of the descriptor whose information follows.
+     *          For standard descriptors, this field could contain, for example,
+     *          USB_DTYPE_DEVICE to identify a device descriptor or
+	 *          USB_DTYPE_ENDPOINT to identify an endpoint descriptor.
+     */
+    uint8 bDescriptorType;
+}
+PACKED tDescriptorHeader;
+
+/** ***************************************************************************
+ *
+ *  @brief This structure describes the USB device descriptor as defined in USB
+ *         2.0 specification section 9.6.1.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The length of this descriptor in bytes.  All device descriptors
+	 *          are 18 bytes long.
+     */
+    uint8 bLength;
+
+    /**
+     *  @brief  The type of the descriptor.  For a device descriptor, this will
+     *          be USB_DTYPE_DEVICE (1).
+     */
+    uint8 bDescriptorType;
+
+    /**
+     *  @brief  The USB Specification Release Number in BCD format.  
+	 *          For USB 2.0, this will be 0x0200.
+     */
+    uint16 bcdUSB;
+
+    /**
+     *  @brief  The device class code.
+     */
+    uint8 bDeviceClass;
+
+    /**
+     *  @brief  The device subclass code.  This value qualifies the value 
+	 *          found in the bDeviceClass field.
+     */
+    uint8 bDeviceSubClass;
+
+    /**
+     *  @brief  The device protocol code.  This value is qualified by the 
+	 *          values of bDeviceClass and bDeviceSubClass.
+     */
+    uint8 bDeviceProtocol;
+
+    /**
+     *  @brief  The maximum packet size for endpoint zero.  Valid values 
+	 *          are 8, 16, 32 and 64.
+     */
+    uint8 bMaxPacketSize0;
+
+    /**
+     *  @brief  The device Vendor ID (VID) as assigned by the USB-IF.
+     */
+    uint16 idVendor;
+
+    /**
+     *  @brief  The device Product ID (PID) as assigned by the manufacturer.
+     */
+    uint16 idProduct;
+
+    /**
+     *  @brief  The device release number in BCD format.
+     */
+    uint16 bcdDevice;
+
+    /**
+     *  @brief  The index of a string descriptor describing the manufacturer.
+     */
+    uint8 iManufacturer;
+
+    /**
+     *  @brief  The index of a string descriptor describing the product.
+     */
+    uint8 iProduct;
+
+    /**
+     *  @brief  The index of a string descriptor describing the device's serial
+     *          number.
+     */
+    uint8 iSerialNumber;
+
+    /**
+     *  @brief  The number of possible configurations offered by the device.
+	 *          This field indicates the number of distinct configuration 
+	 *          descriptors that the device offers.
+     */
+    uint8 bNumConfigurations;
+}
+PACKED tDeviceDescriptor;
+
+/******************************************************************************
+ *
+ * USB Device Class codes used in the tDeviceDescriptor.bDeviceClass field.
+ * Definitions for the bDeviceSubClass and bDeviceProtocol fields are device
+ * specific and can be found in the appropriate device class header files.
+ *
+ *****************************************************************************/
+#define USB_CLASS_DEVICE        0x00u
+#define USB_CLASS_AUDIO         0x01u
+#define USB_CLASS_CDC           0x02u
+#define USB_CLASS_HID           0x03u
+#define USB_CLASS_PHYSICAL      0x05u
+#define USB_CLASS_IMAGE         0x06u
+#define USB_CLASS_PRINTER       0x07u
+#define USB_CLASS_MASS_STORAGE  0x08u
+#define USB_CLASS_HUB           0x09u
+#define USB_CLASS_CDC_DATA      0x0au
+#define USB_CLASS_SMART_CARD    0x0bu
+#define USB_CLASS_SECURITY      0x0du
+#define USB_CLASS_VIDEO         0x0eu
+#define USB_CLASS_HEALTHCARE    0x0fu
+#define USB_CLASS_DIAG_DEVICE   0xdcu
+#define USB_CLASS_WIRELESS      0xe0u
+#define USB_CLASS_MISC          0xefu
+#define USB_CLASS_APP_SPECIFIC  0xfeu
+#define USB_CLASS_VEND_SPECIFIC 0xffu
+#define USB_CLASS_EVENTS        0xffffffffU
+
+/******************************************************************************
+ *
+ * Generic values for undefined subclass and protocol.
+ *
+ *****************************************************************************/
+#define USB_SUBCLASS_UNDEFINED  0x00u
+#define USB_PROTOCOL_UNDEFINED  0x00u
+
+/******************************************************************************
+ *
+ * The following are the miscellaneous subclass values.
+ *
+ *****************************************************************************/
+#define USB_MISC_SUBCLASS_SYNC      0x01u
+#define USB_MISC_SUBCLASS_COMMON    0x02u
+
+/******************************************************************************
+ *
+ * These following are miscellaneous protocol values.
+ *
+ *****************************************************************************/
+#define USB_MISC_PROTOCOL_IAD   0x01u
+
+/** ***************************************************************************
+ *
+ *  @brief  This structure describes the USB device qualifier descriptor as 
+ *          defined in the USB 2.0 specification, section 9.6.2.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The length of this descriptor in bytes.  All device qualifier
+     *          descriptors are 10 bytes long.
+     */
+    uint8 bLength;
+
+    /**
+     *  @brief  The type of the descriptor.  For a device descriptor, this will
+     *          be USB_DTYPE_DEVICE_QUAL (6).
+     */
+    uint8 bDescriptorType;
+
+    /**
+     *  @brief  The USB Specification Release Number in BCD format.  
+	 *          For USB 2.0, this will be 0x0200.
+     */
+    uint16 bcdUSB;
+
+    /**
+     *  @brief  The device class code.
+     */
+    uint8 bDeviceClass;
+
+    /**
+     *  @brief  The device subclass code.  This value qualifies the value 
+	 *          found in the bDeviceClass field.
+     */
+    uint8 bDeviceSubClass;
+
+    /**
+     *  @brief  The device protocol code.  This value is qualified by the 
+	 *          values of bDeviceClass and bDeviceSubClass.
+     */
+    uint8 bDeviceProtocol;
+
+    /**
+     *  @brief  The maximum packet size for endpoint zero when operating at
+     *          a speed other than high speed.
+     */
+    uint8 bMaxPacketSize0;
+
+    /**
+     *  @brief  The number of other-speed configurations supported.
+     */
+    uint8 bNumConfigurations;
+
+    /**
+     *  @brief  Reserved for future use.  Must be set to zero.
+     */
+    uint8 bReserved;
+}
+PACKED tDeviceQualifierDescriptor;
+
+/** ***************************************************************************
+ *
+ *  This structure describes the USB configuration descriptor as defined in
+ *  USB 2.0 specification section 9.6.3.  This structure also applies to the
+ *  USB other speed configuration descriptor defined in section 9.6.4.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The length of this descriptor in bytes.  All configuration 
+	 *          descriptors are 9 bytes long.
+     */
+    uint8 bLength;
+
+    /**
+     *  @brief  The type of the descriptor.  For a configuration descriptor, 
+	 *          this will be USB_DTYPE_CONFIGURATION (2).
+     */
+    uint8 bDescriptorType;
+
+    /**
+     *  @brief  The total length of data returned for this configuration.  
+	 *          This includes the combined length of all descriptors 
+	 *          (configuration, interface, endpoint and class- or 
+	 *           vendor-specific) returned for this configuration.
+     */
+    uint16 wTotalLength;
+
+    /**
+     *  @brief  The number of interface supported by this configuration.
+     */
+    uint8 bNumInterfaces;
+
+    /**
+     *  @brief  The value used as an argument to the SetConfiguration standard
+     *          request to select this configuration.
+     */
+    uint8 bConfigurationValue;
+
+    /**
+     *  @brief  The index of a string descriptor describing this configuration.
+     */
+    uint8 iConfiguration;
+
+    /**
+     *  @brief  Attributes of this configuration.
+     */
+    uint8 bmAttributes;
+
+    /**
+     *  @brief  The maximum power consumption of the USB device from the bus 
+	 *          in this configuration when the device is fully operational.  
+	 *          This is expressed in units of 2mA so, for example, 
+	 *          100 represents 200mA.
+     */
+    uint8 bMaxPower;
+}
+PACKED tConfigDescriptor;
+
+/******************************************************************************
+ *
+ * Flags used in constructing the value assigned to the field
+ * tConfigDescriptor.bmAttributes.  Note that bit 7 is reserved and must be set
+ * to 1.
+ *
+ *****************************************************************************/
+#define USB_CONF_ATTR_PWR_M     0xC0u
+
+#define USB_CONF_ATTR_SELF_PWR  0xC0u
+#define USB_CONF_ATTR_BUS_PWR   0x80u
+#define USB_CONF_ATTR_RWAKE     0xA0u
+
+/** ***************************************************************************
+ *
+ *  This structure describes the USB interface descriptor as defined in USB
+ *  2.0 specification section 9.6.5.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The length of this descriptor in bytes.  All interface 
+	 *          descriptors are 9 bytes long.
+     */
+    uint8 bLength;
+
+    /**
+     *  @brief  The type of the descriptor.  For an interface descriptor, this
+	 *          will be USB_DTYPE_INTERFACE (4).
+     */
+    uint8 bDescriptorType;
+
+    /**
+     *  @brief  The number of this interface.  This is a zero based index into
+	 *          the array of concurrent interfaces supported by this 
+	 *          configuration.
+     */
+    uint8 bInterfaceNumber;
+
+    /**
+     *  @brief  The value used to select this alternate setting for the 
+	 *          interface defined in bInterfaceNumber.
+     */
+    uint8 bAlternateSetting;
+
+    /**
+     *  @brief  The number of endpoints used by this interface (excluding 
+	 *          endpoint zero).
+     */
+    uint8 bNumEndpoints;
+
+    /**
+     *  @brief  The interface class code as assigned by the USB-IF.
+     */
+    uint8 bInterfaceClass;
+
+    /**
+     *  @brief  The interface subclass code as assigned by the USB-IF.
+     */
+    uint8 bInterfaceSubClass;
+
+    /**
+     *  @brief  The interface protocol code as assigned by the USB-IF.
+     */
+    uint8 bInterfaceProtocol;
+
+    /**
+     *  @brief  The index of a string descriptor describing this interface.
+     */
+    uint8 iInterface;
+}
+PACKED tInterfaceDescriptor;
+
+/** ***************************************************************************
+ *
+ *  This structure describes the USB endpoint descriptor as defined in USB
+ *  2.0 specification section 9.6.6.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The length of this descriptor in bytes.  All endpoint 
+	 *          descriptors are 7 bytes long.
+     */
+    uint8 bLength;
+
+    /**
+     *  @brief  The type of the descriptor.  For an endpoint descriptor, this 
+	 *          will be USB_DTYPE_ENDPOINT (5).
+     */
+    uint8 bDescriptorType;
+
+    /**
+     *  @brief  The address of the endpoint.  This field contains the endpoint
+	 *          number ORed with flag USB_EP_DESC_OUT or USB_EP_DESC_IN to 
+	 *          indicate the endpoint direction.
+     */
+    uint8 bEndpointAddress;
+
+    /**
+     *  @brief  The endpoint transfer type, USB_EP_ATTR_CONTROL, 
+	 *          USB_EP_ATTR_ISOC, USB_EP_ATTR_BULK or USB_EP_ATTR_INT and, 
+	 *          if isochronous, additional flags indicating usage type and 
+	 *          synchronization method.
+     */
+    uint8 bmAttributes;
+
+    /**
+     *  @brief  The maximum packet size this endpoint is capable of sending or
+     *          receiving when this configuration is selected.  For high speed
+     *          isochronous or interrupt endpoints, bits 11 and 12 are used to
+     *          pass additional information.
+     */
+    uint16 wMaxPacketSize;
+
+    /**
+     *  @brief  The polling interval for data transfers expressed in frames or
+     *          micro frames depending upon the operating speed.
+     */
+    uint8 bInterval;
+}
+PACKED tEndpointDescriptor;
+
+/******************************************************************************
+ *
+ * Flags used in constructing the value assigned to the field
+ * tEndpointDescriptor.bEndpointAddress.
+ *
+ *****************************************************************************/
+#define USB_EP_DESC_OUT                 0x00u
+#define USB_EP_DESC_IN                  0x80u
+#define USB_EP_DESC_NUM_M               0x0fu
+
+/******************************************************************************
+ *
+ * Mask used to extract the maximum packet size (in bytes) from the
+ * wMaxPacketSize field of the endpoint descriptor.
+ *
+ *****************************************************************************/
+#define USB_EP_MAX_PACKET_COUNT_M       0x07FFu
+
+/******************************************************************************
+ *
+ * Endpoint attributes used in tEndpointDescriptor.bmAttributes.
+ *
+ *****************************************************************************/
+#define USB_EP_ATTR_CONTROL             0x00u
+#define USB_EP_ATTR_ISOC                0x01u
+#define USB_EP_ATTR_BULK                0x02u
+#define USB_EP_ATTR_INT                 0x03u
+#define USB_EP_ATTR_TYPE_M              0x03u
+
+#define USB_EP_ATTR_ISOC_M              0x0cu
+#define USB_EP_ATTR_ISOC_NOSYNC         0x00u
+#define USB_EP_ATTR_ISOC_ASYNC          0x04u
+#define USB_EP_ATTR_ISOC_ADAPT          0x08u
+#define USB_EP_ATTR_ISOC_SYNC           0x0cu
+#define USB_EP_ATTR_USAGE_M             0x30u
+#define USB_EP_ATTR_USAGE_DATA          0x00u
+#define USB_EP_ATTR_USAGE_FEEDBACK      0x10u
+#define USB_EP_ATTR_USAGE_IMPFEEDBACK   0x20u
+
+/** ***************************************************************************
+ *
+ *  @brief  This structure describes the USB string descriptor for index 0 as 
+ *          defined in USB 2.0 specification section 9.6.7.  Note that the 
+ *          number of language IDs is variable and can be determined by 
+ *          examining bLength.  The number of language IDs present in the 
+ *          descriptor is given by ((bLength - 2) / 2).
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The length of this descriptor in bytes.  This value will vary
+     *          depending upon the number of language codes provided in the 
+	 *          descriptor.
+     */
+    uint8 bLength;
+
+    /**
+     *  @brief  The type of the descriptor.  For a string descriptor, this will
+     *          be USB_DTYPE_STRING (3).
+     */
+    uint8 bDescriptorType;
+
+    /**
+     *  @brief  The language code (LANGID) for the first supported language.  
+	 *          Note that this descriptor may support multiple languages, in 
+	 *          which case, the number of elements in the wLANGID array will 
+	 *          increase and bLength will be updated accordingly.
+     */
+    uint16 wLANGID[1];
+}
+PACKED tString0Descriptor;
+
+/** ***************************************************************************
+ *
+ *  @brief  This structure describes the USB string descriptor for all string 
+ *          indexes other than 0 as defined in USB 2.0 specification 
+ *          section 9.6.7.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The length of this descriptor in bytes.  This value will be 
+	 *          2 greater than the number of bytes comprising the UNICODE 
+	 *          string that the descriptor contains.
+     */
+    uint8 bLength;
+
+    /**
+     *  @brief  The type of the descriptor.  For a string descriptor, this will
+     *          be USB_DTYPE_STRING (3).
+     */
+    uint8 bDescriptorType;
+
+    /**
+     *  @brief  The first byte of the UNICODE string.  This string is not NULL
+     *          terminated.  Its length (in bytes) can be computed by 
+	 *          subtracting 2 from the value in the bLength field.
+     */
+    uint8 bString;
+}
+PACKED tStringDescriptor;
+
+/** ***************************************************************************
+ *
+ *  Write a 2 byte uint16 value to a USB descriptor block.
+ *
+ *  @param usValue is the two byte uint16 that is to be written to
+ *  the descriptor.
+ * 
+ *  This helper macro is used in descriptor definitions to write two-byte
+ *  values.  Since the configuration descriptor contains all interface and
+ *  endpoint descriptors in a contiguous block of memory, these descriptors are
+ *  typically defined using an array of bytes rather than as packed structures.
+ * 
+ *  @return Not a function.
+ *
+ *****************************************************************************/
+#define USBShort(usValue)       (uint8_t)((uint16_t)(usValue) & (uint16_t)0x00ffU), (uint8_t)((uint16_t)(usValue) >> 8U)
+
+/** ***************************************************************************
+ *
+ *  Write a 3 byte uint32 value to a USB descriptor block.
+ * 
+ *  @param ulValue is the three byte unsigned value that is to be written to the
+ *  descriptor.
+ * 
+ *  This helper macro is used in descriptor definitions to write three-byte
+ *  values.  Since the configuration descriptor contains all interface and
+ *  endpoint descriptors in a contiguous block of memory, these descriptors are
+ *  typically defined using an array of bytes rather than as packed structures.
+ * 
+ *  @return Not a function.
+ *
+ *****************************************************************************/
+#define USB3Byte(ulValue)       (ulValue & 0xff),              \
+                                ((ulValue >> 8) & 0xff),       \
+                                ((ulValue >> 16) & 0xff)
+
+/** ***************************************************************************
+ *
+ *  Write a 4 byte uint32 value to a USB descriptor block.
+ * 
+ *  @param ulValue is the four byte uint32 that is to be written to the
+ *  descriptor.
+ * 
+ *  This helper macro is used in descriptor definitions to write four-byte
+ *  values.  Since the configuration descriptor contains all interface and
+ *  endpoint descriptors in a contiguous block of memory, these descriptors are
+ *  typically defined using an array of bytes rather than as packed structures.
+ * 
+ *  @return Not a function.
+ *
+ *****************************************************************************/
+#define USBLong(ulValue)        (ulValue & 0xff),              \
+                                ((ulValue >> 8) & 0xff),       \
+                                ((ulValue >> 16) & 0xff),      \
+                                ((ulValue >> 24) & 0xff)
+
+/** ***************************************************************************
+ *
+ *  Traverse to the next USB descriptor in a block.
+ * 
+ *  @param ptr points to the first byte of a descriptor in a block of
+ *  USB descriptors.
+ * 
+ *  This macro aids in traversing lists of descriptors by returning a pointer
+ *  to the next descriptor in the list given a pointer to the current one.
+ * 
+ *  @return Returns a pointer to the next descriptor in the block following
+ *  @e ptr.
+ * 
+ *****************************************************************************/
+#define NEXT_USB_DESCRIPTOR(ptr)                         \
+        (tDescriptorHeader *)(((uint8 *)(ptr)) + \
+                              (ptr)->bLength)
+
+/******************************************************************************
+ *
+ * Return to default packing when using the IAR Embedded Workbench compiler.
+ *
+ *****************************************************************************/
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack()
+#endif
+
+/** ***************************************************************************
+ *
+ *  Close the usbchap9_src Doxygen group.
+ *  @}
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ *  @ingroup device_api
+ *  @{
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ *  @brief  Function prototype for any standard USB request.
+ *
+ *****************************************************************************/
+typedef void (* tStdRequest)(void * pvInstance, tUSBRequest * pUSBRequest);
+
+/** ***************************************************************************
+ *
+ *  @brief  Data callback for receiving data from an endpoint.
+ *
+ *****************************************************************************/
+typedef void (* tInfoCallback)(void * pvInstance, uint32 ulInfo);
+
+/** ***************************************************************************
+ *
+ *  @brief  Callback made to indicate that an interface alternate setting 
+ *          change has occurred.
+ *
+ *****************************************************************************/
+typedef void (* tInterfaceCallback)(void * pvInstance,
+                                    uint8  ucInterfaceNum,
+                                    uint8  ucAlternateSetting);
+
+/** ***************************************************************************
+ *
+ *  @brief  Generic interrupt handler callbacks.
+ *
+ *****************************************************************************/
+typedef void (* tUSBIntHandler)(void * pvInstance);
+
+/** ***************************************************************************
+ *
+ *  @brief  Interrupt handler callbacks that have status information.
+ *
+ *****************************************************************************/
+typedef void (* tUSBEPIntHandler)(void * pvInstance,
+                                  uint32 ulStatus);
+
+/** ***************************************************************************
+ *
+ *  @brief  Generic handler callbacks that are used when the callers needs to 
+ *          call into an instance of class.
+ *
+ *****************************************************************************/
+typedef void (* tUSBDeviceHandler)(void * pvInstance,
+                                   uint32 ulRequest,
+                                   void * pvRequestData);
+
+/** ***************************************************************************
+ *
+ *  @brief  USB event handler functions used during enumeration and operation 
+ *          of the device stack.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  This callback is made whenever the USB host requests a 
+	 *          non-standard descriptor from the device.
+     */
+    tStdRequest pfnGetDescriptor;
+
+    /**
+     *  @brief  This callback is made whenever the USB host makes a 
+	 *          non-standard request.
+     */
+    tStdRequest pfnRequestHandler;
+
+    /**
+     *  @brief  This callback is made in response to a SetInterface request 
+	 *          from the host.
+     */
+    tInterfaceCallback pfnInterfaceChange;
+
+    /**
+     *  @brief  This callback is made in response to a SetConfiguration 
+	 *          request from the host.
+     */
+    tInfoCallback pfnConfigChange;
+
+    /**
+     *  @brief  This callback is made when data has been received following 
+	 *          to a call to USBDCDRequestDataEP0.
+     */
+    tInfoCallback pfnDataReceived;
+
+    /**
+     *  @brief  This callback is made when data has been transmitted following
+	 *          a call to USBDCDSendDataEP0.
+     */
+    tInfoCallback pfnDataSent;
+
+    /**
+     *  @brief  This callback is made when a USB reset is detected.
+     */
+    tUSBIntHandler pfnResetHandler;
+
+    /**
+     *  @brief  This callback is made when the bus has been inactive long 
+	 *          enough to trigger a suspend condition.
+     */
+    tUSBIntHandler pfnSuspendHandler;
+
+    /**
+     *  @brief  This is called when resume signaling is detected.
+     */
+    tUSBIntHandler pfnResumeHandler;
+
+    /**
+     *  @brief  This callback is made when the device is disconnected from 
+	 *          the USB bus.
+     */
+    tUSBIntHandler pfnDisconnectHandler;
+
+    /**
+     *  @brief  This callback is made to inform the device of activity on 
+	 *          all endpoints other than endpoint zero.
+     */
+    tUSBEPIntHandler pfnEndpointHandler;
+
+    /**
+     *  @brief  This generic handler is provided to allow requests based on
+	 *          a given instance to be passed into a device.  This is commonly
+     *          used by a top level composite device that is using multiple 
+	 *          instances of a class.
+     */
+    tUSBDeviceHandler pfnDeviceHandler;
+}
+tCustomHandlers;
+
+/** ***************************************************************************
+ *
+ *  @brief  This structure defines how a given endpoint's FIFO is configured in
+ *          relation to the maximum packet size for the endpoint as specified 
+ *          in the endpoint descriptor.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The multiplier to apply to an endpoint's maximum packet size 
+	 *          when configuring the FIFO for that endpoint.  For example, 
+	 *          setting this value to 2 will result in a 128 byte FIFO being 
+	 *          configured if bDoubleBuffer is FALSE and the associated 
+	 *          endpoint is set to use a 64 byte maximum packet size.
+     */
+    uint8 cMultiplier;
+
+    /**
+     *  @brief  This field indicates whether to configure an endpoint's FIFO 
+	 *          to be double- or single-buffered.  If TRUE, a double-buffered 
+	 *          FIFO is created and the amount of required FIFO storage is 
+	 *          multiplied by two.
+     */
+    tBoolean bDoubleBuffer;
+
+    /**
+     *  @brief  This field defines endpoint mode flags which cannot be deduced
+     *          from the configuration descriptor, namely any in the set 
+	 *          USB_EP_AUTO_xxx or USB_EP_DMA_MODE_x.  USBDCDConfig adds these 
+	 *          flags to the endpoint mode and direction determined from the 
+	 *          config descriptor before it configures the endpoint using a 
+	 *          call to USBDevEndpointConfigSet().
+     */
+    uint16 usEPFlags;
+}
+tFIFOEntry;
+
+/** ***************************************************************************
+ *
+ *  @brief  This structure defines endpoint and FIFO configuration information 
+ *          for all endpoints that the device wishes to use.  This information 
+ *          cannot be determined by examining the USB configuration descriptor 
+ *          and is provided to USBDCDConfig by the application to allow the USB
+ *          controller endpoints to be correctly configured.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  An array containing one FIFO entry for each of the IN
+     *          endpoints. Note that endpoint 0 is configured and managed by 
+	 *          the USB device stack so is excluded from this array.  The 
+	 *          index 0 entry of the array corresponds to endpoint 1, 
+	 *          index 1 to endpoint 2, etc.
+     */
+    tFIFOEntry sIn[USBLIB_NUM_EP - 1];
+
+    /**
+     *  @brief  An array containing one FIFO entry for each of the OUT 
+	 *          endpoints. Note that endpoint 0 is configured and managed by 
+	 *          the USB device stack so is excluded from this array.  
+	 *          The index 0 entry of the array corresponds to endpoint 1, 
+	 *          index 1 to endpoint 2, etc.
+     */
+    tFIFOEntry sOut[USBLIB_NUM_EP - 1];
+}
+tFIFOConfig;
+
+/** ***************************************************************************
+ *
+ *  @brief  This structure defines a contiguous block of data which contains a
+ *          group of descriptors that form part of a configuration descriptor 
+ *          for a device. It is assumed that a config section contains only 
+ *          whole descriptors.  It is not valid to split a single descriptor 
+ *          across multiple sections.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The number of bytes of descriptor data pointed to by pucData.
+     */
+    uint8 ucSize;
+
+    /**
+     *  @brief  A pointer to a block of data containing an integral number of
+     *          SB descriptors which form part of a larger configuration
+	 *          descriptor.
+     */
+    const uint8 * pucData;
+}
+tConfigSection;
+
+/** ***************************************************************************
+ *
+ *  @brief  This is the top level structure defining a USB device configuration
+ *          descriptor.  A configuration descriptor contains a collection of 
+ *          device-specific descriptors in addition to the basic config, 
+ *          interface and endpoint descriptors.  To allow flexibility in 
+ *          constructing the configuration, the descriptor is described in 
+ *          terms of a list of data blocks.  The first block must contain the 
+ *          configuration descriptor itself and the following blocks are 
+ *          appended to this in order to produce the full descriptor sent to 
+ *          the host in response to a GetDescriptor request for the 
+ *          configuration descriptor.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The number of sections comprising the full descriptor for this
+     *          configuration.
+     */
+    uint8 ucNumSections;
+
+    /**
+     *  @brief  A pointer to an array of ucNumSections section pointers which 
+	 *          must be concatenated to form the configuration descriptor.
+     */
+    const tConfigSection * const * psSections;
+}
+tConfigHeader;
+
+/** ***************************************************************************
+ *
+ *  @brief  This structure is passed to the USB library on a call to USBDCDInit
+ *          and provides the library with information about the device that the
+ *          application is implementing.  It contains functions pointers for
+ *          the various USB event handlers and pointers to each of the standard
+ *          device descriptors.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  A pointer to a structure containing pointers to event handler 
+	 *          functions provided by the client to support the operation of 
+	 *          this device.
+     */
+    tCustomHandlers sCallbacks;
+
+    /**
+     *  @brief  A pointer to the device descriptor for this device.
+     */
+    const uint8 * pDeviceDescriptor;
+
+    /**
+     *  @brief  A pointer to an array of configuration descriptor pointers. 
+	 *          Each entry in the array corresponds to one configuration that 
+	 *          the device may be set to use by the USB host.  The number of 
+	 *          entries in the array must match the bNumConfigurations value 
+	 *          in the device descriptor array, pDeviceDescriptor.
+     */
+    const tConfigHeader * const * ppConfigDescriptors;
+
+    /**
+     *  @brief  A pointer to the string descriptor array for this device.  
+	 *          This array must be arranged as follows:
+     *
+     *    - [0]   - Standard descriptor containing supported language codes.
+     *    - [1]   - String 1 for the first language listed in descriptor 0.
+     *    - [2]   - String 2 for the first language listed in descriptor 0.
+     *    - ...
+     *    - [n]   - String n for the first language listed in descriptor 0.
+     *    - [n+1] - String 1 for the second language listed in descriptor 0.
+     *    - ...
+     *    - [2n]  - String n for the second language listed in descriptor 0.
+     *    - [2n+1]- String 1 for the third language listed in descriptor 0.
+     *    - ...
+     *    - [3n]  - String n for the third language listed in descriptor 0.
+     * 
+     *  and so on.
+     */
+    const uint8 * const * ppStringDescriptors;
+
+    /**
+     *  @brief  The total number of descriptors provided in the ppStringDescriptors
+     *          array.
+     */
+    uint32 ulNumStringDescriptors;
+
+    /**
+     *  @brief  A structure defining how the USB controller FIFO is to be 
+	 *          partitioned between the various endpoints.  This member can be
+     *          set to point to g_sUSBDefaultFIFOConfig if the default FIFO 
+	 *          configuration is acceptable. This configuration sets each 
+	 *          endpoint FIFO to be single buffered and sized to hold the 
+	 *          maximum packet size for the endpoint.
+     */
+    const tFIFOConfig * psFIFOConfig;
+
+    /**
+     *  @brief  This value will be passed back to all call back functions so 
+	 *          that they have access to individual instance data based on the 
+	 *          this pointer.
+     */
+    void * pvInstance;
+}
+tDeviceInfo;
+
+/** ***************************************************************************
+ *
+ * Close the Doxygen group.
+ * @}
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @ingroup general_usblib_api
+ * @{
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * USB descriptor parsing functions found in usbdesc.c
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ *  @brief  The USB_DESC_ANY label is used as a wild card in several of the 
+ *          descriptor parsing APIs to determine whether or not particular 
+ *          search criteria should be ignored.
+ *
+ *****************************************************************************/
+#define USB_DESC_ANY 0xFFFFFFFFu
+
+extern uint32 USBDescGetNum(tDescriptorHeader * psDesc,
+                                   uint32 ulSize, uint32 ulType);
+extern tDescriptorHeader * USBDescGet(tDescriptorHeader * psDesc,
+                                     uint32 ulSize,
+                                     uint32 ulType,
+                                     uint32 ulIndex);
+extern uint32
+       USBDescGetNumAlternateInterfaces(tConfigDescriptor * psConfig,
+                                        uint8 ucInterfaceNumber);
+extern tInterfaceDescriptor * USBDescGetInterface(tConfigDescriptor * psConfig,
+                                                 uint32 ulIndex,
+                                                 uint32 ulAltCfg);
+extern tEndpointDescriptor *
+       USBDescGetInterfaceEndpoint(tInterfaceDescriptor * psInterface,
+                                   uint32 ulIndex,
+                                   uint32 ulSize);
+
+/** ***************************************************************************
+ *
+ * The operating mode required by the USB library client.  This type is used
+ * by applications which wish to be able to switch between host and device
+ * modes by calling the USBStackModeSet() API.
+ *
+ *****************************************************************************/
+typedef enum
+{
+    /**
+     *  @brief  The application wishes to operate as a USB device.
+     */
+    USB_MODE_DEVICE = 0,
+
+    /**
+     *  @brief  The application wishes to operate as a USB host.
+     */
+    USB_MODE_HOST,
+
+    /**
+     *  @brief  The application wishes to operate as both a host and device 
+	 *          using On-The-Go protocols to negotiate.
+     */
+    USB_MODE_OTG,
+
+    /**
+     *  @brief  A marker indicating that no USB mode has yet been set by the
+     *          application.
+     */
+    USB_MODE_NONE
+} tUSBMode;
+
+/** ***************************************************************************
+ *
+ * A pointer to a USB mode callback function.  This function is called by the
+ * USB library to indicate to the application which operating mode it should
+ * use, host or device.
+ *
+ *****************************************************************************/
+typedef void (* tUSBModeCallback)(uint32 ulIndex, tUSBMode eMode);
+
+/** ***************************************************************************
+ *
+ * Mode selection and dual mode interrupt steering functions.
+ *
+ *****************************************************************************/
+extern void USBStackModeSet(uint32 ulIndex, tUSBMode eUSBMode,
+                            tUSBModeCallback pfnCallback);
+extern void USBDualModeInit(uint32 ulIndex);
+extern void USBDualModeTerm(uint32 ulIndex);
+extern void USBOTGMain(uint32 ulMsTicks);
+extern void USBOTGPollRate(uint32 ulIndex, uint32 ulPollRate);
+extern void USBOTGModeInit(uint32 ulIndex, uint32 ulPollRate,
+                           void * pHostData, uint32 ulHostDataSize);
+extern void USBOTGModeTerm(uint32 ulIndex);
+extern void USB0OTGModeIntHandler(void);
+extern void USB0DualModeIntHandler(void);
+
+/** ***************************************************************************
+ *
+ *  USB callback function.
+ * 
+ *  @param pvCBData is the callback pointer associated with the instance
+ *   generating the callback.  This is a value provided by the client during
+ *  initialization of the instance making the callback.
+ *  @param ulEvent is the identifier of the asynchronous event which is being
+ *  notified to the client.
+ *  @param ulMsgParam is an event-specific parameter.
+ *  @param pvMsgData is an event-specific data pointer.
+ * 
+ *  A function pointer provided to the USB layer by the application
+ *  which will be called to notify it of all asynchronous events relating to
+ *  data transmission or reception.  This callback is used by device class
+ *  drivers and host pipe functions.
+ * 
+ *  @return Returns an event-dependent value.
+ * 
+ *****************************************************************************/
+typedef uint32 (* tUSBCallback)(void * pvCBData, uint32 ulEvent,
+                                       uint32 ulMsgParam,
+                                       void * pvMsgData);
+
+/** ***************************************************************************
+ * 
+ * Base identifiers for groups of USB events.  These are used by both the
+ * device class drivers and host layer.
+ *
+ * USB_CLASS_EVENT_BASE is the lowest identifier that should be used for
+ * a class-specific event.  Individual event bases are defined for each
+ * of the supported device class drivers.  Events with IDs between
+ * USB_EVENT_BASE and USB_CLASS_EVENT_BASE are reserved for stack use.
+ *
+ *****************************************************************************/
+#define USB_EVENT_BASE          0x0000u
+#define USB_CLASS_EVENT_BASE    0x8000u
+
+/** ***************************************************************************
+ *
+ * Event base identifiers for the various device classes supported in host
+ * and device modes.
+ * The first 0x800 values of a range are reserved for the device specific
+ * messages and the second 0x800 values of a range are used for the host
+ * specific messages for a given class.
+ *
+ *****************************************************************************/
+#define USBD_CDC_EVENT_BASE      (USB_CLASS_EVENT_BASE + 0u)
+#define USBD_HID_EVENT_BASE      (USB_CLASS_EVENT_BASE + 0x1000u)
+#define USBD_HID_KEYB_EVENT_BASE (USBD_HID_EVENT_BASE + 0x100u)
+#define USBD_BULK_EVENT_BASE     (USB_CLASS_EVENT_BASE + 0x2000u)
+#define USBD_MSC_EVENT_BASE      (USB_CLASS_EVENT_BASE + 0x3000u)
+#define USBD_AUDIO_EVENT_BASE    (USB_CLASS_EVENT_BASE + 0x4000u)
+
+#define USBH_CDC_EVENT_BASE   (USBD_CDC_EVENT_BASE  + 0x800u)
+#define USBH_HID_EVENT_BASE   (USBD_HID_EVENT_BASE  + 0x800u)
+#define USBH_BULK_EVENT_BASE  (USBD_BULK_EVENT_BASE + 0x800u)
+#define USBH_MSC_EVENT_BASE   (USBD_MSC_EVENT_BASE  + 0x800u)
+#define USBH_AUDIO_EVENT_BASE (USBD_AUDIO_EVENT_BASE  + 0x800u)
+
+/** ***************************************************************************
+ *
+ * General events supported by device classes and host pipes.
+ *
+ *****************************************************************************/
+
+/**
+ *  @brief  The device is now attached to a USB host and ready to begin sending
+ *          and receiving data (used by device classes only).
+ */
+#define USB_EVENT_CONNECTED (USB_EVENT_BASE + 0u)
+
+/**
+ *  @brief  The device has been disconnected from the USB host (used by device
+ *          classes only).
+ *
+ * Note: Due to a hardware erratum in revision A of LM3S3748, this
+ * event is not posted to self-powered USB devices when they are disconnected
+ * from the USB host.
+ */
+#define USB_EVENT_DISCONNECTED (USB_EVENT_BASE + 1u)
+
+/**
+ *  @brief  Data has been received and is in the buffer provided.
+ */
+#define USB_EVENT_RX_AVAILABLE (USB_EVENT_BASE + 2u)
+
+/**
+ *  @brief  This event is sent by a lower layer to inquire about the amount of
+ *          unprocessed data buffered in the layers above.  It is used in 
+ *          cases where a low level driver needs to ensure that all preceding 
+ *          data has been processed prior to performing some action or making 
+ *          some notification. Clients receiving this event should return the 
+ *          number of bytes of data that are unprocessed or 0 if no outstanding
+ *          data remains.
+ */
+#define USB_EVENT_DATA_REMAINING (USB_EVENT_BASE + 3u)
+
+/**
+ *  @brief  This event is sent by a lower layer supporting DMA to request a 
+ *          buffer in which the next received packet may be stored.  
+ *          The \e ulMsgValue parameter indicates the maximum size of packet 
+ *          that can be received in this channel and \e pvMsgData points to 
+ *          storage which should be written with the returned buffer pointer.  
+ *          The return value from the callback should be the size of the buffer
+ *          allocated (which may be less than the maximum size passed in 
+ *          \e ulMsgValue if the client knows that fewer bytes are expected
+ *          to be received) or 0 if no buffer is being returned.
+ */
+#define USB_EVENT_REQUEST_BUFFER (USB_EVENT_BASE + 4u)
+
+/**
+ *  @brief  Data has been sent and acknowledged.  If this event is received via
+ *          the USB buffer callback, the \e ulMsgValue parameter indicates the 
+ *          number of bytes from the transmit buffer that have been successfully
+ *          transmitted and acknowledged.
+ */
+#define USB_EVENT_TX_COMPLETE (USB_EVENT_BASE + 5u)
+
+/**
+ *  @brief  An error has been reported on the channel or pipe.  The 
+ *          \e ulMsgValue parameter indicates the source(s) of the error and 
+ *          is the logical OR combination of "USBERR_" flags defined below.
+ */
+#define USB_EVENT_ERROR (USB_EVENT_BASE + 6u)
+
+/**
+ *  @brief  The bus has entered suspend state.
+ */
+#define USB_EVENT_SUSPEND (USB_EVENT_BASE + 7u)
+
+/**
+ *  @brief  The bus has left suspend state.
+ */
+#define USB_EVENT_RESUME (USB_EVENT_BASE + 8u)
+
+/**
+ *  @brief  A scheduler event has occurred.
+ */
+#define USB_EVENT_SCHEDULER     (USB_EVENT_BASE + 9u)
+/**
+ *  @brief  A device or host has detected a stall condition.
+ */
+#define USB_EVENT_STALL         (USB_EVENT_BASE + 10u)
+
+/**
+ *  @brief  The host detected a power fault condition.
+ */
+#define USB_EVENT_POWER_FAULT   (USB_EVENT_BASE + 11u)
+
+/**
+ *  @brief  The controller has detected a A-Side cable and needs power applied.
+ *          This is only generated on OTG parts if automatic power control is 
+ *          disabled.
+ */
+#define USB_EVENT_POWER_ENABLE  (USB_EVENT_BASE + 12u)
+
+/**
+ *  @brief  The controller needs power removed,  This is only generated on OTG 
+ *          parts if automatic power control is disabled.
+ */
+#define USB_EVENT_POWER_DISABLE (USB_EVENT_BASE + 13u)
+
+/**
+ *  @brief  Used with pfnDeviceHandler handler function is classes to indicate
+ *          changes in the interface number by a class outside the class being
+ *          accessed. Typically this is when composite device class is in use.
+ *
+ *  The \e pvInstance value should point to an instance of the device being
+ *  accessed.
+ *
+ *  The \e ulRequest should be USB_EVENT_COMP_IFACE_CHANGE.
+ *
+ *  The \e pvRequestData should point to a two byte array where the first value
+ *  is the old interface number and the second is the new interface number.
+ */
+#define USB_EVENT_COMP_IFACE_CHANGE (USB_EVENT_BASE + 14u)
+
+/**
+ *  @brief  Used with pfnDeviceHandler handler function is classes to indicate
+ *          changes in endpoint number by a class outside the class being 
+ *          accessed. Typically this is when composite device class is in use.
+ * 
+ *  The \e pvInstance value should point to an instance of the device being
+ *  accessed.
+ * 
+ *  The \e ulRequest should be USB_EVENT_COMP_EP_CHANGE.
+ * 
+ *  The \e pvRequestData should point to a two byte array where the first value
+ *  is the old endpoint number and the second is the new endpoint number.  The
+ *  endpoint numbers should be exactly as USB specification defines them and
+ *  bit 7 set indicates an IN endpoint and bit 7 clear indicates an OUT
+ *  endpoint.
+ */
+#define USB_EVENT_COMP_EP_CHANGE    (USB_EVENT_BASE + 15u)
+
+/**
+ *  @brief  Used with pfnDeviceHandler handler function is classes to indicate 
+ *          changes in string index number by a class outside the class being 
+ *          accessed. Typically this is when composite device class is in use.
+ *
+ *  The \e pvInstance value should point to an instance of the device being
+ *  accessed.
+ * 
+ *  The \e ulRequest should be USB_EVENT_COMP_STR_CHANGE.
+ * 
+ *  The \e pvRequestData should point to a two byte array where the first value
+ *  is the old string index and the second is the new string index.
+ */
+#define USB_EVENT_COMP_STR_CHANGE    (USB_EVENT_BASE + 16u)
+
+/**
+ *  @brief  Used with pfnDeviceHandler handler function is classes to allow the
+ *          device class to make final adjustments to the configuration 
+ *          descriptor. This is only used when a device class is used in a 
+ *           composite device class is in use.
+ * 
+ *  The \e pvInstance value should point to an instance of the device being
+ *  accessed.
+ * 
+ *  The \e ulRequest should be USB_EVENT_COMP_CONFIG.
+ * 
+ *  The \e pvRequestData should point to the beginning of the configuration
+ *  descriptor for the device instance.
+ */
+#define USB_EVENT_COMP_CONFIG        (USB_EVENT_BASE + 17u)
+
+/** ***************************************************************************
+ *
+ * Error sources reported via USB_EVENT_ERROR.
+ *
+ *****************************************************************************/
+
+/**
+ *  @brief  The host received an invalid PID in a transaction.
+ */
+#define USBERR_HOST_IN_PID_ERROR   0x01000000u
+
+/**
+ *  @brief  The host did not receive a response from a device.
+ */
+#define USBERR_HOST_IN_NOT_COMP    0x00100000u
+
+/**
+ *  @brief  The host received a stall on an IN endpoint.
+ */
+#define USBERR_HOST_IN_STALL       0x00400000u
+
+/**
+ *  @brief  The host detected a CRC or bit-stuffing error (isochronous mode).
+ */
+#define USBERR_HOST_IN_DATA_ERROR  0x00080000u
+
+/**
+ *  @brief  The host received NAK on an IN endpoint for longer than the 
+ *          specified timeout period (interrupt, bulk and control modes).
+ */
+#define USBERR_HOST_IN_NAK_TO      0x00080000u
+
+/**
+ *  @brief  The host failed to communicate with a device via an IN endpoint.
+ */
+#define USBERR_HOST_IN_ERROR       0x00040000u
+
+/**
+ *  @brief  The host receive FIFO is full.
+ */
+#define USBERR_HOST_IN_FIFO_FULL   0x00020000u  /* RX FIFO full */
+/**
+ *  @brief  The host received NAK on an OUT endpoint for longer than the 
+ *          specified timeout period (bulk, interrupt and control modes).
+ */
+#define USBERR_HOST_OUT_NAK_TO     0x00000080u
+
+/**
+ *  @brief  The host did not receive a response from a device (isochronous mode).
+ */
+#define USBERR_HOST_OUT_NOT_COMP   0x00000080u
+
+/**
+ *  @brief  The host received a stall on an OUT endpoint.
+ */
+#define USBERR_HOST_OUT_STALL      0x00000020u
+
+/**
+ *  @brief  The host failed to communicate with a device via an OUT endpoint.
+ */
+#define USBERR_HOST_OUT_ERROR      0x00000004u
+
+/**
+ *  @brief  The host received NAK on endpoint 0 for longer than the configured
+ *          timeout.
+ */
+#define USBERR_HOST_EP0_NAK_TO     0x00000080u
+
+/**
+ *  @brief  The host failed to communicate with a device via an endpoint zero.
+ */
+#define USBERR_HOST_EP0_ERROR      0x00000010u
+
+/**
+ *  @brief  The device detected a CRC error in received data.
+ */
+#define USBERR_DEV_RX_DATA_ERROR   0x00080000u
+
+/**
+ *  @brief  The device was unable to receive a packet from the host since the 
+ *          receive FIFO is full.
+ */
+#define USBERR_DEV_RX_OVERRUN      0x00040000u
+
+/**
+ *  @brief  The device receive FIFO is full.
+ */
+#define USBERR_DEV_RX_FIFO_FULL    0x00020000u  /* RX FIFO full */
+
+/** ***************************************************************************
+ *
+ * Close the general_usblib_api Doxygen group.
+ * @}
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @ingroup usblib_buffer_api
+ * @{
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ *  @brief  A function pointer type which describes either a class driver 
+ *          packet read or packet write function (both have the same prototype)
+ *          to the USB buffer object.
+ *
+ *****************************************************************************/
+typedef uint32 (* tUSBPacketTransfer)(void * pvHandle,
+                                             uint8 *  pcData,
+                                             uint32   ulLength,
+                                             tBoolean bLast);
+
+/** ***************************************************************************
+ *
+ *  @brief  A function pointer type which describes either a class driver 
+ *          transmit or receive packet available function (both have the same
+ *          prototype) to the USB buffer object.
+ *
+ *****************************************************************************/
+typedef uint32 (* tUSBPacketAvailable)(void * pvHandle);
+
+/** ***************************************************************************
+ *
+ *  @brief  The number of bytes of workspace that each USB buffer object 
+ *          requires. This workspace memory is provided to the buffer on 
+ *          USBBufferInit() in the \e pvWorkspace field of the \e tUSBBuffer 
+ *          structure.
+ *
+ *****************************************************************************/
+#define USB_BUFFER_WORKSPACE_SIZE 16
+
+/** ***************************************************************************
+ *
+ *  @brief  The structure used by the application to initialize a buffer object 
+ *          that will provide buffered access to either a transmit or receive 
+ *          channel.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  This field sets the mode of the buffer.  If TRUE, the buffer
+     *          operates as a transmit buffer and supports calls to 
+	 *          USBBufferWrite by the client.  If FALSE, the buffer operates 
+	 *          as a receive buffer and supports calls to USBBufferRead.
+     */
+    tBoolean bTransmitBuffer;
+
+    /**
+     *  @brief  A pointer to the callback function which will be called to 
+	 *          notify the application of all asynchronous events related to
+	 *          the operation of the buffer.
+     */
+    tUSBCallback pfnCBack;
+
+    /**
+     *  @brief  A pointer that the buffer will pass back to the client in the
+     *          first parameter of all callbacks related to this instance.
+     */
+    void * pvCBData;
+
+    /**
+     *  @brief  The function which should be called to transmit a packet of 
+	 *          data in transmit mode or receive a packet in receive mode.
+     */
+    tUSBPacketTransfer pfnTransfer;
+
+    /**
+     *  @brief  The function which should be called to determine if the 
+	 *          endpoint is ready to accept a new packet for transmission in 
+	 *          transmit mode or to determine the size of the buffer required
+	 *          to read a packet in receive mode.
+     */
+    tUSBPacketAvailable pfnAvailable;
+
+    /**
+     *  @brief  The handle to pass to the low level function pointers provided
+     *          in the pfnTransfer and pfnAvailable members.  For USB device
+     *          use, this is the psDevice parameter required by the relevant 
+	 *          device class driver APIs.  For USB host use, this is the pipe 
+	 *          identifier returned by USBHCDPipeAlloc.
+     */
+    void * pvHandle;
+
+    /**
+     *  @brief  A pointer to memory to be used as the ring buffer for this
+     *          instance.
+     */
+    uint8 * pcBuffer;
+
+    /**
+     *  @brief  The size, in bytes, of the buffer pointed to by pcBuffer.
+     */
+    uint32 ulBufferSize;
+
+    /**
+     *  @brief  A pointer to USB_BUFFER_WORKSPACE_SIZE bytes of RAM that the 
+	 *          buffer object can use for workspace.
+     */
+    void * pvWorkspace;
+}
+tUSBBuffer;
+
+/** ***************************************************************************
+ *
+ *  @brief  The structure used for encapsulating all the items associated with
+ *          a ring buffer.
+ *
+ *****************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The ring buffer size.
+     */
+    uint32 ulSize;
+
+    /**
+     *  @brief  The ring buffer write index.
+     */
+    volatile uint32 ulWriteIndex;
+
+    /**
+     *  @brief  The ring buffer read index.
+     */
+    volatile uint32 ulReadIndex;
+
+    /**
+     *  @brief  The ring buffer.
+     */
+    uint8 * pucBuf;
+}
+tUSBRingBufObject;
+
+/** ***************************************************************************
+ *
+ * USB buffer API function prototypes.
+ *
+ *****************************************************************************/
+extern const tUSBBuffer * USBBufferInit(const tUSBBuffer * psBuffer);
+extern void USBBufferInfoGet(const tUSBBuffer * psBuffer,
+                             tUSBRingBufObject * psRingBuf);
+extern void * USBBufferCallbackDataSet(tUSBBuffer * psBuffer, void * pvCBData);
+extern uint32 USBBufferWrite(const tUSBBuffer * psBuffer,
+                                    const uint8 * pucData,
+                                    uint32 ulLength);
+extern void USBBufferDataWritten(const tUSBBuffer * psBuffer,
+                                 uint32 ulLength);
+extern void USBBufferDataRemoved(const tUSBBuffer * psBuffer,
+                                 uint32 ulLength);
+extern void USBBufferFlush(const tUSBBuffer * psBuffer);
+extern uint32 USBBufferRead(const tUSBBuffer * psBuffer,
+                                   uint8 * pucData,
+                                   uint32 ulLength);
+extern uint32 USBBufferDataAvailable(const tUSBBuffer * psBuffer);
+extern uint32 USBBufferSpaceAvailable(const tUSBBuffer * psBuffer);
+extern uint32 USBBufferEventCallback(void * pvCBData,
+                                            uint32 ulEvent,
+                                            uint32 ulMsgValue,
+                                            void * pvMsgData);
+extern tBoolean USBRingBufFull(tUSBRingBufObject * ptUSBRingBuf);
+extern tBoolean USBRingBufEmpty(tUSBRingBufObject * ptUSBRingBuf);
+extern void USBRingBufFlush(tUSBRingBufObject * ptUSBRingBuf);
+extern uint32 USBRingBufUsed(tUSBRingBufObject * ptUSBRingBuf);
+extern uint32 USBRingBufFree(tUSBRingBufObject * ptUSBRingBuf);
+extern uint32 USBRingBufContigUsed(tUSBRingBufObject * ptUSBRingBuf);
+extern uint32 USBRingBufContigFree(tUSBRingBufObject * ptUSBRingBuf);
+extern uint32 USBRingBufSize(tUSBRingBufObject * ptUSBRingBuf);
+extern uint8 USBRingBufReadOne(tUSBRingBufObject * ptUSBRingBuf);
+extern void USBRingBufRead(tUSBRingBufObject * ptUSBRingBuf,
+                           uint8 * pucData, uint32 ulLength);
+extern void USBRingBufWriteOne(tUSBRingBufObject * ptUSBRingBuf,
+                               uint8 ucData);
+extern void USBRingBufWrite(tUSBRingBufObject * ptUSBRingBuf,
+                            const uint8 pucData[],
+                            uint32 ulLength);
+extern void USBRingBufAdvanceWrite(tUSBRingBufObject * ptUSBRingBuf,
+                                   uint32 ulNumBytes);
+extern void USBRingBufAdvanceRead(tUSBRingBufObject * ptUSBRingBuf,
+                                  uint32 ulNumBytes);
+extern void USBRingBufInit(tUSBRingBufObject * ptUSBRingBuf,
+                           uint8 * pucBuf, uint32 ulSize);
+
+/** ***************************************************************************
+ *
+ *  Close the Doxygen group.
+ *  @}
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Mark the end of the C bindings section for C++ compilers.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBLIB_H__ */
diff --git a/mp b/mp
index 60f98b5..703dcb0 100755
--- a/mp
+++ b/mp
@@ -7,6 +7,7 @@
 set -e
 
 find src -name '*.o' -delete
+find src -name '*.obj' -delete
 rm -f build/system.elf
 
 for i in info program; do
diff --git a/mpm b/mpm
index 48680a8..021e5f5 100755
--- a/mpm
+++ b/mpm
@@ -7,6 +7,7 @@
 set -e
 
 find src -name '*.o' -delete
+find src -name '*.obj' -delete
 rm -f build/system.elf
 
 for i in info program monitor; do
diff --git a/src/arch/rm46l8lp/Kconfig b/src/arch/rm46l8lp/Kconfig
new file mode 100644
index 0000000..4b04f57
--- /dev/null
+++ b/src/arch/rm46l8lp/Kconfig
@@ -0,0 +1,10 @@
+# Copyright 2022 Daniel Friesel
+#
+# SPDX-License-Identifier: CC0-1.0
+config arch_rm46l8lp_driver_counter
+bool "Cycle Counter"
+select meta_driver_counter
+
+config arch_rm46l8lp_driver_uptime
+bool "Uptime Counter"
+select meta_driver_uptime
diff --git a/src/arch/rm46l8lp/Makefile.inc b/src/arch/rm46l8lp/Makefile.inc
new file mode 100644
index 0000000..415b1df
--- /dev/null
+++ b/src/arch/rm46l8lp/Makefile.inc
@@ -0,0 +1,122 @@
+# vim:ft=make
+#
+# Copyright 2020 Daniel Friesel
+#
+# SPDX-License-Identifier: BSD-2-Clause
+
+SERIAL_PORT ?= ttyACM2
+
+cpu_freq ?= 160000000
+counter_freq ?= 80000000
+
+INCLUDES += --include_path=/home/derf/lib/local/ti/ccs1200/ccs/tools/compiler/ti-cgt-arm_20.2.6.LTS/include --include_path=include/arch/rm46l8lp/halcogen
+
+# this is not gcc
+COMMON_FLAGS =
+CFLAGS =
+CXXFLAGS =
+
+COMMON_FLAGS += --preinclude=include/config.h
+COMMON_FLAGS += -DF_CPU=${cpu_freq}UL
+COMMON_FLAGS += -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --opt_for_speed=0
+COMMON_FLAGS += --define=_TMS570LS12x_ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi
+#CXXFLAGS += --c++14
+
+CC = /home/derf/lib/local/ti/ccs1200/ccs/tools/compiler/ti-cgt-arm_20.2.6.LTS/bin/armcl
+CXX = ${CC}
+SIZE = /home/derf/lib/local/ti/ccs1200/ccs/tools/compiler/ti-cgt-arm_20.2.6.LTS/bin/armsize
+
+ARCH_SHORTNAME = rm46l8
+
+C_TARGETS += src/arch/rm46l8lp/halcogen/adc.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/errata_SSWF021_45.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/esm.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/gio.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/pinmux.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/notification.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/rti.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/sys_dma.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/sys_phantom.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/sci.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/sys_pcr.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/sys_pmm.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/sys_startup.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/system.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/sys_vim.c
+C_TARGETS += src/arch/rm46l8lp/halcogen/sys_selftest.c
+CXX_TARGETS += src/arch/rm46l8lp/arch.cc
+CXX_TARGETS += src/arch/rm46l8lp/driver/gpio.cc
+CXX_TARGETS += src/arch/rm46l8lp/driver/stdout.cc
+ASM_TARGETS += src/arch/rm46l8lp/halcogen/dabort.asm
+ASM_TARGETS += src/arch/rm46l8lp/halcogen/sys_core.asm
+ASM_TARGETS += src/arch/rm46l8lp/halcogen/sys_intvecs.asm
+ASM_TARGETS += src/arch/rm46l8lp/halcogen/sys_mpu.asm
+ASM_TARGETS += src/arch/rm46l8lp/halcogen/sys_pmu.asm
+
+# special case for TI CC makefile
+ifeq (${loop}, 1)
+	COMMON_FLAGS += -DCONFIG_loop
+endif
+
+ifneq ($(findstring counter,${arch_drivers}), )
+	CONFIG_arch_rm46l8lp_driver_counter = y
+endif
+
+ifeq (${timer_s}, 1)
+	CONFIG_arch_rm46l8lp_driver_uptime = y
+endif
+
+ifdef CONFIG_arch_rm46l8lp_driver_counter
+	CXX_TARGETS += src/arch/rm46l8lp/driver/counter.cc
+endif
+
+ifdef CONFIG_arch_rm46l8lp_driver_uptime
+	COMMON_FLAGS += -DTIMER_S
+	CXX_TARGETS += src/arch/rm46l8lp/driver/uptime.cc
+endif
+
+OBJECTS = ${CXX_TARGETS:.cc=.obj} ${C_TARGETS:.c=.obj} ${ASM_TARGETS:.asm=.obj}
+
+%.obj : %.cc | include/config.h
+	${QUIET}${CXX} ${INCLUDES} ${COMMON_FLAGS} ${CXXFLAGS} --preproc_with_compile --obj_directory=$(dir $@) ${@:.obj=.cc}
+
+%.obj : %.c | include/config.h
+	${QUIET}${CC} ${INCLUDES} ${COMMON_FLAGS} ${CFLAGS} --preproc_with_compile --obj_directory=$(dir $@) ${@:.obj=.c}
+
+%.obj : %.asm | include/config.h
+	${QUIET}${CC} ${INCLUDES} ${COMMON_FLAGS} ${CFLAGS} --preproc_with_compile --obj_directory=$(dir $@) ${@:.obj=.asm}
+
+build/system.elf: ${OBJECTS}
+	${QUIET}mkdir -p build
+	${QUIET}${CXX} ${COMMON_FLAGS} ${CXXFLAGS} \
+		-z --heap_size=0x1000 --stack_size=0x1000 \
+		-i"/home/derf/lib/local/ti/ccs1200/ccs/tools/compiler/ti-cgt-arm_20.2.6.LTS/lib" \
+		-i"/home/derf/lib/local/ti/ccs1200/ccs/tools/compiler/ti-cgt-arm_20.2.6.LTS/include" \
+		--reread_libs --warn_sections --ecc=off --rom_model -o $@ \
+		${OBJECTS} src/arch/rm46l8lp/halcogen/sys_link.cmd \
+		-lrtsv7R4_T_le_v3D16_eabi.lib
+
+program: build/system.elf
+	${QUIET}/opt/ti/uniflash_7.2.0/dslite.sh -c src/arch/rm46l8lp/RM46L852.ccxml -f build/system.elf -u
+
+arch_clean:
+	${QUIET}rm -f ${OBJECTS}
+
+monitor:
+	${QUIET}screen /dev/${SERIAL_PORT} 19200
+
+arch_help:
+
+arch_info:
+	@echo "CPU   Freq: ${cpu_freq} Hz"
+	@echo "Count Freq: ${counter_freq} Hz"
+	@echo "Counter Overflow: 4294967296/4294967295"
+	@echo "Monitor: /dev/${SERIAL_PORT} 19200"
+
+attributes: build/system.elf
+	${QUIET}script/size.py ${SIZE} text,data data,bss
+
+nfpvalues: build/system.elf
+	${QUIET}script/nfpvalues.py ${SIZE} text,data data,bss
+
+.PHONY: arch_clean arch_help arch_info attributes cat monitor program
diff --git a/src/arch/rm46l8lp/RM46L852.ccxml b/src/arch/rm46l8lp/RM46L852.ccxml
new file mode 100644
index 0000000..582d900
--- /dev/null
+++ b/src/arch/rm46l8lp/RM46L852.ccxml
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configurations XML_version="1.2" id="configurations_0">
+<configuration XML_version="1.2" id="configuration_0">
+        <instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
+        <connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe">
+        	
+        		   <instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/>
+        	
+        		   <instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
+        	
+        		   <instance XML_version="1.2" href="drivers/tixds510cortexR.xml" id="drivers" xml="tixds510cortexR.xml" xmlpath="drivers"/>
+        	
+            
+            <platform XML_version="1.2" id="platform_0">
+                <instance XML_version="1.2" desc="RM46L852" href="devices/rm46l852.xml" id="RM46L852" xml="rm46l852.xml" xmlpath="devices"/>
+            </platform>
+        </connection>
+    </configuration>
+</configurations>
diff --git a/src/arch/rm46l8lp/arch.cc b/src/arch/rm46l8lp/arch.cc
new file mode 100644
index 0000000..e07e507
--- /dev/null
+++ b/src/arch/rm46l8lp/arch.cc
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2020 Daniel Friesel
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#include "arch.h"
+#include "gio.h"
+#include "rti.h"
+
+#ifdef __acweaving
+#define __delay_cycles(x)
+#endif
+
+void Arch::setup(void)
+{
+	gioInit();
+
+	// disable counter blocks
+	rtiREG1->GCTRL = 0;
+
+	// internal clock, RTIUC0 -> RTIFRC0
+	rtiREG1->TBCTRL = 0;
+
+	// no capture sources
+	rtiREG1->CAPCTRL = 0;
+
+	// input source: counter 0 -> compare 0/1, counter 1 -> compare 2/3
+	rtiREG1->COMPCTRL = 0x00001100U;
+
+	// reset up / free running counter 0
+	rtiREG1->CNT[0].UCx = 0;
+	rtiREG1->CNT[0].FRCx = 0;
+
+	// reset up / free running counter 1
+	rtiREG1->CNT[1].UCx = 0;
+	rtiREG1->CNT[1].FRCx = 0;
+
+	// free running counter 0 freq = RTICLK/2^32
+	rtiREG1->CNT[0].CPUCx = 0xffffffffU;
+
+	// free running counter 1 freq = RTICLK/2 ( == VCLK/4, see halcogen/system.c)
+	rtiREG1->CNT[1].CPUCx = 1;
+
+	// one interrupt per second
+	rtiREG1->CMP[2].COMPx = F_CPU/4;
+	rtiREG1->CMP[2].UDCPx = F_CPU/4;
+
+	// clear all pending interrupts
+	rtiREG1->INTFLAG = 0x0007000FU;
+
+	// disable all interrupts
+	rtiREG1->CLEARINTENA = 0x00070F0FU;
+
+#if defined(CONFIG_loop) || defined(TIMER_S)
+	rtiEnableNotification(rtiNOTIFICATION_COMPARE2);
+#endif
+	_enable_IRQ();
+#if defined(CONFIG_loop) || defined(TIMER_S)
+	rtiStartCounter(rtiCOUNTER_BLOCK1);
+#endif
+}
+
+#ifdef CONFIG_wakeup
+extern void wakeup();
+#endif
+
+#if defined(CONFIG_loop)
+extern void loop();
+volatile bool run_loop = 0;
+#endif
+
+void Arch::delay_us(unsigned int const us)
+{
+	if (us < 10) {
+		for (unsigned int i = 0; i < us; i++) {
+			__delay_cycles(F_CPU / 4000000UL);
+		}
+	} else {
+		for (unsigned int i = 0; i < us/10; i++) {
+			__delay_cycles(F_CPU / 400000UL);
+		}
+	}
+}
+void Arch::delay_ms(unsigned int const ms)
+{
+	for (unsigned int i = 0; i < ms; i++) {
+		__delay_cycles(F_CPU / 4000UL);
+	}
+}
+
+
+void Arch::idle_loop(void)
+{
+	while (1) {
+#if defined(CONFIG_loop)
+		if (run_loop) {
+			loop();
+			run_loop = 0;
+		}
+#endif
+	}
+}
+
+void Arch::idle(void)
+{
+#ifdef CONFIG_wakeup
+	wakeup();
+#endif
+}
+
+#if defined(CONFIG_loop) || defined(TIMER_S)
+#include "driver/uptime.h"
+void rtiNotification(uint32 notification)
+{
+	if (notification == rtiNOTIFICATION_COMPARE2) {
+#ifdef CONFIG_loop
+		run_loop = 1;
+#endif
+#ifdef TIMER_S
+		uptime.tick_s();
+#endif
+	}
+}
+#endif
+
+Arch arch;
diff --git a/src/arch/rm46l8lp/driver/counter.cc b/src/arch/rm46l8lp/driver/counter.cc
new file mode 100644
index 0000000..4e0bb92
--- /dev/null
+++ b/src/arch/rm46l8lp/driver/counter.cc
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2022 Daniel Friesel
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#include "driver/counter.h"
+
+Counter counter;
diff --git a/src/arch/rm46l8lp/driver/gpio.cc b/src/arch/rm46l8lp/driver/gpio.cc
new file mode 100644
index 0000000..148bcdb
--- /dev/null
+++ b/src/arch/rm46l8lp/driver/gpio.cc
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2020 Daniel Friesel
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#include "driver/gpio.h"
+
+GPIO gpio;
diff --git a/src/arch/rm46l8lp/driver/stdout.cc b/src/arch/rm46l8lp/driver/stdout.cc
new file mode 100644
index 0000000..9d5403c
--- /dev/null
+++ b/src/arch/rm46l8lp/driver/stdout.cc
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2022 Daniel Friesel
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#include "driver/stdout.h"
+#include "sci.h"
+
+void StandardOutput::setup()
+{
+	sciInit();
+}
+
+void StandardOutput::put(char c)
+{
+	while ((scilinREG->FLR & 0x04) == 0x04);
+	sciSendByte(scilinREG, c);
+	if (c == '\n') {
+		put('\r');
+	}
+}
+
+StandardOutput kout;
diff --git a/src/arch/rm46l8lp/driver/uptime.cc b/src/arch/rm46l8lp/driver/uptime.cc
new file mode 100644
index 0000000..8aaff8f
--- /dev/null
+++ b/src/arch/rm46l8lp/driver/uptime.cc
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2022 Daniel Friesel
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#include "driver/uptime.h"
+
+Uptime uptime;
diff --git a/src/arch/rm46l8lp/halcogen/adc.c b/src/arch/rm46l8lp/halcogen/adc.c
new file mode 100644
index 0000000..a888c19
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/adc.c
@@ -0,0 +1,989 @@
+/** @file adc.c 
+*   @brief ADC Driver Source File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file contains:
+*   - API Functions
+*   - Interrupt Handlers
+*   .
+*   which are relevant for the ADC driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Include Files */
+
+#include "adc.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @fn void adcInit(void)
+*   @brief Initializes ADC Driver
+*
+*   This function initializes the ADC driver.
+*
+*/
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+/* SourceId : ADC_SourceId_001 */
+/* DesignId : ADC_DesignId_001 */
+/* Requirements : HL_SR185 */
+void adcInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+    /** @b Initialize @b ADC1: */
+
+    /** - Reset ADC module */
+    adcREG1->RSTCR = 1U;
+    adcREG1->RSTCR = 0U;
+
+    /** - Enable 12-BIT ADC  */
+    adcREG1->OPMODECR |= 0x80000000U;
+	
+    /** - Setup prescaler */
+    adcREG1->CLOCKCR = 7U;
+ 
+    /** - Setup memory boundaries */
+    adcREG1->BNDCR  = (uint32)((uint32)8U << 16U) | (8U + 8U);
+    adcREG1->BNDEND = (adcREG1->BNDEND & 0xFFFF0000U) | (2U);
+ 
+    /** - Setup event group conversion mode
+    *     - Setup data format
+    *     - Enable/Disable channel id in conversion result
+    *     - Enable/Disable continuous conversion
+    */
+    adcREG1->GxMODECR[0U] = (uint32)ADC_12_BIT
+                          | (uint32)0x00000000U
+                          | (uint32)0x00000000U;
+
+    /** - Setup event group hardware trigger
+     *     - Setup hardware trigger edge
+     *     - Setup hardware trigger source
+     */
+    adcREG1->EVSRC = (uint32)0x00000000U
+                   | (uint32)ADC1_EVENT;
+
+    /** - Setup event group sample window */
+    adcREG1->EVSAMP = 1U;
+
+    /** - Setup event group sample discharge 
+    *     - Setup discharge prescaler
+    *     - Enable/Disable discharge
+    */
+    adcREG1->EVSAMPDISEN = (uint32)((uint32)0U << 8U)
+                         | (uint32)0x00000000U;
+
+    /** - Setup group 1 conversion mode
+    *     - Setup data format
+    *     - Enable/Disable channel id in conversion result
+    *     - Enable/Disable continuous conversion
+    */
+    adcREG1->GxMODECR[1U] = (uint32)ADC_12_BIT
+                          | (uint32)0x00000000U
+                          | (uint32)0x00000000U
+                          | (uint32)0x00000000U;
+
+    /** - Setup group 1 hardware trigger
+     *     - Setup hardware trigger edge
+     *     - Setup hardware trigger source
+     */
+    adcREG1->G1SRC = (uint32)0x00000000U
+                   | (uint32)ADC1_EVENT;
+
+    /** - Setup group 1 sample window */
+    adcREG1->G1SAMP = 0U;
+
+    /** - Setup group 1 sample discharge 
+    *     - Setup discharge prescaler
+    *     - Enable/Disable discharge
+    */
+    adcREG1->G1SAMPDISEN = (uint32)((uint32)0U << 8U)
+                         | (uint32)0x00000000U;
+
+    /** - Setup group 2 conversion mode
+     *     - Setup data format
+     *     - Enable/Disable channel id in conversion result
+     *     - Enable/Disable continuous conversion
+     */
+    adcREG1->GxMODECR[2U] = (uint32)ADC_12_BIT
+                          | (uint32)0x00000000U
+                          | (uint32)0x00000000U
+                          | (uint32)0x00000000U;
+
+    /** - Setup group 2 hardware trigger
+	*     - Setup hardware trigger edge
+    *     - Setup hardware trigger source
+	*/
+    adcREG1->G2SRC = (uint32)0x00000000U
+                   | (uint32)ADC1_EVENT;
+
+    /** - Setup group 2 sample window */
+    adcREG1->G2SAMP = 1U;
+
+    /** - Setup group 2 sample discharge 
+    *     - Setup discharge prescaler
+    *     - Enable/Disable discharge
+    */
+    adcREG1->G2SAMPDISEN = (uint32)((uint32)0U << 8U)
+                         | (uint32)0x00000000U;
+
+    /** - ADC1 EVT pin output value */
+    adcREG1->EVTOUT = 0U;
+
+    /** - ADC1 EVT pin direction */
+    adcREG1->EVTDIR = 0U;
+	
+    /** - ADC1 EVT pin open drain enable */
+	adcREG1->EVTPDR = 0U;
+
+    /** - ADC1 EVT pin pullup / pulldown selection */
+	adcREG1->EVTPSEL = 1U;
+
+    /** - ADC1 EVT pin pullup / pulldown enable*/
+	adcREG1->EVTDIS = 0U;
+	
+	/** - Enable ADC module */
+    adcREG1->OPMODECR |= 0x80140001U;
+	
+    /** - Wait for buffer initialization complete */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while (((adcREG1->BNDEND & 0xFFFF0000U) >> 16U ) != 0U) 
+    { 
+	} /* Wait */
+    
+    /** - Setup parity */
+    adcREG1->PARCR = 0x00000005U;
+
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+
+/** - s_adcSelect is used as constant table for channel selection */
+static const uint32 s_adcSelect[2U][3U] =
+{
+    {0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U,
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000040U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U,
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U},
+    {0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U ,
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U,
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U}
+};
+
+/** - s_adcFiFoSize is used as constant table for channel selection */
+static const uint32 s_adcFiFoSize[2U][3U] =
+{
+    {16U,
+    1U,
+    16U},
+    {16U,
+    16U,
+    16U}
+};
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+/** @fn void adcStartConversion(adcBASE_t *adc, uint32 group)
+*   @brief Starts an ADC conversion
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   This function starts a conversion of the ADC hardware group.
+*
+*/
+/* SourceId : ADC_SourceId_002 */
+/* DesignId : ADC_DesignId_002 */
+/* Requirements : HL_SR186 */
+void adcStartConversion(adcBASE_t *adc, uint32 group)
+{
+    uint32 index = (adc == adcREG1) ? 0U : 1U;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+    /** - Setup FiFo size */
+    adc->GxINTCR[group] = s_adcFiFoSize[index][group];
+
+    /** - Start Conversion */
+    adc->GxSEL[group] = s_adcSelect[index][group];
+
+    /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+
+/** @fn void adcStopConversion(adcBASE_t *adc, uint32 group)
+*   @brief Stops an ADC conversion
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   This function stops a conversion of the ADC hardware group.
+*
+*/
+/* SourceId : ADC_SourceId_003 */
+/* DesignId : ADC_DesignId_003 */
+/* Requirements : HL_SR187 */
+void adcStopConversion(adcBASE_t *adc, uint32 group)
+{
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+    /** - Stop Conversion */
+    adc->GxSEL[group] = 0U;
+
+    /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+
+/** @fn void adcResetFiFo(adcBASE_t *adc, uint32 group)
+*   @brief Resets FiFo read and write pointer.
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   This function resets the FiFo read and write pointers.
+*
+*/
+/* SourceId : ADC_SourceId_004 */
+/* DesignId : ADC_DesignId_004*/
+/* Requirements : HL_SR188 */
+void adcResetFiFo(adcBASE_t *adc, uint32 group)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+    /** - Reset FiFo */
+    adc->GxFIFORESETCR[group] = 1U;
+
+    /**   @note The function adcInit has to be called before this function can be used.\n
+    *           the conversion should be stopped before calling this function. 
+    */
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+
+/** @fn uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data)
+*   @brief Gets converted a ADC values
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*   @param[out] data Pointer to store ADC converted data
+*   @return The function will return the number of converted values copied into data buffer:
+*
+*   This function writes a ADC message into a ADC message box.
+*
+*/
+/* SourceId : ADC_SourceId_005 */
+/* DesignId : ADC_DesignId_005 */
+/* Requirements : HL_SR189 */
+uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data)
+{
+    uint32  i;
+    uint32  buf;
+    uint32  mode;    
+    uint32  index = (adc == adcREG1) ? 0U : 1U;
+
+	uint32  intcr_reg = adc->GxINTCR[group];
+    uint32  count = (intcr_reg >= 256U) ? s_adcFiFoSize[index][group] : (s_adcFiFoSize[index][group] - (uint32)(intcr_reg & 0xFFU));
+    adcData_t *ptr = data; 
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+    mode = (adc->OPMODECR & ADC_12_BIT_MODE);
+
+    if(mode == ADC_12_BIT_MODE)
+      {
+        /** -  Get conversion data and channel/pin id */
+        for (i = 0U; i < count; i++)
+        {
+          buf        = adc->GxBUF[group].BUF0;
+		  /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+          ptr->value = (uint16)(buf & 0xFFFU);
+          ptr->id    = (uint32)((buf >> 16U) & 0x1FU);
+          /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
+		  ptr++;
+        }
+      }
+      else
+      {
+        /** -  Get conversion data and channel/pin id */
+        for (i = 0U; i < count; i++)
+        {
+          buf        = adc->GxBUF[group].BUF0;
+		  /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+          ptr->value = (uint16)(buf & 0x3FFU);
+          ptr->id    = (uint32)((buf >> 10U) & 0x1FU);
+          /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
+		  ptr++;
+        }
+      }
+
+
+    adc->GxINTFLG[group] = 9U;
+
+    /**   @note The function adcInit has to be called before this function can be used.\n
+    *           The user is responsible to initialize the message box.
+    */
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+    return count;
+}
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+
+/** @fn uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group)
+*   @brief Checks if FiFo buffer is full
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*   @return The function will return:
+*           - 0: When FiFo buffer is not full   
+*           - 1: When FiFo buffer is full   
+*           - 3: When FiFo buffer overflow occurred    
+*
+*   This function checks FiFo buffer status.
+*
+*/
+/* SourceId : ADC_SourceId_006 */
+/* DesignId : ADC_DesignId_006 */
+/* Requirements : HL_SR190 */
+uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group)
+{
+    uint32 flags;
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+    /** - Read FiFo flags */
+    flags = adc->GxINTFLG[group] & 3U;
+
+    /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+    return flags;
+}
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+
+/** @fn uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group)
+*   @brief Checks if Conversion is complete
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*   @return The function will return:
+*           - 0: When is not finished   
+*           - 8: When conversion is complete   
+*
+*   This function checks if conversion is complete.
+*
+*/
+/* SourceId : ADC_SourceId_007 */
+/* DesignId : ADC_DesignId_007 */
+/* Requirements : HL_SR191 */
+uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group)
+{
+    uint32 flags;
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+    /** - Read conversion flags */
+    flags = adc->GxINTFLG[group] & 8U;
+
+    /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+    return flags;
+}
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+/** @fn void adcCalibration(adcBASE_t *adc)
+*   @brief Computes offset error using Calibration mode
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   This function computes offset error using Calibration mode
+*
+*/
+/* SourceId : ADC_SourceId_008 */
+/* DesignId : ADC_DesignId_010 */
+/* Requirements : HL_SR194 */
+void adcCalibration(adcBASE_t *adc)
+{
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+    
+	uint32 conv_val[5U]={0U,0U,0U,0U,0U};
+	uint32 loop_index=0U;
+	uint32 offset_error=0U;
+	uint32 backup_mode;
+	
+	/** - Backup Mode before Calibration  */
+	backup_mode = adc->OPMODECR;
+	
+	/** - Enable 12-BIT ADC  */
+	adc->OPMODECR |= 0x80000000U;
+
+	/* Disable all channels for conversion */
+	adc->GxSEL[0U]=0x00U;
+	adc->GxSEL[1U]=0x00U;
+	adc->GxSEL[2U]=0x00U;
+
+	for(loop_index=0U;loop_index<4U;loop_index++)
+	{
+		/* Disable Self Test and Calibration mode */
+		adc->CALCR=0x0U;
+	
+		switch(loop_index)
+		{
+			case 0U : 	/* Test 1 : Bride En = 0 , HiLo =0 */
+						adc->CALCR=0x0U;
+						break;
+
+			case 1U :	/* Test 1 : Bride En = 0 , HiLo =1 */
+						adc->CALCR=0x0100U;
+						break;
+
+			case 2U : 	/* Test 1 : Bride En = 1 , HiLo =0 */
+						adc->CALCR=0x0200U;
+						break;
+		
+			case 3U : 	/* Test 1 : Bride En = 1 , HiLo =1 */
+						adc->CALCR=0x0300U;
+						break;
+			default :
+			            break;
+		}
+	
+		/* Enable Calibration mode */
+		adc->CALCR|=0x1U;
+	
+		/* Start calibration conversion */
+		adc->CALCR|=0x00010000U;
+
+		/* Wait for calibration conversion to complete */
+		/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+		while((adc->CALCR & 0x00010000U)==0x00010000U)
+	    { 
+	    } /* Wait */
+
+		/* Read converted value */
+		conv_val[loop_index]= adc->CALR;
+	}
+
+	/* Disable Self Test and Calibration mode */
+	adc->CALCR=0x0U;
+
+	/* Compute the Offset error correction value */
+	conv_val[4U]=conv_val[0U]+ conv_val[1U] + conv_val[2U] + conv_val[3U];
+
+	conv_val[4U]=(conv_val[4U]/4U);
+
+	offset_error=conv_val[4U]-0x7FFU;
+
+	/*Write the offset error to the Calibration register */
+	/* Load 2;s complement of the computed value to ADCALR register */
+	offset_error=~offset_error;
+	offset_error=offset_error & 0xFFFU;
+	offset_error=offset_error+1U;
+
+	adc->CALR = offset_error;
+
+  /** - Restore Mode after Calibration  */
+	adc->OPMODECR = backup_mode;
+	
+ /**   @note The function adcInit has to be called before using this function. */
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+}
+
+
+/** @fn void adcMidPointCalibration(adcBASE_t *adc)
+*   @brief Computes offset error using Mid Point Calibration mode
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*	@return This function will return offset error using Mid Point Calibration mode
+*
+*   This function computes offset error using Mid Point Calibration mode
+*
+*/
+/* SourceId : ADC_SourceId_009 */
+/* DesignId : ADC_DesignId_011 */
+/* Requirements : HL_SR195 */
+uint32 adcMidPointCalibration(adcBASE_t *adc)
+{
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+    
+	uint32 conv_val[3U]={0U,0U,0U};
+	uint32 loop_index=0U;
+	uint32 offset_error=0U;
+	uint32 backup_mode;
+	
+	/** - Backup Mode before Calibration  */
+	backup_mode = adc->OPMODECR;
+	
+	/** - Enable 12-BIT ADC  */
+	adc->OPMODECR |= 0x80000000U;
+
+	/* Disable all channels for conversion */
+	adc->GxSEL[0U]=0x00U;
+	adc->GxSEL[1U]=0x00U;
+	adc->GxSEL[2U]=0x00U;
+
+	for(loop_index=0U;loop_index<2U;loop_index++)
+	{
+		/* Disable Self Test and Calibration mode */
+		adc->CALCR=0x0U;
+	
+		switch(loop_index)
+		{
+			case 0U : 	/* Test 1 : Bride En = 0 , HiLo =0 */
+						adc->CALCR=0x0U;
+						break;
+
+			case 1U :	/* Test 1 : Bride En = 0 , HiLo =1 */
+						adc->CALCR=0x0100U;
+						break;
+
+			default :
+			            break;						
+
+		}
+	
+		/* Enable Calibration mode */
+		adc->CALCR|=0x1U;
+	
+		/* Start calibration conversion */
+		adc->CALCR|=0x00010000U;
+
+		/* Wait for calibration conversion to complete */
+		/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+		while((adc->CALCR & 0x00010000U)==0x00010000U)
+	    { 
+	    } /* Wait */
+
+		/* Read converted value */
+		conv_val[loop_index]= adc->CALR;
+	}
+
+	/* Disable Self Test and Calibration mode */
+	adc->CALCR=0x0U;
+
+	/* Compute the Offset error correction value */
+	conv_val[2U]=(conv_val[0U])+ (conv_val[1U]);
+
+	conv_val[2U]=(conv_val[2U]/2U);
+
+	offset_error=conv_val[2U]-0x7FFU;
+
+	/* Write the offset error to the Calibration register           */
+	/* Load 2's complement of the computed value to ADCALR register */
+	offset_error=~offset_error;
+	offset_error=offset_error+1U;
+	offset_error=offset_error & 0xFFFU;
+
+	adc->CALR = offset_error;
+
+  /** - Restore Mode after Calibration  */
+	adc->OPMODECR = backup_mode;
+	
+	return(offset_error);
+
+ /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+/** @fn void adcEnableNotification(adcBASE_t *adc, uint32 group)
+*   @brief Enable notification
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   This function will enable the notification of a conversion.
+*   In single conversion mode for conversion complete and
+*   in continuous conversion mode when the FiFo buffer is full.
+*
+*/
+/* SourceId : ADC_SourceId_010 */
+/* DesignId : ADC_DesignId_008 */
+/* Requirements : HL_SR192 */
+void adcEnableNotification(adcBASE_t *adc, uint32 group)
+{
+    uint32 notif = (((uint32)(adc->GxMODECR[group]) & 2U) == 2U) ? 1U : 8U;
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+    adc->GxINTENA[group] = notif;
+
+    /**   @note The function adcInit has to be called before this function can be used.\n
+    *           This function should be called before the conversion is started
+    */
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+
+/** @fn void adcDisableNotification(adcBASE_t *adc, uint32 group)
+*   @brief Disable notification
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   This function will disable the notification of a conversion.
+*/
+/* SourceId : ADC_SourceId_011 */
+/* DesignId : ADC_DesignId_009 */
+/* Requirements : HL_SR193 */
+void adcDisableNotification(adcBASE_t *adc, uint32 group)
+{
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+    adc->GxINTENA[group] = 0U;
+
+    /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+}
+
+/** @fn void adcSetEVTPin(adcBASE_t *adc, uint32 value)
+*   @brief Set ADCEVT pin
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*   @param[in] value Value to be set: 0 or 1
+*
+*   This function will set the ADC EVT pin if configured as an output pin.
+*/
+/* SourceId : ADC_SourceId_020 */
+/* DesignId : ADC_DesignId_014 */
+/* Requirements : HL_SR529 */
+void adcSetEVTPin(adcBASE_t *adc, uint32 value)
+{
+    adc->EVTOUT = value;
+}
+
+/** @fn uint32 adcGetEVTPin(adcBASE_t *adc)
+*   @brief Set ADCEVT pin
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*   @return Value of the ADC EVT pin: 0 or 1
+*
+*   This function will return the value of ADC EVT pin.
+*/
+/* SourceId : ADC_SourceId_021 */
+/* DesignId : ADC_DesignId_015 */
+/* Requirements : HL_SR529 */
+uint32 adcGetEVTPin(adcBASE_t *adc)
+{
+    return adc->EVTIN;
+}
+
+/** @fn void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current 
+*                           value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') 
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ADC_SourceId_012 */
+/* DesignId : ADC_DesignId_012 */
+/* Requirements : HL_SR203 */
+void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+        config_reg->CONFIG_OPMODECR = ADC1_OPMODECR_CONFIGVALUE;
+        config_reg->CONFIG_CLOCKCR = ADC1_CLOCKCR_CONFIGVALUE;
+        config_reg->CONFIG_GxMODECR[0U] = ADC1_G0MODECR_CONFIGVALUE;
+        config_reg->CONFIG_GxMODECR[1U] = ADC1_G1MODECR_CONFIGVALUE;
+        config_reg->CONFIG_GxMODECR[2U] = ADC1_G2MODECR_CONFIGVALUE;
+        config_reg->CONFIG_G0SRC = ADC1_G0SRC_CONFIGVALUE;
+        config_reg->CONFIG_G1SRC = ADC1_G1SRC_CONFIGVALUE;
+        config_reg->CONFIG_G2SRC = ADC1_G2SRC_CONFIGVALUE;
+        config_reg->CONFIG_BNDCR = ADC1_BNDCR_CONFIGVALUE;
+        config_reg->CONFIG_BNDEND = ADC1_BNDEND_CONFIGVALUE;
+        config_reg->CONFIG_G0SAMP = ADC1_G0SAMP_CONFIGVALUE;
+        config_reg->CONFIG_G1SAMP = ADC1_G1SAMP_CONFIGVALUE;
+        config_reg->CONFIG_G2SAMP = ADC1_G2SAMP_CONFIGVALUE;
+        config_reg->CONFIG_G0SAMPDISEN = ADC1_G0SAMPDISEN_CONFIGVALUE;
+        config_reg->CONFIG_G1SAMPDISEN = ADC1_G1SAMPDISEN_CONFIGVALUE;
+        config_reg->CONFIG_G2SAMPDISEN = ADC1_G2SAMPDISEN_CONFIGVALUE;
+        config_reg->CONFIG_PARCR = ADC1_PARCR_CONFIGVALUE;
+	}
+	else
+	{
+        config_reg->CONFIG_OPMODECR = adcREG1->OPMODECR;
+        config_reg->CONFIG_CLOCKCR = adcREG1->CLOCKCR;
+        config_reg->CONFIG_GxMODECR[0U] = adcREG1->GxMODECR[0U];
+        config_reg->CONFIG_GxMODECR[1U] = adcREG1->GxMODECR[1U];
+        config_reg->CONFIG_GxMODECR[2U] = adcREG1->GxMODECR[2U];
+        config_reg->CONFIG_G0SRC = adcREG1->EVSRC;
+        config_reg->CONFIG_G1SRC = adcREG1->G1SRC;
+        config_reg->CONFIG_G2SRC = adcREG1->G2SRC;
+        config_reg->CONFIG_BNDCR = adcREG1->BNDCR;
+        config_reg->CONFIG_BNDEND = adcREG1->BNDEND;
+        config_reg->CONFIG_G0SAMP = adcREG1->EVSAMP;
+        config_reg->CONFIG_G1SAMP = adcREG1->G1SAMP;
+        config_reg->CONFIG_G2SAMP = adcREG1->G2SAMP;
+        config_reg->CONFIG_G0SAMPDISEN = adcREG1->EVSAMPDISEN;
+        config_reg->CONFIG_G1SAMPDISEN = adcREG1->G1SAMPDISEN;
+        config_reg->CONFIG_G2SAMPDISEN = adcREG1->G2SAMPDISEN;
+        config_reg->CONFIG_PARCR = adcREG1->PARCR;
+	}
+}
+
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+
+
+
+
+
diff --git a/src/arch/rm46l8lp/halcogen/dabort.asm b/src/arch/rm46l8lp/halcogen/dabort.asm
new file mode 100644
index 0000000..89a4b8c
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/dabort.asm
@@ -0,0 +1,146 @@
+;-------------------------------------------------------------------------------
+; dabort.asm
+;
+; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+; 
+; 
+;  Redistribution and use in source and binary forms, with or without 
+;  modification, are permitted provided that the following conditions 
+;  are met:
+;
+;    Redistributions of source code must retain the above copyright 
+;    notice, this list of conditions and the following disclaimer.
+;
+;    Redistributions in binary form must reproduce the above copyright
+;    notice, this list of conditions and the following disclaimer in the 
+;    documentation and/or other materials provided with the   
+;    distribution.
+;
+;    Neither the name of Texas Instruments Incorporated nor the names of
+;    its contributors may be used to endorse or promote products derived
+;    from this software without specific prior written permission.
+;
+;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;
+;
+
+    .text
+    .arm
+
+
+;-------------------------------------------------------------------------------
+; Run Memory Test
+
+    .ref	custom_dabort
+    .def	_dabort
+    .asmfunc
+
+_dabort
+		stmfd	r13!, {r0 - r12, lr}; push registers and link register on to stack
+
+        ldr		r12, esmsr3			; ESM Group3 status register
+        ldr		r0,  [r12]
+        tst		r0,  #0x8			; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM
+        bne		ramErrorFound
+        tst		r0, #0x20			; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM
+        bne		ramErrorFound2
+
+noRAMerror
+		tst		r0, #0x80			; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM
+		bne		flashErrorFound
+
+		bl		custom_dabort		; custom data abort handler required
+									; If this custom handler is written in assembly, all registers used in the routine
+									; and the link register must be saved on to the stack upon entry, and restored before
+									; return from the routine.
+
+		ldmfd	r13!, {r0 - r12, lr}; pop registers and link register from stack
+		subs	pc, lr, #8			; restore state of CPU when abort occurred, and branch back to instruction that was aborted
+
+ramErrorFound
+		ldr		r1, ramctrl			; RAM control register for B0TCM TCRAMW
+		ldr		r2, [r1]
+		tst		r2, #0x100			; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled
+		beq		ramErrorReal
+		mov		r2, #0x20
+		str		r2, [r1, #0x10]		; clear RAM error status register
+
+		mov		r2, #0x08
+		str		r2, [r12]			; clear ESM group3 channel3 flag for uncorrectable RAM ECC errors
+		mov		r2, #5
+		str		r2, [r12, #0x18]	; The nERROR pin will become inactive once the LTC counter expires
+
+		ldmfd	r13!, {r0 - r12, lr}
+		subs	pc, lr, #4			; branch to instruction after the one that caused the abort
+									; this is the case because the data abort was caused intentionally
+									; and we do not want to cause the same data abort again.
+
+ramErrorFound2
+		ldr		r1, ram2ctrl		; RAM control register for B1TCM TCRAMW
+		ldr		r2, [r1]
+		tst		r2, #0x100			; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled
+		beq		ramErrorReal
+		mov		r2, #0x20
+		str		r2, [r1, #0x10]		; clear RAM error status register
+
+		mov		r2, #0x20
+		str		r2, [r12]			; clear ESM group3 flags channel5 flag for uncorrectable RAM ECC errors
+		mov		r2, #5
+		str		r2, [r12, #0x18]	; The nERROR pin will become inactive once the LTC counter expires
+
+		ldmfd	r13!, {r0 - r12, lr}
+		subs	pc, lr, #4			; branch to instruction after the one that caused the abort
+									; this is the case because the data abort was caused intentionally
+									; and we do not want to cause the same data abort again.
+
+
+ramErrorReal
+		b		ramErrorReal		; branch here forever as continuing operation is not recommended
+
+flashErrorFound
+		ldr		r1, flashbase
+		ldr		r2, [r1, #0x6C]		; read FDIAGCTRL register
+
+		mov     r2, r2, lsr #16
+		tst		r2, #5				; check if bits 19:16 are 5, this indicates diagnostic mode is enabled
+		beq		flashErrorReal
+		mov		r2, #1
+		mov     r2, r2, lsl #8		
+		
+		str		r2, [r1, #0x1C]		; clear FEDACSTATUS error flag
+
+		mov		r2, #0x80
+		str		r2, [r12]			; clear ESM group3 flag for uncorrectable flash ECC error
+;		mov		r2, #5
+;		str		r2, [r12, #0x18]	; The nERROR pin will become inactive once the LTC counter expires
+
+		ldmfd	r13!, {r0 - r12, lr}
+		subs	pc, lr, #4			; branch to instruction after the one that caused the abort
+									; this is the case because the data abort was caused intentionally
+									; and we do not want to cause the same data abort again.
+
+
+flashErrorReal
+		b		flashErrorReal		; branch here forever as continuing operation is not recommended
+		
+esmsr3		.word	0xFFFFF520
+ramctrl		.word	0xFFFFF800
+ram2ctrl	.word	0xFFFFF900
+ram1errstat	.word	0xFFFFF810
+ram2errstat	.word	0xFFFFF910
+flashbase	.word	0xFFF87000
+
+    .endasmfunc
+	
+	
diff --git a/src/arch/rm46l8lp/halcogen/errata_SSWF021_45.c b/src/arch/rm46l8lp/halcogen/errata_SSWF021_45.c
new file mode 100644
index 0000000..36ff1ab
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/errata_SSWF021_45.c
@@ -0,0 +1,358 @@
+/** @file errata_SSWF021_45.c 
+*   @brief errata for PLLs 
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+#include "errata_SSWF021_45_defs.h"
+#include "errata_SSWF021_45.h"
+
+static uint32 check_frequency(uint32 cnt1_clksrc);
+static uint32 disable_plls(uint32 plls);
+
+/** @fn uint32 _errata_SSWF021_45_both_plls(uint32 count)
+*   @brief This handles the errata for PLL1 and PLL2. This function is called in device startup
+*   
+*   @param[in] count : Number of retries until both PLLs are locked successfully
+*                      Minimum value recommended is 5
+*   
+*   @return 0 = Success (the PLL or both PLLs have successfully locked and then been disabled)
+*           1 = PLL1 failed to successfully lock in "count" tries
+*           2 = PLL2 failed to successfully lock in "count" tries
+*           3 = Neither PLL1 nor PLL2 successfully locked in "count" tries
+*           4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason
+                is that a PLL is already being used as a clock source. This can be caused by the workaround function
+                being called from the wrong place in the code.
+*/
+uint32 _errata_SSWF021_45_both_plls(uint32 count)
+{
+    uint32 failCode,retries,clkCntlSav;
+	/* save CLKCNTL */
+    clkCntlSav = systemREG1->CLKCNTL;
+    /* First set VCLK2 = HCLK */ 
+    systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U;
+    /* Now set VCLK = HCLK and enable peripherals */
+    systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA;
+	failCode = 0U;
+    for(retries = 0U;(retries < count);retries++)
+    {
+        failCode = 0U;
+        /* Disable PLL1 and PLL2 */
+		failCode = disable_plls(SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2); 
+        if(failCode != 0U)
+        {
+            break;
+        }
+
+        /* Clear Global Status Register */
+        systemREG1->GBLSTAT = 0x00000301U;
+        /* Clear the ESM PLL slip flags */
+        esmREG->SR1[0U] = ESM_SR1_PLL1SLIP;
+        esmREG->SR4[0U] = ESM_SR4_PLL2SLIP;
+        /* set both PLLs to OSCIN/1*27/(2*1) */
+        systemREG1->PLLCTL1 = 0x20001A00U;
+        systemREG1->PLLCTL2 = 0x3FC0723DU;
+        systemREG2->PLLCTL3 = 0x20001A00U;
+        systemREG1->CSDISCLR =    SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2;
+        /* Check for (PLL1 valid or PLL1 slip) and (PLL2 valid or PLL2 slip) */
+        while  ((((systemREG1->CSVSTAT & SYS_CLKSRC_PLL1) == 0U) && ((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) == 0U)) ||
+                (((systemREG1->CSVSTAT & SYS_CLKSRC_PLL2) == 0U) && ((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) == 0U)))
+        {
+            /* Wait */
+        }
+        /* If PLL1 valid, check the frequency */
+        if(((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U))
+        {
+          failCode |= 1U;
+        }
+        else
+        {
+            failCode |= check_frequency(dcc1CNT1_CLKSRC_PLL1);
+        }
+        /* If PLL2 valid, check the frequency */
+        if(((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U))
+        {
+          failCode |= 2U;
+        }
+        else
+        {
+            failCode |= (check_frequency(dcc1CNT1_CLKSRC_PLL2) << 1U);
+        }
+        if (failCode == 0U)
+        {
+            break;
+        }
+	}
+	/* To avoid MISRA violation 382S 
+	   (void)missing for discarded return value */	
+    failCode = disable_plls(SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2);
+	/* restore CLKCNTL, VCLKR and PENA first */
+    systemREG1->CLKCNTL = (clkCntlSav & 0x000F0100U);
+    /* restore CLKCNTL, VCLK2R */
+    systemREG1->CLKCNTL = clkCntlSav;
+    return failCode;
+}
+/** @fn uint32 _errata_SSWF021_45_pll1(uint32 count)
+*   @brief This handles the errata for PLL1. This function is called in device startup
+*   
+*   @param[in] count : Number of retries until both PLL1 is locked successfully
+*                      Minimum value recommended is 5
+*   
+*   @return 0 = Success (the PLL or both PLLs have successfully locked and then been disabled)
+*           1 = PLL1 failed to successfully lock in "count" tries
+*           2 = PLL2 failed to successfully lock in "count" tries
+*           3 = Neither PLL1 nor PLL2 successfully locked in "count" tries
+*           4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason
+                is that a PLL is already being used as a clock source. This can be caused by the workaround function
+                being called from the wrong place in the code.
+*/
+uint32 _errata_SSWF021_45_pll1(uint32 count)
+{
+    uint32 failCode,retries,clkCntlSav;
+	/* save CLKCNTL */
+    clkCntlSav = systemREG1->CLKCNTL;
+    /* First set VCLK2 = HCLK */ 
+    systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U;
+    /* Now set VCLK = HCLK and enable peripherals */
+    systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA;
+	failCode = 0U;
+    for(retries = 0U;(retries < count);retries++)
+    {
+        failCode = 0U;
+        /* Disable PLL1 */
+        failCode = disable_plls(SYS_CLKSRC_PLL1);
+        if(failCode != 0U)
+        {
+            break;
+        }
+
+        /* Clear Global Status Register */
+        systemREG1->GBLSTAT = 0x00000301U;
+        /* Clear the ESM PLL slip flags */
+        esmREG->SR1[0U] = ESM_SR1_PLL1SLIP;
+        /* set  PLL1 to OSCIN/1*27/(2*1) */
+        systemREG1->PLLCTL1 = 0x20001A00U;
+        systemREG1->PLLCTL2 = 0x3FC0723DU;
+        systemREG1->CSDISCLR =    SYS_CLKSRC_PLL1;
+        /* Check for PLL1 valid or PLL1 slip*/
+        while(((systemREG1->CSVSTAT & SYS_CLKSRC_PLL1) == 0U) && ((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) == 0U))
+        {
+            /* Wait */
+        }
+        /* If PLL1 valid, check the frequency */
+        if(((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U))
+        {
+          failCode |= 1U;
+        }
+        else
+        {
+            failCode |= check_frequency(dcc1CNT1_CLKSRC_PLL1);
+        }
+        if (failCode == 0U)
+        {
+            break;
+        }
+	}
+	/* To avoid MISRA violation 382S 
+	   (void)missing for discarded return value */	
+    failCode = disable_plls(SYS_CLKSRC_PLL1);
+	
+    /* restore CLKCNTL, VCLKR and PENA first */
+    systemREG1->CLKCNTL = (clkCntlSav & 0x000F0100U);
+    /* restore CLKCNTL, VCLK2R */
+    systemREG1->CLKCNTL = clkCntlSav;
+    return failCode;
+}
+/** @fn uint32 _errata_SSWF021_45_pll2(uint32 count)
+*   @brief This handles the errata for PLL2. This function is called in device startup
+*   
+*   @param[in] count : Number of retries until PLL2 is locked successfully
+*                      Minimum value recommended is 5
+*   
+*   @return 0 = Success (the PLL or both PLLs have successfully locked and then been disabled)
+*           1 = PLL1 failed to successfully lock in "count" tries
+*           2 = PLL2 failed to successfully lock in "count" tries
+*           3 = Neither PLL1 nor PLL2 successfully locked in "count" tries
+*           4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason
+                is that a PLL is already being used as a clock source. This can be caused by the workaround function
+                being called from the wrong place in the code.
+*/
+uint32 _errata_SSWF021_45_pll2(uint32 count)
+{
+    uint32 failCode,retries,clkCntlSav;
+	/* save CLKCNTL */
+    clkCntlSav = systemREG1->CLKCNTL;
+    /* First set VCLK2 = HCLK */ 
+    systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U;
+    /* Now set VCLK = HCLK and enable peripherals */
+    systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA;
+	failCode = 0U;
+    for(retries = 0U;(retries < count);retries++)
+    {
+        failCode = 0U;
+        /* Disable PLL2 */
+		failCode = disable_plls(SYS_CLKSRC_PLL2);
+        if(failCode != 0U)
+        {
+            break;
+        }
+
+        /* Clear Global Status Register */
+        systemREG1->GBLSTAT = 0x00000301U;
+        /* Clear the ESM PLL slip flags */
+        esmREG->SR4[0U] = ESM_SR4_PLL2SLIP;
+        /* set PLL2 to OSCIN/1*27/(2*1) */
+        systemREG2->PLLCTL3 = 0x20001A00U;
+        systemREG1->CSDISCLR = SYS_CLKSRC_PLL2;
+        /* Check for PLL2 valid or PLL2 slip */
+        while (((systemREG1->CSVSTAT & SYS_CLKSRC_PLL2) == 0U) && ((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) == 0U))
+        {
+            /* Wait */
+        }
+        /* If PLL2 valid, check the frequency */
+        if(((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U))
+        {
+          failCode |= 2U;
+        }
+        else
+        {
+            failCode |= (check_frequency(dcc1CNT1_CLKSRC_PLL2) << 1U);
+        }
+        if (failCode == 0U)
+        {
+            break;
+        }
+	}	
+	/* To avoid MISRA violation 382S 
+	   (void)missing for discarded return value */	
+    failCode = disable_plls(SYS_CLKSRC_PLL2);
+	/* restore CLKCNTL, VCLKR and PENA first */
+    systemREG1->CLKCNTL = (clkCntlSav & 0x000F0100U);
+    /* restore CLKCNTL, VCLK2R */
+    systemREG1->CLKCNTL = clkCntlSav;
+    return failCode;
+}
+/** @fn uint32 check_frequency(uint32 cnt1_clksrc)
+*   @brief This function checks for the PLL frequency.
+*   
+*   @param[in] cnt1_clksrc : Clock source for Counter1 
+*                            0U - PLL1      (clock source 0)
+*                            1U - PLL2      (clock source 1)
+*   
+*   @return   DCC Error status
+*             0 - DCC error has not occurred
+*             1 - DCC error has occurred
+*/
+static uint32 check_frequency(uint32 cnt1_clksrc)
+{
+    /* Setup DCC1 */
+   /** DCC1 Global Control register configuration */
+    dccREG1->GCTRL      = (uint32)0x5U |       /** Disable  DCC1 */
+                          (uint32)((uint32)0x5U << 4U) | /** No Error Interrupt */
+                          (uint32)((uint32)0xAU << 8U) | /** Single Shot mode */
+                          (uint32)((uint32)0x5U << 12U); /** No Done Interrupt */
+    /* Clear ERR and DONE bits */
+    dccREG1->STAT = 3U;
+    /** DCC1 Clock0 Counter Seed value configuration */
+    dccREG1->CNT0SEED   = 68U;
+    /** DCC1 Clock0 Valid Counter Seed value configuration */
+    dccREG1->VALID0SEED = 4U;
+    /** DCC1 Clock1 Counter Seed value configuration */
+    dccREG1->CNT1SEED   = 972U;
+    /** DCC1 Clock1 Source 1 Select */
+    dccREG1->CNT1CLKSRC = (uint32)((uint32)10U << 12U) |     /** DCC Enable / Disable Key */
+                          (uint32) cnt1_clksrc;  /** DCC1 Clock Source 1 */
+
+    dccREG1->CNT0CLKSRC = (uint32)DCC1_CNT0_OSCIN;  /** DCC1 Clock Source 0 */
+
+    /** DCC1 Global Control register configuration */
+    dccREG1->GCTRL      = (uint32)0xAU |       /** Enable  DCC1 */
+                          (uint32)((uint32)0x5U << 4U) | /** No Error Interrupt */
+                          (uint32)((uint32)0xAU << 8U) | /** Single Shot mode */
+                          (uint32)((uint32)0x5U << 12U); /** No Done Interrupt */
+    while(dccREG1->STAT == 0U)
+    {
+        /* Wait */
+    }
+    return (dccREG1->STAT & 0x01U);
+}
+/** @fn uint32 disable_plls(uint32 plls)
+*   @brief This function disables plls and clears the respective ESM flags.
+*   
+*   @param[in] plls : Clock source for Counter1 
+*                            2U - PLL1
+*                            40U - PLL2
+*   
+*   @return   failCode
+*             0 = Success (the PLL or both PLLs have successfully locked and then been disabled)
+*             4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason
+*                 is that a PLL is already being used as a clock source. This can be caused by the workaround function
+*                 being called from the wrong place in the code.
+*/
+static uint32 disable_plls(uint32 plls)
+{
+    uint32 timeout,failCode;
+	
+    systemREG1->CSDISSET = plls;
+	failCode = 0U;
+    timeout = 0x10U;
+	timeout --;
+    while(((systemREG1->CSVSTAT & (plls)) != 0U) && (timeout != 0U))
+    {
+        /* Clear ESM and GLBSTAT PLL slip flags */
+        systemREG1->GBLSTAT = 0x00000300U;
+
+        if ((plls & SYS_CLKSRC_PLL1) == SYS_CLKSRC_PLL1)
+        {
+            esmREG->SR1[0U] = ESM_SR1_PLL1SLIP;
+        }
+        if ((plls & SYS_CLKSRC_PLL2) == SYS_CLKSRC_PLL2)
+        {
+            esmREG->SR4[0U] = ESM_SR4_PLL2SLIP;
+        }
+		timeout --;
+    /* Wait */
+    }
+    if(timeout == 0U)
+    {
+        failCode = 4U;
+    }
+    else
+    {
+        failCode = 0U;
+    }
+    return failCode;
+}
diff --git a/src/arch/rm46l8lp/halcogen/esm.c b/src/arch/rm46l8lp/halcogen/esm.c
new file mode 100644
index 0000000..16c94cc
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/esm.c
@@ -0,0 +1,844 @@
+/** @file esm.c 
+*   @brief Esm Driver Source File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file contains:
+*   - API Functions
+*   .
+*   which are relevant for the Esm driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Include Files */
+
+#include "esm.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @fn void esmInit(void)
+*   @brief Initializes Esm Driver
+*
+*   This function initializes the Esm driver.
+*
+*/
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+/* SourceId : ESM_SourceId_001 */
+/* DesignId : ESM_DesignId_001 */
+/* Requirements : HL_SR4 */
+void esmInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+    /** - Disable error pin channels */
+    esmREG->DEPAPR1 = 0xFFFFFFFFU;
+    esmREG->IEPCR4 = 0xFFFFFFFFU;
+
+    /** - Disable interrupts */
+    esmREG->IECR1 = 0xFFFFFFFFU;
+    esmREG->IECR4 = 0xFFFFFFFFU;
+
+    /** - Clear error status flags */
+    esmREG->SR1[0U] = 0xFFFFFFFFU;
+    esmREG->SR1[1U] = 0xFFFFFFFFU;
+    esmREG->SSR2  = 0xFFFFFFFFU;
+    esmREG->SR1[2U] = 0xFFFFFFFFU;
+    esmREG->SR4[0U] = 0xFFFFFFFFU;
+
+    /** - Setup LPC preload */
+    esmREG->LTCPR = 16384U - 1U;
+
+    /** - Reset error pin */
+    if (esmREG->EPSR == 0U)
+    {
+        esmREG->EKR = 0x00000005U;
+    }
+    else
+    {
+        esmREG->EKR = 0x00000000U;
+    }
+
+    /** - Clear interrupt level */
+    esmREG->ILCR1 = 0xFFFFFFFFU;
+    esmREG->ILCR4 = 0xFFFFFFFFU;
+
+    /** - Set interrupt level */
+    esmREG->ILSR1 = (uint32)((uint32)0U << 31U)
+                  | (uint32)((uint32)0U << 30U)
+                  | (uint32)((uint32)0U << 29U)
+                  | (uint32)((uint32)0U << 28U)
+                  | (uint32)((uint32)0U << 27U)
+                  | (uint32)((uint32)0U << 26U)
+                  | (uint32)((uint32)0U << 25U)
+                  | (uint32)((uint32)0U << 24U)
+                  | (uint32)((uint32)0U << 23U)
+                  | (uint32)((uint32)0U << 22U)
+                  | (uint32)((uint32)0U << 21U)
+                  | (uint32)((uint32)0U << 20U)
+                  | (uint32)((uint32)0U << 19U)
+                  | (uint32)((uint32)0U << 18U)
+                  | (uint32)((uint32)0U << 17U)
+                  | (uint32)((uint32)0U << 16U)
+                  | (uint32)((uint32)0U << 15U)
+                  | (uint32)((uint32)0U << 14U)
+                  | (uint32)((uint32)0U << 13U)
+                  | (uint32)((uint32)0U << 12U)
+                  | (uint32)((uint32)0U << 11U)
+                  | (uint32)((uint32)0U << 10U)
+                  | (uint32)((uint32)0U <<  9U)
+                  | (uint32)((uint32)0U <<  8U)
+                  | (uint32)((uint32)0U <<  7U)
+                  | (uint32)((uint32)0U <<  6U)
+                  | (uint32)((uint32)0U <<  5U)
+                  | (uint32)((uint32)0U <<  4U)
+                  | (uint32)((uint32)0U <<  3U)
+                  | (uint32)((uint32)0U <<  2U)
+                  | (uint32)((uint32)0U <<  1U)
+                  | (uint32)((uint32)0U <<  0U);
+
+    esmREG->ILSR4 = (uint32)((uint32)0U << 31U)
+                  | (uint32)((uint32)0U << 30U)
+                  | (uint32)((uint32)0U << 29U)
+                  | (uint32)((uint32)0U << 28U)
+                  | (uint32)((uint32)0U << 27U)
+                  | (uint32)((uint32)0U << 26U)
+                  | (uint32)((uint32)0U << 25U)
+                  | (uint32)((uint32)0U << 24U)
+                  | (uint32)((uint32)0U << 23U)
+                  | (uint32)((uint32)0U << 22U)
+                  | (uint32)((uint32)0U << 21U)
+                  | (uint32)((uint32)0U << 20U)
+                  | (uint32)((uint32)0U << 19U)
+                  | (uint32)((uint32)0U << 18U)
+                  | (uint32)((uint32)0U << 17U)
+                  | (uint32)((uint32)0U << 16U)
+                  | (uint32)((uint32)0U << 15U)
+                  | (uint32)((uint32)0U << 14U)
+                  | (uint32)((uint32)0U << 13U)
+                  | (uint32)((uint32)0U << 12U)
+                  | (uint32)((uint32)0U << 11U)
+                  | (uint32)((uint32)0U << 10U)
+                  | (uint32)((uint32)0U <<  9U)
+                  | (uint32)((uint32)0U <<  8U)
+                  | (uint32)((uint32)0U <<  7U)
+                  | (uint32)((uint32)0U <<  6U)
+                  | (uint32)((uint32)0U <<  5U)
+                  | (uint32)((uint32)0U <<  4U)
+                  | (uint32)((uint32)0U <<  3U)
+                  | (uint32)((uint32)0U <<  2U)
+                  | (uint32)((uint32)0U <<  1U)
+                  | (uint32)((uint32)0U <<  0U);
+
+    /** - Enable error pin channels */
+    esmREG->EEPAPR1 = (uint32)((uint32)1U << 31U)
+                    | (uint32)((uint32)0U << 30U)
+                    | (uint32)((uint32)0U << 29U)
+                    | (uint32)((uint32)0U << 28U)
+                    | (uint32)((uint32)0U << 27U)
+                    | (uint32)((uint32)0U << 26U)
+                    | (uint32)((uint32)0U << 25U)
+                    | (uint32)((uint32)0U << 24U)
+                    | (uint32)((uint32)0U << 23U)
+                    | (uint32)((uint32)0U << 22U)
+                    | (uint32)((uint32)0U << 21U)
+                    | (uint32)((uint32)0U << 20U)
+                    | (uint32)((uint32)0U << 19U)
+                    | (uint32)((uint32)0U << 18U)
+                    | (uint32)((uint32)0U << 17U)
+                    | (uint32)((uint32)0U << 16U)
+                    | (uint32)((uint32)0U << 15U)
+                    | (uint32)((uint32)0U << 14U)
+                    | (uint32)((uint32)0U << 13U)
+                    | (uint32)((uint32)0U << 12U)
+                    | (uint32)((uint32)1U << 11U)
+                    | (uint32)((uint32)1U << 10U)
+                    | (uint32)((uint32)0U <<  9U)
+                    | (uint32)((uint32)0U <<  8U)
+                    | (uint32)((uint32)0U <<  7U)
+                    | (uint32)((uint32)0U <<  6U)
+                    | (uint32)((uint32)0U <<  5U)
+                    | (uint32)((uint32)0U <<  4U)
+                    | (uint32)((uint32)0U <<  3U)
+                    | (uint32)((uint32)0U <<  2U)
+                    | (uint32)((uint32)0U <<  1U)
+                    | (uint32)((uint32)0U <<  0U);
+
+    esmREG->IEPSR4 = (uint32)((uint32)0U << 31U)
+                   | (uint32)((uint32)0U << 30U)
+                   | (uint32)((uint32)0U << 29U)
+                   | (uint32)((uint32)0U << 28U)
+                   | (uint32)((uint32)0U << 27U)
+                   | (uint32)((uint32)0U << 26U)
+                   | (uint32)((uint32)0U << 25U)
+                   | (uint32)((uint32)0U << 24U)
+                   | (uint32)((uint32)0U << 23U)
+                   | (uint32)((uint32)0U << 22U)
+                   | (uint32)((uint32)0U << 21U)
+                   | (uint32)((uint32)0U << 20U)
+                   | (uint32)((uint32)0U << 19U)
+                   | (uint32)((uint32)0U << 18U)
+                   | (uint32)((uint32)0U << 17U)
+                   | (uint32)((uint32)0U << 16U)
+                   | (uint32)((uint32)0U << 15U)
+                   | (uint32)((uint32)0U << 14U)
+                   | (uint32)((uint32)0U << 13U)
+                   | (uint32)((uint32)0U << 12U)
+                   | (uint32)((uint32)0U << 11U)
+                   | (uint32)((uint32)0U << 10U)
+                   | (uint32)((uint32)0U <<  9U)
+                   | (uint32)((uint32)0U <<  8U)
+                   | (uint32)((uint32)0U <<  7U)
+                   | (uint32)((uint32)0U <<  6U)
+                   | (uint32)((uint32)0U <<  5U)
+                   | (uint32)((uint32)0U <<  4U)
+                   | (uint32)((uint32)0U <<  3U)
+                   | (uint32)((uint32)0U <<  2U)
+                   | (uint32)((uint32)0U <<  1U)
+                   | (uint32)((uint32)0U <<  0U);
+
+    /** - Enable interrupts */
+    esmREG->IESR1 = (uint32)((uint32)1U << 31U)
+                  | (uint32)((uint32)0U << 30U)
+                  | (uint32)((uint32)0U << 29U)
+                  | (uint32)((uint32)1U << 28U)
+                  | (uint32)((uint32)1U << 27U)
+                  | (uint32)((uint32)1U << 26U)
+                  | (uint32)((uint32)0U << 25U)
+                  | (uint32)((uint32)0U << 24U)
+                  | (uint32)((uint32)0U << 23U)
+                  | (uint32)((uint32)0U << 22U)
+                  | (uint32)((uint32)0U << 21U)
+                  | (uint32)((uint32)0U << 20U)
+                  | (uint32)((uint32)0U << 19U)
+                  | (uint32)((uint32)0U << 18U)
+                  | (uint32)((uint32)0U << 17U)
+                  | (uint32)((uint32)0U << 16U)
+                  | (uint32)((uint32)0U << 15U)
+                  | (uint32)((uint32)0U << 14U)
+                  | (uint32)((uint32)0U << 13U)
+                  | (uint32)((uint32)0U << 12U)
+                  | (uint32)((uint32)1U << 11U)
+                  | (uint32)((uint32)1U << 10U)
+                  | (uint32)((uint32)0U <<  9U)
+                  | (uint32)((uint32)0U <<  8U)
+                  | (uint32)((uint32)0U <<  7U)
+                  | (uint32)((uint32)1U <<  6U)
+                  | (uint32)((uint32)0U <<  5U)
+                  | (uint32)((uint32)0U <<  4U)
+                  | (uint32)((uint32)0U <<  3U)
+                  | (uint32)((uint32)0U <<  2U)
+                  | (uint32)((uint32)0U <<  1U)
+                  | (uint32)((uint32)0U <<  0U);
+
+    esmREG->IESR4 = (uint32)((uint32)0U << 31U)
+                  | (uint32)((uint32)0U << 30U)
+                  | (uint32)((uint32)0U << 29U)
+                  | (uint32)((uint32)0U << 28U)
+                  | (uint32)((uint32)0U << 27U)
+                  | (uint32)((uint32)0U << 26U)
+                  | (uint32)((uint32)0U << 25U)
+                  | (uint32)((uint32)0U << 24U)
+                  | (uint32)((uint32)0U << 23U)
+                  | (uint32)((uint32)0U << 22U)
+                  | (uint32)((uint32)0U << 21U)
+                  | (uint32)((uint32)0U << 20U)
+                  | (uint32)((uint32)0U << 19U)
+                  | (uint32)((uint32)0U << 18U)
+                  | (uint32)((uint32)0U << 17U)
+                  | (uint32)((uint32)0U << 16U)
+                  | (uint32)((uint32)0U << 15U)
+                  | (uint32)((uint32)0U << 14U)
+                  | (uint32)((uint32)0U << 13U)
+                  | (uint32)((uint32)0U << 12U)
+                  | (uint32)((uint32)0U << 11U)
+                  | (uint32)((uint32)1U << 10U)
+                  | (uint32)((uint32)1U <<  9U)
+                  | (uint32)((uint32)1U <<  8U)
+                  | (uint32)((uint32)0U <<  7U)
+                  | (uint32)((uint32)0U <<  6U)
+                  | (uint32)((uint32)0U <<  5U)
+                  | (uint32)((uint32)0U <<  4U)
+                  | (uint32)((uint32)0U <<  3U)
+                  | (uint32)((uint32)0U <<  2U)
+                  | (uint32)((uint32)0U <<  1U)
+                  | (uint32)((uint32)0U <<  0U);
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+
+/** @fn uint32 esmError(void)
+*   @brief Return Error status
+*
+*   @return The error status
+*
+*   Returns the error status.
+*/
+/* SourceId : ESM_SourceId_002 */
+/* DesignId : ESM_DesignId_002 */
+/* Requirements : HL_SR5 */
+uint32 esmError(void)
+{
+    uint32 status;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+    status = esmREG->EPSR;
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+    return status;
+}
+
+
+/** @fn void esmEnableError(uint64 channels)
+*   @brief Enable Group 1 Channels Error Signals propagation
+*
+*   @param[in] channels - Channel mask
+*
+*   Enable Group 1 Channels Error Signals propagation to the error pin.
+*/
+/* SourceId : ESM_SourceId_003 */
+/* DesignId : ESM_DesignId_003 */
+/* Requirements : HL_SR6 */
+void esmEnableError(uint64 channels)
+{
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+    esmREG->IEPSR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+    esmREG->EEPAPR1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmDisableError(uint64 channels)
+*   @brief Disable Group 1 Channels Error Signals propagation
+*
+*   @param[in] channels - Channel mask
+*
+*   Disable Group 1 Channels Error Signals propagation to the error pin.
+*/
+/* SourceId : ESM_SourceId_004 */
+/* DesignId : ESM_DesignId_004 */
+/* Requirements : HL_SR7 */
+void esmDisableError(uint64 channels)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+    esmREG->IEPCR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+    esmREG->DEPAPR1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmTriggerErrorPinReset(void)
+*   @brief Trigger error pin reset and switch back to normal operation
+*
+*   Trigger error pin reset and switch back to normal operation.
+*/
+/* SourceId : ESM_SourceId_005 */
+/* DesignId : ESM_DesignId_005 */
+/* Requirements : HL_SR8 */
+void esmTriggerErrorPinReset(void)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+    esmREG->EKR = 5U;
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmActivateNormalOperation(void)
+*   @brief Activate normal operation
+*
+*   Activates normal operation mode.
+*/
+/* SourceId : ESM_SourceId_006 */
+/* DesignId : ESM_DesignId_006 */
+/* Requirements : HL_SR9 */
+void esmActivateNormalOperation(void)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+    esmREG->EKR = 0U;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmEnableInterrupt(uint64 channels)
+*   @brief Enable Group 1 Channels Interrupts
+*
+*   @param[in] channels - Channel mask
+*
+*   Enable Group 1 Channels Interrupts.
+*/
+/* SourceId : ESM_SourceId_007 */
+/* DesignId : ESM_DesignId_007 */
+/* Requirements : HL_SR10 */
+void esmEnableInterrupt(uint64 channels)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+    esmREG->IESR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+    esmREG->IESR1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmDisableInterrupt(uint64 channels)
+*   @brief Disable Group 1 Channels Interrupts
+*
+*   @param[in] channels - Channel mask
+*
+*   Disable Group 1 Channels Interrupts.
+*/
+/* SourceId : ESM_SourceId_008 */
+/* DesignId : ESM_DesignId_008 */
+/* Requirements : HL_SR11 */
+void esmDisableInterrupt(uint64 channels)
+{
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+    esmREG->IECR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+    esmREG->IECR1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags)
+*   @brief Set Group 1 Channels Interrupt Levels
+*
+*   @param[in] channels - Channel mask
+*   @param[in] flags - Level mask: - 0: Low priority interrupt
+*                                  - 1: High priority interrupt
+*
+*   Set Group 1 Channels Interrupts levels.
+*/
+/* SourceId : ESM_SourceId_009 */
+/* DesignId : ESM_DesignId_009 */
+/* Requirements : HL_SR12 */
+void esmSetInterruptLevel(uint64 channels, uint64 flags)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+    esmREG->ILCR4 = (uint32)(((channels & (~flags)) >> 32U) & 0xFFFFFFFFU);
+    esmREG->ILSR4 = (uint32)(((channels & flags) >> 32U) & 0xFFFFFFFFU);
+    esmREG->ILCR1 = (uint32)((channels & (~flags)) & 0xFFFFFFFFU);
+    esmREG->ILSR1 = (uint32)((channels & flags) & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmClearStatus(uint32 group, uint64 channels)
+*   @brief Clear Group error status
+*
+*   @param[in] group    - Error group
+*   @param[in] channels - Channel mask
+*
+*   Clear Group error status.
+*/
+/* SourceId : ESM_SourceId_010 */
+/* DesignId : ESM_DesignId_010 */
+/* Requirements : HL_SR13 */
+void esmClearStatus(uint32 group, uint64 channels)
+{
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+    esmREG->SR1[group] = (uint32)(channels & 0xFFFFFFFFU);
+	if(group == 0U)
+	{
+	    esmREG->SR4[group] = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+	}
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmClearStatusBuffer(uint64 channels)
+*   @brief Clear Group 2 error status buffer
+*
+*   @param[in] channels - Channel mask
+*
+*   Clear Group 2 error status buffer.
+*/
+/* SourceId : ESM_SourceId_011 */
+/* DesignId : ESM_DesignId_011 */
+/* Requirements : HL_SR14 */
+void esmClearStatusBuffer(uint64 channels)
+{
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+    esmREG->SSR2 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmSetCounterPreloadValue(uint32 value)
+*   @brief Set counter preload value
+*
+*   @param[in] value - Counter preload value
+*
+*   Set counter preload value.
+*/
+/* SourceId : ESM_SourceId_012 */
+/* DesignId : ESM_DesignId_012 */
+/* Requirements : HL_SR15 */
+void esmSetCounterPreloadValue(uint32 value)
+{
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+    esmREG->LTCPR = value & 0xC000U;
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+}
+
+
+/** @fn uint64 esmGetStatus(uint32 group, uint64 channels)
+*   @brief Return Error status
+*
+*   @param[in] group   - Error group
+*   @param[in] channels - Error Channels
+*
+*   @return The channels status of selected group
+*
+*   Returns the channels status of selected group.
+*/
+/* SourceId : ESM_SourceId_013 */
+/* DesignId : ESM_DesignId_013 */
+/* Requirements : HL_SR16 */
+uint64 esmGetStatus(uint32 group, uint64 channels)
+{
+    uint64 status;
+	uint32 ESM_ESTATUS4, ESM_ESTATUS1;
+	if(group == 0U)
+	{
+		ESM_ESTATUS4 = esmREG->SR4[group];
+	}
+	else
+	{
+		ESM_ESTATUS4 = 0U;
+	}
+	ESM_ESTATUS1 = esmREG->SR1[group];
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+    status = (((uint64)(ESM_ESTATUS4) << 32U) | (uint64)ESM_ESTATUS1) & channels;
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+    return status;
+}
+
+
+/** @fn uint64 esmGetStatusBuffer(uint64 channels)
+*   @brief Return Group 2 channel x Error status buffer
+*
+*   @param[in] channels - Error Channels
+*
+*   @return The channels status
+*
+*   Returns the group 2 buffered status of selected channels.
+*/
+/* SourceId : ESM_SourceId_014 */
+/* DesignId : ESM_DesignId_014 */
+/* Requirements : HL_SR17 */
+uint64 esmGetStatusBuffer(uint64 channels)
+{
+    uint64 status;
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+    status = ((uint64)esmREG->SSR2) & channels;
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+    return status;
+}
+
+/** @fn esmSelfTestFlag_t esmEnterSelfTest(void)
+*   @brief Return ESM Self test status
+*
+*   @return ESM Self test status
+*
+*   Returns the ESM Self test status.
+*/
+/* SourceId : ESM_SourceId_015 */
+/* DesignId : ESM_DesignId_015 */
+/* Requirements : HL_SR19 */
+esmSelfTestFlag_t esmEnterSelfTest(void)
+{
+    esmSelfTestFlag_t status;
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+	uint32 errPinStat = esmREG->EPSR & 0x1U;
+	uint32 esmKeyReg  = esmREG->EKR;
+	if((errPinStat == 0x0U) && (esmKeyReg == 0x0U))
+	{
+	  status = esmSelfTest_NotStarted;
+	}
+	else
+	{
+	  esmREG->EKR = 0xAU;
+	  status = esmSelfTest_Active;
+	  if((esmREG->EPSR & 0x1U) != 0x0U)
+	  {
+	    status = esmSelfTest_Failed;
+	  }
+	  esmREG->EKR = 0x5U;
+	}
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+	return status;
+}
+
+/** @fn esmSelfTestFlag_t esmSelfTestStatus(void)
+*   @brief Return ESM Self test status
+*
+*   Returns the ESM Self test status.
+*/
+/* SourceId : ESM_SourceId_016 */
+/* DesignId : ESM_DesignId_016 */
+/* Requirements : HL_SR18 */
+esmSelfTestFlag_t esmSelfTestStatus(void)
+{
+    esmSelfTestFlag_t status;
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+	if((esmREG->EPSR & 0x1U) == 0x0U) 
+	{
+	  if(esmREG->EKR == 0x5U)
+	  { 
+	    status = esmSelfTest_Active;
+	  }
+	  else
+	  {
+	    status = esmSelfTest_Failed;
+	  }
+	}
+	else
+	{
+	    status = esmSelfTest_Passed;
+	}
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+
+	return status;
+}
+
+/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current 
+*                           value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') 
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ESM_SourceId_017 */
+/* DesignId : ESM_DesignId_017 */
+/* Requirements : HL_SR20, HL_SR24 */
+void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_EEPAPR1 = ESM_EEPAPR1_CONFIGVALUE;
+		config_reg->CONFIG_IESR1 = ESM_IESR1_CONFIGVALUE;
+		config_reg->CONFIG_ILSR1 = ESM_ILSR1_CONFIGVALUE;
+		config_reg->CONFIG_LTCPR = ESM_LTCPR_CONFIGVALUE;
+		config_reg->CONFIG_EKR = ESM_EKR_CONFIGVALUE;  
+		config_reg->CONFIG_IEPSR4 = ESM_IEPSR4_CONFIGVALUE;
+		config_reg->CONFIG_IESR4 = ESM_IESR4_CONFIGVALUE;
+		config_reg->CONFIG_ILSR4 = ESM_ILSR4_CONFIGVALUE;
+	}
+	else
+	{
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+		config_reg->CONFIG_EEPAPR1 = esmREG->EEPAPR1;
+		config_reg->CONFIG_IESR1 = esmREG->IESR1;
+		config_reg->CONFIG_ILSR1 = esmREG->ILSR1;
+		config_reg->CONFIG_LTCPR = esmREG->LTCPR;
+		config_reg->CONFIG_EKR = esmREG->EKR;  
+		config_reg->CONFIG_IEPSR4 = esmREG->IEPSR4;
+		config_reg->CONFIG_IESR4 = esmREG->IESR4;
+		config_reg->CONFIG_ILSR4 = esmREG->ILSR4;
+	}
+}
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+/** @fn void esmHighInterrupt(void)
+*   @brief High Level Interrupt for ESM
+*/
+#pragma CODE_STATE(esmHighInterrupt, 32)
+#pragma INTERRUPT(esmHighInterrupt, FIQ)
+/* SourceId : ESM_SourceId_018 */
+/* DesignId : ESM_DesignId_018 */
+/* Requirements : HL_SR21, HL_SR22 */
+void esmHighInterrupt(void)
+{
+    uint32 vec = esmREG->IOFFHR - 1U;
+
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+    if (vec < 32U)
+    {
+        esmREG->SR1[0U] = (uint32)1U << vec;
+        esmGroup1Notification(vec);
+    }
+    else if (vec < 64U)
+    {
+        esmREG->SR1[1U] = (uint32)1U << (vec-32U);
+        esmGroup2Notification(vec-32U);
+    }
+    else if (vec < 96U)
+    {
+        esmREG->SR4[0U] = (uint32)1U << (vec-64U);
+        esmGroup1Notification(vec-32U);
+    }
+    else
+    {
+        esmREG->SR4[0U] = 0xFFFFFFFFU;
+        esmREG->SR1[1U] = 0xFFFFFFFFU;
+        esmREG->SR1[0U] = 0xFFFFFFFFU;
+    }
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+
+/** @fn void esmLowInterrupt(void)
+*   @brief Low Level Interrupt for ESM
+*/
+#pragma CODE_STATE(esmLowInterrupt, 32)
+#pragma INTERRUPT(esmLowInterrupt, IRQ)
+/* SourceId : ESM_SourceId_019 */
+/* DesignId : ESM_DesignId_018 */
+/* Requirements : HL_SR21, HL_SR22 */
+void esmLowInterrupt(void)
+{
+
+    /* Note : Group 1 Error         */
+    /* 1  to 32 -> channel 0  to 31 */
+    /* 65 to 96 -> channel 32 to 63 */
+
+    uint32 vec = esmREG->IOFFLR - 1U;
+
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+
+    if (vec < 32U) /* channel 0 to 31  */
+    {
+        esmREG->SR1[0U] = (uint32)1U << vec;
+        esmGroup1Notification(vec);
+    }
+    else if ((vec >= 64U) && (vec < 96U))     /* channel 32 to 63 */
+    {
+        esmREG->SR4[0U] = (uint32)1U << (vec-64U);
+        esmGroup1Notification(vec-32U);
+    }
+    else
+    {
+        esmREG->SR4[0U] = 0xFFFFFFFFU;
+        esmREG->SR1[0U] = 0xFFFFFFFFU;
+    }
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
diff --git a/src/arch/rm46l8lp/halcogen/gio.c b/src/arch/rm46l8lp/halcogen/gio.c
new file mode 100644
index 0000000..2365e18
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/gio.c
@@ -0,0 +1,518 @@
+/** @file gio.c
+*   @brief GIO Driver Implementation File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "gio.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void gioInit(void)
+*   @brief Initializes the GIO Driver
+*
+*   This function initializes the GIO module and set the GIO ports
+*   to the initial values.
+*/
+/* SourceId : GIO_SourceId_001 */
+/* DesignId : GIO_DesignId_001 */
+/* Requirements : HL_SR26 */
+void gioInit(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+    /** bring GIO module out of reset */
+    gioREG->GCR0   = 1U;
+    gioREG->ENACLR = 0xFFU;
+    gioREG->LVLCLR = 0xFFU;
+
+    /** @b initialize @b Port @b A */
+
+    /** - Port A output values */
+    gioPORTA->DOUT = (uint32)((uint32)0U << 0U)  /* Bit 0 */
+                   | (uint32)((uint32)0U << 1U)  /* Bit 1 */
+                   | (uint32)((uint32)0U << 2U)  /* Bit 2 */
+                   | (uint32)((uint32)0U << 3U)  /* Bit 3 */
+                   | (uint32)((uint32)0U << 4U)  /* Bit 4 */
+                   | (uint32)((uint32)0U << 5U)  /* Bit 5 */
+                   | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                   | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+    /** - Port A direction */
+    gioPORTA->DIR  = (uint32)((uint32)1U << 0U)  /* Bit 0 */
+                   | (uint32)((uint32)1U << 1U)  /* Bit 1 */
+                   | (uint32)((uint32)1U << 2U)  /* Bit 2 */
+                   | (uint32)((uint32)0U << 3U)  /* Bit 3 */
+                   | (uint32)((uint32)0U << 4U)  /* Bit 4 */
+                   | (uint32)((uint32)0U << 5U)  /* Bit 5 */
+                   | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                   | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+    /** - Port A open drain enable */
+    gioPORTA->PDR  = (uint32)((uint32)0U << 0U)  /* Bit 0 */
+                   | (uint32)((uint32)0U << 1U)  /* Bit 1 */
+                   | (uint32)((uint32)0U << 2U)  /* Bit 2 */
+                   | (uint32)((uint32)0U << 3U)  /* Bit 3 */
+                   | (uint32)((uint32)0U << 4U)  /* Bit 4 */
+                   | (uint32)((uint32)0U << 5U)  /* Bit 5 */
+                   | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                   | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+    /** - Port A pullup / pulldown selection */
+    gioPORTA->PSL  = (uint32)((uint32)0U << 0U)  /* Bit 0 */
+                   | (uint32)((uint32)0U << 1U)  /* Bit 1 */
+                   | (uint32)((uint32)0U << 2U)  /* Bit 2 */
+                   | (uint32)((uint32)0U << 3U)  /* Bit 3 */
+                   | (uint32)((uint32)0U << 4U)  /* Bit 4 */
+                   | (uint32)((uint32)0U << 5U)  /* Bit 5 */
+                   | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                   | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+    /** - Port A pullup / pulldown enable*/
+    gioPORTA->PULDIS  = (uint32)((uint32)0U << 0U)  /* Bit 0 */
+                      | (uint32)((uint32)0U << 1U)  /* Bit 1 */
+                      | (uint32)((uint32)0U << 2U)  /* Bit 2 */
+                      | (uint32)((uint32)0U << 3U)  /* Bit 3 */
+                      | (uint32)((uint32)0U << 4U)  /* Bit 4 */
+                      | (uint32)((uint32)0U << 5U)  /* Bit 5 */
+                      | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                      | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+    /** @b initialize @b Port @b B */
+
+    /** - Port B output values */
+    gioPORTB->DOUT = (uint32)((uint32)0U << 0U)  /* Bit 0 */
+                   | (uint32)((uint32)0U << 1U)  /* Bit 1 */
+                   | (uint32)((uint32)0U << 2U)  /* Bit 2 */
+                   | (uint32)((uint32)0U << 3U)  /* Bit 3 */
+                   | (uint32)((uint32)0U << 4U)  /* Bit 4 */
+                   | (uint32)((uint32)0U << 5U)  /* Bit 5 */
+                   | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                   | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+    /** - Port B direction */
+    gioPORTB->DIR  = (uint32)((uint32)0U << 0U)  /* Bit 0 */
+                   | (uint32)((uint32)1U << 1U)  /* Bit 1 */
+                   | (uint32)((uint32)1U << 2U)  /* Bit 2 */
+                   | (uint32)((uint32)0U << 3U)  /* Bit 3 */
+                   | (uint32)((uint32)0U << 4U)  /* Bit 4 */
+                   | (uint32)((uint32)0U << 5U)  /* Bit 5 */
+                   | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                   | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+    /** - Port B open drain enable */
+    gioPORTB->PDR  = (uint32)((uint32)0U << 0U)  /* Bit 0 */
+                   | (uint32)((uint32)0U << 1U)  /* Bit 1 */
+                   | (uint32)((uint32)0U << 2U)  /* Bit 2 */
+                   | (uint32)((uint32)0U << 3U)  /* Bit 3 */
+                   | (uint32)((uint32)0U << 4U)  /* Bit 4 */
+                   | (uint32)((uint32)0U << 5U)  /* Bit 5 */
+                   | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                   | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+    /** - Port B pullup / pulldown selection */
+    gioPORTB->PSL  = (uint32)((uint32)0U << 0U)  /* Bit 0 */
+                   | (uint32)((uint32)0U << 1U)  /* Bit 1 */
+                   | (uint32)((uint32)0U << 2U)  /* Bit 2 */
+                   | (uint32)((uint32)0U << 3U)  /* Bit 3 */
+                   | (uint32)((uint32)0U << 4U)  /* Bit 4 */
+                   | (uint32)((uint32)0U << 5U)  /* Bit 5 */
+                   | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                   | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+    /** - Port B pullup / pulldown enable*/
+    gioPORTB->PULDIS  = (uint32)((uint32)0U << 0U) /* Bit 0 */
+                      | (uint32)((uint32)0U << 1U)  /* Bit 1 */
+                      | (uint32)((uint32)0U << 2U)  /* Bit 2 */
+                      | (uint32)((uint32)0U << 3U)  /* Bit 3 */
+                      | (uint32)((uint32)0U << 4U)  /* Bit 4 */
+                      | (uint32)((uint32)0U << 5U)  /* Bit 5 */
+                      | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                      | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+    /** @b initialize @b interrupts */
+
+    /** - interrupt polarity */
+    gioREG->POL = (uint32)((uint32)0U << 0U)   /* Bit 0 */
+                | (uint32)((uint32)0U << 1U)   /* Bit 1 */
+                | (uint32)((uint32)0U << 2U)   /* Bit 2 */
+                | (uint32)((uint32)0U << 3U)   /* Bit 3 */
+                | (uint32)((uint32)0U << 4U)   /* Bit 4 */
+                | (uint32)((uint32)0U << 5U)   /* Bit 5 */
+                | (uint32)((uint32)0U << 6U)   /* Bit 6 */
+                | (uint32)((uint32)0U << 7U)   /* Bit 7 */
+                | (uint32)((uint32)0U << 8U)   /* Bit 8  */
+                | (uint32)((uint32)0U << 9U)   /* Bit 9  */
+                | (uint32)((uint32)0U << 10U)  /* Bit 10 */
+                | (uint32)((uint32)0U << 11U)  /* Bit 11 */
+                | (uint32)((uint32)0U << 12U)  /* Bit 12 */
+                | (uint32)((uint32)0U << 13U)  /* Bit 13 */
+                | (uint32)((uint32)0U << 14U)  /* Bit 14 */
+                | (uint32)((uint32)0U << 15U); /* Bit 15 */
+
+
+    /** - interrupt level */
+    gioREG->LVLSET = (uint32)((uint32)0U << 0U)   /* Bit 0 */
+                   | (uint32)((uint32)0U << 1U)   /* Bit 1 */
+                   | (uint32)((uint32)0U << 2U)   /* Bit 2 */
+                   | (uint32)((uint32)0U << 3U)   /* Bit 3 */
+                   | (uint32)((uint32)0U << 4U)   /* Bit 4 */
+                   | (uint32)((uint32)0U << 5U)   /* Bit 5 */
+                   | (uint32)((uint32)0U << 6U)   /* Bit 6 */
+                   | (uint32)((uint32)0U << 7U)   /* Bit 7 */
+                   | (uint32)((uint32)0U << 8U)   /* Bit 8  */
+                   | (uint32)((uint32)0U << 9U)   /* Bit 9  */
+                   | (uint32)((uint32)0U << 10U)  /* Bit 10 */
+                   | (uint32)((uint32)0U << 11U)  /* Bit 11 */
+                   | (uint32)((uint32)0U << 12U)  /* Bit 12 */
+                   | (uint32)((uint32)0U << 13U)  /* Bit 13 */
+                   | (uint32)((uint32)0U << 14U)  /* Bit 14 */
+                   | (uint32)((uint32)0U << 15U); /* Bit 15 */
+
+
+
+
+    /** - clear all pending interrupts */
+    gioREG->FLG = 0xFFU;
+
+    /** - enable interrupts */
+    gioREG->ENASET = (uint32)((uint32)0U << 0U)   /* Bit 0 */
+                   | (uint32)((uint32)0U << 1U)   /* Bit 1 */
+                   | (uint32)((uint32)0U << 2U)   /* Bit 2 */
+                   | (uint32)((uint32)0U << 3U)   /* Bit 3 */
+                   | (uint32)((uint32)0U << 4U)   /* Bit 4 */
+                   | (uint32)((uint32)0U << 5U)   /* Bit 5 */
+                   | (uint32)((uint32)0U << 6U)   /* Bit 6 */
+                   | (uint32)((uint32)0U << 7U)   /* Bit 7 */
+                   | (uint32)((uint32)0U << 8U)   /* Bit 8  */
+                   | (uint32)((uint32)0U << 9U)   /* Bit 9  */
+                   | (uint32)((uint32)0U << 10U)  /* Bit 10 */
+                   | (uint32)((uint32)0U << 11U)  /* Bit 11 */
+                   | (uint32)((uint32)0U << 12U)  /* Bit 12 */
+                   | (uint32)((uint32)0U << 13U)  /* Bit 13 */
+                   | (uint32)((uint32)0U << 14U)  /* Bit 14 */
+                   | (uint32)((uint32)0U << 15U); /* Bit 15 */
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+
+/** @fn void gioSetDirection(gioPORT_t *port, uint32 dir)
+*   @brief Set Port Direction
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] dir value to write to DIR register
+*
+*   Set the direction of GIO pins at runtime.
+*/
+/* SourceId : GIO_SourceId_002 */
+/* DesignId : GIO_DesignId_002 */
+/* Requirements : HL_SR27 */
+void gioSetDirection(gioPORT_t *port, uint32 dir)
+{
+    port->DIR = dir;
+}
+
+
+/** @fn void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value)
+*   @brief Write Bit
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] bit number 0-7 that specifies the bit to be written to.
+*              - 0: LSB
+*              - 7: MSB
+*   @param[in] value binary value to write to bit
+*
+*   Writes a value to the specified pin of the given GIO port
+*/
+/* SourceId : GIO_SourceId_003 */
+/* DesignId : GIO_DesignId_003 */
+/* Requirements : HL_SR28 */
+void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value)
+{
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+    if (value != 0U)
+    {
+        port->DSET = (uint32)1U << bit;
+    }
+    else
+    {
+        port->DCLR = (uint32)1U << bit;
+    }
+}
+
+
+/** @fn void gioSetPort(gioPORT_t *port, uint32 value)
+*   @brief Write Port Value
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] value value to write to port
+*
+*   Writes a value to all pin of a given GIO port
+*/
+/* SourceId : GIO_SourceId_004 */
+/* DesignId : GIO_DesignId_004 */
+/* Requirements : HL_SR29 */
+void gioSetPort(gioPORT_t *port, uint32 value)
+{
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+    port->DOUT = value;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+}
+
+
+/** @fn uint32 gioGetBit(gioPORT_t *port, uint32 bit)
+*   @brief Read Bit
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] bit number 0-7 that specifies the bit to be written to.
+*              - 0: LSB
+*              - 7: MSB
+*
+*   Reads a the current value from the specified pin of the given GIO port
+*/
+/* SourceId : GIO_SourceId_005 */
+/* DesignId : GIO_DesignId_005 */
+/* Requirements : HL_SR30 */
+uint32 gioGetBit(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+    return (port->DIN >> bit) & 1U;
+}
+
+
+/** @fn uint32 gioGetPort(gioPORT_t *port)
+*   @brief Read Port Value
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*
+*   Reads a the current value of a given GIO port
+*/
+/* SourceId : GIO_SourceId_006 */
+/* DesignId : GIO_DesignId_006 */
+/* Requirements : HL_SR31 */
+uint32 gioGetPort(gioPORT_t *port)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+    return port->DIN;
+}
+
+/** @fn void gioToggleBit(gioPORT_t *port, uint32 bit)
+*   @brief Write Bit
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] bit number 0-7 that specifies the bit to be written to.
+*              - 0: LSB
+*              - 7: MSB
+*
+*   Toggle a value to the specified pin of the given GIO port
+*/
+/* SourceId : GIO_SourceId_007 */
+/* DesignId : GIO_DesignId_007 */
+/* Requirements : HL_SR32 */
+void gioToggleBit(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+    if ((port->DIN & (uint32)((uint32)1U << bit)) != 0U)
+    {
+        port->DCLR = (uint32)1U << bit;
+    }
+    else
+    {
+        port->DSET = (uint32)1U << bit;
+    }
+}
+
+/** @fn void gioEnableNotification(uint32 bit)
+*   @brief Enable Interrupt
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] bit interrupt pin to enable
+*              - 0: LSB
+*              - 7: MSB
+*
+*   Enables an interrupt pin of selected port
+*/
+/* SourceId : GIO_SourceId_008 */
+/* DesignId : GIO_DesignId_008 */
+/* Requirements : HL_SR33 */
+void gioEnableNotification(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+    if (port == gioPORTA)
+    {
+        gioREG->ENASET = (uint32)1U << bit;
+    }
+    else if (port == gioPORTB)
+    {
+        gioREG->ENASET = (uint32)1U << (bit + 8U);
+    }
+    else
+    {
+        /* Empty */
+    }
+}
+
+
+/** @fn void gioDisableNotification(uint32 bit)
+*   @brief Disable Interrupt
+*   @param[in] port pointer to GIO port:
+*              - gioPORTA: PortA pointer
+*              - gioPORTB: PortB pointer
+*   @param[in] bit interrupt pin to enable
+*              - 0: LSB
+*              - 7: MSB
+*
+*   Disables an interrupt pin of selected port
+*/
+/* SourceId : GIO_SourceId_009 */
+/* DesignId : GIO_DesignId_009 */
+/* Requirements : HL_SR34 */
+void gioDisableNotification(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+    if (port == gioPORTA)
+    {
+        gioREG->ENACLR = (uint32)1U << bit;
+    }
+    else if (port == gioPORTB)
+    {
+        gioREG->ENACLR = (uint32)1U << (bit + 8U);
+    }
+    else
+    {
+        /* Empty */
+    }
+}
+
+/** @fn void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*   @param[in] *config_reg: pointer to the struct to which the initial or current
+*                           value of the configuration registers need to be stored
+*   @param[in] type:    whether initial or current value of the configuration registers need to be stored
+*                       - InitialValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*                       - CurrentValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type')
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : GIO_SourceId_010 */
+/* DesignId : GIO_DesignId_010 */
+/* Requirements : HL_SR37 */
+void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_INTDET    = GIO_INTDET_CONFIGVALUE;
+        config_reg->CONFIG_POL       = GIO_POL_CONFIGVALUE;
+        config_reg->CONFIG_INTENASET = GIO_INTENASET_CONFIGVALUE;
+        config_reg->CONFIG_LVLSET    = GIO_LVLSET_CONFIGVALUE;
+
+        config_reg->CONFIG_PORTADIR    = GIO_PORTADIR_CONFIGVALUE;
+        config_reg->CONFIG_PORTAPDR    = GIO_PORTAPDR_CONFIGVALUE;
+        config_reg->CONFIG_PORTAPSL    = GIO_PORTAPSL_CONFIGVALUE;
+        config_reg->CONFIG_PORTAPULDIS = GIO_PORTAPULDIS_CONFIGVALUE;
+
+        config_reg->CONFIG_PORTBDIR    = GIO_PORTBDIR_CONFIGVALUE;
+        config_reg->CONFIG_PORTBPDR    = GIO_PORTBPDR_CONFIGVALUE;
+        config_reg->CONFIG_PORTBPSL    = GIO_PORTBPSL_CONFIGVALUE;
+        config_reg->CONFIG_PORTBPULDIS = GIO_PORTBPULDIS_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_INTDET    = gioREG->INTDET;
+        config_reg->CONFIG_POL       = gioREG->POL;
+        config_reg->CONFIG_INTENASET = gioREG->ENASET;
+        config_reg->CONFIG_LVLSET    = gioREG->LVLSET;
+
+        config_reg->CONFIG_PORTADIR    = gioPORTA->DIR;
+        config_reg->CONFIG_PORTAPDR    = gioPORTA->PDR;
+        config_reg->CONFIG_PORTAPSL    = gioPORTA->PSL;
+        config_reg->CONFIG_PORTAPULDIS = gioPORTA->PULDIS;
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_PORTBDIR    = gioPORTB->DIR;
+        config_reg->CONFIG_PORTBPDR    = gioPORTB->PDR;
+        config_reg->CONFIG_PORTBPSL    = gioPORTB->PSL;
+        config_reg->CONFIG_PORTBPULDIS = gioPORTB->PULDIS;
+    }
+}
+
+
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
diff --git a/src/arch/rm46l8lp/halcogen/het.c b/src/arch/rm46l8lp/halcogen/het.c
new file mode 100644
index 0000000..b83fab4
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/het.c
@@ -0,0 +1,1936 @@
+/** @file het.c
+*   @brief HET Driver Implementation File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#include "het.h"
+#include "sys_vim.h"
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/*----------------------------------------------------------------------------*/
+/* Global variables                                                           */
+
+static const uint32 s_het1pwmPolarity[8U] =
+{
+    3U,
+    3U,
+    3U,
+    3U,
+    3U,
+    3U,
+    3U,
+    3U,
+};
+
+
+/*----------------------------------------------------------------------------*/
+/* Default Program                                                            */
+
+/** @var static const hetINSTRUCTION_t het1PROGRAM[58]
+*   @brief Default Program
+*
+*   Het program running after initialization.
+*/
+
+static const hetINSTRUCTION_t het1PROGRAM[58U] =
+{
+    /* CNT: Timebase
+    *       - Instruction                  = 0
+    *       - Next instruction             = 1
+    *       - Conditional next instruction = na
+    *       - Interrupt                    = na
+    *       - Pin                          = na
+    *       - Reg                          = T
+    */
+    {
+        /* Program */
+        0x00002C80U,
+        /* Control */
+        0x01FFFFFFU,
+        /* Data */
+        0xFFFFFF80U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PWCNT: PWM 0 -> Duty Cycle
+    *         - Instruction                  = 1
+    *         - Next instruction             = 2
+    *         - Conditional next instruction = 2
+    *         - Interrupt                    = 1
+    *         - Pin                          = 8
+    */
+    {
+        /* Program */
+        0x000055C0U,
+        /* Control */
+        (0x00004006U | (uint32)((uint32)8U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* DJZ: PWM 0 -> Period
+    *         - Instruction                  = 2
+    *         - Next instruction             = 3
+    *         - Conditional next instruction = 41
+    *         - Interrupt                    = 2
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x00007480U,
+        /* Control */
+        0x00052006U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PWCNT: PWM 1 -> Duty Cycle
+    *         - Instruction                  = 3
+    *         - Next instruction             = 4
+    *         - Conditional next instruction = 4
+    *         - Interrupt                    = 3
+    *         - Pin                          = 10
+    */
+    {
+        /* Program */
+        0x000095C0U,
+        /* Control */
+        (0x00008006U | (uint32)((uint32)10U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* DJZ: PWM 1 -> Period
+    *         - Instruction                  = 4
+    *         - Next instruction             = 5
+    *         - Conditional next instruction = 43
+    *         - Interrupt                    = 4
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x0000B480U,
+        /* Control */
+        0x00056006U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PWCNT: PWM 2 -> Duty Cycle
+    *         - Instruction                  = 5
+    *         - Next instruction             = 6
+    *         - Conditional next instruction = 6
+    *         - Interrupt                    = 5
+    *         - Pin                          = 12
+    */
+    {
+        /* Program */
+        0x0000D5C0U,
+        /* Control */
+        (0x0000C006U | (uint32)((uint32)12U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* DJZ: PWM 2 -> Period
+    *         - Instruction                  = 6
+    *         - Next instruction             = 7
+    *         - Conditional next instruction = 45
+    *         - Interrupt                    = 6
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x0000F480U,
+        /* Control */
+        0x0005A006U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PWCNT: PWM 3 -> Duty Cycle
+    *         - Instruction                  = 7
+    *         - Next instruction             = 8
+    *         - Conditional next instruction = 8
+    *         - Interrupt                    = 7
+    *         - Pin                          = 14
+    */
+    {
+        /* Program */
+        0x000115C0U,
+        /* Control */
+        (0x00010006U | (uint32)((uint32)14U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* DJZ: PWM 3 -> Period
+    *         - Instruction                  = 8
+    *         - Next instruction             = 9
+    *         - Conditional next instruction = 47
+    *         - Interrupt                    = 8
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x00013480U,
+        /* Control */
+        0x0005E006U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PWCNT: PWM 4 -> Duty Cycle
+    *         - Instruction                  = 9
+    *         - Next instruction             = 10
+    *         - Conditional next instruction = 10
+    *         - Interrupt                    = 9
+    *         - Pin                          = 16
+    */
+    {
+        /* Program */
+        0x000155C0U,
+        /* Control */
+        (0x00014006U | (uint32)((uint32)16U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* DJZ: PWM 4 -> Period
+    *         - Instruction                  = 10
+    *         - Next instruction             = 11
+    *         - Conditional next instruction = 49
+    *         - Interrupt                    = 10
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x00017480U,
+        /* Control */
+        0x00062006U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PWCNT: PWM 5 -> Duty Cycle
+    *         - Instruction                  = 11
+    *         - Next instruction             = 12
+    *         - Conditional next instruction = 12
+    *         - Interrupt                    = 11
+    *         - Pin                          = 17
+    */
+    {
+        /* Program */
+        0x000195C0U,
+        /* Control */
+        (0x00018006U | (uint32)((uint32)17U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* DJZ: PWM 5 -> Period
+    *         - Instruction                  = 12
+    *         - Next instruction             = 13
+    *         - Conditional next instruction = 51
+    *         - Interrupt                    = 12
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x0001B480U,
+        /* Control */
+        0x00066006U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PWCNT: PWM 6 -> Duty Cycle
+    *         - Instruction                  = 13
+    *         - Next instruction             = 14
+    *         - Conditional next instruction = 14
+    *         - Interrupt                    = 13
+    *         - Pin                          = 18
+    */
+    {
+        /* Program */
+        0x0001D5C0U,
+        /* Control */
+        (0x0001C006U | (uint32)((uint32)18U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* DJZ: PWM 6 -> Period
+    *         - Instruction                  = 14
+    *         - Next instruction             = 15
+    *         - Conditional next instruction = 53
+    *         - Interrupt                    = 14
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x0001F480U,
+        /* Control */
+        0x0006A006U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PWCNT: PWM 7 -> Duty Cycle
+    *         - Instruction                  = 15
+    *         - Next instruction             = 16
+    *         - Conditional next instruction = 16
+    *         - Interrupt                    = 15
+    *         - Pin                          = 19
+    */
+    {
+        /* Program */
+        0x000215C0U,
+        /* Control */
+        (0x00020006U | (uint32)((uint32)19U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* DJZ: PWM 7 -> Period
+    *         - Instruction                  = 16
+    *         - Next instruction             = 17
+    *         - Conditional next instruction = 55
+    *         - Interrupt                    = 16
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x00023480U,
+        /* Control */
+        0x0006E006U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* ECNT: CCU Edge 0
+    *         - Instruction                  = 17
+    *         - Next instruction             = 18
+    *         - Conditional next instruction = 18
+    *         - Interrupt                    = 17
+    *         - Pin                          = 9
+    */
+    {
+        /* Program */
+        0x00025440U,
+        /* Control */
+        (0x00024007U | (uint32)((uint32)9U << 8U) | (uint32)((uint32)1U << 4U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* ECNT: CCU Edge 1
+    *         - Instruction                  = 18
+    *         - Next instruction             = 19
+    *         - Conditional next instruction = 19
+    *         - Interrupt                    = 18
+    *         - Pin                          = 11
+    */
+    {
+        /* Program */
+        0x00027440U,
+        /* Control */
+        (0x00026007U | (uint32)((uint32)11U << 8U) | (uint32)((uint32)1U << 4U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* ECNT: CCU Edge 2
+    *         - Instruction                  = 19
+    *         - Next instruction             = 20
+    *         - Conditional next instruction = 20
+    *         - Interrupt                    = 19
+    *         - Pin                          = 13
+    */
+    {
+        /* Program */
+        0x00029440U,
+        /* Control */
+        (0x00028007U | (uint32)((uint32)13U << 8U) | (uint32)((uint32)1U << 4U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* ECNT: CCU Edge 3
+    *         - Instruction                  = 20
+    *         - Next instruction             = 21
+    *         - Conditional next instruction = 21
+    *         - Interrupt                    = 20
+    *         - Pin                          = 15
+    */
+    {
+        /* Program */
+        0x0002B440U,
+        /* Control */
+        (0x0002A007U | (uint32)((uint32)15U << 8U) | (uint32)((uint32)1U << 4U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* ECNT: CCU Edge 4
+    *         - Instruction                  = 21
+    *         - Next instruction             = 22
+    *         - Conditional next instruction = 22
+    *         - Interrupt                    = 21
+    *         - Pin                          = 20
+    */
+    {
+        /* Program */
+        0x0002D440U,
+        /* Control */
+        (0x0002C007U | (uint32)((uint32)20U << 8U) | (uint32)((uint32)1U << 4U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* ECNT: CCU Edge 5
+    *         - Instruction                  = 22
+    *         - Next instruction             = 23
+    *         - Conditional next instruction = 23
+    *         - Interrupt                    = 22
+    *         - Pin                          = 21
+    */
+    {
+        /* Program */
+        0x0002F440U,
+        /* Control */
+        (0x0002E007U | (uint32)((uint32)21U << 8U) | (uint32)((uint32)1U << 4U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* ECNT: CCU Edge 6
+    *         - Instruction                  = 23
+    *         - Next instruction             = 24
+    *         - Conditional next instruction = 24
+    *         - Interrupt                    = 23
+    *         - Pin                          = 22
+    */
+    {
+        /* Program */
+        0x00031440U,
+        /* Control */
+        (0x00030007U | (uint32)((uint32)22U << 8U) | (uint32)((uint32)1U << 4U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* ECNT: CCU Edge 7
+    *         - Instruction                  = 24
+    *         - Next instruction             = 25
+    *         - Conditional next instruction = 25
+    *         - Interrupt                    = 24
+    *         - Pin                          = 23
+    */
+    {
+        /* Program */
+        0x00033440U,
+        /* Control */
+        (0x00032007U | (uint32)((uint32)23U << 8U) | (uint32)((uint32)1U << 4U)),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Duty 0
+    *         - Instruction                  = 25
+    *         - Next instruction             = 26
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 0
+    */
+    {
+        /* Program */
+        0x00034E00U | (uint32)((uint32)0U << 6U)  | (uint32)(0U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Period 0
+    *         - Instruction                  = 26
+    *         - Next instruction             = 27
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 0  + 1
+    */
+    {
+        /* Program */
+        0x00036E80U | (uint32)((uint32)0U << 6U)  | (uint32)((0U) + 1U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Duty 1
+    *         - Instruction                  = 27
+    *         - Next instruction             = 28
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 2
+    */
+    {
+        /* Program */
+        0x00038E00U | (uint32)((uint32)0U << 6U)  | (uint32)(2U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Period 1
+    *         - Instruction                  = 28
+    *         - Next instruction             = 29
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 2  + 1
+    */
+    {
+        /* Program */
+        0x0003AE80U | (uint32)((uint32)0U << 6U)  | (uint32)((2U) + 1U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Duty 2
+    *         - Instruction                  = 29
+    *         - Next instruction             = 30
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 4
+    */
+    {
+        /* Program */
+        0x0003CE00U | (uint32)((uint32)0U << 6U)  | (uint32)(4U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Period 2
+    *         - Instruction                  = 30
+    *         - Next instruction             = 31
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 4  + 1
+    */
+    {
+        /* Program */
+        0x0003EE80U | (uint32)((uint32)0U << 6U)  | (uint32)((4U) + 1U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Duty 3
+    *         - Instruction                  = 31
+    *         - Next instruction             = 32
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 6
+    */
+    {
+        /* Program */
+        0x00040E00U | (uint32)((uint32)0U << 6U)  | (uint32)(6U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Period 3
+    *         - Instruction                  = 32
+    *         - Next instruction             = 33
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 6  + 1
+    */
+    {
+        /* Program */
+        0x00042E80U | (uint32)((uint32)0U << 6U)  | (uint32)((6U) + 1U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Duty 4
+    *         - Instruction                  = 33
+    *         - Next instruction             = 34
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 24
+    */
+    {
+        /* Program */
+        0x00044E00U | (uint32)((uint32)0U << 6U)  | (uint32)(24U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Period 4
+    *         - Instruction                  = 34
+    *         - Next instruction             = 35
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 24  + 1
+    */
+    {
+        /* Program */
+        0x00046E80U | (uint32)((uint32)0U << 6U)  | (uint32)((24U) + 1U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Duty 5
+    *         - Instruction                  = 35
+    *         - Next instruction             = 36
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 26
+    */
+    {
+        /* Program */
+        0x00048E00U | (uint32)((uint32)0U << 6U)  | (uint32)(26U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Period 5
+    *         - Instruction                  = 36
+    *         - Next instruction             = 37
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 26  + 1
+    */
+    {
+        /* Program */
+        0x0004AE80U | (uint32)((uint32)0U << 6U)  | (uint32)((26U) + 1U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Duty 6
+    *         - Instruction                  = 37
+    *         - Next instruction             = 38
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 28
+    */
+    {
+        /* Program */
+        0x0004CE00U | (uint32)((uint32)0U << 6U)  | (uint32)(28U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Period 6
+    *         - Instruction                  = 38
+    *         - Next instruction             = 39
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 28  + 1
+    */
+    {
+        /* Program */
+        0x0004EE80U | (uint32)((uint32)0U << 6U)  | (uint32)((28U) + 1U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Duty 7
+    *         - Instruction                  = 39
+    *         - Next instruction             = 40
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 30
+    */
+    {
+        /* Program */
+        0x00050E00U | (uint32)((uint32)0U << 6U)  | (uint32)(30U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* PCNT: Capture Period 7
+    *         - Instruction                  = 40
+    *         - Next instruction             = 57
+    *         - Conditional next instruction = na
+    *         - Interrupt                    = na
+    *         - Pin                          = 30  + 1
+    */
+    {
+        /* Program */
+        0x00072E80U | (uint32)((uint32)0U << 6U)  | (uint32)((30U) + 1U),
+        /* Control */
+        0x00000000U,
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 0 -> Duty Cycle Update
+    *         - Instruction                  = 41
+    *         - Next instruction             = 42
+    *         - Conditional next instruction = 2
+    *         - Interrupt                    = 1
+    *         - Pin                          = 8
+    */
+    {
+        /* Program */
+        0x00054201U,
+        /* Control */
+        (0x00004007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)8U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        80128U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 0 -> Period Update
+    *         - Instruction                  = 42
+    *         - Next instruction             = 3
+    *         - Conditional next instruction = 41
+    *         - Interrupt                    = 2
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x00006202U,
+        /* Control */
+        (0x00052007U),
+        /* Data */
+        159872U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 1 -> Duty Cycle Update
+    *         - Instruction                  = 43
+    *         - Next instruction             = 44
+    *         - Conditional next instruction = 4
+    *         - Interrupt                    = 3
+    *         - Pin                          = 10
+    */
+    {
+        /* Program */
+        0x00058203U,
+        /* Control */
+        (0x00008007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)10U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        80128U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 1 -> Period Update
+    *         - Instruction                  = 44
+    *         - Next instruction             = 5
+    *         - Conditional next instruction = 43
+    *         - Interrupt                    = 4
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x0000A204U,
+        /* Control */
+        (0x00056007U),
+        /* Data */
+        159872U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 2 -> Duty Cycle Update
+    *         - Instruction                  = 45
+    *         - Next instruction             = 46
+    *         - Conditional next instruction = 6
+    *         - Interrupt                    = 5
+    *         - Pin                          = 12
+    */
+    {
+        /* Program */
+        0x0005C205U,
+        /* Control */
+        (0x0000C007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)12U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        80128U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 2 -> Period Update
+    *         - Instruction                  = 46
+    *         - Next instruction             = 7
+    *         - Conditional next instruction = 45
+    *         - Interrupt                    = 6
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x0000E206U,
+        /* Control */
+        (0x0005A007U),
+        /* Data */
+        159872U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 3 -> Duty Cycle Update
+    *         - Instruction                  = 47
+    *         - Next instruction             = 48
+    *         - Conditional next instruction = 8
+    *         - Interrupt                    = 7
+    *         - Pin                          = 14
+    */
+    {
+        /* Program */
+        0x00060207U,
+        /* Control */
+        (0x00010007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)14U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        80128U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 3 -> Period Update
+    *         - Instruction                  = 48
+    *         - Next instruction             = 9
+    *         - Conditional next instruction = 47
+    *         - Interrupt                    = 8
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x00012208U,
+        /* Control */
+        (0x0005E007U),
+        /* Data */
+        159872U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 4 -> Duty Cycle Update
+    *         - Instruction                  = 49
+    *         - Next instruction             = 50
+    *         - Conditional next instruction = 10
+    *         - Interrupt                    = 9
+    *         - Pin                          = 16
+    */
+    {
+        /* Program */
+        0x00064209U,
+        /* Control */
+        (0x00014007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)16U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        80128U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 4 -> Period Update
+    *         - Instruction                  = 50
+    *         - Next instruction             = 11
+    *         - Conditional next instruction = 49
+    *         - Interrupt                    = 10
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x0001620AU,
+        /* Control */
+        (0x00062007U),
+        /* Data */
+        159872U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 5 -> Duty Cycle Update
+    *         - Instruction                  = 51
+    *         - Next instruction             = 52
+    *         - Conditional next instruction = 12
+    *         - Interrupt                    = 11
+    *         - Pin                          = 17
+    */
+    {
+        /* Program */
+        0x0006820BU,
+        /* Control */
+        (0x00018007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)17U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        80128U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 5 -> Period Update
+    *         - Instruction                  = 52
+    *         - Next instruction             = 13
+    *         - Conditional next instruction = 51
+    *         - Interrupt                    = 12
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x0001A20CU,
+        /* Control */
+        (0x00066007U),
+        /* Data */
+        159872U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 6 -> Duty Cycle Update
+    *         - Instruction                  = 53
+    *         - Next instruction             = 54
+    *         - Conditional next instruction = 14
+    *         - Interrupt                    = 13
+    *         - Pin                          = 18
+    */
+    {
+        /* Program */
+        0x0006C20DU,
+        /* Control */
+        (0x0001C007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)18U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        80128U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 6 -> Period Update
+    *         - Instruction                  = 54
+    *         - Next instruction             = 15
+    *         - Conditional next instruction = 53
+    *         - Interrupt                    = 14
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x0001E20EU,
+        /* Control */
+        (0x0006A007U),
+        /* Data */
+        159872U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 7 -> Duty Cycle Update
+    *         - Instruction                  = 55
+    *         - Next instruction             = 56
+    *         - Conditional next instruction = 16
+    *         - Interrupt                    = 15
+    *         - Pin                          = 19
+    */
+    {
+        /* Program */
+        0x0007020FU,
+        /* Control */
+        (0x00020007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)19U << 8U) | (uint32)((uint32)3U << 3U)),
+        /* Data */
+        80128U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* MOV64: PWM 7 -> Period Update
+    *         - Instruction                  = 56
+    *         - Next instruction             = 17
+    *         - Conditional next instruction = 55
+    *         - Interrupt                    = 16
+    *         - Pin                          = na
+    */
+    {
+        /* Program */
+        0x00022210U,
+        /* Control */
+        (0x0006E007U),
+        /* Data */
+        159872U,
+        /* Reserved */
+        0x00000000U
+    },
+    /* WCAP: Capture timestamp
+    *         - Instruction                  = 57
+    *         - Next instruction             = 0
+    *         - Conditional next instruction = 0
+    *         - Interrupt                    = na
+    *         - Pin                          = na
+    *         - Reg                          = T
+    */
+    {
+        /* Program */
+        0x00001600U,
+        /* Control */
+        (0x00000004U),
+        /* Data */
+        0x00000000U,
+        /* Reserved */
+        0x00000000U
+    },
+};
+
+
+
+/** @fn void hetInit(void)
+*   @brief Initializes the het Driver
+*
+*   This function initializes the het 1 module.
+*/
+/* SourceId : HET_SourceId_001 */
+/* DesignId : HET_DesignId_001 */
+/* Requirements : HL_SR363 */
+void hetInit(void)
+{
+    /** @b initialize @b HET */
+
+    /** - Set HET pins default output value */
+    hetREG1->DOUT = (uint32)((uint32)0U << 31U)
+                  | (uint32)((uint32)0U << 30U)
+                  | (uint32)((uint32)0U << 29U)
+                  | (uint32)((uint32)0U << 28U)
+                  | (uint32)((uint32)0U << 27U)
+                  | (uint32)((uint32)0U << 26U)
+                  | (uint32)((uint32)0U << 25U)
+                  | (uint32)((uint32)0U << 24U)
+                  | (uint32)((uint32)0U << 23U)
+                  | (uint32)((uint32)0U << 22U)
+                  | (uint32)((uint32)0U << 21U)
+                  | (uint32)((uint32)0U << 20U)
+                  | (uint32)((uint32)0U << 19U)
+                  | (uint32)((uint32)0U << 18U)
+                  | (uint32)((uint32)0U << 17U)
+                  | (uint32)((uint32)0U << 16U)
+                  | (uint32)((uint32)0U << 15U)
+                  | (uint32)((uint32)0U << 14U)
+                  | (uint32)((uint32)0U << 13U)
+                  | (uint32)((uint32)0U << 12U)
+                  | (uint32)((uint32)0U << 11U)
+                  | (uint32)((uint32)0U << 10U)
+                  | (uint32)((uint32)0U << 9U)
+                  | (uint32)((uint32)0U << 8U)
+                  | (uint32)((uint32)0U << 7U)
+                  | (uint32)((uint32)0U << 6U)
+                  | (uint32)((uint32)0U << 5U)
+                  | (uint32)((uint32)0U << 4U)
+                  | (uint32)((uint32)0U << 3U)
+                  | (uint32)((uint32)0U << 2U)
+                  | (uint32)((uint32)0U << 1U)
+                  | (uint32)((uint32)0U << 0U);
+
+    /** - Set HET pins direction */
+    hetREG1->DIR = (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U;
+
+    /** - Set HET pins open drain enable */
+    hetREG1->PDR = (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00008000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U;
+
+    /** - Set HET pins pullup/down enable */
+    hetREG1->PULDIS = (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U
+                    | (uint32) 0x00000000U;
+
+    /** - Set HET pins pullup/down select */
+    hetREG1->PSL = (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00008000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U;
+
+    /** - Set HET pins high resolution share */
+    hetREG1->HRSH = (uint32) 0x00008000U
+                  | (uint32) 0x00004000U
+                  | (uint32) 0x00002000U
+                  | (uint32) 0x00001000U
+                  | (uint32) 0x00000000U
+                  | (uint32) 0x00000000U
+                  | (uint32) 0x00000000U
+                  | (uint32) 0x00000000U
+                  | (uint32) 0x00000000U
+                  | (uint32) 0x00000000U
+                  | (uint32) 0x00000000U
+                  | (uint32) 0x00000000U
+                  | (uint32) 0x00000008U
+                  | (uint32) 0x00000004U
+                  | (uint32) 0x00000002U
+                  | (uint32) 0x00000001U;
+
+    /** - Set HET pins AND share */
+    hetREG1->AND = (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U;
+
+    /** - Set HET pins XOR share */
+    hetREG1->XOR = (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+    /** - Setup prescaler values
+    *     - Loop resolution prescaler
+    *     - High resolution prescaler
+    */
+    hetREG1->PFR = (uint32)((uint32) 6U << 8U)
+                | ((uint32) 0U);
+
+
+   /** - Parity control register
+    *     - Enable/Disable Parity check
+    */
+    hetREG1->PCR = (uint32) 0x00000005U;
+
+    /** - Fill HET RAM with opcodes and Data */
+    /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 <APPROVED> "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */
+    /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 <APPROVED> "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */
+    /*SAFETYMCUSW 95 S MR:11.1,11.4 <APPROVED> "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */
+    /*SAFETYMCUSW 95 S MR:11.1,11.4 <APPROVED> "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */
+    (void)memcpy((void *)hetRAM1, (const void *)het1PROGRAM, sizeof(het1PROGRAM));
+
+    /** - Setup interrupt priority level
+    *     - PWM 0 end of duty  level
+    *     - PWM 0 end of period level
+    *     - PWM 1 end of duty  level
+    *     - PWM 1 end of period level
+    *     - PWM 2 end of duty  level
+    *     - PWM 2 end of period level
+    *     - PWM 3 end of duty  level
+    *     - PWM 3 end of period level
+    *     - PWM 4 end of duty  level
+    *     - PWM 4 end of period level
+    *     - PWM 5 end of duty  level
+    *     - PWM 5 end of period level
+    *     - PWM 6 end of duty  level
+    *     - PWM 6 end of period level
+    *     - PWM 7 end of duty  level
+    *     - PWM 7 end of period level
+
+    *     - CCU Edge Detection 0 level
+    *     - CCU Edge Detection 1 level
+    *     - CCU Edge Detection 2 level
+    *     - CCU Edge Detection 3 level
+    *     - CCU Edge Detection 4 level
+    *     - CCU Edge Detection 5 level
+    *     - CCU Edge Detection 6 level
+    *     - CCU Edge Detection 7 level
+    */
+    hetREG1->PRY = (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U
+                 | (uint32) 0x00000000U;
+
+    /** - Enable interrupts
+    *     - PWM 0 end of duty
+    *     - PWM 0 end of period
+    *     - PWM 1 end of duty
+    *     - PWM 1 end of period
+    *     - PWM 2 end of duty
+    *     - PWM 2 end of period
+    *     - PWM 3 end of duty
+    *     - PWM 3 end of period
+    *     - PWM 4 end of duty
+    *     - PWM 4 end of period
+    *     - PWM 5 end of duty
+    *     - PWM 5 end of period
+    *     - PWM 6 end of duty
+    *     - PWM 6 end of period
+    *     - PWM 7 end of duty
+    *     - PWM 7 end of period
+    *     - CCU Edge Detection 0
+    *     - CCU Edge Detection 1
+    *     - CCU Edge Detection 2
+    *     - CCU Edge Detection 3
+    *     - CCU Edge Detection 4
+    *     - CCU Edge Detection 5
+    *     - CCU Edge Detection 6
+    *     - CCU Edge Detection 7
+    */
+    hetREG1->INTENAC = 0xFFFFFFFFU;
+    hetREG1->INTENAS = (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U
+                     | (uint32) 0x00000000U;
+
+
+   /** - Setup control register
+    *     - Enable output buffers
+    *     - Ignore software breakpoints
+    *     - Master or Slave Clock Mode
+    *     - Enable HET
+    */
+    hetREG1->GCR = ( 0x00000001U 
+                   | (uint32)((uint32)0U << 24U)
+	               | (uint32)((uint32)1U << 16U)
+                   | (0x00020000U));
+
+
+}
+/** @fn void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm)
+*   @brief Start pwm signal
+*   @param[in] hetRAM Pointer to HET RAM:
+*              - hetRAM1: HET1 RAM pointer
+*              - hetRAM2: HET2 RAM pointer
+*   @param[in] pwm Pwm signal:
+*              - pwm0: Pwm 0
+*              - pwm1: Pwm 1
+*              - pwm2: Pwm 2
+*              - pwm3: Pwm 3
+*              - pwm4: Pwm 4
+*              - pwm5: Pwm 5
+*              - pwm6: Pwm 6
+*              - pwm7: Pwm 7
+*
+*   Start the given pwm signal
+*/
+/* SourceId : HET_SourceId_002 */
+/* DesignId : HET_DesignId_002 */
+/* Requirements : HL_SR364 */
+void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm)
+{
+
+   hetRAM->Instruction[(pwm << 1U) + 41U].Control  |= 0x00400000U;
+}
+
+
+/** @fn void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm)
+*   @brief Stop pwm signal
+*   @param[in] hetRAM Pointer to HET RAM:
+*              - hetRAM1: HET1 RAM pointer
+*              - hetRAM2: HET2 RAM pointer
+*   @param[in] pwm Pwm signal:
+*              - pwm0: Pwm 0
+*              - pwm1: Pwm 1
+*              - pwm2: Pwm 2
+*              - pwm3: Pwm 3
+*              - pwm4: Pwm 4
+*              - pwm5: Pwm 5
+*              - pwm6: Pwm 6
+*              - pwm7: Pwm 7
+*
+*   Stop the given pwm signal
+*/
+/* SourceId : HET_SourceId_003 */
+/* DesignId : HET_DesignId_003 */
+/* Requirements : HL_SR365 */
+void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm)
+{
+    hetRAM->Instruction[(pwm << 1U) + 41U].Control  &= ~(uint32)0x00400000U;
+}
+
+
+/** @fn void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty)
+*   @brief Set duty cycle
+*   @param[in] hetRAM Pointer to HET RAM:
+*              - hetRAM1: HET1 RAM pointer
+*              - hetRAM2: HET2 RAM pointer
+*   @param[in] pwm Pwm signal:
+*              - pwm0: Pwm 0
+*              - pwm1: Pwm 1
+*              - pwm2: Pwm 2
+*              - pwm3: Pwm 3
+*              - pwm4: Pwm 4
+*              - pwm5: Pwm 5
+*              - pwm6: Pwm 6
+*              - pwm7: Pwm 7
+*   @param[in] pwmDuty duty cycle in %.
+*
+*   Sets a new duty cycle on the given pwm signal
+*/
+/* SourceId : HET_SourceId_004 */
+/* DesignId : HET_DesignId_004 */
+/* Requirements : HL_SR366 */
+void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty)
+{
+    uint32 action;
+    uint32 pwmPolarity =0U;
+    uint32 pwmPeriod = hetRAM->Instruction[(pwm << 1U) + 42U].Data + 128U;
+    pwmPeriod = pwmPeriod >> 7U;
+
+    if(hetRAM == hetRAM1)
+    {
+        pwmPolarity = s_het1pwmPolarity[pwm];
+    }
+    else
+    {
+    }
+    if (pwmDuty == 0U)
+    {
+        action = (pwmPolarity == 3U) ? 0U : 2U;
+    }
+    else if (pwmDuty >= 100U)
+    {
+        action = (pwmPolarity == 3U) ? 2U : 0U;
+    }
+    else
+    {
+        action = pwmPolarity;
+    }
+
+    hetRAM->Instruction[(pwm << 1U) + 41U].Control = ((hetRAM->Instruction[(pwm << 1U) + 41U].Control) & (~(uint32)(0x00000018U))) | (action << 3U);
+    hetRAM->Instruction[(pwm << 1U) + 41U].Data = (((pwmPeriod * pwmDuty) / 100U) << 7U) + 128U;
+}
+
+
+/** @fn void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal)
+*   @brief Set period
+*   @param[in] hetRAM Pointer to HET RAM:
+*              - hetRAM1: HET1 RAM pointer
+*              - hetRAM2: HET2 RAM pointer
+*   @param[in] pwm Pwm signal:
+*              - pwm0: Pwm 0
+*              - pwm1: Pwm 1
+*              - pwm2: Pwm 2
+*              - pwm3: Pwm 3
+*              - pwm4: Pwm 4
+*              - pwm5: Pwm 5
+*              - pwm6: Pwm 6
+*              - pwm7: Pwm 7
+*   @param[in] signal signal
+               - duty cycle in %.
+*              - period period in us.
+*
+*   Sets a new pwm signal
+*/
+/* SourceId : HET_SourceId_005 */
+/* DesignId : HET_DesignId_005 */
+/* Requirements : HL_SR367 */
+void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal)
+{
+    uint32 action;
+    uint32 pwmPolarity = 0U;
+    float64 pwmPeriod = 0.0F;
+
+    if(hetRAM == hetRAM1)
+    {
+        pwmPeriod = (signal.period * 1000.0F) / 800.000F;
+        pwmPolarity = s_het1pwmPolarity[pwm];
+    }
+    else
+    {
+    }
+    if (signal.duty == 0U)
+    {
+        action = (pwmPolarity == 3U) ? 0U : 2U;
+    }
+    else if (signal.duty >= 100U)
+    {
+        action = (pwmPolarity == 3U) ? 2U : 0U;
+    }
+    else
+    {
+        action = pwmPolarity;
+    }
+
+    hetRAM->Instruction[(pwm << 1U) + 41U].Control = ((hetRAM->Instruction[(pwm << 1U) + 41U].Control) & (~(uint32)(0x00000018U))) | (action << 3U);
+    hetRAM->Instruction[(pwm << 1U) + 41U].Data = ((((uint32)pwmPeriod * signal.duty) / 100U) << 7U ) + 128U;
+    hetRAM->Instruction[(pwm << 1U) + 42U].Data = ((uint32)pwmPeriod << 7U) - 128U;
+
+}
+
+
+/** @fn void pwmGetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal)
+*   @brief Get duty cycle
+*   @param[in] hetRAM Pointer to HET RAM:
+*              - hetRAM1: HET1 RAM pointer
+*              - hetRAM2: HET2 RAM pointer
+*   @param[in] pwm Pwm signal:
+*              - pwm0: Pwm 0
+*              - pwm1: Pwm 1
+*              - pwm2: Pwm 2
+*              - pwm3: Pwm 3
+*              - pwm4: Pwm 4
+*              - pwm5: Pwm 5
+*              - pwm6: Pwm 6
+*              - pwm7: Pwm 7
+*   @param[in] signal signal
+*              - duty cycle in %.
+*              - period period in us.
+*
+*   Gets current signal of the given pwm signal.
+*/
+/* SourceId : HET_SourceId_006 */
+/* DesignId : HET_DesignId_006 */
+/* Requirements : HL_SR368 */
+void pwmGetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t* signal)
+{
+    uint32    pwmDuty   = (hetRAM->Instruction[(pwm << 1U) + 41U].Data - 128U) >> 7U;
+    uint32    pwmPeriod = (hetRAM->Instruction[(pwm << 1U) + 42U].Data + 128U) >> 7U;
+
+    signal->duty   = (pwmDuty * 100U) / pwmPeriod;
+
+    if(hetRAM == hetRAM1)
+    {
+        signal->period = ((float64)pwmPeriod * 800.000F) / 1000.0F;
+    }
+    else
+    {
+        signal->period = ((float64)pwmPeriod * 800.000F) / 1000.0F;
+    }
+}
+
+/** @fn void pwmEnableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification)
+*   @brief Enable pwm notification
+*   @param[in] hetREG Pointer to HET Module:
+*              - hetREG1: HET1 Module pointer
+*              - hetREG2: HET2 Module pointer
+*   @param[in] pwm Pwm signal:
+*              - pwm0: Pwm 0
+*              - pwm1: Pwm 1
+*              - pwm2: Pwm 2
+*              - pwm3: Pwm 3
+*              - pwm4: Pwm 4
+*              - pwm5: Pwm 5
+*              - pwm6: Pwm 6
+*              - pwm7: Pwm 7
+*   @param[in] notification Pwm notification:
+*              - pwmEND_OF_DUTY:   Notification on end of duty
+*              - pwmEND_OF_PERIOD: Notification on end of end period
+*              - pwmEND_OF_BOTH:   Notification on end of both duty and period
+*/
+/* SourceId : HET_SourceId_007 */
+/* DesignId : HET_DesignId_007 */
+/* Requirements : HL_SR369 */
+void pwmEnableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification)
+{
+    hetREG->FLG     = notification << (pwm << 1U);
+    hetREG->INTENAS = notification << (pwm << 1U);
+}
+
+
+/** @fn void pwmDisableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification)
+*   @brief Enable pwm notification
+*   @param[in] hetREG Pointer to HET Module:
+*              - hetREG1: HET1 Module pointer
+*              - hetREG2: HET2 Module pointer
+*   @param[in] pwm Pwm signal:
+*              - pwm0: Pwm 0
+*              - pwm1: Pwm 1
+*              - pwm2: Pwm 2
+*              - pwm3: Pwm 3
+*              - pwm4: Pwm 4
+*              - pwm5: Pwm 5
+*              - pwm6: Pwm 6
+*              - pwm7: Pwm 7
+*   @param[in] notification Pwm notification:
+*              - pwmEND_OF_DUTY:   Notification on end of duty
+*              - pwmEND_OF_PERIOD: Notification on end of end period
+*              - pwmEND_OF_BOTH:   Notification on end of both duty and period
+*/
+/* SourceId : HET_SourceId_008 */
+/* DesignId : HET_DesignId_008 */
+/* Requirements : HL_SR370 */
+void pwmDisableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification)
+{
+    hetREG->INTENAC = notification << (pwm << 1U);
+}
+
+
+/** @fn void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32 edge)
+*   @brief Resets edge counter to 0
+*   @param[in] hetRAM Pointer to HET RAM:
+*              - hetRAM1: HET1 RAM pointer
+*              - hetRAM2: HET2 RAM pointer
+*   @param[in] edge Edge signal:
+*              - edge0: Edge 0
+*              - edge1: Edge 1
+*              - edge2: Edge 2
+*              - edge3: Edge 3
+*              - edge4: Edge 4
+*              - edge5: Edge 5
+*              - edge6: Edge 6
+*              - edge7: Edge 7
+*
+*   Reset edge counter to 0.
+*/
+/* SourceId : HET_SourceId_009 */
+/* DesignId : HET_DesignId_009 */
+/* Requirements : HL_SR372 */
+void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32 edge)
+{
+    hetRAM->Instruction[edge + 17U].Data = 0U;
+}
+
+
+/** @fn uint32 edgeGetCounter(hetRAMBASE_t * hetRAM, uint32 edge)
+*   @brief Get current edge counter value
+*   @param[in] hetRAM Pointer to HET RAM:
+*              - hetRAM1: HET1 RAM pointer
+*              - hetRAM2: HET2 RAM pointer
+*   @param[in] edge Edge signal:
+*              - edge0: Edge 0
+*              - edge1: Edge 1
+*              - edge2: Edge 2
+*              - edge3: Edge 3
+*              - edge4: Edge 4
+*              - edge5: Edge 5
+*              - edge6: Edge 6
+*              - edge7: Edge 7
+*
+*   Gets current edge counter value.
+*/
+/* SourceId : HET_SourceId_010 */
+/* DesignId : HET_DesignId_010 */
+/* Requirements : HL_SR373 */
+uint32 edgeGetCounter(hetRAMBASE_t * hetRAM, uint32 edge)
+{
+    return hetRAM->Instruction[edge + 17U].Data >> 7U;
+}
+
+
+/** @fn void edgeEnableNotification(hetBASE_t * hetREG, uint32 edge)
+*   @brief Enable edge notification
+*   @param[in] hetREG Pointer to HET Module:
+*              - hetREG1: HET1 Module pointer
+*              - hetREG2: HET2 Module pointer
+*   @param[in] edge Edge signal:
+*              - edge0: Edge 0
+*              - edge1: Edge 1
+*              - edge2: Edge 2
+*              - edge3: Edge 3
+*              - edge4: Edge 4
+*              - edge5: Edge 5
+*              - edge6: Edge 6
+*              - edge7: Edge 7
+*/
+/* SourceId : HET_SourceId_011 */
+/* DesignId : HET_DesignId_011 */
+/* Requirements : HL_SR374 */
+void edgeEnableNotification(hetBASE_t * hetREG, uint32 edge)
+{
+    hetREG->FLG     = (uint32)0x20000U << edge;
+    hetREG->INTENAS = (uint32)0x20000U << edge;
+}
+
+
+/** @fn void edgeDisableNotification(hetBASE_t * hetREG, uint32 edge)
+*   @brief Enable edge notification
+*   @param[in] hetREG Pointer to HET Module:
+*              - hetREG1: HET1 Module pointer
+*              - hetREG2: HET2 Module pointer
+*   @param[in] edge Edge signal:
+*              - edge0: Edge 0
+*              - edge1: Edge 1
+*              - edge2: Edge 2
+*              - edge3: Edge 3
+*              - edge4: Edge 4
+*              - edge5: Edge 5
+*              - edge6: Edge 6
+*              - edge7: Edge 7
+*/
+/* SourceId : HET_SourceId_012 */
+/* DesignId : HET_DesignId_012 */
+/* Requirements : HL_SR375 */
+void edgeDisableNotification(hetBASE_t * hetREG, uint32 edge)
+{
+    hetREG->INTENAC = (uint32)0x20000U << edge;
+}
+
+
+/** @fn void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t signal)
+*   @brief Get capture signal
+*   @param[in] hetRAM Pointer to HET RAM:
+*              - hetRAM1: HET1 RAM pointer
+*              - hetRAM2: HET2 RAM pointer
+*   @param[in] cap captured signal:
+*              - cap0: Captured signal 0
+*              - cap1: Captured signal 1
+*              - cap2: Captured signal 2
+*              - cap3: Captured signal 3
+*              - cap4: Captured signal 4
+*              - cap5: Captured signal 5
+*              - cap6: Captured signal 6
+*              - cap7: Captured signal 7
+*   @param[in] signal signal
+*              - duty cycle in %.
+*              - period period in us.
+*
+*   Gets current signal of the given capture signal.
+*/
+/* SourceId : HET_SourceId_013 */
+/* DesignId : HET_DesignId_013 */
+/* Requirements : HL_SR377 */
+void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t *signal)
+{
+    uint32    pwmDuty   = (hetRAM->Instruction[(cap << 1U) + 25U].Data) >> 7U;
+    uint32    pwmPeriod = (hetRAM->Instruction[(cap << 1U) + 26U].Data) >> 7U;
+
+    signal->duty   = (pwmDuty * 100U) / pwmPeriod;
+
+    if( hetRAM == hetRAM1)
+    {
+        signal->period = ((float64)pwmPeriod * 800.000F) / 1000.0F;
+    }
+    else
+    {
+        signal->period = ((float64)pwmPeriod * 800.000F) / 1000.0F;
+    }
+}
+
+
+/** @fn void hetResetTimestamp(hetRAMBASE_t *hetRAM)
+*   @brief Resets timestamp
+*   @param[in] hetRAM Pointer to HET RAM:
+*              - hetRAM1: HET1 RAM pointer
+*              - hetRAM2: HET2 RAM pointer
+*
+*   Resets loop count based timestamp.
+*/
+/* SourceId : HET_SourceId_014 */
+/* DesignId : HET_DesignId_014 */
+/* Requirements : HL_SR378 */
+void hetResetTimestamp(hetRAMBASE_t * hetRAM)
+{
+    hetRAM->Instruction[0U].Data = 0U;
+}
+
+
+/** @fn uint32 hetGetTimestamp(hetRAMBASE_t *hetRAM)
+*   @brief Returns timestamp
+*
+*   Returns loop count based timestamp.
+*/
+/* SourceId : HET_SourceId_015 */
+/* DesignId : HET_DesignId_015 */
+/* Requirements : HL_SR379 */
+uint32 hetGetTimestamp(hetRAMBASE_t * hetRAM)
+{
+    return hetRAM->Instruction[57U].Data;
+}
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+
+/** @fn void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the HET1 configuration registers
+*
+*   @param[in] *config_reg: pointer to the struct to which the initial or current
+*                           value of the configuration registers need to be stored
+*   @param[in] type:    whether initial or current value of the configuration registers need to be stored
+*                       - InitialValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*                       - CurrentValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type')
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : HET_SourceId_016 */
+/* DesignId : HET_DesignId_016 */
+/* Requirements : HL_SR379 */
+void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_GCR     = HET1_GCR_CONFIGVALUE;
+        config_reg->CONFIG_PFR     = HET1_PFR_CONFIGVALUE;
+        config_reg->CONFIG_INTENAS = HET1_INTENAS_CONFIGVALUE;
+        config_reg->CONFIG_INTENAC = HET1_INTENAC_CONFIGVALUE;
+        config_reg->CONFIG_PRY     = HET1_PRY_CONFIGVALUE;
+        config_reg->CONFIG_AND     = HET1_AND_CONFIGVALUE;
+        config_reg->CONFIG_HRSH    = HET1_HRSH_CONFIGVALUE;
+        config_reg->CONFIG_XOR     = HET1_XOR_CONFIGVALUE;
+        config_reg->CONFIG_DIR     = HET1_DIR_CONFIGVALUE;
+        config_reg->CONFIG_PDR     = HET1_PDR_CONFIGVALUE;
+        config_reg->CONFIG_PULDIS  = HET1_PULDIS_CONFIGVALUE;
+        config_reg->CONFIG_PSL     = HET1_PSL_CONFIGVALUE;
+        config_reg->CONFIG_PCR     = HET1_PCR_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_GCR     = hetREG1->GCR;
+        config_reg->CONFIG_PFR     = hetREG1->PFR;
+        config_reg->CONFIG_INTENAS = hetREG1->INTENAS;
+        config_reg->CONFIG_INTENAC = hetREG1->INTENAC;
+        config_reg->CONFIG_PRY     = hetREG1->PRY;
+        config_reg->CONFIG_AND     = hetREG1->AND;
+        config_reg->CONFIG_HRSH    = hetREG1->HRSH;
+        config_reg->CONFIG_XOR     = hetREG1->XOR;
+        config_reg->CONFIG_DIR     = hetREG1->DIR;
+        config_reg->CONFIG_PDR     = hetREG1->PDR;
+        config_reg->CONFIG_PULDIS  = hetREG1->PULDIS;
+        config_reg->CONFIG_PSL     = hetREG1->PSL;
+        config_reg->CONFIG_PCR     = hetREG1->PCR;
+    }
+}
+
+
+
diff --git a/src/arch/rm46l8lp/halcogen/mibspi.c b/src/arch/rm46l8lp/halcogen/mibspi.c
new file mode 100644
index 0000000..c8adcef
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/mibspi.c
@@ -0,0 +1,922 @@
+/** @file mibspi.c
+*   @brief MIBSPI Driver Implementation File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "mibspi.h"
+#include "sys_vim.h"
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void mibspiInit(void)
+*   @brief Initializes the MIBSPI Driver
+*
+*   This function initializes the MIBSPI module.
+*/
+/* SourceId : MIBSPI_SourceId_001 */
+/* DesignId : MIBSPI_DesignId_001 */
+/* Requirements : HL_SR153 */
+void mibspiInit(void)
+{
+uint32 i ;
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+
+     /** @b initialize @b MIBSPI3 */
+
+    /** bring MIBSPI out of reset */
+    mibspiREG3->GCR0 = 0U;
+    mibspiREG3->GCR0 = 1U;
+
+    /** enable MIBSPI3 multibuffered mode and enable buffer RAM */
+    mibspiREG3->MIBSPIE = (mibspiREG3->MIBSPIE & 0xFFFFFFFEU) | 1U;
+
+    /** MIBSPI3 master mode and clock configuration */
+    mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U)  /* CLOKMOD */
+                  | 1U);  /* MASTER */
+
+    /** MIBSPI3 enable pin configuration */
+    mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U);  /* ENABLE HIGHZ */
+
+    /** - Delays */
+    mibspiREG3->DELAY = (uint32)((uint32)0U << 24U)  /* C2TDELAY */
+                      | (uint32)((uint32)0U << 16U)  /* T2CDELAY */
+                      | (uint32)((uint32)0U << 8U)   /* T2EDELAY */
+                      | (uint32)((uint32)0U << 0U);  /* C2EDELAY */
+
+    /** - Data Format 0 */
+    mibspiREG3->FMT0 = (uint32)((uint32)0U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)0U << 16U)  /* clock phase */
+                     | (uint32)((uint32)79U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)16U << 0U); /* data word length */
+
+    /** - Data Format 1 */
+    mibspiREG3->FMT1 = (uint32)((uint32)0U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)0U << 16U)  /* clock phase */
+                     | (uint32)((uint32)79U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)16U << 0U); /* data word length */
+
+    /** - Data Format 2 */
+    mibspiREG3->FMT2 = (uint32)((uint32)0U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)0U << 16U)  /* clock phase */
+                     | (uint32)((uint32)79U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)16U << 0U); /* data word length */
+
+    /** - Data Format 3 */
+    mibspiREG3->FMT3 = (uint32)((uint32)0U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)0U << 16U)  /* clock phase */
+                     | (uint32)((uint32)79U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)16U << 0U); /* data word length */
+
+    /** - Default Chip Select */
+    mibspiREG3->DEF = (uint32)(0xFFU);
+
+    /** - wait for buffer initialization complete before accessing MibSPI registers */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ((mibspiREG3->FLG & 0x01000000U) != 0U)
+    {
+    } /* Wait */
+
+    /** enable MIBSPI RAM Parity */
+    mibspiREG3->UERRCTRL = (mibspiREG3->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U);
+
+    /** - initialize transfer groups */
+    mibspiREG3->TGCTRL[0U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)0U << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[1U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)8U << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[2U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U) << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[3U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[4U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[5U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[6U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[7U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U);  /* start buffer */
+
+
+    mibspiREG3->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U;
+
+    mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
+
+    /** - initialize buffer ram */
+    {
+        i = 0U;
+
+#if (8U > 0U)
+        {
+
+#if (8U > 1U)
+
+            while (i < (8U-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU);  /* chip select */
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU);  /* chip select */
+
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U+0U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU);  /* chip select */
+            i++;
+        }
+#endif
+    }
+
+    /** - set interrupt levels */
+    mibspiREG3->LVL = (uint32)((uint32)0U << 9U)  /* TXINT */
+                    | (uint32)((uint32)0U << 8U)  /* RXINT */
+                    | (uint32)((uint32)0U << 6U)  /* OVRNINT */
+                    | (uint32)((uint32)0U << 4U)  /* BITERR */
+                    | (uint32)((uint32)0U << 3U)  /* DESYNC */
+                    | (uint32)((uint32)0U << 2U)  /* PARERR */
+                    | (uint32)((uint32)0U << 1U)  /* TIMEOUT */
+                    | (uint32)((uint32)0U << 0U); /* DLENERR */
+
+    /** - clear any pending interrupts */
+    mibspiREG3->FLG |= 0xFFFFU;
+
+    /** - enable interrupts */
+    mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U)
+                     | (uint32)((uint32)0U << 9U)  /* TXINT */
+                     | (uint32)((uint32)0U << 8U)  /* RXINT */
+                     | (uint32)((uint32)0U << 6U)  /* OVRNINT */
+                     | (uint32)((uint32)0U << 4U)  /* BITERR */
+                     | (uint32)((uint32)0U << 3U)  /* DESYNC */
+                     | (uint32)((uint32)0U << 2U)  /* PARERR */
+                     | (uint32)((uint32)0U << 1U)  /* TIMEOUT */
+                     | (uint32)((uint32)0U << 0U); /* DLENERR */
+
+    /** @b initialize @b MIBSPI3 @b Port */
+
+    /** - MIBSPI3 Port output values */
+    mibspiREG3->PC3 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)1U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)1U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)1U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)1U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 9U)  /* CLK */
+                    | (uint32)((uint32)0U << 10U)  /* SIMO */
+                    | (uint32)((uint32)0U << 11U); /* SOMI */
+
+    /** - MIBSPI3 Port direction */
+    mibspiREG3->PC1 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)1U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)1U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)1U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)1U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)1U << 9U)  /* CLK */
+                    | (uint32)((uint32)1U << 10U)  /* SIMO */
+                    | (uint32)((uint32)0U << 11U); /* SOMI */
+
+    /** - MIBSPI3 Port open drain enable */
+    mibspiREG3->PC6 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)0U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)0U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)0U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)0U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 9U)  /* CLK */
+                    | (uint32)((uint32)0U << 10U)  /* SIMO */
+                    | (uint32)((uint32)0U << 11U); /* SOMI */
+
+
+    /** - MIBSPI3 Port pullup / pulldown selection */
+    mibspiREG3->PC8 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)1U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)1U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)1U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)1U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)1U << 8U)  /* ENA */
+                    | (uint32)((uint32)1U << 9U)  /* CLK */
+                    | (uint32)((uint32)1U << 10U)  /* SIMO */
+                    | (uint32)((uint32)1U << 11U); /* SOMI */
+
+
+    /** - MIBSPI3 Port pullup / pulldown enable*/
+    mibspiREG3->PC7 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)0U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)0U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)0U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)0U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 9U)  /* CLK */
+                    | (uint32)((uint32)0U << 10U)  /* SIMO */
+                    | (uint32)((uint32)0U << 11U); /* SOMI */
+
+
+    /* MIBSPI3 set all pins to functional */
+    mibspiREG3->PC0 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)0U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)0U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)0U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)0U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)1U << 8U)  /* ENA */
+                    | (uint32)((uint32)1U << 9U)  /* CLK */
+                    | (uint32)((uint32)1U << 10U)  /* SIMO */
+                    | (uint32)((uint32)1U << 11U); /* SOMI */
+
+    /** - Finally start MIBSPI3 */
+    mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
+
+
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+}
+
+
+/** @fn void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port)
+*   @brief Change functional behavior of pins at runtime.
+*   @param[in] mibspi   - mibspi module base address
+*   @param[in] port  - Value to write to PC0 register
+*
+*   Change the value of the PC0 register at runtime, this allows to
+*   dynamically change the functionality of the MIBSPI pins between functional
+*   and GIO mode.
+*/
+/* SourceId : MIBSPI_SourceId_002 */
+/* DesignId : MIBSPI_DesignId_002 */
+/* Requirements : HL_SR154 */
+void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port)
+{
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+    mibspi->PC0 = port;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+}
+
+
+/** @fn void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data)
+*   @brief Set Buffer Data
+*   @param[in] mibspi   - Spi module base address
+*   @param[in] group - Transfer group (0..7)
+*   @param[in] data  - new data for transfer group
+*
+*   This function updates the data for the specified transfer group,
+*   the length of the data must match the length of the transfer group.
+*/
+/* SourceId : MIBSPI_SourceId_003 */
+/* DesignId : MIBSPI_DesignId_003 */
+/* Requirements : HL_SR155 */
+void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data)
+{
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+    mibspiRAM_t *ram    = (mibspi == mibspiREG1) ? mibspiRAM1 : ((mibspi == mibspiREG3) ? mibspiRAM3 : mibspiRAM5);
+    uint32 start  = (mibspi->TGCTRL[group] >> 8U) & 0xFFU;
+    uint32 end    = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU);
+
+    if (end == 0U) {end = 128U;}
+
+    while (start < end)
+    {
+    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+        ram->tx[start].data = *data;
+        /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
+        data++;
+        start++;
+    }
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+}
+
+
+/** @fn void mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data)
+*   @brief Retrieves Buffer Data from receive buffer
+*   @param[in]  mibspi   - Spi module base address
+*   @param[in]  group - Transfer group (0..7)
+*   @param[out] data  - pointer to data array
+*
+*   @return error flags from data buffer, if there was a receive error on
+*           one of the buffers this will be reflected in the return value.
+*
+*   This function transfers the data from the specified transfer group receive
+*   buffers to the data array,  the length of the data must match the length
+*   of the transfer group.
+*/
+/* SourceId : MIBSPI_SourceId_004 */
+/* DesignId : MIBSPI_DesignId_004 */
+/* Requirements : HL_SR156 */
+uint32 mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data)
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+    mibspiRAM_t *ram    = (mibspi == mibspiREG1) ? mibspiRAM1 : ((mibspi == mibspiREG3) ? mibspiRAM3 : mibspiRAM5);
+    uint32 start  = (mibspi->TGCTRL[group] >> 8U) & 0xFFU;
+    uint32 end    = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU);
+    uint16 mibspiFlags  = 0U;
+	uint32 ret;
+    if (end == 0U) {end = 128U;}
+
+    while (start < end)
+    {
+        mibspiFlags  |= ram->rx[start].flags;
+        /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+        *data = ram->rx[start].data;
+        /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
+        data++;
+        start++;
+    }
+
+	ret = ((uint32)mibspiFlags >> 8U) & 0x5FU;
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+    return ret;
+}
+
+
+/** @fn void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group)
+*   @brief Transmit Transfer Group
+*   @param[in] mibspi   - Spi module base address
+*   @param[in] group - Transfer group (0..7)
+*
+*   Initiates a transfer for the specified transfer group.
+*/
+/* SourceId : MIBSPI_SourceId_005 */
+/* DesignId : MIBSPI_DesignId_005 */
+/* Requirements : HL_SR157 */
+void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group)
+{
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+    mibspi->TGCTRL[group] |= 0x80000000U;
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+}
+
+
+/** @fn boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group)
+*   @brief Check for Transfer Group Ready
+*   @param[in] mibspi   - Spi module base address
+*   @param[in] group - Transfer group (0..7)
+*
+*   @return TRUE is transfer complete, otherwise FALSE.
+*
+*   Checks to see if the transfer for the specified transfer group
+*   has finished.
+*/
+/* SourceId : MIBSPI_SourceId_006 */
+/* DesignId : MIBSPI_DesignId_006 */
+/* Requirements : HL_SR158 */
+boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group)
+{
+    boolean status;
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+    if(((((mibspi->TGINTFLG & 0xFFFF0000U) >> 16U)>> group) & 1U) == 1U)
+    {
+       mibspi->TGINTFLG = (mibspi->TGINTFLG & 0x0000FFFFU) | ((uint32)((uint32)1U << group) << 16U);
+       status = TRUE;
+    }
+    else
+    {
+       status = FALSE;
+    }
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+    return (status);
+}
+
+
+/** @fn void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype)
+*   @brief Enable Loopback mode for self test
+*   @param[in] mibspi        - Mibspi module base address
+*   @param[in] Loopbacktype  - Digital or Analog
+*
+*   This function enables the Loopback mode for self test.
+*/
+/* SourceId : MIBSPI_SourceId_007 */
+/* DesignId : MIBSPI_DesignId_009 */
+/* Requirements : HL_SR161 */
+void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype)
+{
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+    /* Clear Loopback incase enabled already */
+    mibspi->IOLPKTSTCR = 0U;
+
+    /* Enable Loopback either in Analog or Digital Mode */
+    mibspi->IOLPKTSTCR = (uint32)0x00000A00U
+                       | (uint32)((uint32)Loopbacktype << 1U);
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+}
+
+/** @fn void mibspiDisableLoopback(mibspiBASE_t *mibspi)
+*   @brief Enable Loopback mode for self test
+*   @param[in] mibspi        - Mibspi module base address
+*
+*   This function disable the Loopback mode.
+*/
+/* SourceId : MIBSPI_SourceId_008 */
+/* DesignId : MIBSPI_DesignId_010 */
+/* Requirements : HL_SR162 */
+void mibspiDisableLoopback(mibspiBASE_t *mibspi)
+{
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+    /* Disable Loopback Mode */
+    mibspi->IOLPKTSTCR = 0x00000500U;
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+}
+
+/** @fn void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT)
+*   @brief Set the Pmode for the selected Data Format register
+*   @param[in] mibspi   - Mibspi module base address
+*   @param[in] Pmode    - Mibspi Parellel mode
+*                            PMODE_NORMAL
+*                            PMODE_2_DATALINE
+*                            PMODE_4_DATALINE
+*                            PMODE_8_DATALINE
+*   @param[in] DFMT     - Mibspi Data Format register
+*                            DATA_FORMAT0
+*                            DATA_FORMAT1
+*                            DATA_FORMAT2
+*                            DATA_FORMAT3
+*
+*   This function sets the Pmode for the selected Data Format register.
+*/
+/* SourceId : MIBSPI_SourceId_009 */
+/* DesignId : MIBSPI_DesignId_011 */
+/* Requirements : HL_SR524 */
+void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT)
+{
+    uint32 pmctrl_reg;
+    /* Set the Pmode for the selected Data Format register */
+    pmctrl_reg     = (mibspi->PMCTRL & (~(uint32)((uint32)0xFFU << (8U * DFMT))));
+    mibspi->PMCTRL = (pmctrl_reg | (uint32)((uint32)Pmode <<  ((8U * DFMT))));
+
+}
+
+/** @fn void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level)
+*   @brief Enable Transfer Group interrupt
+*   @param[in] mibspi   - Spi module base address
+*   @param[in] group - Transfer group (0..7)
+*   @param[in] level - Interrupt level
+*
+*   This function enables the transfer group finished interrupt.
+*/
+/* SourceId : MIBSPI_SourceId_010 */
+/* DesignId : MIBSPI_DesignId_007 */
+/* Requirements : HL_SR159 */
+void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level)
+{
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+    if (level != 0U)
+    {
+        mibspi->TGITLVST = (mibspi->TGITLVST & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U);
+    }
+    else
+    {
+        mibspi->TGITLVCR = (mibspi->TGITLVCR & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U);
+    }
+    mibspi->TGITENST = (mibspi->TGITENST & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U);
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+}
+
+
+/** @fn void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group)
+*   @brief Disable Transfer Group interrupt
+*   @param[in] mibspi   - Spi module base address
+*   @param[in] group - Transfer group (0..7)
+*
+*   This function disables the transfer group finished interrupt.
+*/
+/* SourceId : MIBSPI_SourceId_011 */
+/* DesignId : MIBSPI_DesignId_008 */
+/* Requirements : HL_SR160 */
+void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group)
+{
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+    mibspi->TGITENCR = (mibspi->TGITENCR & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U);
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+}
+
+
+/** @fn void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*    @param[in] *config_reg: pointer to the struct to which the initial or current
+*                           value of the configuration registers need to be stored
+*    @param[in] type:     whether initial or current value of the configuration registers need to be stored
+*                        - InitialValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*                        - CurrentValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type')
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : MIBSPI_SourceId_013 */
+/* DesignId : MIBSPI_DesignId_012 */
+/* Requirements : HL_SR166 */
+void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_GCR1       = MIBSPI3_GCR1_CONFIGVALUE;
+        config_reg->CONFIG_INT0       = MIBSPI3_INT0_CONFIGVALUE;
+        config_reg->CONFIG_LVL        = MIBSPI3_LVL_CONFIGVALUE;
+        config_reg->CONFIG_PCFUN      = MIBSPI3_PCFUN_CONFIGVALUE;
+        config_reg->CONFIG_PCDIR      = MIBSPI3_PCDIR_CONFIGVALUE;
+        config_reg->CONFIG_PCPDR      = MIBSPI3_PCPDR_CONFIGVALUE;
+        config_reg->CONFIG_PCDIS      = MIBSPI3_PCDIS_CONFIGVALUE;
+        config_reg->CONFIG_PCPSL      = MIBSPI3_PCPSL_CONFIGVALUE;
+        config_reg->CONFIG_DELAY      = MIBSPI3_DELAY_CONFIGVALUE;
+        config_reg->CONFIG_FMT0       = MIBSPI3_FMT0_CONFIGVALUE;
+        config_reg->CONFIG_FMT1       = MIBSPI3_FMT1_CONFIGVALUE;
+        config_reg->CONFIG_FMT2       = MIBSPI3_FMT2_CONFIGVALUE;
+        config_reg->CONFIG_FMT3       = MIBSPI3_FMT3_CONFIGVALUE;
+        config_reg->CONFIG_MIBSPIE    = MIBSPI3_MIBSPIE_CONFIGVALUE;
+        config_reg->CONFIG_LTGPEND    = MIBSPI3_LTGPEND_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[0U] = MIBSPI3_TGCTRL0_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[1U] = MIBSPI3_TGCTRL1_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[2U] = MIBSPI3_TGCTRL2_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[3U] = MIBSPI3_TGCTRL3_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[4U] = MIBSPI3_TGCTRL4_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[5U] = MIBSPI3_TGCTRL5_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[6U] = MIBSPI3_TGCTRL6_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[7U] = MIBSPI3_TGCTRL7_CONFIGVALUE;
+        config_reg->CONFIG_UERRCTRL   = MIBSPI3_UERRCTRL_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_GCR1       = mibspiREG3->GCR1;
+        config_reg->CONFIG_INT0       = mibspiREG3->INT0;
+        config_reg->CONFIG_LVL        = mibspiREG3->LVL;
+        config_reg->CONFIG_PCFUN      = mibspiREG3->PC0;
+        config_reg->CONFIG_PCDIR      = mibspiREG3->PC1;
+        config_reg->CONFIG_PCPDR      = mibspiREG3->PC6;
+        config_reg->CONFIG_PCDIS      = mibspiREG3->PC7;
+        config_reg->CONFIG_PCPSL      = mibspiREG3->PC8;
+        config_reg->CONFIG_DELAY      = mibspiREG3->DELAY;
+        config_reg->CONFIG_FMT0       = mibspiREG3->FMT0;
+        config_reg->CONFIG_FMT1       = mibspiREG3->FMT1;
+        config_reg->CONFIG_FMT2       = mibspiREG3->FMT2;
+        config_reg->CONFIG_FMT3       = mibspiREG3->FMT3;
+        config_reg->CONFIG_MIBSPIE    = mibspiREG3->MIBSPIE;
+        config_reg->CONFIG_LTGPEND    = mibspiREG3->LTGPEND;
+        config_reg->CONFIG_TGCTRL[0U] = mibspiREG3->TGCTRL[0U];
+        config_reg->CONFIG_TGCTRL[1U] = mibspiREG3->TGCTRL[1U];
+        config_reg->CONFIG_TGCTRL[2U] = mibspiREG3->TGCTRL[2U];
+        config_reg->CONFIG_TGCTRL[3U] = mibspiREG3->TGCTRL[3U];
+        config_reg->CONFIG_TGCTRL[4U] = mibspiREG3->TGCTRL[4U];
+        config_reg->CONFIG_TGCTRL[5U] = mibspiREG3->TGCTRL[5U];
+        config_reg->CONFIG_TGCTRL[6U] = mibspiREG3->TGCTRL[6U];
+        config_reg->CONFIG_TGCTRL[7U] = mibspiREG3->TGCTRL[7U];
+        config_reg->CONFIG_UERRCTRL   = mibspiREG3->UERRCTRL;
+    }
+}
+
+
+
+
+
+
diff --git a/src/arch/rm46l8lp/halcogen/notification.c b/src/arch/rm46l8lp/halcogen/notification.c
new file mode 100644
index 0000000..3371143
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/notification.c
@@ -0,0 +1,228 @@
+/** @file notification.c 
+*   @brief User Notification Definition File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file  defines  empty  notification  routines to avoid
+*   linker errors, Driver expects user to define the notification. 
+*   The user needs to either remove this file and use their custom 
+*   notification function or place their code sequence in this file 
+*   between the provided USER CODE BEGIN and USER CODE END.
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* Include Files */
+
+#include "esm.h"
+#include "sys_selftest.h"
+#include "adc.h"
+#include "gio.h"
+#include "mibspi.h"
+#include "sci.h"
+#include "het.h"
+#include "rti.h"
+#include "sys_dma.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+#pragma WEAK(esmGroup1Notification)
+void esmGroup1Notification(uint32 channel)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+#pragma WEAK(esmGroup2Notification)
+void esmGroup2Notification(uint32 channel)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+#pragma WEAK(memoryPort0TestFailNotification)
+void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+#pragma WEAK(memoryPort1TestFailNotification)
+void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+#pragma WEAK(rtiNotification)
+void rtiNotification(uint32 notification)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+#pragma WEAK(adcNotification)
+void adcNotification(adcBASE_t *adc, uint32 group)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+#pragma WEAK(gioNotification)
+void gioNotification(gioPORT_t *port, uint32 bit)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+#pragma WEAK(mibspiNotification)
+void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+#pragma WEAK(mibspiGroupNotification)
+void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+}
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+#pragma WEAK(sciNotification)
+void sciNotification(sciBASE_t *sci, uint32 flags)     
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+#pragma WEAK(pwmNotification)
+void pwmNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+#pragma WEAK(edgeNotification)
+void edgeNotification(hetBASE_t * hetREG,uint32 edge)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+#pragma WEAK(hetNotification)
+void hetNotification(hetBASE_t *het, uint32 offset)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (53) */
+/* USER CODE END */
+
+#pragma WEAK(dmaGroupANotification)
+void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (54) */
+/* USER CODE END */
+}
+/* USER CODE BEGIN (55) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (58) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (60) */
+/* USER CODE END */
diff --git a/src/arch/rm46l8lp/halcogen/pinmux.c b/src/arch/rm46l8lp/halcogen/pinmux.c
new file mode 100644
index 0000000..aa37535
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/pinmux.c
@@ -0,0 +1,367 @@
+/** @file pinmux.c 
+*   @brief PINMUX Driver Implementation File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* Include Files */
+
+#include "pinmux.h"
+
+/*LDRA_INSPECTWINDOW 50 */
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */
+/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */
+/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */
+/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */
+/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */
+/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */
+/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */
+/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */
+#define PINMUX_SET(REG, PINNUM, MUX)                                \
+            (pinMuxReg->PINMMR##REG = (pinMuxReg->PINMMR##REG & PINMUX_PIN_##PINNUM##_MASK) | (PINMUX_PIN_##PINNUM##_##MUX))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */
+#define PINMUX_GATE_EMIF_CLK_ENABLE(state)      \
+            (pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | (PINMUX_GATE_EMIF_CLK_##state))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */
+#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state)  \
+            (pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ALT_ADC_TRIGGER_SELECT(num)  \
+            (pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETHERNET_SELECT(interface)   \
+            (pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM1_EQEPERR_ENABLE(interface)     \
+            (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM1_MASK) | (PINMUX_ETPWM1_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM2_EQEPERR_ENABLE(interface)     \
+            (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM2_MASK) | (PINMUX_ETPWM2_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM3_EQEPERR_ENABLE(interface)     \
+            (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM3_MASK) | (PINMUX_ETPWM3_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM4_EQEPERR_ENABLE(interface)     \
+            (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM4_MASK) | (PINMUX_ETPWM4_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM5_EQEPERR_ENABLE(interface)     \
+            (pinMuxReg->PINMMR42 = (pinMuxReg->PINMMR42 & PINMUX_ETPWM5_MASK) | (PINMUX_ETPWM5_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM6_EQEPERR_ENABLE(interface)     \
+            (pinMuxReg->PINMMR42 = (pinMuxReg->PINMMR42 & PINMUX_ETPWM6_MASK) | (PINMUX_ETPWM6_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM7_EQEPERR_ENABLE(interface)     \
+            (pinMuxReg->PINMMR42 = (pinMuxReg->PINMMR42 & PINMUX_ETPWM7_MASK) | (PINMUX_ETPWM7_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM_TZ1_ENABLE(interface)      \
+            (pinMuxReg->PINMMR46 = (pinMuxReg->PINMMR46 & PINMUX_TZ1_SHIFT) | (PINMUX_TZ1_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM_TZ2_ENABLE(interface)      \
+            (pinMuxReg->PINMMR46 = (pinMuxReg->PINMMR46 & PINMUX_TZ2_SHIFT) | (PINMUX_TZ2_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM_TZ3_ENABLE(interface)      \
+            (pinMuxReg->PINMMR47 = (pinMuxReg->PINMMR47 & PINMUX_TZ3_SHIFT) | (PINMUX_TZ3_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM_EPWM1SYNCI_ENABLE(interface)       \
+            (pinMuxReg->PINMMR47 = (pinMuxReg->PINMMR47 & PINMUX_EPWM1SYNCI_SHIFT) | (PINMUX_EPWM1SYNCI_##interface))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE(state)       \
+            (pinMuxReg->PINMMR36 = (pinMuxReg->PINMMR36 & PINMUX_ETPWM_TIME_BASE_SYNC_MASK) | (PINMUX_ETPWM_TIME_BASE_SYNC_##state))
+
+/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */
+/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ 
+#define PINMUX_ETPWM_TBCLK_SYNC_ENABLE(state)       \
+            (pinMuxReg->PINMMR37 = (pinMuxReg->PINMMR37 & PINMUX_ETPWM_TBCLK_SYNC_MASK) | (PINMUX_ETPWM_TBCLK_SYNC_##state))
+
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* SourceId : PINMUX_SourceId_001 */
+/* DesignId : PINMUX_DesignId_001 */
+/* Requirements : HL_SR325 */
+void muxInit(void){
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+    /* Enable Pin Muxing */
+    kickerReg->KICKER0 = 0x83E70B13U;
+    kickerReg->KICKER1 = 0x95A4F1E0U;
+    
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+    pinMuxReg->PINMMR0 =    PINMUX_PIN_1_GIOB_3 | PINMUX_PIN_2_GIOA_0 | PINMUX_PIN_3_HET1_29 | PINMUX_PIN_4_HET1_27;
+    
+    pinMuxReg->PINMMR1 =    PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_HET1_11;
+    
+    pinMuxReg->PINMMR2 =    PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_GIOA_5;
+    
+    pinMuxReg->PINMMR3 =    PINMUX_PIN_15_HET1_22 | PINMUX_PIN_16_GIOA_6;
+    
+    pinMuxReg->PINMMR4 =    PINMUX_PIN_22_GIOA_7 | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03;
+    
+    pinMuxReg->PINMMR5 =    PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_HET1_02 | PINMUX_PIN_31_HET1_05;
+    
+    pinMuxReg->PINMMR6 =    PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_HET1_09;
+    
+    pinMuxReg->PINMMR7 =    PINMUX_PIN_37_HET1_25 | PINMUX_PIN_38_HET1_06;
+    
+    pinMuxReg->PINMMR8 =    PINMUX_PIN_39_HET1_13 | PINMUX_PIN_40_HET1_19 | PINMUX_PIN_41_HET1_15;
+    
+    pinMuxReg->PINMMR9 =  ((~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_PIN_54_HET1_31 | PINMUX_PIN_55_MIBSPI3NCS_0;
+    
+    pinMuxReg->PINMMR10 =   PINMUX_PIN_86_AD1EVT;
+    
+    pinMuxReg->PINMMR11 =   PINMUX_PIN_91_HET1_24;
+    
+    pinMuxReg->PINMMR12 =   PINMUX_PIN_92_HET1_26 | PINMUX_PIN_96_HET1_23 | PINMUX_PIN_97_MIBSPI5NENA;
+    
+    pinMuxReg->PINMMR13 =   PINMUX_PIN_98_MIBSPI5SOMI_0 | PINMUX_PIN_99_MIBSPI5SIMO_0 | PINMUX_PIN_100_MIBSPI5CLK | PINMUX_PIN_105_MIBSPI1NCS_0;
+    
+    pinMuxReg->PINMMR14 =   PINMUX_PIN_106_HET1_08 | PINMUX_PIN_107_HET1_28;
+    
+    pinMuxReg->PINMMR15 =   0x01010101U;
+    
+    pinMuxReg->PINMMR16 =   0x01010101U;
+    
+    pinMuxReg->PINMMR17 =   PINMUX_PIN_118_HET1_10 | PINMUX_PIN_124_HET1_12;
+    
+    pinMuxReg->PINMMR18 =   PINMUX_PIN_125_HET1_14 | PINMUX_PIN_126_GIOB_0;
+    
+    pinMuxReg->PINMMR19 =   PINMUX_PIN_127_HET1_30;
+    
+    pinMuxReg->PINMMR20 =   PINMUX_PIN_130_HET1_17;
+    
+    pinMuxReg->PINMMR21 =   PINMUX_PIN_133_GIOB_1;
+    
+    pinMuxReg->PINMMR22 =   0x01010101U;
+    
+    pinMuxReg->PINMMR23 =   ((~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U);
+    
+    pinMuxReg->PINMMR24 =   ((~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U);
+    
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    pinMuxReg->PINMMR25 =   ((~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U);
+    
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    pinMuxReg->PINMMR26 =   ((~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U);
+    
+    pinMuxReg->PINMMR27 =   PINMUX_PIN_32_MIBSPI5NCS_0;
+        
+    pinMuxReg->PINMMR29 =   0x01010101U;
+
+    pinMuxReg->PINMMR30 = 0x01010100U;
+
+    pinMuxReg->PINMMR31 = 0x01010101U;
+
+    pinMuxReg->PINMMR32 = 0x00010101U;    
+
+    pinMuxReg->PINMMR33 =   PINMUX_PIN_36_HET1_04 | PINMUX_PIN_51_ECAP2 | PINMUX_PIN_52_MIBSPI3SIMO | PINMUX_PIN_53_MIBSPI3CLK;
+
+    pinMuxReg->PINMMR34 =   PINMUX_PIN_139_HET1_16 | PINMUX_PIN_140_HET1_18 | PINMUX_PIN_141_HET1_20;
+
+    
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+    PINMUX_GATE_EMIF_CLK_ENABLE(OFF);
+    PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
+    PINMUX_ALT_ADC_TRIGGER_SELECT(1);
+    PINMUX_ETHERNET_SELECT(RMII);
+    
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    PINMUX_SET(0,1,GIOB_3);
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    PINMUX_SET(0,2,GIOA_0);
+    PINMUX_SET(1,5,GIOA_1);
+    PINMUX_SET(3,15,HET1_22);
+    PINMUX_SET(18,125,HET1_14);
+    PINMUX_SET(18,126,GIOB_0);
+    PINMUX_SET(21,133,GIOB_1);
+    
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+    PINMUX_ETPWM1_EQEPERR_ENABLE(EQEPERR12);
+    PINMUX_ETPWM2_EQEPERR_ENABLE(EQEPERR12);
+    PINMUX_ETPWM3_EQEPERR_ENABLE(EQEPERR12);
+    PINMUX_ETPWM4_EQEPERR_ENABLE(EQEPERR12);
+    PINMUX_ETPWM5_EQEPERR_ENABLE(EQEPERR12);
+    PINMUX_ETPWM6_EQEPERR_ENABLE(EQEPERR12);
+    PINMUX_ETPWM7_EQEPERR_ENABLE(EQEPERR12);
+    PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE(OFF);
+    PINMUX_ETPWM_TZ1_ENABLE(ASYNC);
+    PINMUX_ETPWM_TZ2_ENABLE(ASYNC);
+    PINMUX_ETPWM_TZ3_ENABLE(ASYNC);
+    PINMUX_ETPWM_EPWM1SYNCI_ENABLE(ASYNC);
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+    
+    /* Disable Pin Muxing */
+    kickerReg->KICKER0 = 0x00000000U;
+    kickerReg->KICKER1 = 0x00000000U;
+    
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+}
+
+/** @fn void pinmuxGetConfigValue(pinmux_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*   @param[in] *config_reg: pointer to the struct to which the initial or current 
+*                           value of the configuration registers need to be stored
+*   @param[in] type:    whether initial or current value of the configuration registers need to be stored
+*                       - InitialValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*                       - CurrentValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') 
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : PINMUX_SourceId_002 */
+/* DesignId : PINMUX_DesignId_002 */
+/* Requirements : HL_SR328 */
+void pinmuxGetConfigValue(pinmux_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {/* Do not pass Initial Value as parameter */
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_PINMMR0  = pinMuxReg->PINMMR0;
+        config_reg->CONFIG_PINMMR1  = pinMuxReg->PINMMR1;
+        config_reg->CONFIG_PINMMR2  = pinMuxReg->PINMMR2;
+        config_reg->CONFIG_PINMMR3  = pinMuxReg->PINMMR3;
+        config_reg->CONFIG_PINMMR4  = pinMuxReg->PINMMR4;
+        config_reg->CONFIG_PINMMR5  = pinMuxReg->PINMMR5;
+        config_reg->CONFIG_PINMMR6  = pinMuxReg->PINMMR6;
+        config_reg->CONFIG_PINMMR7  = pinMuxReg->PINMMR7;
+        config_reg->CONFIG_PINMMR8  = pinMuxReg->PINMMR8;
+        config_reg->CONFIG_PINMMR9  = pinMuxReg->PINMMR9;
+        config_reg->CONFIG_PINMMR10 = pinMuxReg->PINMMR10;
+        config_reg->CONFIG_PINMMR11 = pinMuxReg->PINMMR11;
+        config_reg->CONFIG_PINMMR12 = pinMuxReg->PINMMR12;
+        config_reg->CONFIG_PINMMR13 = pinMuxReg->PINMMR13;
+        config_reg->CONFIG_PINMMR14 = pinMuxReg->PINMMR14;
+        config_reg->CONFIG_PINMMR15 = pinMuxReg->PINMMR15;
+        config_reg->CONFIG_PINMMR16 = pinMuxReg->PINMMR16;
+        config_reg->CONFIG_PINMMR17 = pinMuxReg->PINMMR17;
+        config_reg->CONFIG_PINMMR18 = pinMuxReg->PINMMR18;
+        config_reg->CONFIG_PINMMR19 = pinMuxReg->PINMMR19;
+        config_reg->CONFIG_PINMMR20 = pinMuxReg->PINMMR20;
+        config_reg->CONFIG_PINMMR21 = pinMuxReg->PINMMR21;
+        config_reg->CONFIG_PINMMR22 = pinMuxReg->PINMMR22;
+        config_reg->CONFIG_PINMMR23 = pinMuxReg->PINMMR23;
+        config_reg->CONFIG_PINMMR24 = pinMuxReg->PINMMR24;
+        config_reg->CONFIG_PINMMR25 = pinMuxReg->PINMMR25;
+        config_reg->CONFIG_PINMMR26 = pinMuxReg->PINMMR26;
+        config_reg->CONFIG_PINMMR27 = pinMuxReg->PINMMR27;
+        config_reg->CONFIG_PINMMR28 = pinMuxReg->PINMMR28;
+        config_reg->CONFIG_PINMMR29 = pinMuxReg->PINMMR29;
+        config_reg->CONFIG_PINMMR30 = pinMuxReg->PINMMR30;
+        config_reg->CONFIG_PINMMR32 = pinMuxReg->PINMMR32;
+        config_reg->CONFIG_PINMMR33 = pinMuxReg->PINMMR33;
+        config_reg->CONFIG_PINMMR34 = pinMuxReg->PINMMR34;
+        config_reg->CONFIG_PINMMR35 = pinMuxReg->PINMMR35;
+        config_reg->CONFIG_PINMMR36 = pinMuxReg->PINMMR36;
+        config_reg->CONFIG_PINMMR37 = pinMuxReg->PINMMR37;
+        config_reg->CONFIG_PINMMR38 = pinMuxReg->PINMMR38;
+        config_reg->CONFIG_PINMMR39 = pinMuxReg->PINMMR39;
+        config_reg->CONFIG_PINMMR40 = pinMuxReg->PINMMR40;
+        config_reg->CONFIG_PINMMR41 = pinMuxReg->PINMMR41;
+        config_reg->CONFIG_PINMMR42 = pinMuxReg->PINMMR42;
+        config_reg->CONFIG_PINMMR43 = pinMuxReg->PINMMR43;
+        config_reg->CONFIG_PINMMR44 = pinMuxReg->PINMMR44;
+        config_reg->CONFIG_PINMMR45 = pinMuxReg->PINMMR45;
+        config_reg->CONFIG_PINMMR46 = pinMuxReg->PINMMR46;
+        config_reg->CONFIG_PINMMR47 = pinMuxReg->PINMMR47;
+    }
+}
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
diff --git a/src/arch/rm46l8lp/halcogen/rti.c b/src/arch/rm46l8lp/halcogen/rti.c
new file mode 100644
index 0000000..a7298cf
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/rti.c
@@ -0,0 +1,959 @@
+/** @file rti.c 
+*   @brief RTI Driver Source File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file contains:
+*   - API Functions
+*   - Interrupt Handlers
+*   .
+*   which are relevant for the RTI driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Include Files */
+
+#include "rti.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @fn void rtiInit(void)
+*   @brief Initializes RTI Driver
+*
+*   This function initializes the RTI driver.
+*
+*/
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/* SourceId : RTI_SourceId_001 */
+/* DesignId : RTI_DesignId_001 */
+/* Requirements : HL_SR76 */
+void rtiInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+    /** @b Initialize @b RTI1: */
+
+    /** - Setup NTU source, debug options and disable both counter blocks */
+    rtiREG1->GCTRL = (uint32)((uint32)0x0U << 16U) | 0x00000000U;
+
+    /** - Setup timebase for free running counter 0 */
+    rtiREG1->TBCTRL = 0x00000000U;
+
+    /** - Enable/Disable capture event sources for both counter blocks */
+    rtiREG1->CAPCTRL = 0U | 0U;
+
+    /** - Setup input source compare 0-3 */
+    rtiREG1->COMPCTRL = 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U;
+
+    /** - Reset up counter 0 */
+    rtiREG1->CNT[0U].UCx = 0x00000000U;
+
+    /** - Reset free running counter 0 */
+    rtiREG1->CNT[0U].FRCx = 0x00000000U;
+
+    /** - Setup up counter 0 compare value 
+    *     - 0x00000000: Divide by 2^32
+    *     - 0x00000001-0xFFFFFFFF: Divide by (CPUC0 + 1)
+    */
+    rtiREG1->CNT[0U].CPUCx = 7U;
+
+    /** - Reset up counter 1 */
+    rtiREG1->CNT[1U].UCx = 0x00000000U;
+
+    /** - Reset free running counter 1 */
+    rtiREG1->CNT[1U].FRCx  = 0x00000000U;
+
+    /** - Setup up counter 1 compare value 
+    *     - 0x00000000: Divide by 2^32
+    *     - 0x00000001-0xFFFFFFFF: Divide by (CPUC1 + 1)
+    */
+    rtiREG1->CNT[1U].CPUCx = 7U;
+
+    /** - Setup compare 0 value. This value is compared with selected free running counter. */
+    rtiREG1->CMP[0U].COMPx = 50000U;
+
+    /** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */
+    rtiREG1->CMP[0U].UDCPx = 50000U;
+
+    /** - Setup compare 1 value. This value is compared with selected free running counter. */
+    rtiREG1->CMP[1U].COMPx = 50000000U;
+
+    /** - Setup update compare 1 value. This value is added to the compare 1 value on each compare match. */
+    rtiREG1->CMP[1U].UDCPx = 50000000U;
+
+    /** - Setup compare 2 value. This value is compared with selected free running counter. */
+    rtiREG1->CMP[2U].COMPx = 5000000U;
+
+    /** - Setup update compare 2 value. This value is added to the compare 2 value on each compare match. */
+    rtiREG1->CMP[2U].UDCPx = 5000000U;
+
+    /** - Setup compare 3 value. This value is compared with selected free running counter. */
+    rtiREG1->CMP[3U].COMPx = 50000000U;
+
+    /** - Setup update compare 3 value. This value is added to the compare 3 value on each compare match. */
+    rtiREG1->CMP[3U].UDCPx = 50000000U;
+
+    /** - Clear all pending interrupts */
+    rtiREG1->INTFLAG = 0x0007000FU;
+
+    /** - Disable all interrupts */
+    rtiREG1->CLEARINTENA = 0x00070F0FU;
+
+    /**   @note This function has to be called before the driver can be used.\n
+    *           This function has to be executed in privileged mode.\n
+    *           This function does not start the counters.
+    */
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+
+/** @fn void rtiStartCounter(uint32 counter)
+*   @brief Starts RTI Counter block
+*   @param[in] counter Select counter block to be started:
+*              - rtiCOUNTER_BLOCK0: RTI counter block 0 will be started
+*              - rtiCOUNTER_BLOCK1: RTI counter block 1 will be started
+*
+*   This function starts selected counter block of the selected RTI module.
+*/
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+/* SourceId : RTI_SourceId_002 */
+/* DesignId : RTI_DesignId_002 */
+/* Requirements : HL_SR77 */
+void rtiStartCounter(uint32 counter)
+{
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+    rtiREG1->GCTRL |= ((uint32)1U << (counter & 3U));
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.
+    */
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+
+/** @fn void rtiStopCounter(uint32 counter)
+*   @brief Stops RTI Counter block
+*   @param[in] counter Select counter to be stopped:
+*              - rtiCOUNTER_BLOCK0: RTI counter block 0 will be stopped
+*              - rtiCOUNTER_BLOCK1: RTI counter block 1 will be stopped
+*
+*   This function stops selected counter block of the selected RTI module.
+*/
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+/* SourceId : RTI_SourceId_003 */
+/* DesignId : RTI_DesignId_003 */
+/* Requirements : HL_SR78 */
+void rtiStopCounter(uint32 counter)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+    rtiREG1->GCTRL &= ~(uint32)((uint32)1U << (counter & 3U));
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.
+    */
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+
+/** @fn uint32 rtiResetCounter(uint32 counter)
+*   @brief Reset RTI Counter block
+*   @param[in] counter Select counter block to be reset:
+*              - rtiCOUNTER_BLOCK0: RTI counter block 0 will be reset
+*              - rtiCOUNTER_BLOCK1: RTI counter block 1 will be reset
+*   @return The function will return:
+*           - 0: When the counter reset wasn't successful   
+*           - 1: When the counter reset was successful   
+*
+*   This function resets selected counter block of the selected RTI module.
+*/
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+/* SourceId : RTI_SourceId_004 */
+/* DesignId : RTI_DesignId_004 */
+/* Requirements : HL_SR79 */
+uint32 rtiResetCounter(uint32 counter)
+{
+    uint32 success = 0U;
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    if ((rtiREG1->GCTRL & (uint32)((uint32)1U << (counter & 3U))) == 0U)
+    {
+        rtiREG1->CNT[counter].UCx = 0x00000000U;
+        rtiREG1->CNT[counter].FRCx = 0x00000000U;
+
+        success = 1U;
+    }
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.\n
+    *           The selected counter block has to be stopped before it can reset.
+    */
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+    return success;
+}
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+
+/** @fn void rtiSetPeriod(uint32 compare, uint32 period)
+*   @brief Set new period of RTI compare
+*   @param[in] compare Select compare to change period:
+*              - rtiCOMPARE0: RTI compare 0 will change the period
+*              - rtiCOMPARE1: RTI compare 1 will change the period
+*              - rtiCOMPARE2: RTI compare 2 will change the period
+*              - rtiCOMPARE3: RTI compare 3 will change the period
+*   @param[in] period new period in [ticks - 1]:
+*              - 0x00000000: Divide by 1
+*              - n: Divide by n + 1
+*
+*   This function will change the period of the selected compare.
+*/
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+/* SourceId : RTI_SourceId_005 */
+/* DesignId : RTI_DesignId_005 */
+/* Requirements : HL_SR80 */
+void rtiSetPeriod(uint32 compare, uint32 period)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+    rtiREG1->CMP[compare].UDCPx = period;
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.\n
+    *           When the corresponding counter block is not stopped,\n
+    *           the period will change on the next compare match of the old period.
+    */
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+
+/** @fn uint32 rtiGetPeriod(uint32 compare)
+*   @brief Get current period of RTI compare
+*   @param[in] compare Select compare to return the current period:
+*              - rtiCOMPARE0: RTI compare 0 will return the current period
+*              - rtiCOMPARE1: RTI compare 1 will return the current period
+*              - rtiCOMPARE2: RTI compare 2 will return the current period
+*              - rtiCOMPARE3: RTI compare 3 will return the current period
+*   @return Current period of selected compare in [ticks - 1]:
+*           - 0x00000000: Divide by 1
+*           - n: Divide by n + 1
+*
+*   This function will return the period of the selected compare.
+*/
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+/* SourceId : RTI_SourceId_006 */
+/* DesignId : RTI_DesignId_006 */
+/* Requirements : HL_SR81 */
+uint32 rtiGetPeriod(uint32 compare)
+{
+    uint32 period;
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+    period = rtiREG1->CMP[compare].UDCPx;
+
+    /**   @note The function rtiInit has to be called before this function can be used.
+    */
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+    return period;
+}
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+
+/** @fn uint32 rtiGetCurrentTick(uint32 compare)
+*   @brief Get current tick of RTI compare
+*   @param[in] compare Select compare to return the current tick:
+*              - rtiCOMPARE0: RTI compare 0 will return the current tick
+*              - rtiCOMPARE1: RTI compare 1 will return the current tick
+*              - rtiCOMPARE2: RTI compare 2 will return the current tick
+*              - rtiCOMPARE3: RTI compare 3 will return the current tick
+*   @return Current tick of selected compare
+*
+*   This function will return the current tick of the selected compare.
+*/
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+/* SourceId : RTI_SourceId_007 */
+/* DesignId : RTI_DesignId_007 */
+/* Requirements : HL_SR82 */
+uint32 rtiGetCurrentTick(uint32 compare)
+{
+    uint32 tick;
+    uint32 counter = ((rtiREG1->COMPCTRL & (uint32)((uint32)1U << (compare << 2U))) != 0U ) ? 1U : 0U;
+	uint32 RTI_CNT_FRCx = rtiREG1->CNT[counter].FRCx;
+	uint32 RTI_CMP_COMPx = rtiREG1->CMP[compare].COMPx;
+	uint32 RTI_CMP_UDCPx = rtiREG1->CMP[compare].UDCPx;
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+
+    tick = RTI_CNT_FRCx - (RTI_CMP_COMPx - RTI_CMP_UDCPx);
+
+    /**   @note The function rtiInit has to be called before this function can be used.
+    */
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+    return tick;
+}
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+/** @fn void dwdInit(uint16 dwdPreload)
+*   @brief Initialize DWD Expiration Period 
+*   @param[in] dwdPreload DWD Preload value for expiration time.
+*              - Texp = (dwdPreload +1) / RTICLK
+*              - n: Divide by n + 1
+*
+*   This function can be called to set the DWD expiration
+*   
+*/
+/* SourceId : RTI_SourceId_008 */
+/* DesignId : RTI_DesignId_010 */
+/* Requirements : HL_SR85 */
+void dwdInit(uint16 dwdPreload)
+{
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+    /* Clear the violations if already present */
+	rtiREG1->WDSTATUS = 0xFFU;
+	
+	rtiREG1->DWDPRLD = dwdPreload;
+	
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+/** @fn void dwwdInit(dwwdReaction_t Reaction, uint16 dwdPreload, dwwdWindowSize_t Window_Size)
+*   @brief Initialize DWD Expiration Period 
+*   @param[in] Reaction DWWD reaction if the watchdog is serviced outside the time window.
+*              - Generate_Reset  
+*              - Generate_NMI
+*   @param[in] dwdPreload DWWD Preload value for the watchdog expiration time.
+*              - Texp = (dwdPreload +1) / RTICLK
+*              - n: Divide by n + 1
+*   @param[in] Window_Size DWWD time window size
+*              - Size_100_Percent
+*              - Size_50_Percent
+*              - Size_25_Percent
+*              - Size_12_5_Percent
+*              - Size_6_25_Percent
+*              - Size_3_125_Percent
+*
+*   This function can be called to set the DWD expiration
+*   
+*/
+/* SourceId : RTI_SourceId_009 */
+/* DesignId : RTI_DesignId_011 */
+/* Requirements : HL_SR86 */
+void dwwdInit(dwwdReaction_t Reaction, uint16 dwdPreload, dwwdWindowSize_t Window_Size)
+{
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+    /* Clear the violations if already present */
+	rtiREG1->WDSTATUS = 0xFFU;
+
+    rtiREG1->WWDSIZECTRL = (uint32) Window_Size;
+	rtiREG1->DWDPRLD     = (uint32) dwdPreload;
+	rtiREG1->WWDRXNCTRL  = (uint32) Reaction;
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+/** @fn uint32 dwwdGetCurrentDownCounter(void)
+*   @brief Get the current DWWD Down Counter 
+*   @return Current tick of selected compare
+*
+*   This function will get the current DWWD down counter value.
+*   
+*/
+/* SourceId : RTI_SourceId_010 */
+/* DesignId : RTI_DesignId_012 */
+/* Requirements : HL_SR87 */
+uint32 dwwdGetCurrentDownCounter(void)
+{
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+    return (rtiREG1->DWDCNTR);
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+
+/** @fn void dwdCounterEnable(void)
+*   @brief Enable DWD
+*
+*   This function will Enable the DWD counter.
+*   
+*/
+/* SourceId : RTI_SourceId_011 */
+/* DesignId : RTI_DesignId_013 */
+/* Requirements : HL_SR88 */
+void dwdCounterEnable(void)
+{
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+
+	rtiREG1->DWDCTRL = 0xA98559DAU;
+	
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (42) */
+/* USER CODE END */
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+/** @fn void dwdSetPreload(uint16 dwdPreload)
+*   @brief Initialize DWD Expiration Period 
+*   @param[in] dwdPreload DWD Preload value for the watchdog expiration time.
+*              - Texp = (dwdPreload +1) / RTICLK
+*              - n: Divide by n + 1
+*
+*   This function can be called to set the Preload value for the watchdog expiration time.
+*   
+*/
+/* SourceId : RTI_SourceId_012 */
+/* DesignId : RTI_DesignId_014 */
+/* Requirements : HL_SR85 */
+void dwdSetPreload(uint16 dwdPreload)
+{
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+	rtiREG1->DWDPRLD = dwdPreload;
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+
+/** @fn void dwdReset(void)
+*   @brief Reset Digital Watchdog 
+*
+*   This function can be called to reset Digital Watchdog.
+*   
+*/
+/* SourceId : RTI_SourceId_013 */
+/* DesignId : RTI_DesignId_015 */
+/* Requirements : HL_SR89 */
+void dwdReset(void)
+{
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+	rtiREG1->WDKEY = 0x0000E51AU;
+	rtiREG1->WDKEY = 0x0000A35CU;
+/* USER CODE BEGIN (49) */
+/* USER CODE END */
+}
+
+/** @fn void dwdGenerateSysReset(void)
+*   @brief Generate System Reset through DWD
+*
+*   This function can be called to generate system reset using DWD.
+*   
+*/
+/* SourceId : RTI_SourceId_014 */
+/* DesignId : RTI_DesignId_016 */
+/* Requirements : HL_SR90 */
+void dwdGenerateSysReset(void)
+{
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+	rtiREG1->WDKEY = 0x0000E51AU;
+	rtiREG1->WDKEY = 0x00002345U;
+/* USER CODE BEGIN (51) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (52) */
+/* USER CODE END */
+
+/** @fn boolean IsdwdKeySequenceCorrect(void)
+*   @brief Check if DWD Key sequence correct.
+*   @return The function will return:
+*           - TRUE: When the DWD key sequence is written correctly.
+*           - FALSE: When the DWD key sequence is written incorrectly / not written.
+*
+*   This function will get status of the DWD Key sequence.
+*   
+*/
+/* SourceId : RTI_SourceId_015 */
+/* DesignId : RTI_DesignId_017 */
+/* Requirements : HL_SR91 */
+boolean IsdwdKeySequenceCorrect(void)
+{
+	boolean Status;
+
+/* USER CODE BEGIN (53) */
+/* USER CODE END */
+
+	if((rtiREG1->WDSTATUS & 0x4U) == 0x4U)
+	{
+		Status = FALSE;
+	}
+	else
+	{
+		Status = TRUE;
+	}
+
+/* USER CODE BEGIN (54) */
+/* USER CODE END */
+
+	return Status;
+}
+
+/* USER CODE BEGIN (55) */
+/* USER CODE END */
+
+/** @fn dwdResetStatus_t dwdGetStatus(void)
+*   @brief Check if Reset is generated due to DWD.
+*   @return The function will return:
+*           - Reset_Generated: When the Reset is generated due to DWD.
+*           - No_Reset_Generated: No Reset is generated due to DWD.
+*
+*   This function will get dwd Reset status.
+*   
+*/
+/* SourceId : RTI_SourceId_016 */
+/* DesignId : RTI_DesignId_018 */
+/* Requirements : HL_SR92 */
+dwdResetStatus_t dwdGetStatus(void)
+{
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
+	dwdResetStatus_t Reset_Status;
+	if((rtiREG1->WDSTATUS & 0x2U) == 0x2U)
+	{
+		Reset_Status = Reset_Generated;
+	}
+	else
+	{
+		Reset_Status = No_Reset_Generated;
+	}
+
+/* USER CODE BEGIN (57) */
+/* USER CODE END */
+	return Reset_Status;
+}
+
+/* USER CODE BEGIN (58) */
+/* USER CODE END */
+
+/** @fn void dwdClearFlag(void)
+*   @brief Clear the DWD violation flag.
+*
+*   This function will clear dwd status register.
+*   
+*/
+/* SourceId : RTI_SourceId_017 */
+/* DesignId : RTI_DesignId_020 */
+/* Requirements : HL_SR94 */
+void dwdClearFlag(void)
+{
+/* USER CODE BEGIN (59) */
+/* USER CODE END */
+
+	rtiREG1->WDSTATUS = 0xFFU;
+
+/* USER CODE BEGIN (60) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (61) */
+/* USER CODE END */
+
+/** @fn dwdViolation_t dwdGetViolationStatus(void)
+*   @brief Check the status of the DWD or DWWD violation happened.
+*   @return The function will return one of following violations occured:
+*           - NoTime_Violation
+*           - Key_Seq_Violation
+*           - Time_Window_Violation
+*           - EndTime_Window_Violation
+*           - StartTime_Window_Violation
+*
+*   This function will get status of the DWD or DWWD violation status.
+*   
+*/
+/* SourceId : RTI_SourceId_018 */
+/* DesignId : RTI_DesignId_019 */
+/* Requirements : HL_SR93 */
+dwdViolation_t dwdGetViolationStatus(void)
+{
+/* USER CODE BEGIN (62) */
+/* USER CODE END */
+	dwdViolation_t Violation_Status;
+
+	if ((rtiREG1->WDSTATUS & 0x04U) == 0x04U)
+	{
+		Violation_Status = Key_Seq_Violation;
+	}	
+	else if((rtiREG1->WDSTATUS & 0x8U) == 0x8U)
+	{
+		Violation_Status = StartTime_Window_Violation;
+	}
+	else if ((rtiREG1->WDSTATUS & 0x10U) == 0x10U)
+	{
+		Violation_Status = EndTime_Window_Violation;
+	}
+	else if ((rtiREG1->WDSTATUS & 0x20U) == 0x20U)
+	{
+		Violation_Status = Time_Window_Violation;
+	}
+	else
+	{
+		Violation_Status = NoTime_Violation;
+	}
+	
+/* USER CODE BEGIN (63) */
+/* USER CODE END */
+
+	return Violation_Status;
+}
+
+/* USER CODE BEGIN (64) */
+/* USER CODE END */
+
+/** @fn void rtiEnableNotification(uint32 notification)
+*   @brief Enable notification of RTI module
+*   @param[in] notification Select notification of RTI module:
+*              - rtiNOTIFICATION_COMPARE0: RTI compare 0 notification
+*              - rtiNOTIFICATION_COMPARE1: RTI compare 1 notification
+*              - rtiNOTIFICATION_COMPARE2: RTI compare 2 notification
+*              - rtiNOTIFICATION_COMPARE3: RTI compare 3 notification
+*              - rtiNOTIFICATION_TIMEBASE: RTI Timebase notification
+*              - rtiNOTIFICATION_COUNTER0: RTI counter 0 overflow notification
+*              - rtiNOTIFICATION_COUNTER1: RTI counter 1 overflow notification
+*
+*   This function will enable the selected notification of a RTI module.
+*   It is possible to enable multiple notifications masked.
+*/
+
+/* USER CODE BEGIN (65) */
+/* USER CODE END */
+/* SourceId : RTI_SourceId_019 */
+/* DesignId : RTI_DesignId_008 */
+/* Requirements : HL_SR83 */
+void rtiEnableNotification(uint32 notification)
+{
+/* USER CODE BEGIN (66) */
+/* USER CODE END */
+
+    rtiREG1->INTFLAG = notification;
+    rtiREG1->SETINTENA   = notification;
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.
+    */
+
+/* USER CODE BEGIN (67) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (68) */
+/* USER CODE END */
+
+/** @fn void rtiDisableNotification(uint32 notification)
+*   @brief Disable notification of RTI module
+*   @param[in] notification Select notification of RTI module:
+*              - rtiNOTIFICATION_COMPARE0: RTI compare 0 notification
+*              - rtiNOTIFICATION_COMPARE1: RTI compare 1 notification
+*              - rtiNOTIFICATION_COMPARE2: RTI compare 2 notification
+*              - rtiNOTIFICATION_COMPARE3: RTI compare 3 notification
+*              - rtiNOTIFICATION_TIMEBASE: RTI Timebase notification
+*              - rtiNOTIFICATION_COUNTER0: RTI counter 0 overflow notification
+*              - rtiNOTIFICATION_COUNTER1: RTI counter 1 overflow notification
+*
+*   This function will disable the selected notification of a RTI module.
+*   It is possible to disable multiple notifications masked.
+*/
+
+/* USER CODE BEGIN (69) */
+/* USER CODE END */
+/* SourceId : RTI_SourceId_020 */
+/* DesignId : RTI_DesignId_009 */
+/* Requirements : HL_SR84 */
+void rtiDisableNotification(uint32 notification)
+{
+/* USER CODE BEGIN (70) */
+/* USER CODE END */
+
+    rtiREG1->CLEARINTENA = notification;
+
+    /**   @note The function rtiInit has to be called before this function can be used.\n
+    *           This function has to be executed in privileged mode.
+    */
+
+/* USER CODE BEGIN (71) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (72) */
+/* USER CODE END */
+
+/** @fn void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration 
+*   registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : RTI_SourceId_021 */
+/* DesignId : RTI_DesignId_021 */
+/* Requirements : HL_SR97 */
+void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_GCTRL = RTI_GCTRL_CONFIGVALUE;
+		config_reg->CONFIG_TBCTRL = RTI_TBCTRL_CONFIGVALUE;
+		config_reg->CONFIG_CAPCTRL = RTI_CAPCTRL_CONFIGVALUE;
+		config_reg->CONFIG_COMPCTRL = RTI_COMPCTRL_CONFIGVALUE;
+		config_reg->CONFIG_UDCP0 = RTI_UDCP0_CONFIGVALUE;
+		config_reg->CONFIG_UDCP1 = RTI_UDCP1_CONFIGVALUE;
+		config_reg->CONFIG_UDCP2 = RTI_UDCP2_CONFIGVALUE;
+		config_reg->CONFIG_UDCP3 = RTI_UDCP3_CONFIGVALUE;
+	}
+	else
+	{
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+		config_reg->CONFIG_GCTRL = rtiREG1->GCTRL;
+		config_reg->CONFIG_TBCTRL = rtiREG1->TBCTRL;
+		config_reg->CONFIG_CAPCTRL = rtiREG1->CAPCTRL;
+		config_reg->CONFIG_COMPCTRL = rtiREG1->COMPCTRL;
+		config_reg->CONFIG_UDCP0 = rtiREG1->CMP[0U].UDCPx;
+		config_reg->CONFIG_UDCP1 = rtiREG1->CMP[1U].UDCPx;
+		config_reg->CONFIG_UDCP2 = rtiREG1->CMP[2U].UDCPx;
+		config_reg->CONFIG_UDCP3 = rtiREG1->CMP[3U].UDCPx;
+	}
+}
+
+/* USER CODE BEGIN (73) */
+/* USER CODE END */
+
+/** @fn void rtiCompare0Interrupt(void)
+*   @brief RTI1 Compare 0 Interrupt Handler
+*
+*   RTI1 Compare 0 interrupt handler 
+*
+*/
+#pragma CODE_STATE(rtiCompare0Interrupt, 32)
+#pragma INTERRUPT(rtiCompare0Interrupt, IRQ)
+
+/* SourceId : RTI_SourceId_022 */
+/* DesignId : RTI_DesignId_022 */
+/* Requirements : HL_SR95 */
+void rtiCompare0Interrupt(void)
+{
+/* USER CODE BEGIN (74) */
+/* USER CODE END */
+
+    rtiREG1->INTFLAG = 1U;
+    rtiNotification(rtiNOTIFICATION_COMPARE0);
+
+/* USER CODE BEGIN (75) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (76) */
+/* USER CODE END */
+
+/** @fn void rtiCompare1Interrupt(void)
+*   @brief RTI1 Compare 1 Interrupt Handler
+*
+*   RTI1 Compare 1 interrupt handler 
+*
+*/
+#pragma CODE_STATE(rtiCompare1Interrupt, 32)
+#pragma INTERRUPT(rtiCompare1Interrupt, IRQ)
+
+/* SourceId : RTI_SourceId_023 */
+/* DesignId : RTI_DesignId_022 */
+/* Requirements : HL_SR95 */
+void rtiCompare1Interrupt(void)
+{
+/* USER CODE BEGIN (77) */
+/* USER CODE END */
+
+    rtiREG1->INTFLAG = 2U;
+    rtiNotification(rtiNOTIFICATION_COMPARE1);
+
+/* USER CODE BEGIN (78) */
+/* USER CODE END */
+}
+
+
+/* USER CODE BEGIN (79) */
+/* USER CODE END */
+
+/** @fn void rtiCompare2Interrupt(void)
+*   @brief RTI1 Compare 2 Interrupt Handler
+*
+*   RTI1 Compare 2 interrupt handler 
+*
+*/
+#pragma CODE_STATE(rtiCompare2Interrupt, 32)
+#pragma INTERRUPT(rtiCompare2Interrupt, IRQ)
+
+/* SourceId : RTI_SourceId_024 */
+/* DesignId : RTI_DesignId_022 */
+/* Requirements : HL_SR95 */
+void rtiCompare2Interrupt(void)
+{
+/* USER CODE BEGIN (80) */
+/* USER CODE END */
+
+    rtiREG1->INTFLAG = 4U;
+    rtiNotification(rtiNOTIFICATION_COMPARE2);
+
+/* USER CODE BEGIN (81) */
+/* USER CODE END */
+}
+
+
+/* USER CODE BEGIN (82) */
+/* USER CODE END */
+
+/** @fn void rtiCompare3Interrupt(void)
+*   @brief RTI1 Compare 3 Interrupt Handler
+*
+*   RTI1 Compare 3 interrupt handler 
+*
+*/
+#pragma CODE_STATE(rtiCompare3Interrupt, 32)
+#pragma INTERRUPT(rtiCompare3Interrupt, IRQ)
+
+/* SourceId : RTI_SourceId_025 */
+/* DesignId : RTI_DesignId_022 */
+/* Requirements : HL_SR95 */
+void rtiCompare3Interrupt(void)
+{
+/* USER CODE BEGIN (83) */
+/* USER CODE END */
+
+    rtiREG1->INTFLAG = 8U;
+    rtiNotification(rtiNOTIFICATION_COMPARE3);
+
+/* USER CODE BEGIN (84) */
+/* USER CODE END */
+}
+
+
+
+
diff --git a/src/arch/rm46l8lp/halcogen/sci.c b/src/arch/rm46l8lp/halcogen/sci.c
new file mode 100644
index 0000000..10d3590
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sci.c
@@ -0,0 +1,673 @@
+/** @file sci.c 
+*   @brief SCI Driver Implementation File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sci.h"
+#include "sys_vim.h"
+#include "math.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+/** @struct g_sciTransfer
+*   @brief Interrupt mode globals
+*
+*/
+static volatile struct g_sciTransfer
+{
+    uint32   mode;         /* Used to check for TX interrupt Enable */  
+    uint32   tx_length;    /* Transmit data length in number of Bytes */
+	uint32   rx_length;    /* Receive data length in number of Bytes */  
+    uint8    * tx_data;    /* Transmit data pointer */  	
+    uint8    * rx_data;    /* Receive data pointer */  
+} g_sciTransfer_t[2U];
+
+
+/** @fn void sciInit(void)
+*   @brief Initializes the SCI Driver
+*
+*   This function initializes the SCI module.
+*/
+/* SourceId : SCI_SourceId_001 */
+/* DesignId : SCI_DesignId_001 */
+/* Requirements : HL_SR230 */
+void sciInit(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+    /** @b initialize @b SCILIN */
+
+    /** - bring SCI out of reset */
+    scilinREG->GCR0 = 0U;
+    scilinREG->GCR0 = 1U;
+
+    /** - Disable all interrupts */
+    scilinREG->CLEARINT    = 0xFFFFFFFFU;
+    scilinREG->CLEARINTLVL = 0xFFFFFFFFU;
+
+    /** - global control 1 */
+    scilinREG->GCR1 = (uint32)((uint32)1U << 25U)  /* enable transmit */
+                    | (uint32)((uint32)1U << 24U)  /* enable receive */
+                    | (uint32)((uint32)1U << 5U)   /* internal clock (device has no clock pin) */
+                    | (uint32)((uint32)(2U-1U) << 4U)  /* number of stop bits */
+                    | (uint32)((uint32)0U << 3U)  /* even parity, otherwise odd */
+                    | (uint32)((uint32)0U << 2U)  /* enable parity */
+                    | (uint32)((uint32)1U << 1U);  /* asynchronous timing mode */
+                    
+    /** - set baudrate */
+    scilinREG->BRS = 259U;  /* baudrate */
+
+    /** - transmission length */
+    scilinREG->FORMAT = 8U - 1U;  /* length */
+
+    /** - set SCI pins functional mode */
+    scilinREG->PIO0 = (uint32)((uint32)1U << 2U)  /* tx pin */
+                    | (uint32)((uint32)1U << 1U); /* rx pin */
+
+
+    /** - set SCI pins default output value */
+    scilinREG->PIO3 = (uint32)((uint32)0U << 2U)  /* tx pin */
+                    | (uint32)((uint32)0U << 1U); /* rx pin */
+
+
+    /** - set SCI pins output direction */
+    scilinREG->PIO1 = (uint32)((uint32)0U << 2U)  /* tx pin */
+                    | (uint32)((uint32)0U << 1U); /* rx pin */
+
+
+    /** - set SCI pins open drain enable */
+    scilinREG->PIO6 = (uint32)((uint32)0U << 2U)  /* tx pin */
+                    | (uint32)((uint32)0U << 1U); /* rx pin */
+
+
+    /** - set SCI pins pullup/pulldown enable */
+    scilinREG->PIO7 = (uint32)((uint32)0U << 2U)  /* tx pin */
+                    | (uint32)((uint32)0U << 1U); /* rx pin */
+
+
+    /** - set SCI pins pullup/pulldown select */
+    scilinREG->PIO8 = (uint32)((uint32)1U << 2U)  /* tx pin */
+                    | (uint32)((uint32)1U << 1U); /* rx pin */
+
+
+    /** - set interrupt level */
+    scilinREG->SETINTLVL = (uint32)((uint32)0U << 26U)  /* Framing error */
+                         | (uint32)((uint32)0U << 25U)  /* Overrun error */
+                         | (uint32)((uint32)0U << 24U)  /* Parity error */
+                         | (uint32)((uint32)0U << 9U)  /* Receive */
+                         | (uint32)((uint32)0U << 8U)  /* Transmit */
+                         | (uint32)((uint32)0U << 1U)  /* Wakeup */
+                         | (uint32)((uint32)0U);  /* Break detect */
+
+    /** - set interrupt enable */
+    scilinREG->SETINT = (uint32)((uint32)0U << 26U)  /* Framing error */
+                      | (uint32)((uint32)0U << 25U)  /* Overrun error */
+                      | (uint32)((uint32)0U << 24U)  /* Parity error */
+                      | (uint32)((uint32)0U << 9U)  /* Receive */
+                      | (uint32)((uint32)0U << 1U)  /* Wakeup */
+                      | (uint32)((uint32)0U);  /* Break detect */
+
+    /** - initialize global transfer variables */
+    g_sciTransfer_t[1U].mode   = (uint32)0U << 8U;
+    g_sciTransfer_t[1U].tx_length = 0U;
+	g_sciTransfer_t[1U].rx_length = 0U;
+
+    /** - Finaly start SCILIN */
+    scilinREG->GCR1 |= 0x80U;
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+}
+
+
+/** @fn void sciSetFunctional(sciBASE_t *sci, uint32 port)
+*   @brief Change functional behavior of pins at runtime.
+*   @param[in] sci   - sci module base address
+*   @param[in] port  - Value to write to PIO0 register
+*
+*   Change the value of the PCPIO0 register at runtime, this allows to
+*   dynamically change the functionality of the SCI pins between functional
+*   and GIO mode.
+*/
+/* SourceId : SCI_SourceId_002 */
+/* DesignId : SCI_DesignId_002 */
+/* Requirements : HL_SR231 */
+void sciSetFunctional(sciBASE_t *sci, uint32 port)
+{
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+    sci->PIO0 = port;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+}
+
+
+/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32 baud)
+*   @brief Change baudrate at runtime.
+*   @param[in] sci  - sci module base address
+*   @param[in] baud - baudrate in Hz
+*
+*   Change the SCI baudrate at runtime.
+*/
+/* SourceId : SCI_SourceId_003 */
+/* DesignId : SCI_DesignId_003 */
+/* Requirements : HL_SR232 */
+void sciSetBaudrate(sciBASE_t *sci, uint32 baud)
+{
+    float64 vclk = 80.000 * 1000000.0;
+    uint32 f = ((sci->GCR1 & 2U) == 2U) ? 16U : 1U;
+	uint32 temp;
+	float64 temp2;
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+    /*SAFETYMCUSW 96 S MR:6.1 <APPROVED> "Calculations including int and float cannot be avoided" */
+	temp = (f*(baud));
+	temp2 = ((vclk)/((float64)temp))-1U;
+	temp2 = floor(temp2 + 0.5);        /* Rounding-off to the closest integer */
+	sci->BRS = (uint32)((uint32)temp2 & 0x00FFFFFFU);
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+}
+
+
+/** @fn uint32 sciIsTxReady(sciBASE_t *sci)
+*   @brief Check if Tx buffer empty
+*   @param[in] sci - sci module base address
+*
+*   @return The TX ready flag
+*
+*   Checks to see if the Tx buffer ready flag is set, returns
+*   0 is flags not set otherwise will return the Tx flag itself.
+*/
+/* SourceId : SCI_SourceId_004 */
+/* DesignId : SCI_DesignId_004 */
+/* Requirements : HL_SR233 */
+uint32 sciIsTxReady(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+    return sci->FLR & (uint32)SCI_TX_INT;
+}
+
+
+/** @fn void sciSendByte(sciBASE_t *sci, uint8 byte)
+*   @brief Send Byte
+*   @param[in] sci  - sci module base address
+*   @param[in] byte - byte to transfer
+*
+*   Sends a single byte in polling mode, will wait in the
+*   routine until the transmit buffer is empty before sending
+*   the byte.  Use sciIsTxReady to check for Tx buffer empty
+*   before calling sciSendByte to avoid waiting.
+*/
+/* SourceId : SCI_SourceId_005 */
+/* DesignId : SCI_DesignId_005 */
+/* Requirements : HL_SR234 */
+void sciSendByte(sciBASE_t *sci, uint8 byte)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+	/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+    while ((sci->FLR & (uint32)SCI_TX_INT) == 0U) 
+    { 
+    } /* Wait */
+    sci->TD = byte;
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+}
+
+
+/** @fn void sciSend(sciBASE_t *sci, uint32 length, uint8 * data)
+*   @brief Send Data
+*   @param[in] sci    - sci module base address
+*   @param[in] length - number of data words to transfer
+*   @param[in] data   - pointer to data to send
+*
+*   Send a block of data pointed to by 'data' and 'length' bytes
+*   long.  If interrupts have been enabled the data is sent using
+*   interrupt mode, otherwise polling mode is used.  In interrupt
+*   mode transmission of the first byte is started and the routine
+*   returns immediately, sciSend must not be called again until the
+*   transfer is complete, when the sciNotification callback will
+*   be called.  In polling mode, sciSend will not return  until 
+*   the transfer is complete.
+*
+*   @note if data word is less than 8 bits, then the data must be left
+*         aligned in the data byte.
+*/
+/* SourceId : SCI_SourceId_006 */
+/* DesignId : SCI_DesignId_006 */
+/* Requirements : HL_SR235 */
+void sciSend(sciBASE_t *sci, uint32 length, uint8 * data)
+{
+    uint32 index = (sci == sciREG) ? 0U : 1U;
+    uint8 txdata;
+	
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Mode variable is configured in sciEnableNotification()" */
+    if ((g_sciTransfer_t[index].mode & (uint32)SCI_TX_INT) != 0U)
+    {
+        /* we are in interrupt mode */
+        
+        g_sciTransfer_t[index].tx_length = length;
+        /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+        g_sciTransfer_t[index].tx_data   = data;
+
+        /* start transmit by sending first byte */        
+        /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+		txdata = *g_sciTransfer_t[index].tx_data;
+		sci->TD     = (uint32)(txdata);
+		/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+        /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
+		g_sciTransfer_t[index].tx_data++;
+        sci->SETINT = (uint32)SCI_TX_INT;
+    }
+    else
+    {
+        /* send the data */
+        while (length > 0U)
+        {
+	        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+            while ((sci->FLR & (uint32)SCI_TX_INT) == 0U)
+            { 
+            } /* Wait */
+			/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+			txdata = *data;
+            sci->TD = (uint32)(txdata);
+			/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+            /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
+			data++;
+			length--;
+        }
+    }
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+
+/** @fn uint32 sciIsRxReady(sciBASE_t *sci)
+*   @brief Check if Rx buffer full
+*   @param[in] sci - sci module base address
+*
+*   @return The Rx ready flag
+*
+*   Checks to see if the Rx buffer full flag is set, returns
+*   0 is flags not set otherwise will return the Rx flag itself.
+*/
+/* SourceId : SCI_SourceId_007 */
+/* DesignId : SCI_DesignId_007 */
+/* Requirements : HL_SR236 */
+uint32 sciIsRxReady(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+    return sci->FLR & (uint32)SCI_RX_INT;
+}
+
+/** @fn uint32 sciIsIdleDetected(sciBASE_t *sci)
+*   @brief Check if Idle Period is Detected
+*   @param[in] sci - sci module base address
+*
+*   @return The Idle flag
+*
+*   Checks to see if the SCI Idle flag is set, returns 0 if idle
+*	period has been detected and SCI is ready to receive, otherwise returns the Idle flag itself.
+*/
+/* SourceId : SCI_SourceId_008 */
+/* DesignId : SCI_DesignId_008 */
+/* Requirements : HL_SR237 */
+uint32 sciIsIdleDetected(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+    return sci->FLR & (uint32)SCI_IDLE;
+}
+
+
+/** @fn uint32 sciRxError(sciBASE_t *sci)
+*   @brief Return Rx Error flags
+*   @param[in] sci - sci module base address
+*
+*   @return The Rx error flags
+*
+*   Returns the Rx framing, overrun and parity errors flags,
+*   also clears the error flags before returning.
+*/
+/* SourceId : SCI_SourceId_009 */
+/* DesignId : SCI_DesignId_009 */
+/* Requirements : HL_SR238 */
+uint32 sciRxError(sciBASE_t *sci)
+{
+    uint32 status = (sci->FLR & ((uint32)SCI_FE_INT | (uint32)SCI_OE_INT |(uint32)SCI_PE_INT));
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+    sci->FLR = ((uint32)SCI_FE_INT | (uint32)SCI_OE_INT | (uint32)SCI_PE_INT);
+    return status;
+}
+
+
+/** @fn uint32 sciReceiveByte(sciBASE_t *sci)
+*   @brief Receive Byte
+*   @param[in] sci - sci module base address
+*
+*   @return Received byte
+*
+*    Receives a single byte in polling mode.  If there is
+*    not a byte in the receive buffer the routine will wait
+*    until one is received.   Use sciIsRxReady to check to
+*    see if the buffer is full to avoid waiting.
+*/
+/* SourceId : SCI_SourceId_010 */
+/* DesignId : SCI_DesignId_010 */
+/* Requirements : HL_SR239 */
+uint32 sciReceiveByte(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+	/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+    while ((sci->FLR & (uint32)SCI_RX_INT) == 0U) 
+    { 
+    } /* Wait */
+
+    return (sci->RD & (uint32)0x000000FFU);
+}
+
+
+/** @fn void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data)
+*   @brief Receive Data
+*   @param[in] sci    - sci module base address
+*   @param[in] length - number of data words to transfer
+*   @param[in] data   - pointer to data buffer to receive data
+*
+*   Receive a block of 'length' bytes long and place it into the 
+*   data buffer pointed to by 'data'.  If interrupts have been 
+*   enabled the data is received using interrupt mode, otherwise
+*   polling mode is used.  In interrupt mode receive is setup and
+*   the routine returns immediately, sciReceive must not be called 
+*   again until the transfer is complete, when the sciNotification 
+*   callback will be called.  In polling mode, sciReceive will not
+*   return  until the transfer is complete.
+*/
+/* SourceId : SCI_SourceId_011 */
+/* DesignId : SCI_DesignId_011 */
+/* Requirements : HL_SR240 */
+void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data)
+{
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+    if ((sci->SETINT & (uint32)SCI_RX_INT) == (uint32)SCI_RX_INT)
+    {
+        /* we are in interrupt mode */
+        uint32 index = (sci == sciREG) ? 0U : 1U;
+        
+        /* clear error flags */
+        sci->FLR = ((uint32) SCI_FE_INT | (uint32) SCI_OE_INT | (uint32) SCI_PE_INT);
+
+        g_sciTransfer_t[index].rx_length = length;
+		/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+        g_sciTransfer_t[index].rx_data   = data;
+    }
+    else
+    {   
+        while (length > 0U)
+        {
+	        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+            while ((sci->FLR & (uint32)SCI_RX_INT) == 0U) 
+            { 
+            } /* Wait */
+			/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+            *data = (uint8)(sci->RD & 0x000000FFU);
+			/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+            /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
+			data++;
+			length--;
+        }
+    }
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+/** @fn void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype)
+*   @brief Enable Loopback mode for self test
+*   @param[in] sci        - sci module base address
+*   @param[in] Loopbacktype  - Digital or Analog
+*
+*   This function enables the Loopback mode for self test.
+*/
+/* SourceId : SCI_SourceId_012 */
+/* DesignId : SCI_DesignId_014 */
+/* Requirements : HL_SR243 */
+void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+    
+    /* Clear Loopback incase enabled already */
+    sci->IODFTCTRL = 0U;
+    
+    /* Enable Loopback either in Analog or Digital Mode */
+    sci->IODFTCTRL = (uint32)0x00000A00U
+                   | (uint32)((uint32)Loopbacktype << 1U);
+    
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+}
+
+/** @fn void sciDisableLoopback(sciBASE_t *sci)
+*   @brief Enable Loopback mode for self test
+*   @param[in] sci        - sci module base address
+*
+*   This function disable the Loopback mode.
+*/
+/* SourceId : SCI_SourceId_013 */
+/* DesignId : SCI_DesignId_015 */
+/* Requirements : HL_SR244 */
+void sciDisableLoopback(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+    
+    /* Disable Loopback Mode */
+    sci->IODFTCTRL = 0x00000500U;
+    
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+}
+
+/** @fn sciEnableNotification(sciBASE_t *sci, uint32 flags)
+*   @brief Enable interrupts
+*   @param[in] sci   - sci module base address
+*   @param[in] flags - Interrupts to be enabled, can be ored value of:
+*                      SCI_FE_INT    - framing error,
+*                      SCI_OE_INT    - overrun error,
+*                      SCI_PE_INT    - parity error,
+*                      SCI_RX_INT    - receive buffer ready,
+*                      SCI_TX_INT    - transmit buffer ready,
+*                      SCI_WAKE_INT  - wakeup,
+*                      SCI_BREAK_INT - break detect
+*/
+/* SourceId : SCI_SourceId_014 */
+/* DesignId : SCI_DesignId_012 */
+/* Requirements : HL_SR241 */
+void sciEnableNotification(sciBASE_t *sci, uint32 flags)
+{
+    uint32 index = (sci == sciREG) ? 0U : 1U;
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+    g_sciTransfer_t[index].mode |= (flags & (uint32)SCI_TX_INT);
+    sci->SETINT                = (flags & (uint32)(~(uint32)(SCI_TX_INT)));
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+}
+
+
+/** @fn sciDisableNotification(sciBASE_t *sci, uint32 flags)
+*   @brief Disable interrupts
+*   @param[in] sci   - sci module base address
+*   @param[in] flags - Interrupts to be disabled, can be ored value of:
+*                      SCI_FE_INT    - framing error,
+*                      SCI_OE_INT    - overrun error,
+*                      SCI_PE_INT    - parity error,
+*                      SCI_RX_INT    - receive buffer ready,
+*                      SCI_TX_INT    - transmit buffer ready,
+*                      SCI_WAKE_INT  - wakeup,
+*                      SCI_BREAK_INT - break detect
+*/
+/* SourceId : SCI_SourceId_015 */
+/* DesignId : SCI_DesignId_013 */
+/* Requirements : HL_SR242 */
+void sciDisableNotification(sciBASE_t *sci, uint32 flags)
+{
+    uint32 index = (sci == sciREG) ? 0U : 1U;
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+    g_sciTransfer_t[index].mode &= (uint32)(~(flags & (uint32)SCI_TX_INT));
+    sci->CLEARINT                = (flags & (uint32)(~(uint32)(SCI_TX_INT)));
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+}
+
+/** @fn sciEnterResetState(sciBASE_t *sci)
+*   @brief Enter reset state
+*   @param[in] sci   - sci module base address
+*   @note The SCI should only be configured while in reset state
+*/
+/* SourceId : SCI_SourceId_022 */
+/* DesignId : SCI_DesignId_018 */
+/* Requirements : HL_SR548 */
+void sciEnterResetState(sciBASE_t *sci)
+{
+	sci->GCR1 &= 0xFFFFFF7FU;
+}
+
+/** @fn scixitResetState(sciBASE_t *sci)
+*   @brief Exit reset state
+*   @param[in] sci   - sci module base address
+*   @note The SCI should only be configured while in reset state
+*/
+/* SourceId : SCI_SourceId_023 */
+/* DesignId : SCI_DesignId_018 */
+/* Requirements : HL_SR548 */
+void sciExitResetState(sciBASE_t *sci)
+{
+	sci->GCR1 |= 0x00000080U;
+}
+
+
+/** @fn void scilinGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the SCILIN ( SCI2) configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current 
+*                           value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') 
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : SCI_SourceId_017 */
+/* DesignId : SCI_DesignId_016 */
+/* Requirements : HL_SR247 */
+void scilinGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+		config_reg->CONFIG_GCR0      = SCILIN_GCR0_CONFIGVALUE;
+		config_reg->CONFIG_GCR1      = SCILIN_GCR1_CONFIGVALUE;
+		config_reg->CONFIG_SETINT    = SCILIN_SETINT_CONFIGVALUE;
+		config_reg->CONFIG_SETINTLVL = SCILIN_SETINTLVL_CONFIGVALUE;
+		config_reg->CONFIG_FORMAT    = SCILIN_FORMAT_CONFIGVALUE;
+		config_reg->CONFIG_BRS       = SCILIN_BRS_CONFIGVALUE;
+		config_reg->CONFIG_PIO0      = SCILIN_PIO0_CONFIGVALUE;
+		config_reg->CONFIG_PIO1      = SCILIN_PIO1_CONFIGVALUE;
+		config_reg->CONFIG_PIO6      = SCILIN_PIO6_CONFIGVALUE;
+		config_reg->CONFIG_PIO7	     = SCILIN_PIO7_CONFIGVALUE;
+		config_reg->CONFIG_PIO8      = SCILIN_PIO8_CONFIGVALUE;	
+	}
+	else
+	{
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+		config_reg->CONFIG_GCR0      = scilinREG->GCR0;
+		config_reg->CONFIG_GCR1      = scilinREG->GCR1; 
+		config_reg->CONFIG_SETINT    = scilinREG->SETINT; 
+		config_reg->CONFIG_SETINTLVL = scilinREG->SETINTLVL; 
+		config_reg->CONFIG_FORMAT    = scilinREG->FORMAT; 
+		config_reg->CONFIG_BRS       = scilinREG->BRS; 
+		config_reg->CONFIG_PIO0      = scilinREG->PIO0; 
+		config_reg->CONFIG_PIO1      = scilinREG->PIO1; 
+		config_reg->CONFIG_PIO6      = scilinREG->PIO6; 
+		config_reg->CONFIG_PIO7	     = scilinREG->PIO7;	 
+		config_reg->CONFIG_PIO8      = scilinREG->PIO8; 
+	}
+}
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+
diff --git a/src/arch/rm46l8lp/halcogen/sys_core.asm b/src/arch/rm46l8lp/halcogen/sys_core.asm
new file mode 100644
index 0000000..f02616e
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_core.asm
@@ -0,0 +1,734 @@
+;-------------------------------------------------------------------------------
+; sys_core.asm
+;
+; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+;
+;
+;  Redistribution and use in source and binary forms, with or without
+;  modification, are permitted provided that the following conditions
+;  are met:
+;
+;    Redistributions of source code must retain the above copyright
+;    notice, this list of conditions and the following disclaimer.
+;
+;    Redistributions in binary form must reproduce the above copyright
+;    notice, this list of conditions and the following disclaimer in the
+;    documentation and/or other materials provided with the
+;    distribution.
+;
+;    Neither the name of Texas Instruments Incorporated nor the names of
+;    its contributors may be used to endorse or promote products derived
+;    from this software without specific prior written permission.
+;
+;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;
+;
+
+    .text
+    .arm
+
+;-------------------------------------------------------------------------------
+; Initialize CPU Registers
+; SourceId : CORE_SourceId_001
+; DesignId : CORE_DesignId_001
+; Requirements: HL_SR477, HL_SR476, HL_SR492
+
+    .def     _coreInitRegisters_
+    .asmfunc
+
+
+_coreInitRegisters_
+
+
+    ; After reset, the CPU is in the Supervisor mode (M = 10011)
+        mov r0, lr
+        mov r1, #0x0000
+        mov r2, #0x0000
+        mov r3, #0x0000
+        mov r4, #0x0000
+        mov r5, #0x0000
+        mov r6, #0x0000
+        mov r7, #0x0000
+        mov r8, #0x0000
+        mov r9, #0x0000
+        mov r10, #0x0000
+        mov r11, #0x0000
+        mov r12, #0x0000
+        mov r13, #0x0000
+        mrs r1, cpsr
+        msr spsr_cxsf, r1
+        ; Switch to FIQ mode (M = 10001)
+        cps #17
+        mov lr, r0
+        mov r8, #0x0000
+        mov r9, #0x0000
+        mov r10, #0x0000
+        mov r11, #0x0000
+        mov r12, #0x0000
+        mrs r1, cpsr
+        msr spsr_cxsf, r1
+        ; Switch to IRQ mode (M = 10010)
+        cps #18
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1
+        ; Switch to Abort mode (M = 10111)
+        cps #23
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1
+        ; Switch to Undefined Instruction Mode (M = 11011)
+        cps #27
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1
+        ; Switch to System Mode ( Shares User Mode registers ) (M = 11111)
+        cps #31
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1
+
+
+        mrc   p15,     #0x00,      r2,       c1, c0, #0x02
+        orr   r2,      r2,         #0xF00000
+        mcr   p15,     #0x00,      r2,       c1, c0, #0x02
+        mov   r2,      #0x40000000
+        fmxr  fpexc,   r2
+
+        fmdrr d0,         r1,     r1
+        fmdrr d1,         r1,     r1
+        fmdrr d2,         r1,     r1
+        fmdrr d3,         r1,     r1
+        fmdrr d4,         r1,     r1
+        fmdrr d5,         r1,     r1
+        fmdrr d6,         r1,     r1
+        fmdrr d7,         r1,     r1
+        fmdrr d8,         r1,     r1
+        fmdrr d9,         r1,     r1
+        fmdrr d10,        r1,     r1
+        fmdrr d11,        r1,     r1
+        fmdrr d12,        r1,     r1
+        fmdrr d13,        r1,     r1
+        fmdrr d14,        r1,     r1
+        fmdrr d15,        r1,     r1
+        bl    next1
+next1
+        bl    next2
+next2
+        bl    next3
+next3
+        bl    next4
+next4
+        bx    r0
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Initialize Stack Pointers
+; SourceId : CORE_SourceId_002
+; DesignId : CORE_DesignId_002
+; Requirements: HL_SR478
+
+    .def     _coreInitStackPointer_
+    .asmfunc
+
+_coreInitStackPointer_
+
+        cps   #17
+        ldr   sp,       fiqSp
+        cps   #18
+        ldr   sp,       irqSp
+        cps   #19
+        ldr   sp,       svcSp
+        cps   #23
+        ldr   sp,       abortSp
+        cps   #27
+        ldr   sp,       undefSp
+        cps   #31
+        ldr   sp,       userSp
+        bx    lr
+
+userSp  .word 0x08000000+0x00001000
+svcSp   .word 0x08000000+0x00001000+0x00000100
+fiqSp   .word 0x08000000+0x00001000+0x00000100+0x00000100
+irqSp   .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000200
+abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000200+0x00000100
+undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000200+0x00000100+0x00000100
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Get CPSR Value
+; SourceId : CORE_SourceId_003
+; DesignId : CORE_DesignId_003
+; Requirements:
+
+    .def     _getCPSRValue_
+    .asmfunc
+
+_getCPSRValue_
+
+        mrs   r0, CPSR
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Take CPU to IDLE state
+; SourceId : CORE_SourceId_004
+; DesignId : CORE_DesignId_004
+; Requirements: HL_SR493
+
+    .def     _gotoCPUIdle_
+    .asmfunc
+
+_gotoCPUIdle_
+
+        WFI
+        nop
+        nop
+        nop
+        nop
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable VFP Unit
+; SourceId : CORE_SourceId_005
+; DesignId : CORE_DesignId_006
+; Requirements: HL_SR492, HL_SR476
+
+    .def     _coreEnableVfp_
+    .asmfunc
+
+_coreEnableVfp_
+
+        mrc   p15,     #0x00,      r0,       c1, c0, #0x02
+        orr   r0,      r0,         #0xF00000
+        mcr   p15,     #0x00,      r0,       c1, c0, #0x02
+        mov   r0,      #0x40000000
+        fmxr  fpexc,   r0
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Enable Event Bus Export
+; SourceId : CORE_SourceId_006
+; DesignId : CORE_DesignId_007
+; Requirements: HL_SR479
+
+    .def     _coreEnableEventBusExport_
+    .asmfunc
+
+_coreEnableEventBusExport_
+
+        mrc   p15, #0x00, r0,         c9, c12, #0x00
+        orr   r0,  r0,    #0x10
+        mcr   p15, #0x00, r0,         c9, c12, #0x00
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Disable Event Bus Export
+; SourceId : CORE_SourceId_007
+; DesignId : CORE_DesignId_008
+; Requirements: HL_SR481
+
+
+    .def     _coreDisableEventBusExport_
+    .asmfunc
+
+_coreDisableEventBusExport_
+
+        mrc   p15, #0x00, r0,         c9, c12, #0x00
+        bic   r0,  r0,    #0x10
+        mcr   p15, #0x00, r0,         c9, c12, #0x00
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable RAM ECC Support
+; SourceId : CORE_SourceId_008
+; DesignId : CORE_DesignId_009
+; Requirements: HL_SR480
+
+    .def     _coreEnableRamEcc_
+    .asmfunc
+
+_coreEnableRamEcc_
+
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        orr   r0,  r0,    #0x0C000000
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Disable RAM ECC Support
+; SourceId : CORE_SourceId_009
+; DesignId : CORE_DesignId_010
+; Requirements: HL_SR482
+
+    .def     _coreDisableRamEcc_
+    .asmfunc
+
+_coreDisableRamEcc_
+
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        bic   r0,  r0,    #0x0C000000
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable Flash ECC Support
+; SourceId : CORE_SourceId_010
+; DesignId : CORE_DesignId_011
+; Requirements: HL_SR480, HL_SR458
+
+    .def     _coreEnableFlashEcc_
+    .asmfunc
+
+_coreEnableFlashEcc_
+
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        orr   r0,  r0,    #0x02000000
+        dmb
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Disable Flash ECC Support
+; SourceId : CORE_SourceId_011
+; DesignId : CORE_DesignId_012
+; Requirements: HL_SR482
+
+    .def     _coreDisableFlashEcc_
+    .asmfunc
+
+_coreDisableFlashEcc_
+
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        bic   r0,  r0,    #0x02000000
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable Offset via Vic controller
+; SourceId : CORE_SourceId_012
+; DesignId : CORE_DesignId_005
+; Requirements: HL_SR483, HL_SR491
+
+    .def     _coreEnableIrqVicOffset_
+    .asmfunc
+
+_coreEnableIrqVicOffset_
+
+        mrc   p15, #0, r0,         c1, c0,  #0
+        orr   r0,  r0,    #0x01000000
+        mcr   p15, #0, r0,         c1, c0,  #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get data fault status register
+; SourceId : CORE_SourceId_013
+; DesignId : CORE_DesignId_013
+; Requirements: HL_SR495
+
+    .def     _coreGetDataFault_
+    .asmfunc
+
+_coreGetDataFault_
+
+        mrc   p15, #0, r0, c5, c0,  #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Clear data fault status register
+; SourceId : CORE_SourceId_014
+; DesignId : CORE_DesignId_014
+; Requirements: HL_SR495
+
+    .def     _coreClearDataFault_
+    .asmfunc
+
+_coreClearDataFault_
+
+        mov   r0,  #0
+        mcr   p15, #0, r0, c5, c0,  #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get instruction fault status register
+; SourceId : CORE_SourceId_015
+; DesignId : CORE_DesignId_015
+; Requirements: HL_SR495
+
+    .def     _coreGetInstructionFault_
+    .asmfunc
+
+_coreGetInstructionFault_
+
+        mrc   p15, #0, r0, c5, c0, #1
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Clear instruction fault status register
+; SourceId : CORE_SourceId_016
+; DesignId : CORE_DesignId_016
+; Requirements: HL_SR495
+
+    .def     _coreClearInstructionFault_
+    .asmfunc
+
+_coreClearInstructionFault_
+
+        mov   r0,  #0
+        mcr   p15, #0, r0, c5, c0, #1
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get data fault address register
+; SourceId : CORE_SourceId_017
+; DesignId : CORE_DesignId_017
+; Requirements: HL_SR495
+
+    .def     _coreGetDataFaultAddress_
+    .asmfunc
+
+_coreGetDataFaultAddress_
+
+        mrc   p15, #0, r0, c6, c0,  #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Clear data fault address register
+; SourceId : CORE_SourceId_018
+; DesignId : CORE_DesignId_018
+; Requirements: HL_SR495
+
+    .def     _coreClearDataFaultAddress_
+    .asmfunc
+
+_coreClearDataFaultAddress_
+
+        mov   r0,  #0
+        mcr   p15, #0, r0, c6, c0,  #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get instruction fault address register
+; SourceId : CORE_SourceId_019
+; DesignId : CORE_DesignId_019
+; Requirements: HL_SR495
+
+    .def     _coreGetInstructionFaultAddress_
+    .asmfunc
+
+_coreGetInstructionFaultAddress_
+
+        mrc   p15, #0, r0, c6, c0, #2
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Clear instruction fault address register
+; SourceId : CORE_SourceId_020
+; DesignId : CORE_DesignId_020
+; Requirements: HL_SR495
+
+    .def     _coreClearInstructionFaultAddress_
+    .asmfunc
+
+_coreClearInstructionFaultAddress_
+
+        mov   r0,  #0
+        mcr   p15, #0, r0, c6, c0, #2
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get auxiliary data fault status register
+; SourceId : CORE_SourceId_021
+; DesignId : CORE_DesignId_021
+; Requirements: HL_SR496
+
+    .def     _coreGetAuxiliaryDataFault_
+    .asmfunc
+
+_coreGetAuxiliaryDataFault_
+
+        mrc   p15, #0, r0, c5, c1, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Clear auxiliary data fault status register
+; SourceId : CORE_SourceId_022
+; DesignId : CORE_DesignId_022
+; Requirements: HL_SR496
+
+    .def     _coreClearAuxiliaryDataFault_
+    .asmfunc
+
+_coreClearAuxiliaryDataFault_
+
+        mov   r0,  #0
+        mcr   p15, #0, r0, c5, c1, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get auxiliary instruction fault status register
+; SourceId : CORE_SourceId_023
+; DesignId : CORE_DesignId_023
+; Requirements: HL_SR496
+
+    .def     _coreGetAuxiliaryInstructionFault_
+    .asmfunc
+
+_coreGetAuxiliaryInstructionFault_
+
+        mrc   p15, #0, r0, c5, c1, #1
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Clear auxiliary instruction fault status register
+; SourceId : CORE_SourceId_024
+; DesignId : CORE_DesignId_024
+; Requirements: HL_SR496
+
+    .def     _coreClearAuxiliaryInstructionFault_
+    .asmfunc
+
+_coreClearAuxiliaryInstructionFault_
+
+        mov   r0,  #0
+        mrc   p15, #0, r0, c5, c1, #1
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Disable interrupts - R4 IRQ & FIQ
+; SourceId : CORE_SourceId_025
+; DesignId : CORE_DesignId_025
+; Requirements: HL_SR494
+
+        .def _disable_interrupt_
+        .asmfunc
+
+_disable_interrupt_
+
+        cpsid if
+        bx    lr
+
+        .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Disable FIQ interrupt
+; SourceId : CORE_SourceId_026
+; DesignId : CORE_DesignId_026
+; Requirements: HL_SR494
+
+        .def _disable_FIQ_interrupt_
+        .asmfunc
+
+_disable_FIQ_interrupt_
+
+        cpsid f
+        bx    lr
+
+        .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Disable FIQ interrupt
+
+        .def _disable_IRQ_interrupt_
+        .asmfunc
+
+_disable_IRQ_interrupt_
+
+        cpsid i
+        bx    lr
+
+        .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Enable interrupts - R4 IRQ & FIQ
+
+       .def _enable_interrupt_
+       .asmfunc
+
+_enable_interrupt_
+
+        cpsie if
+        bx    lr
+
+        .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Clear ESM CCM errorss
+
+       .def _esmCcmErrorsClear_
+       .asmfunc
+
+_esmCcmErrorsClear_
+
+        stmfd sp!, {r0-r2}
+        ldr   r0, ESMSR1_REG    ; load the ESMSR1 status register address
+        ldr   r2, ESMSR1_ERR_CLR
+        str   r2, [r0]         ; clear the ESMSR1 register
+
+        ldr   r0, ESMSR2_REG    ; load the ESMSR2 status register address
+        ldr   r2, ESMSR2_ERR_CLR
+        str   r2, [r0]         ; clear the ESMSR2 register
+
+        ldr   r0, ESMSSR2_REG    ; load the ESMSSR2 status register address
+        ldr   r2, ESMSSR2_ERR_CLR
+        str   r2, [r0]             ; clear the ESMSSR2 register
+
+        ldr   r0, ESMKEY_REG    ; load the ESMKEY register address
+        mov   r2, #0x5             ; load R2 with 0x5
+        str   r2, [r0]             ; clear the ESMKEY register
+
+        ldr   r0, VIM_INTREQ    ; load the INTREQ register address
+        ldr   r2, VIM_INT_CLR
+        str   r2, [r0]         ; clear the INTREQ register
+        ldr   r0, CCMR4_STAT_REG    ; load the CCMR4 status register address
+        ldr   r2, CCMR4_ERR_CLR
+        str   r2, [r0]         ; clear the CCMR4 status register
+        ldmfd sp!, {r0-r2}
+        bx    lr
+
+ESMSR1_REG        .word 0xFFFFF518
+ESMSR2_REG        .word 0xFFFFF51C
+ESMSR3_REG        .word 0xFFFFF520
+ESMKEY_REG        .word 0xFFFFF538
+ESMSSR2_REG       .word 0xFFFFF53C
+CCMR4_STAT_REG    .word 0xFFFFF600
+ERR_CLR_WRD       .word 0xFFFFFFFF
+CCMR4_ERR_CLR     .word 0x00010000
+ESMSR1_ERR_CLR    .word 0x80000000
+ESMSR2_ERR_CLR    .word 0x00000004
+ESMSSR2_ERR_CLR   .word 0x00000004
+VIM_INT_CLR       .word 0x00000001
+VIM_INTREQ        .word 0xFFFFFE20
+
+        .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Work Around for Errata CORTEX-R4#57:
+;
+; Errata Description:
+;            Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
+; Workaround:
+;            Disable out-of-order single-precision floating point
+;            multiply-accumulate instruction completion
+
+        .def     _errata_CORTEXR4_57_
+        .asmfunc
+
+_errata_CORTEXR4_57_
+
+        mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register
+        orr r0, r0, #0x10000         ; Set BIT 16 (Set DOOFMACS)
+        mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register
+        bx lr
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Work Around for Errata CORTEX-R4#66:
+;
+; Errata Description:
+;            Register Corruption During A Load-Multiple Instruction At
+;            an Exception Vector
+; Workaround:
+;            Disable out-of-order completion for divide instructions in
+;            Auxiliary Control register
+
+        .def     _errata_CORTEXR4_66_
+        .asmfunc
+
+_errata_CORTEXR4_66_
+
+        mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register
+          orr r0, r0, #0x80           ; Set BIT 7 (Disable out-of-order completion
+                                    ; for divide instructions.)
+           mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register
+        bx lr
+    .endasmfunc
+;-------------------------------------------------------------------------------
+; C++ construct table pointers
+
+    .def    __TI_PINIT_Base, __TI_PINIT_Limit
+    .weak   SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit
+
+__TI_PINIT_Base  .long SHT$$INIT_ARRAY$$Base
+__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit
+
+
+    
+;-------------------------------------------------------------------------------
+
diff --git a/src/arch/rm46l8lp/halcogen/sys_dma.c b/src/arch/rm46l8lp/halcogen/sys_dma.c
new file mode 100644
index 0000000..3bbed4f
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_dma.c
@@ -0,0 +1,449 @@
+/** @file dma.c
+*   @brief DMA Driver Implementation File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#include "sys_dma.h"
+#include "sys_vim.h"
+
+/** @fn void dmaEnable(void)
+*   @brief enables DMA module
+*
+*   This function brings DMA out of reset
+*/
+/* SourceId : DMA_SourceId_001 */
+/* DesignId : DMA_DesignId_001 */
+/* Requirements: HL_SR167 */
+void dmaEnable(void)
+{
+  dmaREG->GCTRL  = 0x00010000U; /* enable dma      */
+  dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */
+}
+
+/** @fn void dmaDisable(void)
+*   @brief disables DMA module
+*
+*   This function disables DMA module
+*/
+/* SourceId : DMA_SourceId_002 */
+/* DesignId : DMA_DesignId_002 */
+/* Requirements: HL_SR168 */
+void dmaDisable(void)
+{
+    /* Wait until DMA's external bus has completed data transfer */
+    /*SAFETYMCUSW 134 S MR: 12.2 <APPROVED> "Tool issue" */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while((dmaREG->GCTRL & DMA_GCTRL_BUSBUSY) != 0U)
+    {
+    } /* Wait */
+    /* Disable DMA module */
+    dmaREG->GCTRL = 0U;
+}
+
+
+/** @fn void dmaReqAssign(uint32 channel,uint32 reqline)
+*   @brief Assign DMA request lines to channels
+*   @param[in] channel DMA channel
+*   @param[in] reqline DMA request line
+*
+*   This function assigns DMA request lines to channels
+*/
+/* SourceId : DMA_SourceId_003 */
+/* DesignId : DMA_DesignId_005 */
+/* Requirements: HL_SR169 */
+void dmaReqAssign(uint32 channel,uint32 reqline)
+{
+    register uint32 i=0U,j=0U;
+
+    i = channel >> 2U;              /* Find the register to configure */
+    j = channel - (i << 2U);        /* Find the offset of the type    */
+    j = 3U - j;                     /* reverse the byte order         */
+    j = j << 3U;                    /* find the bit location          */
+
+    /* mapping channel 'i' to request line 'j' */
+    dmaREG->DREQASI[i] &= ~(uint32)((uint32)0xFFU << j);
+    dmaREG->DREQASI[i] |= (reqline << j);
+}
+
+
+/** @fn uint32 dmaGetReq(uint32 channel)
+*   @brief Gets the request line number mapped to the selected channel
+*   @param[in] channel DMA channel
+*
+*   This function returns the request line number mapped to the selected channel
+*/
+/* SourceId : DMA_SourceId_004 */
+/* DesignId : DMA_DesignId_006 */
+/* Requirements: HL_SR170 */
+uint32 dmaGetReq(uint32 channel)
+{
+    register uint32 i=0U,j=0U;
+
+    i = channel >> 2U;              /* Find the register to configure */
+    j = channel - (i << 2U);        /* Find the offset of the type    */
+    j = 3U - j;                     /* reverse the byte order         */
+    j = j << 3U;                    /* find the bit location          */
+    return ((dmaREG->DREQASI[i] >> j) & 0xFFU);
+}
+
+
+/** @fn void dmaSetCtrlPacket(uint32 channel)
+*   @brief Set control packet
+*
+*   This function sets control packet
+*/
+/* SourceId : DMA_SourceId_005 */
+/* DesignId : DMA_DesignId_003 */
+/* Requirements: HL_SR171 */
+void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT)
+{
+    register uint32 i=0U,j=0U;
+
+    dmaRAMREG->PCP[channel].ISADDR  =  g_dmaCTRLPKT.SADD;
+
+    dmaRAMREG->PCP[channel].IDADDR  =  g_dmaCTRLPKT.DADD;
+
+    dmaRAMREG->PCP[channel].ITCOUNT = (g_dmaCTRLPKT.FRCNT << 16U) | g_dmaCTRLPKT.ELCNT;
+
+    dmaRAMREG->PCP[channel].CHCTRL  = (g_dmaCTRLPKT.RDSIZE    << 14U) | (g_dmaCTRLPKT.WRSIZE    << 12U) | (g_dmaCTRLPKT.TTYPE << 8U)| \
+                                      (g_dmaCTRLPKT.ADDMODERD << 3U ) | (g_dmaCTRLPKT.ADDMODEWR << 1U ) | (g_dmaCTRLPKT.AUTOINIT);
+
+    dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16U);
+
+    dmaRAMREG->PCP[channel].EIOFF   = (g_dmaCTRLPKT.ELDOFFSET << 16U) | (g_dmaCTRLPKT.ELSOFFSET);
+
+    dmaRAMREG->PCP[channel].FIOFF   = (g_dmaCTRLPKT.FRDOFFSET << 16U) | (g_dmaCTRLPKT.FRSOFFSET);
+
+    i = channel >> 3U;                /* Find the register to write                    */
+    j = channel - (i << 3U);          /* Find the offset of the 4th bit                */
+    j = 7U - j;                       /* Reverse the order of the 4th bit offset       */
+    j = j << 2U;                      /* Find the bit location of the 4th bit to write */
+
+    dmaREG->PAR[i] &= ~(uint32)((uint32)0xFU << j);
+    dmaREG->PAR[i] |= (g_dmaCTRLPKT.PORTASGN << j);
+}
+
+
+
+/** @fn void dmaSetChEnable(uint32 channel,uint32 type)
+*   @brief Enable channel
+*   @param[in] channel DMA channel
+*   @param[in] type Type of triggering
+*                    - DMA_HW: Enables the selected DMA channel for hardware triggering
+*                    - DMA_SW: Enables the selected DMA channel for software triggering
+*
+*   This function enables the DMA channel for hardware or software triggering
+*/
+/* SourceId : DMA_SourceId_006 */
+/* DesignId : DMA_DesignId_004 */
+/* Requirements: HL_SR172 */
+void dmaSetChEnable(uint32 channel,uint32 type)
+{
+    if(type == (uint32)DMA_HW)
+    {
+     dmaREG->HWCHENAS = (uint32)1U << channel;
+    }
+    else if(type == (uint32)DMA_SW)
+    {
+     dmaREG->SWCHENAS = (uint32)1U << channel;
+    }
+    else
+    {
+    /* Empty  */
+    }
+}
+
+
+
+/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
+*   @brief Assign Priority to the channel
+*   @param[in] channel DMA channel
+*   @param[in] priority Priority queue to which channel needs to be assigned
+*                        - LOWPRIORITY : The selected channel will be assigned to low priority queue
+*                        - HIGHPRIORITY: The selected channel will be assigned to high priority queue
+*
+*   This function assigns the selected priority to the selected channel
+*/
+/* SourceId : DMA_SourceId_007 */
+/* DesignId : DMA_DesignId_007 */
+/* Requirements: HL_SR173 */
+void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
+{
+    if (priority == LOWPRIORITY)
+    {
+        dmaREG->CHPRIOR = (uint32)1U << channel;
+    }
+    else
+    {
+        dmaREG->CHPRIOS = (uint32)1U << channel;
+    }
+}
+
+
+/** @fn void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
+*   @brief Enable selected interrupt
+*   @param[in] channel DMA channel
+*   @param[in] inttype Interrupt to be enabled
+*                       - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
+*                       - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
+*                       - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
+*                       - BTC: Block transfer complete Interrupt will be disabled for the selected channel
+*                       - BER: Bus Error Interrupt will be disabled for the selected channel
+*
+*   This function enables the selected interrupt for the selected channel
+*/
+/* SourceId : DMA_SourceId_008 */
+/* DesignId : DMA_DesignId_008 */
+/* Requirements: HL_SR174 */
+void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
+{
+    dmaREG->GCHIENAS = (uint32)1U << channel;
+
+    switch (inttype)
+    {
+    case FTC:   dmaREG->FTCINTENAS = (uint32)1U << channel;
+                break;
+    case LFS:   dmaREG->LFSINTENAS = (uint32)1U << channel;
+                break;
+    case HBC:   dmaREG->HBCINTENAS = (uint32)1U << channel;
+                break;
+    case BTC:   dmaREG->BTCINTENAS = (uint32)1U << channel;
+                break;
+    default :
+                break;
+    }
+}
+
+
+
+/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
+*   @brief Disable selected interrupt
+*   @param[in] channel DMA channel
+*   @param[in] inttype Interrupt to be disabled
+*                       - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
+*                       - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
+*                       - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
+*                       - BTC: Block transfer complete Interrupt will be disabled for the selected channel
+*                       - BER: Bus Error Interrupt will be disabled for the selected channel
+*
+*   This function disables the selected interrupt for the selected channel
+*/
+/* SourceId : DMA_SourceId_009 */
+/* DesignId : DMA_DesignId_009 */
+/* Requirements: HL_SR175 */
+void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
+{
+    switch (inttype)
+    {
+    case FTC:   dmaREG->FTCINTENAR = (uint32)1U << channel;
+                break;
+    case LFS:   dmaREG->LFSINTENAR = (uint32)1U << channel;
+                break;
+    case HBC:   dmaREG->HBCINTENAR = (uint32)1U << channel;
+                break;
+    case BTC:   dmaREG->BTCINTENAR = (uint32)1U << channel;
+                break;
+    default :
+                break;
+    }
+}
+
+
+
+/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
+*   @brief Configure start and end address of the region
+*   @param[in] region Memory Region
+*                     - DMA_REGION0
+*                     - DMA_REGION1
+*                     - DMA_REGION2
+*                     - DMA_REGION3
+*   @param[in] start_add Start address of the the region
+*   @param[in] end_add End address of the region
+*
+*   This function configure start and end address of the selected region
+*/
+/* SourceId : DMA_SourceId_010 */
+/* DesignId : DMA_DesignId_010 */
+/* Requirements: HL_SR176 */
+void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
+{
+    dmaREG->DMAMPR[region].STARTADD = start_add;
+    dmaREG->DMAMPR[region].ENDADD = end_add;
+}
+
+
+
+/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
+*   @brief Enable the selected region
+*   @param[in] region Memory Region
+*                     - DMA_REGION0
+*                     - DMA_REGION1
+*                     - DMA_REGION2
+*                     - DMA_REGION3
+*   @param[in] access Access permission of the selected region
+*                      - FULLACCESS
+*                      - READONLY
+*                      - WRITEONLY
+*                      - NOACCESS
+*   @param[in] intenable Interrupt to be enabled or not
+*                         - INTERRUPT_ENABLE : Enable interrupt for the selected region
+*                         - INTERRUPT_DISABLE: Disable interrupt for the selected region
+*
+*   This function enables the selected region with selected access permission with or without interrupt enable
+*/
+/* SourceId : DMA_SourceId_011 */
+/* DesignId : DMA_DesignId_011 */
+/* Requirements: HL_SR177 */
+void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
+{
+    dmaREG->DMAMPCTRL &= ~(uint32)((uint32)0xFFU << (region*8U));
+
+    /* Enable the region */
+    dmaREG->DMAMPCTRL |= (uint32)1U << (region*8U);
+
+    /* Set access permission for the region */
+    dmaREG->DMAMPCTRL |= (uint32)access << ((region*8U) + 1U);
+
+    if(intenable)
+    {
+        /* Enable interrupt */
+        dmaREG->DMAMPCTRL |= (uint32)1U << ((region*8U) + 3U);
+    }
+}
+
+
+
+/** @fn void dmaDisableRegion(dmaREGION_t region)
+*   @brief Disable the selected region
+*   @param[in] region Memory Region
+*                     - DMA_REGION0
+*                     - DMA_REGION1
+*                     - DMA_REGION2
+*                     - DMA_REGION3
+*
+*   This function disables the selected region(no address checking done).
+*/
+/* SourceId : DMA_SourceId_012 */
+/* DesignId : DMA_DesignId_012 */
+/* Requirements: HL_SR178 */
+void dmaDisableRegion(dmaREGION_t region)
+{
+    dmaREG->DMAMPCTRL &= ~(uint32)((uint32)1U << ((uint32)region*8U));
+}
+
+
+
+/** @fn void dmaEnableParityCheck(void)
+*   @brief Enable Parity Check
+*
+*   This function enables parity check
+*/
+/* SourceId : DMA_SourceId_013 */
+/* DesignId : DMA_DesignId_013 */
+/* Requirements: HL_SR179 */
+void dmaEnableParityCheck(void)
+{
+    dmaREG->DMAPCR = 0xAU;
+}
+
+
+
+/** @fn void dmaDisableParityCheck(void)
+*   @brief Disable Parity Check
+*
+*   This function disables parity check
+*/
+/* SourceId : DMA_SourceId_014 */
+/* DesignId : DMA_DesignId_014 */
+/* Requirements: HL_SR180 */
+void dmaDisableParityCheck(void)
+{
+    dmaREG->DMAPCR = 0x5U;
+}
+
+/** @fn void dmaGetConfigValue(dma_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*   @param[in] *config_reg: pointer to the struct to which the initial or current
+*                           value of the configuration registers need to be stored
+*   @param[in] type:    whether initial or current value of the configuration registers need to be stored
+*                       - InitialValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*                       - CurrentValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type')
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : DMA_SourceId_015 */
+/* DesignId : DMA_DesignId_015 */
+/* Requirements: HL_SR183 */
+void dmaGetConfigValue(dma_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {/* Do not pass Initial value as parameter as there is no DMA initialization API */
+    }
+    else
+    {
+        config_reg->CONFIG_CHPRIOS     = dmaREG->CHPRIOS;
+        config_reg->CONFIG_GCHIENAS    = dmaREG->GCHIENAS;
+        config_reg->CONFIG_DREQASI[0U] = dmaREG->DREQASI[0U];
+        config_reg->CONFIG_DREQASI[1U] = dmaREG->DREQASI[1U];
+        config_reg->CONFIG_DREQASI[2U] = dmaREG->DREQASI[2U];
+        config_reg->CONFIG_DREQASI[3U] = dmaREG->DREQASI[3U];
+        config_reg->CONFIG_DREQASI[4U] = dmaREG->DREQASI[4U];
+        config_reg->CONFIG_DREQASI[5U] = dmaREG->DREQASI[5U];
+        config_reg->CONFIG_DREQASI[6U] = dmaREG->DREQASI[6U];
+        config_reg->CONFIG_DREQASI[7U] = dmaREG->DREQASI[7U];
+        config_reg->CONFIG_FTCINTENAS  = dmaREG->FTCINTENAS;
+        config_reg->CONFIG_LFSINTENAS  = dmaREG->LFSINTENAS;
+        config_reg->CONFIG_HBCINTENAS  = dmaREG->HBCINTENAS;
+        config_reg->CONFIG_BTCINTENAS  = dmaREG->BTCINTENAS;
+        config_reg->CONFIG_DMAPCR      = dmaREG->DMAPCR;
+        config_reg->CONFIG_DMAMPCTRL   = dmaREG->DMAMPCTRL;
+    }
+}
+
+
+
+
+
diff --git a/src/arch/rm46l8lp/halcogen/sys_intvecs.asm b/src/arch/rm46l8lp/halcogen/sys_intvecs.asm
new file mode 100644
index 0000000..e0833fc
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_intvecs.asm
@@ -0,0 +1,66 @@
+;-------------------------------------------------------------------------------
+; sys_intvecs.asm
+;
+; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+; 
+; 
+;  Redistribution and use in source and binary forms, with or without 
+;  modification, are permitted provided that the following conditions 
+;  are met:
+;
+;    Redistributions of source code must retain the above copyright 
+;    notice, this list of conditions and the following disclaimer.
+;
+;    Redistributions in binary form must reproduce the above copyright
+;    notice, this list of conditions and the following disclaimer in the 
+;    documentation and/or other materials provided with the   
+;    distribution.
+;
+;    Neither the name of Texas Instruments Incorporated nor the names of
+;    its contributors may be used to endorse or promote products derived
+;    from this software without specific prior written permission.
+;
+;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;
+;
+
+    .sect ".intvecs"
+    .arm
+
+;-------------------------------------------------------------------------------
+; import reference for interrupt routines
+
+    .ref _c_int00
+    .ref _dabort
+    .ref phantomInterrupt
+    .def resetEntry
+
+;-------------------------------------------------------------------------------
+; interrupt vectors
+
+resetEntry
+        b   _c_int00
+undefEntry
+        b   undefEntry
+svcEntry
+        b   svcEntry
+prefetchEntry
+        b   prefetchEntry
+        b   _dabort
+        b   phantomInterrupt
+        ldr pc,[pc,#-0x1b0]
+        ldr pc,[pc,#-0x1b0]
+
+    
+;-------------------------------------------------------------------------------
diff --git a/src/arch/rm46l8lp/halcogen/sys_link.cmd b/src/arch/rm46l8lp/halcogen/sys_link.cmd
new file mode 100644
index 0000000..04ef758c
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_link.cmd
@@ -0,0 +1,134 @@
+/*----------------------------------------------------------------------------*/
+/* sys_link.cmd                                                               */
+/*                                                                            */
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+/*                                                                            */
+/*----------------------------------------------------------------------------*/
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/*----------------------------------------------------------------------------*/
+/* Linker Settings                                                            */
+
+--retain="*(.intvecs)"
+
+/* USER CODE BEGIN (1) */
+#if 1
+/* USER CODE END */
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map                                                                 */
+
+MEMORY
+{
+    VECTORS (X)  : origin=0x00000000 length=0x00000020
+    FLASH0  (RX) : origin=0x00000020 length=0x0013FFE0
+    STACKS  (RW) : origin=0x08000000 length=0x00001600
+    RAM     (RW) : origin=0x08001600 length=0x0002ea00
+
+/* USER CODE BEGIN (2) */
+#endif
+#if 0
+MEMORY
+{
+
+    VECTORS (X)  	: origin=0x00000000 length=0x00000020
+    FLASH0  (RX)    : origin=0x00000020 length=0x0013FF00
+    FLASH1  (RX) 	: origin=0x00180000 length=0x00180000
+
+    STACKS  (RW) 	: origin=0x08000000 length=0x00001800
+    RAM (RW)		: origin=0x08001800 length=0x0002E7FF
+#endif
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (3) */
+#if 1
+/* USER CODE END */
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration                                                      */
+
+SECTIONS
+{
+    .intvecs : {} > VECTORS
+    .text    : {} > FLASH0 
+    .const   : {} > FLASH0 
+    .cinit   : {} > FLASH0 
+    .pinit   : {} > FLASH0 
+    .bss     : {} > RAM
+    .data    : {} > RAM
+    .sysmem  : {} > RAM
+    
+
+/* USER CODE BEGIN (4) */
+#endif
+#if 0
+SECTIONS
+{
+    .intvecs 	: {} > VECTORS
+    .text   	: {} > FLASH0 | FLASH1
+    .const   	: {} > FLASH0 | FLASH1
+    .cinit      : {} > FLASH0 | FLASH1
+    .pinit    	: {} > FLASH0 | FLASH1
+    .bss    		    : {} > RAM
+    .data    		    : {} > RAM
+	.sysmem			    : {} > RAM
+
+    .STACK_DATA_svc     : {. += 1024;} > STACKS, RUN_START(StackModeSVC)
+    .STACK_DATA_fiq     : {. += 1024;} > STACKS, RUN_START(StackModeFIQ)
+    .STACK_DATA_irq     : {. += 1024;} > STACKS, RUN_START(StackModeIRQ)
+    .STACK_DATA_abt     : {. += 1024;} > STACKS, RUN_START(StackModeABT)
+    .STACK_DATA_und     : {. += 1024;} > STACKS, RUN_START(StackModeUND)
+    .STACK_DATA_sys     : {. += 1024;} > STACKS, RUN_START(StackModeSYS)
+    .bss    		    : {} > RAM
+    .data    		    : {} > RAM
+	.sysmem			    : {} > RAM
+#endif
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+
+/*----------------------------------------------------------------------------*/
+/* Misc                                                                       */
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+/*----------------------------------------------------------------------------*/
diff --git a/src/arch/rm46l8lp/halcogen/sys_main.c b/src/arch/rm46l8lp/halcogen/sys_main.c
new file mode 100644
index 0000000..a8d5070
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_main.c
@@ -0,0 +1,76 @@
+/** @file sys_main.c 
+*   @brief Application main file
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file contains an empty main function,
+*   which can be used for the application.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Include Files */
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void main(void)
+*   @brief Application main function
+*   @note This function is empty by default.
+*
+*   This function is called after startup.
+*   The user can use this function to implement the application.
+*/
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+int main(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+    return 0;
+}
+
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
diff --git a/src/arch/rm46l8lp/halcogen/sys_mpu.asm b/src/arch/rm46l8lp/halcogen/sys_mpu.asm
new file mode 100644
index 0000000..990f177
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_mpu.asm
@@ -0,0 +1,470 @@
+;-------------------------------------------------------------------------------
+; sys_mpu.asm
+;
+; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+;
+;
+;  Redistribution and use in source and binary forms, with or without
+;  modification, are permitted provided that the following conditions
+;  are met:
+;
+;    Redistributions of source code must retain the above copyright
+;    notice, this list of conditions and the following disclaimer.
+;
+;    Redistributions in binary form must reproduce the above copyright
+;    notice, this list of conditions and the following disclaimer in the
+;    documentation and/or other materials provided with the
+;    distribution.
+;
+;    Neither the name of Texas Instruments Incorporated nor the names of
+;    its contributors may be used to endorse or promote products derived
+;    from this software without specific prior written permission.
+;
+;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;
+;
+
+    .text
+    .arm
+
+
+;-------------------------------------------------------------------------------
+; Initalize Mpu
+; SourceId : MPU_SourceId_001
+; DesignId : MPU_DesignId_001
+; Requirements : HL_SR487
+
+    .def     _mpuInit_
+    .asmfunc
+
+_mpuInit_
+        ; Disable mpu
+        mrc   p15, #0, r0, c1, c0, #0
+        bic   r0,  r0, #1
+        dsb
+        mcr   p15, #0, r0, c1, c0, #0
+        isb
+        ; Disable background region
+        mrc   p15, #0, r0,      c1, c0, #0
+        bic   r0,  r0, #0x20000
+        mcr   p15, #0, r0,      c1, c0, #0
+        ; Setup region 1
+        mov   r0,  #0
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r1Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x1000
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 <<  9) + (1 <<  8) + (0x1F << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 2
+        mov   r0,  #1
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r2Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x0600
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x15 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region
+        mov   r0,  #2
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r3Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x0300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x11 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 4
+        mov   r0,  #3
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r4Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x0300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x11 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 5
+        mov   r0,  #4
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r5Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0000
+        orr   r0,  r0,    #0x0300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x19 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 6
+        mov   r0,  #5
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r6Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0000
+        orr   r0,  r0,    #0x0300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x1A << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 7
+        mov   r0,  #6
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r7Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x1200
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x16 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 8
+        mov   r0,  #7
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r8Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0010
+        orr   r0,  r0,    #0x1300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x17 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 9
+        mov   r0,  #8
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r9Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0010
+        orr   r0,  r0,    #0x1300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x08 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 10
+        mov   r0,  #9
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r10Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0010
+        orr   r0,  r0,    #0x1300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x17 << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 11
+        mov   r0,  #10
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r11Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x0300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((1 << 15) + (1 << 14) + (1 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x0A << 1) + (1))
+        mcr   p15, #0,    r0, c6, c1, #2
+        ; Setup region 12
+        mov   r0,  #11
+        mcr   p15, #0,    r0, c6, c2, #0
+        ldr   r0,  r12Base
+        mcr   p15, #0,    r0, c6, c1, #0
+        mov   r0,  #0x0008
+        orr   r0,  r0,    #0x1300
+        mcr   p15, #0,    r0, c6, c1, #4
+        movw  r0,  #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 <<  9) + (0 <<  8) + (0x15 << 1) + (0))
+        mcr   p15, #0,    r0, c6, c1, #2
+
+
+        ; Enable mpu background region
+        mrc   p15, #0, r0,      c1, c0, #0
+        orr   r0,  r0, #0x20000
+        mcr   p15, #0, r0,      c1, c0, #0
+        ; Enable mpu
+        mrc   p15, #0, r0, c1, c0, #0
+        orr   r0,  r0, #1
+        dsb
+        mcr   p15, #0, r0, c1, c0, #0
+        isb
+        bx    lr
+
+r1Base  .word 0x00000000
+r2Base  .word 0x00000000
+r3Base  .word 0x08000000
+r4Base  .word 0x08400000
+r5Base  .word 0x60000000
+r6Base  .word 0x80000000
+r7Base  .word 0xF0000000
+r8Base  .word 0xFC000000
+r9Base  .word 0xFE000000
+r10Base  .word 0xFF000000
+r11Base  .word 0x08001800
+r12Base  .word 0x20000000
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable Mpu
+; SourceId : MPU_SourceId_002
+; DesignId : MPU_DesignId_002
+; Requirements : HL_SR488
+
+    .def     _mpuEnable_
+    .asmfunc
+
+_mpuEnable_
+
+        mrc   p15, #0, r0, c1, c0, #0
+        orr   r0,  r0, #1
+        dsb
+        mcr   p15, #0, r0, c1, c0, #0
+        isb
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Disable Mpu
+; SourceId : MPU_SourceId_003
+; DesignId : MPU_DesignId_003
+; Requirements : HL_SR488
+
+    .def     _mpuDisable_
+    .asmfunc
+
+_mpuDisable_
+
+        mrc   p15, #0, r0, c1, c0, #0
+        bic   r0,  r0, #1
+        dsb
+        mcr   p15, #0, r0, c1, c0, #0
+        isb
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable Mpu background region
+; SourceId : MPU_SourceId_004
+; DesignId : MPU_DesignId_004
+; Requirements : HL_SR488
+
+    .def     _mpuEnableBackgroundRegion_
+    .asmfunc
+
+_mpuEnableBackgroundRegion_
+
+        mrc   p15, #0, r0,      c1, c0, #0
+        orr   r0,  r0, #0x20000
+        mcr   p15, #0, r0,      c1, c0, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Disable Mpu background region
+; SourceId : MPU_SourceId_005
+; DesignId : MPU_DesignId_005
+; Requirements : HL_SR488
+
+    .def     _mpuDisableBackgroundRegion_
+    .asmfunc
+
+_mpuDisableBackgroundRegion_
+
+        mrc   p15, #0, r0,      c1, c0, #0
+        bic   r0,  r0, #0x20000
+        mcr   p15, #0, r0,      c1, c0, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Returns number of implemented Mpu regions
+; SourceId : MPU_SourceId_006
+; DesignId : MPU_DesignId_006
+; Requirements : HL_SR490
+
+    .def     _mpuGetNumberOfRegions_
+    .asmfunc
+
+_mpuGetNumberOfRegions_
+
+        mrc   p15, #0, r0,      c0, c0, #4
+        uxtb  r0,  r0, ROR #8
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Returns the type of the implemented mpu regions
+; SourceId : MPU_SourceId_007
+; DesignId : MPU_DesignId_007
+; Requirements : HL_SR490
+
+    .def     _mpuAreRegionsSeparate_
+    .asmfunc
+
+_mpuAreRegionsSeparate_
+
+        mrc   p15, #0, r0,      c0, c0, #4
+        uxtb  r0,  r0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Set mpu region number
+; SourceId : MPU_SourceId_008
+; DesignId : MPU_DesignId_008
+; Requirements : HL_SR489
+
+    .def     _mpuSetRegion_
+    .asmfunc
+
+_mpuSetRegion_
+
+        mcr   p15, #0, r0, c6, c2, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get mpu region number
+; SourceId : MPU_SourceId_009
+; DesignId : MPU_DesignId_009
+; Requirements : HL_SR490
+
+    .def     _mpuGetRegion_
+    .asmfunc
+
+_mpuGetRegion_
+
+        mrc   p15, #0, r0, c6, c2, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Set base address
+; SourceId : MPU_SourceId_010
+; DesignId : MPU_DesignId_010
+; Requirements : HL_SR489
+
+    .def     _mpuSetRegionBaseAddress_
+    .asmfunc
+
+_mpuSetRegionBaseAddress_
+
+        mcr   p15, #0, r0, c6, c1, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get base address
+; SourceId : MPU_SourceId_011
+; DesignId : MPU_DesignId_011
+; Requirements : HL_SR490
+
+    .def     _mpuGetRegionBaseAddress_
+    .asmfunc
+
+_mpuGetRegionBaseAddress_
+
+        mrc   p15, #0, r0, c6, c1, #0
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Set type and permission
+; SourceId : MPU_SourceId_012
+; DesignId : MPU_DesignId_012
+; Requirements : HL_SR489
+
+    .def     _mpuSetRegionTypeAndPermission_
+    .asmfunc
+
+_mpuSetRegionTypeAndPermission_
+
+        orr   r0,  r0, r1
+        mcr   p15, #0, r0, c6, c1, #4
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get type
+; SourceId : MPU_SourceId_013
+; DesignId : MPU_DesignId_013
+; Requirements : HL_SR490
+
+    .def     _mpuGetRegionType_
+    .asmfunc
+
+_mpuGetRegionType_
+
+        mrc   p15, #0, r0,     c6, c1, #4
+        bic   r0,  r0, #0xFF00
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Get permission
+; SourceId : MPU_SourceId_014
+; DesignId : MPU_DesignId_014
+; Requirements : HL_SR490
+
+    .def     _mpuGetRegionPermission_
+    .asmfunc
+
+_mpuGetRegionPermission_
+
+        mrc   p15, #0, r0,   c6, c1, #4
+        bic   r0,  r0, #0xFF
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Set region size register value
+; SourceId : MPU_SourceId_015
+; DesignId : MPU_DesignId_015
+; Requirements : HL_SR489
+
+    .def     _mpuSetRegionSizeRegister_
+    .asmfunc
+
+_mpuSetRegionSizeRegister_
+
+
+        mcr   p15, #0, r0, c6, c1, #2
+        bx    lr
+
+    .endasmfunc
+
+    
+
+;-------------------------------------------------------------------------------
+
diff --git a/src/arch/rm46l8lp/halcogen/sys_pcr.c b/src/arch/rm46l8lp/halcogen/sys_pcr.c
new file mode 100644
index 0000000..4da7d62
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_pcr.c
@@ -0,0 +1,725 @@
+/** @file sys_pcr.c
+*   @brief PCR Driver Implementation File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#include "sys_pcr.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame)
+*   @brief Set the peripheral protection of the selected frame 
+*   @param[in] peripheral_Frame - Peripheral frame to be protected
+*
+*   This function sets the protection for the selected frame.
+*/
+/* SourceId : PCR_SourceId_001 */
+/* DesignId : PCR_DesignId_001 */
+/* Requirements : HL_SR41 */
+void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame)
+{
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+	uint32 Quarant_selct;
+
+	chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
+	Quarant_selct  = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
+
+    if (chip_select_grp >= 3U)
+    {
+        pcrREG->PPROTSET3 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 2U)
+    {
+        pcrREG->PPROTSET2 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 1U)
+    {
+        pcrREG->PPROTSET1 = Quarant_selct;
+    }
+	else
+    {
+        pcrREG->PPROTSET0 = Quarant_selct;
+    }
+	
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+/** @fn void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame)
+*   @brief Clear the peripheral protection of the selected frame 
+*   @param[in] peripheral_Frame - Peripheral frame to be out of protection
+*
+*   This function clears the protection set for the selected frame.
+*/
+/* SourceId : PCR_SourceId_002 */
+/* DesignId : PCR_DesignId_002 */
+/* Requirements : HL_SR42 */
+void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame)
+{
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+	uint32 Quarant_selct;
+
+	chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
+	Quarant_selct  = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
+
+    if (chip_select_grp >= 3U)
+    {
+        pcrREG->PPROTCLR3 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 2U)
+    {
+        pcrREG->PPROTCLR2 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 1U)
+    {
+        pcrREG->PPROTCLR1 = Quarant_selct;
+    }
+	else
+    {
+        pcrREG->PPROTCLR0 = Quarant_selct;
+    }
+	
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+/** @fn void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame)
+*   @brief Take the selected peripheral to powerdown
+*   @param[in] peripheral_Frame - Peripheral frame to be taken to powerdown
+*
+*   This function will set the selected peripheral frame to powerdown.
+*/
+/* SourceId : PCR_SourceId_003 */
+/* DesignId : PCR_DesignId_003 */
+/* Requirements : HL_SR43 */
+void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame)
+{
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+	uint32 Quarant_selct;
+
+	chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
+	Quarant_selct  = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
+	
+    if (chip_select_grp >= 3U)
+    {
+        pcrREG->PSPWRDWNSET3 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 2U)
+    {
+        pcrREG->PSPWRDWNSET2 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 1U)
+    {
+        pcrREG->PSPWRDWNSET1 = Quarant_selct;
+    }
+	else
+    {
+        pcrREG->PSPWRDWNSET0 = Quarant_selct;
+    }
+	
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+/** @fn void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame)
+*   @brief Bring the selected peripheral frame out of powerdown
+*   @param[in] peripheral_Frame - Peripheral frame to be taken out of powerdown
+*
+*   This function will bring the selected peripheral frame out of powerdown.
+*/
+/* SourceId : PCR_SourceId_004 */
+/* DesignId : PCR_DesignId_004 */
+/* Requirements : HL_SR44 */
+void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame)
+{
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+	uint32 Quarant_selct;
+
+	chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
+	Quarant_selct  = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
+	
+    if (chip_select_grp >= 3U)
+    {
+        pcrREG->PSPWRDWNCLR3 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 2U)
+    {
+        pcrREG->PSPWRDWNCLR2 = Quarant_selct;
+    }
+    else if (chip_select_grp >= 1U)
+    {
+        pcrREG->PSPWRDWNCLR1 = Quarant_selct;
+    }
+	else
+    {
+        pcrREG->PSPWRDWNCLR0 = Quarant_selct;
+    }
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+/** @fn void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+*   @brief Set the peripheral memory protection of the selected frame 
+*   @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be protected
+*
+*   This function sets the protection for the selected peripheral memory frame.
+*/
+/* SourceId : PCR_SourceId_005 */
+/* DesignId : PCR_DesignId_017 */
+/* Requirements : HL_SR57 */
+void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+{
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+
+	chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
+
+	if (chip_select_grp >= 1U)
+    {
+        pcrREG->PMPROTSET1 = (uint32)1U << (peripheral_Memory_Frame_CS & 0xFU);
+    }
+	else
+    {
+        pcrREG->PMPROTSET0 = (uint32)1U << peripheral_Memory_Frame_CS;
+    }
+	
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+/** @fn void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+*   @brief Clear the peripheral memory protection of the selected frame 
+*   @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be cleared from protection
+*
+*   This function clears the protection set for the selected peripheral memory frame.
+*/
+/* SourceId : PCR_SourceId_006 */
+/* DesignId : PCR_DesignId_018 */
+/* Requirements : HL_SR58 */
+void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+{
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+
+	chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
+
+	if (chip_select_grp >= 1U)
+    {
+        pcrREG->PMPROTCLR1 = (uint32)1U << (peripheral_Memory_Frame_CS & 0xFU);
+    }
+	else
+    {
+        pcrREG->PMPROTCLR0 = (uint32)1U << peripheral_Memory_Frame_CS;
+    }
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+/** @fn void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+*   @brief Take the selected peripheral memory frame to powerdown
+*   @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken to powerdown
+*
+*   This function will set the selected peripheral memory frame to powerdown.
+*/
+/* SourceId : PCR_SourceId_007 */
+/* DesignId : PCR_DesignId_019 */
+/* Requirements : HL_SR59 */
+void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+{
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+
+	chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
+
+	if (chip_select_grp >= 1U)
+    {
+        pcrREG->PCSPWRDWNSET0 = (uint32)1U << (peripheral_Memory_Frame_CS & 0xFU);
+    }
+	else
+    {
+        pcrREG->PCSPWRDWNSET1 = (uint32)1U << peripheral_Memory_Frame_CS;
+    }
+	
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+/** @fn void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+*   @brief Bring the selected peripheral Memory frame out of powerdown
+*   @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken out of powerdown
+*
+*   This function will bring the selected peripheral memory frame out of powerdown.
+*/
+/* SourceId : PCR_SourceId_008 */
+/* DesignId : PCR_DesignId_020 */
+/* Requirements : HL_SR60 */
+void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
+{
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+	uint32 chip_select_grp;
+
+	chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
+
+	if (chip_select_grp >= 1U)
+    {
+        pcrREG->PCSPWRDWNCLR0 = (uint32)1U << (peripheral_Memory_Frame_CS & 0xFU);
+    }
+	else
+    {
+        pcrREG->PCSPWRDWNCLR1 = (uint32)1U << peripheral_Memory_Frame_CS;
+    }
+	
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+/** @fn void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+*   @brief Set the peripheral protection of all the selected frames 
+*   @param[in] peripheral_Quad_CS - All Peripheral frames to be protected
+*
+*   This function sets the protection for all the selected frames.
+*/
+/* SourceId : PCR_SourceId_009 */
+/* DesignId : PCR_DesignId_005 */
+/* Requirements : HL_SR45 */
+void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+{
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+    pcrREG->PPROTSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
+    pcrREG->PPROTSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
+    pcrREG->PPROTSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
+    pcrREG->PPROTSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
+	
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+/** @fn void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+*   @brief Clear the peripheral protection of all the selected frames 
+*   @param[in] peripheral_Quad_CS - All Peripheral frames to be out of protection.
+*
+*   This function clears the protection set for all the selected frame.
+*/
+/* SourceId : PCR_SourceId_010 */
+/* DesignId : PCR_DesignId_006 */
+/* Requirements : HL_SR46 */
+void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+{
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+    pcrREG->PPROTCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
+    pcrREG->PPROTCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
+    pcrREG->PPROTCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
+    pcrREG->PPROTCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+/** @fn void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+*   @brief Take all the selected peripheral frame to powerdown
+*   @param[in] peripheral_Quad_CS - Peripheral frames to be taken to powerdown
+*
+*   This function will set all the selected peripheral frame to powerdown.
+*/
+/* SourceId : PCR_SourceId_011 */
+/* DesignId : PCR_DesignId_008 */
+/* Requirements : HL_SR48 */
+void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+{
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+    pcrREG->PSPWRDWNSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
+    pcrREG->PSPWRDWNSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
+    pcrREG->PSPWRDWNSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
+    pcrREG->PSPWRDWNSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+
+/** @fn void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+*   @brief Bring all the selected peripheral frame out of powerdown
+*   @param[in] peripheral_Quad_CS - Peripheral frames to be taken out of powerdown
+*
+*   This function will bring all the selected peripheral frame out of powerdown.
+*/
+/* SourceId : PCR_SourceId_012 */
+/* DesignId : PCR_DesignId_009 */
+/* Requirements : HL_SR49 */
+void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
+{
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+    pcrREG->PSPWRDWNCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
+    pcrREG->PSPWRDWNCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
+    pcrREG->PSPWRDWNCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
+    pcrREG->PSPWRDWNCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
+
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+
+/** @fn void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+*   @brief Set the peripheral memory protection of all the selected frame 
+*   @param[in] peripheral_Memory_CS - Peripheral memory frames to be protected
+*
+*   This function sets the protection for all the selected peripheral memory frame.
+*/
+/* SourceId : PCR_SourceId_013 */
+/* DesignId : PCR_DesignId_011 */
+/* Requirements : HL_SR51 */
+void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+{
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+
+    pcrREG->PMPROTSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
+    pcrREG->PMPROTSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
+
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+
+/** @fn void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+*   @brief Clear the peripheral memory protection of all the selected frame 
+*   @param[in] peripheral_Memory_CS - Peripheral memory frames to be cleared from protection
+*
+*   This function clears the protection set for all the selected peripheral memory frame.
+*/
+/* SourceId : PCR_SourceId_014 */
+/* DesignId : PCR_DesignId_012 */
+/* Requirements : HL_SR52 */
+void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+{
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+
+    pcrREG->PMPROTCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
+    pcrREG->PMPROTCLR1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
+
+/* USER CODE BEGIN (42) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+
+/** @fn void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+*   @brief Take all the selected peripheral memory frame to powerdown
+*   @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken to powerdown
+*
+*   This function will set all the selected peripheral memory frame to powerdown.
+*/
+/* SourceId : PCR_SourceId_015 */
+/* DesignId : PCR_DesignId_014 */
+/* Requirements : HL_SR54 */
+void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+{
+
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+
+    pcrREG->PCSPWRDWNSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
+    pcrREG->PCSPWRDWNSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
+	
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+
+/** @fn void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+*   @brief Bring all the selected peripheral Memory frame out of powerdown
+*   @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken out of powerdown
+*
+*   This function will bring all the selected peripheral memory frame out of powerdown.
+*/
+/* SourceId : PCR_SourceId_016 */
+/* DesignId : PCR_DesignId_015 */
+/* Requirements : HL_SR55 */
+void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
+{
+
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+
+    pcrREG->PCSPWRDWNSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
+    pcrREG->PCSPWRDWNCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
+
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (49) */
+/* USER CODE END */
+
+/** @fn void peripheral_Powerdown_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS)
+*   @brief Get the powerdown status of the peripheral frames.
+*   @param[out] peripheral_Quad_CS Peripheral frames power down status
+*
+*   This function gets the powerdown status of the peripheral frames.
+*/
+/* SourceId : PCR_SourceId_017 */
+/* DesignId : PCR_DesignId_010 */
+/* Requirements : HL_SR50 */
+void peripheral_Powerdown_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS)
+{
+
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+
+    peripheral_Quad_CS->Peripheral_Quad0_3_CS0_7      = pcrREG->PSPWRDWNSET0;
+    peripheral_Quad_CS->Peripheral_Quad4_7_CS8_15     = pcrREG->PSPWRDWNSET1; 
+    peripheral_Quad_CS->Peripheral_Quad8_11_CS16_23   = pcrREG->PSPWRDWNSET2; 
+    peripheral_Quad_CS->Peripheral_Quad12_15_CS24_31  = pcrREG->PSPWRDWNSET3; 
+
+/* USER CODE BEGIN (51) */
+/* USER CODE END */
+
+}
+
+/* USER CODE BEGIN (52) */
+/* USER CODE END */
+
+/** @fn void peripheral_Protection_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS )
+*   @brief Get the protection status of the peripheral frames
+*   @param[out] peripheral_Quad_CS Peripheral frames protection status
+*
+*   This function gets the protection status of the peripheral frames.
+*/
+/* SourceId : PCR_SourceId_018 */
+/* DesignId : PCR_DesignId_007 */
+/* Requirements : HL_SR47 */
+void peripheral_Protection_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS)
+{
+
+/* USER CODE BEGIN (53) */
+/* USER CODE END */
+
+    peripheral_Quad_CS->Peripheral_Quad0_3_CS0_7     = pcrREG->PPROTSET0; 
+    peripheral_Quad_CS->Peripheral_Quad4_7_CS8_15    = pcrREG->PPROTSET1; 
+    peripheral_Quad_CS->Peripheral_Quad8_11_CS16_23  = pcrREG->PPROTSET2; 
+    peripheral_Quad_CS->Peripheral_Quad12_15_CS24_31 = pcrREG->PPROTSET3;
+
+/* USER CODE BEGIN (54) */
+/* USER CODE END */
+
+}
+
+/* USER CODE BEGIN (55) */
+/* USER CODE END */
+
+/** @fn void peripheral_Memory_Protection_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS)
+*   @brief Get the protection set of all the peripheral Memory frame
+*   @param[out] peripheral_Memory_CS Peripheral memory frames protection status
+*   
+*   This function gets the protection status of all the peripheral Memory frame.
+*/
+/* SourceId : PCR_SourceId_019 */
+/* DesignId : PCR_DesignId_013 */
+/* Requirements : HL_SR53 */
+void peripheral_Memory_Protection_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS)
+{
+
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
+
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Hardware status bit read" */
+    peripheral_Memory_CS->Peripheral_Mem_CS0_31 = pcrREG->PMPROTSET0;
+    peripheral_Memory_CS->Peripheral_Mem_CS32_63 = pcrREG->PMPROTSET1;
+
+/* USER CODE BEGIN (57) */
+/* USER CODE END */
+
+}
+
+/* USER CODE BEGIN (58) */
+/* USER CODE END */
+
+/** @fn void peripheral_Memory_Powerdown_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS)
+*   @brief Get the powerdown status of all the peripheral Memory frame
+*   @param[out] peripheral_Memory_CS Peripheral memory frames powerdown status
+*
+*   This function gets the powerdown status of all the peripheral Memory frame.
+*/
+/* SourceId : PCR_SourceId_020 */
+/* DesignId : PCR_DesignId_016 */
+/* Requirements : HL_SR56 */
+void peripheral_Memory_Powerdown_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS)
+{
+
+/* USER CODE BEGIN (59) */
+/* USER CODE END */
+
+    peripheral_Memory_CS->Peripheral_Mem_CS0_31 = pcrREG->PCSPWRDWNSET0;
+    peripheral_Memory_CS->Peripheral_Mem_CS32_63 = pcrREG->PCSPWRDWNSET1;
+
+/* USER CODE BEGIN (60) */
+/* USER CODE END */
+
+}
+
+/* USER CODE BEGIN (61) */
+/* USER CODE END */
+
+/** @fn void pcrGetConfigValue(pcr_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current 
+*                           value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') 
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : PCR_SourceId_021 */
+/* DesignId : PCR_DesignId_021 */
+/* Requirements : HL_SR61 */
+void pcrGetConfigValue(pcr_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{/* Do not pass Initial value as parameter as there is no PCR initialization API */
+	}
+	else
+	{
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_PMPROTSET0    = pcrREG->PMPROTSET0;
+        config_reg->CONFIG_PMPROTSET1    = pcrREG->PMPROTSET1;
+        config_reg->CONFIG_PPROTSET0     = pcrREG->PPROTSET0;
+        config_reg->CONFIG_PPROTSET1     = pcrREG->PPROTSET1;
+        config_reg->CONFIG_PPROTSET2     = pcrREG->PPROTSET2;
+        config_reg->CONFIG_PPROTSET3     = pcrREG->PPROTSET3;
+        config_reg->CONFIG_PCSPWRDWNSET0 = pcrREG->PCSPWRDWNSET0;
+        config_reg->CONFIG_PCSPWRDWNSET1 = pcrREG->PCSPWRDWNSET1;
+        config_reg->CONFIG_PSPWRDWNSET0  = pcrREG->PSPWRDWNSET0;
+        config_reg->CONFIG_PSPWRDWNSET1  = pcrREG->PSPWRDWNSET1;
+        config_reg->CONFIG_PSPWRDWNSET2  = pcrREG->PSPWRDWNSET2;
+        config_reg->CONFIG_PSPWRDWNSET3  = pcrREG->PSPWRDWNSET3;
+	}
+}
diff --git a/src/arch/rm46l8lp/halcogen/sys_phantom.c b/src/arch/rm46l8lp/halcogen/sys_phantom.c
new file mode 100644
index 0000000..346ff30
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_phantom.c
@@ -0,0 +1,67 @@
+/** @file sys_phantom.c 
+*   @brief Phantom Interrupt Source File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file contains:
+*   - Phantom Interrupt Handler
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#include "sys_common.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Phantom Interrupt Handler */
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#pragma CODE_STATE(phantomInterrupt, 32)
+#pragma INTERRUPT(phantomInterrupt, IRQ)
+#pragma WEAK(phantomInterrupt)
+
+void phantomInterrupt(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
diff --git a/src/arch/rm46l8lp/halcogen/sys_pmm.c b/src/arch/rm46l8lp/halcogen/sys_pmm.c
new file mode 100644
index 0000000..35db7f4
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_pmm.c
@@ -0,0 +1,434 @@
+/** @file sys_pmm.c
+*   @brief PCR Driver Implementation File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#include "sys_pmm.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @fn void pmmInit(void)
+*   @brief Initializes the PMM Driver
+*
+*   This function initializes the PMM module.
+*/
+/* SourceId : PMM_SourceId_001 */
+/* DesignId : PMM_DesignId_001 */
+/* Requirements : HL_SR63 */
+void pmmInit(void)
+{
+    /*Disable clocks to all logic domains*/
+    pmmREG->PDCLKDISREG = 0xFU;
+    /*Enable or disable clock to pmctrl_wakeup block and automatic clock wake up*/
+    pmmREG->GLOBALCTRL1 = (uint32)((uint32)0U << 8U) | (uint32)0U; /*from GUI*/
+    /*Power on the logic power domains*/
+    pmmREG->LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE;
+    /*Power on the memory-only power domains*/
+    pmmREG->MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE;
+
+    /*wait till Logic Power Domain PD2 turns ON*/
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */
+	while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD2] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
+    { 
+    }/* Wait */  
+    /*wait till Logic Power Domain PD3 turns ON*/
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */
+	while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD3] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
+    { 
+    }/* Wait */  
+    /*wait till Logic Power Domain PD3 turns ON*/
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */
+	while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD4] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
+    { 
+    }/* Wait */  
+    /*wait till Logic Power Domain PD5 turns ON*/
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */
+	while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD5] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
+    { 
+    }/* Wait */  
+
+    /*wait till Memory Only Power Domain RAM_PD1 turns ON*/
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */
+	while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD1] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
+    { 
+    }/* Wait */  
+    /*wait till Memory Only Power Domain RAM_PD2 turns ON*/
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */
+	while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD2] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
+    { 
+    }/* Wait */  
+    if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U)
+    {
+        /* Enable clocks for the selected logic domain */
+        pmmREG->PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE;
+    }
+
+}
+
+
+/** @fn void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD)
+*   @brief Turns on Logic Power Domain
+*   @param[in] logicPD - Power Domain to be turned on
+*              - PMM_LOGICPD2: Power domain PD2 will be turned on
+*              - PMM_LOGICPD3: Power domain PD3 will be turned on
+*              - PMM_LOGICPD4: Power domain PD4 will be turned on
+*              - PMM_LOGICPD5: Power domain PD5 will be turned on
+*
+*   This function turns on the selected Logic Power Domain
+*
+*/
+/* SourceId : PMM_SourceId_002 */
+/* DesignId : PMM_DesignId_002 */
+/* Requirements : HL_SR67 */
+void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD)
+{
+    if (logicPD != PMM_LOGICPD1)
+    {
+        /* Power on the domain */
+        if (logicPD == PMM_LOGICPD2)
+        {
+		    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+            pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | 0x05000000U;
+        }
+        else if (logicPD == PMM_LOGICPD3)
+        {
+		   /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+            pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | 0x00050000U;
+        }
+        else if (logicPD == PMM_LOGICPD4)
+        {
+		   /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+            pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | 0x00000500U;
+        }
+        else
+        {
+		   /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+            pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | 0x00000005U;
+        }
+        /* Wait until the power domain turns on */
+        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */
+		while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
+        { 
+        }/* Wait */  
+        if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U)
+        {
+            /* Enable clocks to the power domain */
+            pmmREG->PDCLKDISCLRREG = (uint32)1U << (uint32)logicPD;
+        }
+    }
+}
+
+/** @fn void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD)
+*   @brief Turns on Memory Power Domain
+*   @param[in] memPD - Power Domain to be tured on
+*              - PMM_MEMPD1: Power domain RAM_PD1 will be turned on
+*              - PMM_MEMPD2: Power domain RAM_PD2 will be turned on
+*              - PMM_MEMPD3: Power domain RAM_PD3 will be turned on
+*
+*   This function turns on the selected Memory Power Domain
+*
+*/
+/* SourceId : PMM_SourceId_003 */
+/* DesignId : PMM_DesignId_003 */
+/* Requirements : HL_SR66 */
+void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD)
+{
+    /* Power on the domain */
+    if (memPD == PMM_MEMPD1)
+    {
+        pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | 0x05000000U;
+    }
+    else if (memPD == PMM_MEMPD2)
+    {
+        pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | 0x00050000U;
+    }
+    else
+    {
+        pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | 0x00000500U;
+    }
+    /*Wait until the power domain turns on*/
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */
+	while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
+    { 
+    }/* Wait */  
+}
+
+/** @fn void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD)
+*   @brief Turns off Logic Power Domain
+*    @param[in] logicPD - Power Domain to be tured off
+*              - PMM_LOGICPD2: Power domain PD2 will be turned off
+*              - PMM_LOGICPD3: Power domain PD3 will be turned off
+*              - PMM_LOGICPD4: Power domain PD4 will be turned off
+*              - PMM_LOGICPD5: Power doamin PD5 will be turned off
+*
+*   This function turns off the selected Logic Power Domain
+*
+*/
+/* SourceId : PMM_SourceId_004 */
+/* DesignId : PMM_DesignId_004 */
+/* Requirements : HL_SR67 */
+void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD)
+{
+    if (logicPD != PMM_LOGICPD1)
+    {
+        /* Disable all clocks to the power domain */
+        pmmREG->PDCLKDISSETREG = (uint32)1U << (uint32)logicPD;
+        
+        /* Power down the domain */
+        if (logicPD == PMM_LOGICPD2)
+        {
+		    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue*/
+            pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | 0x0A000000U;
+        }
+        else if (logicPD == PMM_LOGICPD3)
+        {
+		    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+            pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | 0x000A0000U;
+        }
+        else if (logicPD == PMM_LOGICPD4)
+        {
+		    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+            pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | 0x00000A00U;
+        }
+        else
+        {
+		    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+            pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | 0x0000000AU;
+        }
+        /* Wait until the power domain turns off */
+        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */
+		while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U)
+        { 
+        }/* Wait */  
+    }
+}
+
+/** @fn void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD)
+*   @brief Turns off Memory Power Domain
+*   @param[in] memPD - Power Domain to be tured off
+*              - PMM_MEMPD1: Power domain RAM_PD1 will be turned off
+*              - PMM_MEMPD2: Power domain RAM_PD2 will be turned off
+*              - PMM_MEMPD3: Power domain RAM_PD3 will be turned off
+*
+*   This function turns off the selected Memory Power Domain
+*
+*/
+/* SourceId : PMM_SourceId_005 */
+/* DesignId : PMM_DesignId_005 */
+/* Requirements : HL_SR66 */
+void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD)
+{
+    /* Power down the domain */
+    if (memPD == PMM_MEMPD1)
+    {
+        pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | 0x0A000000U;
+    }
+    else if (memPD == PMM_MEMPD2)
+    {
+        pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | 0x000A0000U;
+    }
+    else
+    {
+        pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | 0x00000A00U;
+    }
+    /*Wait until the power domain turns off*/
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */
+	while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_MEMPDPWRSTAT) != 0U)
+    { 
+    }/* Wait */  
+}
+
+/** @fn boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD)
+*   @brief Check if the power domain is active or not
+*    @param[in] logicPD - Power Domain to be be checked
+*              - PMM_LOGICPD2: Checks whether Power domain PD2 is active or not
+*              - PMM_LOGICPD3: Checks whether Power domain PD3 is active or not
+*              - PMM_LOGICPD4: Checks whether Power domain PD4 is active or not
+*              - PMM_LOGICPD5: Checks whether Power domain PD5 is active or not
+*    @return The function will return:
+*              - TRUE : When the selected power domain is in Active state.
+*              - FALSE: When the selected power domain is in OFF state.
+*
+*   This function checks whether the selected power domain is active or not.
+*
+*/
+/* SourceId : PMM_SourceId_006 */
+/* DesignId : PMM_DesignId_006 */
+/* Requirements : HL_SR62 */
+boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD)
+{
+    boolean status;
+    if ((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
+    {
+        status = FALSE;
+    }
+    else
+    {
+        status = TRUE;
+    }
+    return status;
+}
+
+/** @fn boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD)
+*   @brief Check if the power domain is active or not
+*    @param[in] memPD - Power Domain to be tured off
+*              - PMM_MEMPD1: Checks whether Power domain RAM_PD1 is active or not
+*              - PMM_MEMPD2: Checks whether Power domain RAM_PD2 is active or not
+*              - PMM_MEMPD3: Checks whether Power domain RAM_PD3 is active or not
+*    @return The function will return:
+*              - TRUE : When the selected power domain is in Active state.
+*              - FALSE: When the selected power domain is in OFF state.
+*
+*   This function checks whether the selected power domain is active or not.
+*
+*/
+/* SourceId : PMM_SourceId_007 */
+/* DesignId : PMM_DesignId_007 */
+/* Requirements : HL_SR65 */
+boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD)
+{
+    boolean status;
+    if ((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
+    {
+        status = FALSE;
+    }
+    else
+    {
+        status = TRUE;
+    }
+    return status;
+}
+
+/** @fn void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration register
+*    @param[in] *config_reg - pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*    @param[in] type  -     whether initial or current value of the configuration registers need to be stored
+*                        - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*                        - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*/
+/* SourceId : PMM_SourceId_008 */
+/* DesignId : PMM_DesignId_008 */
+/* Requirements : HL_SR64 */
+void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE;
+        config_reg->CONFIG_MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE;
+        config_reg->CONFIG_PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE;
+        config_reg->CONFIG_GLOBALCTRL1 = PMM_GLOBALCTRL1_CONFIGVALUE;
+    }
+    else
+    {
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_LOGICPDPWRCTRL0 = pmmREG->LOGICPDPWRCTRL0;
+        config_reg->CONFIG_MEMPDPWRCTRL0 = pmmREG->MEMPDPWRCTRL0;
+        config_reg->CONFIG_PDCLKDISREG = pmmREG->PDCLKDISREG;
+        config_reg->CONFIG_GLOBALCTRL1 = pmmREG->GLOBALCTRL1;
+    }
+}
+
+/** @fn void pmmSetMode(pmm_Mode_t mode)
+*   @brief Set PSCON Compare Block Mode
+*    @param[in] mode - PSCON Compare Block mode
+*                - LockStep                : PSCON compare block is set to Lock-Step mode
+*                - SelfTest                : PSCON compare block is set to Self-Test mode
+*                - ErrorForcing            : PSCON compare block is set to Error-Forcing mode
+*                - SelfTestErrorForcing    : PSCON compare block is set to Self-Test-Error-Forcing mode
+*
+*   This function sets the PSCON Compare block to the selected mode
+*
+*/
+/* SourceId : PMM_SourceId_009 */
+/* DesignId : PMM_DesignId_009 */
+/* Requirements : HL_SR68 */
+void pmmSetMode(pmm_Mode_t mode)
+{
+    /* Set PSCON Compare Block Mode */
+    pmmREG->PRCKEYREG = mode;
+}
+
+/** @fn boolean pmmPerformSelfTest(void)
+*   @brief Perform self test and return the result
+*
+*    @return The function will return
+*            - TRUE if PSCON compare block passed self-test
+*            - FALSE if PSCON compare block failed in self-test
+*
+*   This function checks whether PSCON compare block passed the self-test or not.
+*
+*/
+/* SourceId : PMM_SourceId_010 */
+/* DesignId : PMM_DesignId_010 */
+/* Requirements : HL_SR72 */
+boolean pmmPerformSelfTest(void)
+{
+    boolean status = TRUE;
+    /*Enter self-test mode*/
+    pmmREG->PRCKEYREG = (uint32)SelfTest;
+    /*Wait till self test is completed*/
+	/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ((pmmREG->LPDDCSTAT1 & 0xFU) != 0xFU)
+    { 
+    }/* Wait */                 
+    
+	/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ((pmmREG->MPDDCSTAT1 & 0x3U) != 0x3U)
+    { 
+    }/* Wait */   
+
+    /*Check whether self-test passed or not*/
+    if ((pmmREG->LPDDCSTAT2 & 0xFU) != 0U)
+    {
+        status = FALSE;
+    }
+    if ((pmmREG->MPDDCSTAT2 & 0x7U) != 0U)
+    {
+        status = FALSE;
+    }
+    /*Enter lock-step mode*/
+    pmmREG->PRCKEYREG = (uint32)LockStep;
+
+    return status;
+}
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
diff --git a/src/arch/rm46l8lp/halcogen/sys_pmu.asm b/src/arch/rm46l8lp/halcogen/sys_pmu.asm
new file mode 100644
index 0000000..0f48047
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_pmu.asm
@@ -0,0 +1,277 @@
+;-------------------------------------------------------------------------------
+; sys_pmu.asm
+;
+; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+;
+;
+;  Redistribution and use in source and binary forms, with or without
+;  modification, are permitted provided that the following conditions
+;  are met:
+;
+;    Redistributions of source code must retain the above copyright
+;    notice, this list of conditions and the following disclaimer.
+;
+;    Redistributions in binary form must reproduce the above copyright
+;    notice, this list of conditions and the following disclaimer in the
+;    documentation and/or other materials provided with the
+;    distribution.
+;
+;    Neither the name of Texas Instruments Incorporated nor the names of
+;    its contributors may be used to endorse or promote products derived
+;    from this software without specific prior written permission.
+;
+;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;
+;
+
+    .text
+    .arm
+
+
+;-------------------------------------------------------------------------------
+; Initialize Pmu
+; Note: It will reset all counters
+; SourceId : PMU_SourceId_001
+; DesignId : PMU_DesignId_001
+; Requirements : HL_SR484
+
+    .def     _pmuInit_
+    .asmfunc
+
+_pmuInit_
+
+        ; set control register
+        mrc   p15, #0, r0, c9, c12, #0
+        orr   r0,  r0, #(1 << 4) + 6 + 1
+        mcr   p15, #0, r0, c9, c12, #0
+        ; clear flags
+        mov   r0,  #0
+        sub   r0,  r0,  #1
+        mcr   p15, #0, r0, c9, c12, #3
+        ; select counter 0 event
+        mov   r0,  #0
+        mcr   p15, #0, r0, c9, c12, #5 ; select counter
+        mov   r0,  #0x11
+        mcr   p15, #0, r0, c9, c13, #1 ; select event
+        ; select counter 1 event
+        mov   r0,  #1
+        mcr   p15, #0, r0, c9, c12, #5 ; select counter
+        mov   r0,  #0x11
+        mcr   p15, #0, r0, c9, c13, #1 ; select event
+        ; select counter 2 event
+        mov   r0,  #2
+        mcr   p15, #0, r0, c9, c12, #5 ; select counter
+        mov   r0,  #0x11
+        mcr   p15, #0, r0, c9, c13, #1 ; select event
+        bx    lr
+
+    .endasmfunc
+
+
+;-------------------------------------------------------------------------------
+; Enable Counters Global [Cycle, Event [0..2]]
+; Note: It will reset all counters
+; SourceId : PMU_SourceId_002
+; DesignId : PMU_DesignId_002
+; Requirements : HL_SR485
+
+    .def     _pmuEnableCountersGlobal_
+    .asmfunc
+
+_pmuEnableCountersGlobal_
+
+        mrc   p15, #0, r0, c9, c12, #0
+        orr   r0,  r0, #7
+        mcr   p15, #0, r0, c9, c12, #0
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Disable Counters Global [Cycle, Event [0..2]]
+; SourceId : PMU_SourceId_003
+; DesignId : PMU_DesignId_003
+; Requirements : HL_SR485
+
+    .def     _pmuDisableCountersGlobal_
+    .asmfunc
+
+_pmuDisableCountersGlobal_
+
+        mrc   p15, #0, r0, c9, c12, #0
+        bic   r0,  r0, #1
+        mcr   p15, #0, r0, c9, c12, #0
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Reset Cycle Counter
+; SourceId : PMU_SourceId_004
+; DesignId : PMU_DesignId_004
+; Requirements : HL_SR485
+
+    .def     _pmuResetCycleCounter_
+    .asmfunc
+
+_pmuResetCycleCounter_
+
+        mrc   p15, #0, r0, c9, c12, #0
+        orr   r0,  r0, #4
+        mcr   p15, #0, r0, c9, c12, #0
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Reset Event Counters [0..2]
+; SourceId : PMU_SourceId_005
+; DesignId : PMU_DesignId_005
+; Requirements : HL_SR485
+
+    .def     _pmuResetEventCounters_
+    .asmfunc
+
+_pmuResetEventCounters_
+
+        mrc   p15, #0, r0, c9, c12, #0
+        orr   r0,  r0, #2
+        mcr   p15, #0, r0, c9, c12, #0
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Reset Cycle Counter abd Event Counters [0..2]
+; SourceId : PMU_SourceId_006
+; DesignId : PMU_DesignId_006
+; Requirements : HL_SR485
+
+    .def     _pmuResetCounters_
+    .asmfunc
+
+_pmuResetCounters_
+
+        mrc   p15, #0, r0, c9, c12, #0
+        orr   r0,  r0, #6
+        mcr   p15, #0, r0, c9, c12, #0
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Start Counters [Cycle, 0..2]
+; SourceId : PMU_SourceId_007
+; DesignId : PMU_DesignId_007
+; Requirements : HL_SR485
+
+    .def     _pmuStartCounters_
+    .asmfunc
+
+_pmuStartCounters_
+
+        mcr   p15, #0, r0, c9, c12, #1
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Stop Counters [Cycle, 0..2]
+; SourceId : PMU_SourceId_008
+; DesignId : PMU_DesignId_008
+; Requirements : HL_SR485
+
+    .def     _pmuStopCounters_
+    .asmfunc
+
+_pmuStopCounters_
+
+        mcr   p15, #0, r0, c9, c12, #2
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Set Count event
+; SourceId : PMU_SourceId_009
+; DesignId : PMU_DesignId_009
+; Requirements : HL_SR485
+
+    .def     _pmuSetCountEvent_
+    .asmfunc
+
+_pmuSetCountEvent_
+
+        mcr   p15, #0, r0, c9, c12, #5 ; select counter
+        mcr   p15, #0, r1, c9, c13, #1 ; select event
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Get Cycle Count
+; SourceId : PMU_SourceId_010
+; DesignId : PMU_DesignId_010
+; Requirements : HL_SR486
+
+    .def     _pmuGetCycleCount_
+    .asmfunc
+
+_pmuGetCycleCount_
+
+        mrc   p15, #0, r0, c9, c13, #0
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Get Event Counter Count Value
+; SourceId : PMU_SourceId_011
+; DesignId : PMU_DesignId_011
+; Requirements : HL_SR486
+
+    .def     _pmuGetEventCount_
+    .asmfunc
+
+_pmuGetEventCount_
+
+        mcr   p15, #0, r0, c9, c12, #5 ; select counter
+        mrc   p15, #0, r0, c9, c13, #2 ; read event counter
+        bx    lr
+
+    .endasmfunc
+
+;-------------------------------------------------------------------------------
+; Get Overflow Flags
+; SourceId : PMU_SourceId_012
+; DesignId : PMU_DesignId_012
+; Requirements : HL_SR486
+
+    .def     _pmuGetOverflow_
+    .asmfunc
+
+_pmuGetOverflow_
+
+        mrc   p15, #0, r0, c9, c12, #3 ; read overflow
+        mov   r1,  #0
+        sub   r1,  r1,  #1
+        mcr   p15, #0, r1, c9, c12, #3 ; clear flags
+        bx    lr
+
+    .endasmfunc
+
+    
+
+;-------------------------------------------------------------------------------
+
diff --git a/src/arch/rm46l8lp/halcogen/sys_selftest.c b/src/arch/rm46l8lp/halcogen/sys_selftest.c
new file mode 100644
index 0000000..d72273e
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_selftest.c
@@ -0,0 +1,2985 @@
+/** @file sys_selftest.c
+*   @brief Selftest Source File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file contains:
+*   - Selftest API's
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_selftest.h"
+#include "sys_core.h"
+#include "sys_pmu.h"
+
+/** @fn void selftestFailNotification(uint32 flag)
+*   @brief Self test fail service routine
+*
+*    This function is called if there is a self test fail with appropriate flag
+*/
+#pragma WEAK(selftestFailNotification)
+void selftestFailNotification(uint32 flag)
+{
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+}
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/** @fn void ccmSelfCheck(void)
+*   @brief CCM module self check Driver
+*
+*   This function self checks the CCM module.
+*/
+/* SourceId : SELFTEST_SourceId_001 */
+/* DesignId : SELFTEST_DesignId_001 */
+/* Requirements : HL_SR395 */
+void ccmSelfCheck(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+    /* Run a diagnostic check on the CCM-R4F module */
+    /* This step ensures that the CCM-R4F can actually indicate an error */
+
+    /* Configure CCM in self-test mode */
+    CCMKEYR = 0x6U;
+    /* Wait for CCM self-test to complete */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ((CCMSR & 0x100U) != 0x100U)
+    {
+    }/* Wait */
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+    /* Check if there was an error during the self-test */
+    if ((CCMSR & 0x1U) == 0x1U)
+    {
+        /* STE is set */
+        selftestFailNotification(CCMSELFCHECK_FAIL1);
+    }
+    else
+    {
+        /* Check CCM-R4 self-test error flag by itself (without compare error) */
+        if ((esmREG->SR1[0U] & 0x80000000U) == 0x80000000U)
+        {
+            /* ESM flag is not set */
+            selftestFailNotification(CCMSELFCHECK_FAIL2);
+        }
+        else
+        {
+            /* Configure CCM in error-forcing mode */
+            CCMKEYR = 0x9U;
+
+            /* Wait till error-forcing is completed. */
+            /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+            while (CCMKEYR != 0U)
+            {
+            }/* Wait */
+
+            /* check if compare error flag is set */
+            if ((esmREG->SR1[1U] & 0x4U) != 0x4U)
+            {
+                /* ESM flag is not set */
+                selftestFailNotification(CCMSELFCHECK_FAIL3);
+            }
+            else
+            {
+                /* Check FIQIVEC to ESM High Interrupt flag is set */
+                if((vimREG->FIQINDEX & 0x000000FFU) != 1U)
+                {
+                   /* ESM High Interrupt flag is not set in VIM*/
+                   selftestFailNotification(CCMSELFCHECK_FAIL4);
+                }
+
+                /* clear ESM group2 channel 2 flag */
+                esmREG->SR1[1U] = 0x4U;
+
+                /* clear ESM group2 shadow status flag */
+                esmREG->SSR2 = 0x4U;
+
+                /* ESM self-test error needs to also be cleared */
+                esmREG->SR1[0U] = 0x80000000U;
+
+                /* The nERROR pin will become inactive once the LTC counter expires */
+                esmREG->EKR = 0x5U;
+
+                /* Configure CCM in selftest error-forcing mode */
+                CCMKEYR = 0xFU;
+
+                /* Wait till selftest error-forcing is completed. */
+                /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+                while (CCMKEYR != 0U)
+                {
+                }/* Wait */
+
+                if((esmREG->SR1[0U] & 0x80000000U) != 0x80000000U)
+                {
+                    /* ESM flag not set */
+                    selftestFailNotification(CCMSELFCHECK_FAIL2);
+                }
+                else
+                {
+                    /* clear ESM flag */
+                    esmREG->SR1[0U] = 0x80000000U;
+                }
+            }
+        }
+    }
+}
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+
+/** @fn void memoryInit(uint32 ram)
+*   @brief Memory Initialization Driver
+*
+*   This function is called to perform Memory initialization of selected RAM's.
+*/
+/* SourceId : SELFTEST_SourceId_002 */
+/* DesignId : SELFTEST_DesignId_004 */
+/* Requirements : HL_SR396 */
+void memoryInit(uint32 ram)
+{
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+    /* Enable Memory Hardware Initialization */
+    systemREG1->MINITGCR = 0xAU;
+
+    /* Enable Memory Hardware Initialization for selected RAM's */
+    systemREG1->MSINENA  = ram;
+
+    /* Wait until Memory Hardware Initialization complete */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while((systemREG1->MSTCGSTAT & 0x00000100U) != 0x00000100U)
+    {
+    }/* Wait */
+
+    /* Disable Memory Hardware Initialization */
+    systemREG1->MINITGCR = 0x5U;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+}
+
+/** @fn void stcSelfCheck(void)
+*   @brief STC module self check Driver
+*
+*   This function is called to perform STC module self check.
+*/
+/* SourceId : SELFTEST_SourceId_003 */
+/* DesignId : SELFTEST_DesignId_002 */
+/* Requirements : HL_SR397 */
+void stcSelfCheck(void)
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+    volatile uint32 i = 0U;
+
+    /* Run a diagnostic check on the CPU self-test controller */
+    /* First set up the STC clock divider as STC is only supported up to 90MHz */
+
+    /* STC clock is now normal mode CPU clock frequency/2 = 180MHz/2 */
+    systemREG2->STCCLKDIV = 0x01000000U;
+
+    /* Select one test interval, restart self-test next time, 0x00010001 */
+    stcREG->STCGCR0 = 0x00010001U;
+
+    /* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */
+    stcREG->STCSCSCR = 0x1AU;
+
+    /* Maximum time-out period */
+    stcREG->STCTPR = 0xFFFFFFFFU;
+
+    /* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+    for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ }
+
+    /* Enable self-test */
+    stcREG->STCGCR1 = 0xAU;
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+    /* Idle the CPU so that the self-test can start */
+    _gotoCPUIdle_();
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+}
+
+/** @fn void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test)
+*   @brief CPU self test Driver
+*   @param[in] no_of_intervals - Number of Test Intervals to be
+*   @param[in] max_timeout     - Maximum Timeout to complete selected test Intervals
+*   @param[in] restart_test    - Restart the test from Interval 0 or Continue from where it stopped.
+*
+*   This function is called to perform CPU self test using STC module.
+*/
+/* SourceId : SELFTEST_SourceId_004 */
+/* DesignId : SELFTEST_DesignId_003 */
+/* Requirements : HL_SR398 */
+void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test)
+{
+    volatile uint32 i = 0U;
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+    /* Run specified no of test intervals starting from interval 0 */
+    /* Start test from interval 0 or continue the test. */
+    stcREG->STCGCR0 = no_of_intervals << 16U;
+	if(restart_test)
+	{
+	    stcREG->STCGCR0 |= 0x00000001U;
+	}
+
+    /* Configure Maximum time-out period */
+    stcREG->STCTPR = max_timeout;
+
+    /* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+    for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ }
+
+    /* Enable self-test */
+    stcREG->STCGCR1 = 0xAU;
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+    /* Idle the CPU so that the self-test can start */
+
+    _gotoCPUIdle_();
+
+}
+
+/** @fn void pbistSelfCheck(void)
+*   @brief PBIST self test Driver
+*
+*   This function is called to perform PBIST self test.
+*
+*   @note This Function uses register's which are not exposed to users through
+*   TRM , to run custom algorithm to make PBIST Fail. Users can use this function as Black box.
+*
+*/
+/* SourceId : SELFTEST_SourceId_005 */
+/* DesignId : SELFTEST_DesignId_005 */
+/* Requirements : HL_SR399 */
+void pbistSelfCheck(void)
+{
+    volatile uint32 i = 0U;
+    uint32 PBIST_wait_done_loop = 0U;
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+    /* Run a diagnostic check on the memory self-test controller */
+    /* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */
+
+    /* Disable PBIST clocks and ROM clock */
+    pbistREG->PACT = 0x0U;
+    
+    /* PBIST ROM clock frequency = HCLK frequency /2 */
+    /* Disable memory self controller */
+    systemREG1->MSTGCR = 0x00000105U;                
+    
+    /* Disable Memory Initialization controller */
+    systemREG1->MINITGCR = 0x5U;
+
+    /* Enable memory self controller */
+    systemREG1->MSTGCR = 0x0000010AU;                               
+
+    /* Clear PBIST Done */
+    systemREG1->MSTCGSTAT = 0x1U;
+    
+    /* Enable PBIST controller */
+    systemREG1->MSINENA = 0x1U;
+
+    /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+    for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ }
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+    /* Enable PBIST clocks and ROM clock */
+    pbistREG->PACT = 0x3U;
+
+    /* CPU control of PBIST */
+    pbistREG->DLR = 0x10U;
+
+    /* Custom always fail algo, this will not use the ROM and just set a fail */
+    pbistREG->RAMT         = 0x00002000U;
+    *(volatile uint32 *)0xFFFFE400U = 0x4C000001U;
+    *(volatile uint32 *)0xFFFFE440U = 0x00000075U;
+    *(volatile uint32 *)0xFFFFE404U = 0x4C000002U;
+    *(volatile uint32 *)0xFFFFE444U = 0x00000075U;
+    *(volatile uint32 *)0xFFFFE408U = 0x4C000003U;
+    *(volatile uint32 *)0xFFFFE448U = 0x00000075U;
+    *(volatile uint32 *)0xFFFFE40CU = 0x4C000004U;
+    *(volatile uint32 *)0xFFFFE44CU = 0x00000075U;
+    *(volatile uint32 *)0xFFFFE410U = 0x4C000005U;
+    *(volatile uint32 *)0xFFFFE450U = 0x00000075U;
+    *(volatile uint32 *)0xFFFFE414U = 0x4C000006U;
+    *(volatile uint32 *)0xFFFFE454U = 0x00000075U;
+    *(volatile uint32 *)0xFFFFE418U = 0x00000000U;
+    *(volatile uint32 *)0xFFFFE458U = 0x00000001U;
+
+    /* PBIST_RUN */
+    pbistREG->rsvd1[1U]    = 1U;
+
+    /* wait until memory self-test done is indicated */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ((systemREG1->MSTCGSTAT & 0x1U) != 0x1U) 
+    {
+        PBIST_wait_done_loop++;
+    }/* Wait */
+
+    /* Check for the failure */
+    if ((pbistREG->FSRF0 & 0x1U) != 0x1U)
+    {
+        /* No failure was indicated even if the always fail algorithm was run*/
+        selftestFailNotification(PBISTSELFCHECK_FAIL1);
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+    }
+    else
+    {
+        /* Check that the algorithm executed in the expected amount of time. */
+        /* This time is dependent on the ROMCLKDIV selected above            */
+        if (PBIST_wait_done_loop >= 2U)
+        {
+            selftestFailNotification(PBISTSELFCHECK_FAIL2);
+        }
+        
+        /* Disable PBIST clocks and ROM clock */
+        pbistREG->PACT = 0x0U;
+
+        /* Disable PBIST */
+        systemREG1->MSTGCR &= 0xFFFFFFF0U;
+        systemREG1->MSTGCR |= 0x5U;
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+    }
+}
+
+/** @fn void pbistRun(uint32 raminfoL, uint32 algomask)
+*   @brief CPU self test Driver
+*   @param[in] raminfoL   - Select the list of RAM to be tested.
+*   @param[in] algomask   - Select the list of Algorithm to be run.
+*
+*   This function performs Memory Built-in Self test using PBIST module.
+*/
+/* SourceId : SELFTEST_SourceId_006 */
+/* DesignId : SELFTEST_DesignId_006 */
+/* Requirements : HL_SR400 */
+void pbistRun(uint32 raminfoL, uint32 algomask)
+{
+    volatile uint32 i = 0U;
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+    /* PBIST ROM clock frequency = HCLK frequency /2 */
+    /* Disable memory self controller */
+    systemREG1->MSTGCR = 0x00000105U;
+
+    /* Disable Memory Initialization controller */
+    systemREG1->MINITGCR = 0x5U;
+
+    /* Enable PBIST controller */
+    systemREG1->MSINENA = 0x1U;
+
+    /* Enable memory self controller */
+    systemREG1->MSTGCR = 0x0000010AU;
+
+    /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+    for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ }
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+    /* Enable PBIST clocks and ROM clock */
+    pbistREG->PACT = 0x3U;
+
+    /* Select all algorithms to be tested */
+    pbistREG->ALGO = algomask;
+
+    /* Select RAM groups */
+    pbistREG->RINFOL = raminfoL;
+
+    /* Select all RAM groups */
+    pbistREG->RINFOU = 0x00000000U;
+
+    /* ROM contents will not override RINFOx settings */
+    pbistREG->OVER = 0x0U;
+
+    /* Algorithm code is loaded from ROM */
+    pbistREG->ROM = 0x3U;
+
+    /* Start PBIST */
+    pbistREG->DLR = 0x14U;
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+}
+
+/** @fn void pbistStop(void)
+*   @brief Routine to stop PBIST test enabled.
+*
+*   This function is called to stop PBIST after test is performed.
+*/
+/* SourceId : SELFTEST_SourceId_007 */
+/* DesignId : SELFTEST_DesignId_007 */
+/* Requirements : HL_SR523 */
+void pbistStop(void)
+{
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+    /* disable pbist clocks and ROM clock */
+    pbistREG->PACT = 0x0U;
+    systemREG1->MSTGCR &= 0xFFFFFFF0U;
+    systemREG1->MSTGCR |= 0x5U;
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+}
+
+/** @fn boolean pbistIsTestCompleted(void)
+*   @brief Checks to see if the PBIST test is completed.
+*   @return 1 if PBIST test completed, otherwise 0.
+*
+*   Checks to see if the PBIST test is completed.
+*/
+/* SourceId : SELFTEST_SourceId_008 */
+/* DesignId : SELFTEST_DesignId_008 */
+/* Requirements : HL_SR401 */
+boolean pbistIsTestCompleted(void)
+{
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+    return ((systemREG1->MSTCGSTAT & 0x1U) != 0U);
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+}
+
+/** @fn boolean pbistIsTestPassed(void)
+*   @brief Checks to see if the PBIST test is completed successfully.
+*   @return 1 if PBIST test passed, otherwise 0.
+*
+*   Checks to see if the PBIST test is completed successfully.
+*/
+/* SourceId : SELFTEST_SourceId_009 */
+/* DesignId : SELFTEST_DesignId_009 */
+/* Requirements : HL_SR401 */
+boolean pbistIsTestPassed(void)
+{
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+	boolean status;
+
+    if (pbistREG->FSRF0 == 0U)
+	{
+		status = TRUE;
+	}
+	else
+	{
+		status = FALSE;
+	}
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+	return status;
+}
+
+/** @fn boolean pbistPortTestStatus(uint32 port)
+*   @brief Checks to see if the PBIST Port test is completed successfully.
+*   @param[in] port   - Select the port to get the status.
+*   @return 1 if PBIST Port test completed successfully, otherwise 0.
+*
+*   Checks to see if the selected PBIST Port test is completed successfully.
+*/
+/* SourceId : SELFTEST_SourceId_010 */
+/* DesignId : SELFTEST_DesignId_010 */
+/* Requirements : HL_SR401 */
+boolean pbistPortTestStatus(uint32 port)
+{
+    boolean status;
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+    if(port == (uint32)PBIST_PORT0)
+    {
+      status =  (pbistREG->FSRF0 == 0U);
+    }
+    else
+    {
+      /* Invalid Input */
+      status =  FALSE;
+    }
+
+    return  status;
+}
+
+/** @fn uint32 efcCheck(void)
+*   @brief EFUSE module self check Driver
+*   @return Returns 0 if no error was detected during autoload and Stuck At Zero Test passed
+*                   1 if no error was detected during autoload but Stuck At Zero Test failed
+*                   2 if there was a single-bit error detected during autoload
+*                   3 if some other error occurred during autoload
+*
+*   This function self checks the EFUSE module.
+*/
+/* SourceId : SELFTEST_SourceId_011 */
+/* DesignId : SELFTEST_DesignId_012 */
+/* Requirements : HL_SR402 */
+uint32 efcCheck(void)
+{
+    uint32 efcStatus = 0U;
+    uint32 status;
+    
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+
+    /* read the EFC Error Status Register */
+    efcStatus = efcREG->ERROR;
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+    if (efcStatus == 0x0U)
+    {
+        /* run stuck-at-zero test and check if it passed */
+        if (efcStuckZeroTest()== TRUE)
+        {
+            /* start EFC ECC logic self-test */
+            efcSelfTest();
+            status = 0U;
+        }
+        else
+        {
+            /* EFC output is stuck-at-zero, device operation unreliable */
+            selftestFailNotification(EFCCHECK_FAIL1);
+            status = 1U;
+        }
+    }
+    /* EFC Error Register is not zero */
+    else
+    {
+        /* one-bit error detected during autoload */
+        if (efcStatus == 0x15U)
+        {
+            /* start EFC ECC logic self-test */
+            efcSelfTest();
+            status = 2U;
+        }
+        else
+        {
+            /* Some other EFC error was detected */
+            selftestFailNotification(EFCCHECK_FAIL1);
+            status = 3U;
+        }
+    }
+    return status;
+}
+
+/** @fn boolean efcStuckZeroTest(void)
+*   @brief Checks to see if the EFUSE Stuck at zero test is completed successfully.
+*   @return 1 if EFUSE Stuck at zero test completed, otherwise 0.
+*
+*   Checks to see if the EFUSE Stuck at zero test is completed successfully.
+*/
+/* SourceId : SELFTEST_SourceId_012 */
+/* DesignId : SELFTEST_DesignId_014 */
+/* Requirements : HL_SR402 */
+boolean efcStuckZeroTest(void)
+{
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+    uint32 ESM_ESTATUS4, ESM_ESTATUS1;
+
+    boolean result = FALSE;
+    uint32 error_checks = EFC_INSTRUCTION_INFO_EN  |
+                                  EFC_INSTRUCTION_ERROR_EN |
+                                  EFC_AUTOLOAD_ERROR_EN      |
+                                  EFC_SELF_TEST_ERROR_EN   ;
+
+    /* configure the output enable for auto load error , instruction info,
+         instruction error, and self test error using boundary register
+         and drive values one across all the errors */
+    efcREG->BOUNDARY = ((uint32)OUTPUT_ENABLE | error_checks);
+
+    /* Read from the pin register. This register holds the current values
+         of above errors. This value should be 0x5c00.If not at least one of
+         the above errors is stuck at 0. */
+    if ((efcREG->PINS & 0x5C00U) == 0x5C00U)
+    {
+        ESM_ESTATUS4 = esmREG->SR4[0U];
+        ESM_ESTATUS1 = esmREG->SR1[2U];
+        /* check if the ESM group1 channel 41 is set and group3 channel 1 is set */
+        if (((ESM_ESTATUS4 & 0x200U) == 0x200U) && ((ESM_ESTATUS1 & 0x2U) == 0x2U))
+        {
+           /* stuck-at-zero test passed */
+           result = TRUE;
+        }
+    }
+
+    /* put the pins back low */
+    efcREG->BOUNDARY = OUTPUT_ENABLE;
+
+    /* clear group1 flag */
+    esmREG->SR4[0U] = 0x200U;
+
+    /* clear group3 flag */
+    esmREG->SR1[2U] = 0x2U;
+
+    /* The nERROR pin will become inactive once the LTC counter expires */
+    esmREG->EKR = 0x5U;
+
+    return result;
+}
+
+/** @fn void efcSelfTest(void)
+*   @brief EFUSE module self check Driver
+*
+*   This function self checks the EFSUE module.
+*/
+/* SourceId : SELFTEST_SourceId_013 */
+/* DesignId : SELFTEST_DesignId_013 */
+/* Requirements : HL_SR402 */
+void efcSelfTest(void)
+{
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+    /* configure self-test cycles */
+    efcREG->SELF_TEST_CYCLES = 0x258U;
+
+    /* configure self-test signature */
+    efcREG->SELF_TEST_SIGN = 0x5362F97FU;
+
+    /* configure boundary register to start ECC self-test */
+    efcREG->BOUNDARY = 0x0000200FU;
+}
+
+/** @fn boolean checkefcSelfTest(void)
+*   @brief EFUSE module self check Driver
+*   @return Returns TRUE if EFC Selftest was a PASS, else FALSE
+*
+*   This function returns the status of efcSelfTest.
+*   Note: This function can be called only after calling efcSelfTest
+*/
+/* SourceId : SELFTEST_SourceId_014 */
+/* DesignId : SELFTEST_DesignId_015 */
+/* Requirements : HL_SR403 */
+boolean checkefcSelfTest(void)
+{
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+    boolean result = FALSE;
+
+    uint32 EFC_PINS, EFC_ERROR;
+	uint32 esmCh40Stat, esmCh41Stat = 0U;
+
+    /* wait until EFC self-test is done */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while((efcREG->PINS & EFC_SELF_TEST_DONE) == 0U)
+    {
+    }/* Wait */
+
+    /* check if EFC self-test error occurred */
+    EFC_PINS = efcREG->PINS;
+    EFC_ERROR = efcREG->ERROR;
+    if(((EFC_PINS & EFC_SELF_TEST_ERROR) == 0U) && ((EFC_ERROR & 0x1FU) == 0U))
+    {
+        /* check if EFC self-test error is set */
+		esmCh40Stat = esmREG->SR4[0U] & 0x100U;
+		esmCh41Stat = esmREG->SR4[0U] & 0x200U;
+        if ((esmCh40Stat == 0U) && (esmCh41Stat == 0U))
+        {
+            result = TRUE;
+        }
+    }
+    return result;
+}
+
+/** @fn void fmcBus2Check(void)
+*   @brief Self Check Flash Bus2 Interface
+*
+*   This function self checks Flash Bus2 Interface
+*/
+/* SourceId : SELFTEST_SourceId_015 */
+/* DesignId : SELFTEST_DesignId_016 */
+/* Requirements : HL_SR404, HL_SR405 */
+void fmcBus2Check(void)
+{
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+    /* enable ECC logic inside FMC */
+    flashWREG->FEDACCTRL1 = 0x000A060AU;
+
+    if ((esmREG->SR1[0U] & 0x40U) == 0x40U)
+    {
+        /* a 1-bit error was detected during flash OTP read by flash module
+           run a self-check on ECC logic inside FMC */
+
+        /* clear ESM group1 channel 6 flag */
+        esmREG->SR1[0U] = 0x40U;
+
+        fmcECCcheck();
+    }
+
+    /* no 2-bit or 1-bit error detected during power-up */
+    else
+    {
+        fmcECCcheck();
+    }
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+}
+
+/** @fn void fmcECCcheck(void)
+*   @brief Check Flash ECC Single Bit and multi Bit errors detection logic.
+*
+*   This function Checks Flash ECC Single Bit and multi Bit errors detection logic.
+*/
+/* SourceId : SELFTEST_SourceId_016 */
+/* DesignId : SELFTEST_DesignId_017 */
+/* Requirements : HL_SR404, HL_SR405 */
+void fmcECCcheck(void)
+{
+    volatile uint32 otpread;
+    volatile uint32 temp;
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+
+    /* read location with deliberate 1-bit error */
+    otpread = flash1bitError;
+    if ((esmREG->SR1[0U] & 0x40U) == 0x40U)
+    {
+        /* 1-bit failure was indicated and corrected */
+        flashWREG->FEDACSTATUS = 0x00010006U;
+
+        /* clear ESM group1 channel 6 flag */
+        esmREG->SR1[0U] = 0x40U;
+
+        /* read location with deliberate 2-bit error */
+        otpread = flash2bitError;
+        if ((esmREG->SR1[2U] & 0x80U) == 0x80U)
+        {
+            /* 2-bit failure was detected correctly */
+            temp = flashWREG->FUNCERRADD;
+            flashWREG->FEDACSTATUS = 0x00020100U;
+
+            /* clear ESM group3 channel 7 */
+            esmREG->SR1[2U] = 0x80U;
+
+            /* The nERROR pin will become inactive once the LTC counter expires */
+            esmREG->EKR = 0x5U;
+
+        }
+        else
+        {
+            /* ECC logic inside FMC cannot detect 2-bit error */
+            selftestFailNotification(FMCECCCHECK_FAIL1);
+        }
+    }
+    else
+    {
+        /* ECC logic inside FMC cannot detect 1-bit error */
+        selftestFailNotification(FMCECCCHECK_FAIL1);
+    }
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+}
+
+/** @fn void checkB0RAMECC(void)
+*   @brief Check TCRAM1 ECC error detection logic.
+*
+*   This function checks TCRAM1 ECC error detection logic.
+*/
+/* SourceId : SELFTEST_SourceId_017 */
+/* DesignId : SELFTEST_DesignId_019 */
+/* Requirements : HL_SR408 */
+void checkB0RAMECC(void)
+{
+    volatile uint64 ramread = 0U;
+	volatile uint32 regread = 0U;
+	uint32 tcram1ErrStat, tcram2ErrStat = 0U;
+	
+    uint64 tcramA1_bk = tcramA1bit;
+    uint64 tcramA2_bk = tcramA2bit;
+    volatile uint32 i;
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+    /* enable writes to ECC RAM, enable ECC error response */
+    tcram1REG->RAMCTRL = 0x0005010AU;
+    tcram2REG->RAMCTRL = 0x0005010AU;
+
+    /* the first 1-bit error will cause an error response */
+    tcram1REG->RAMTHRESHOLD = 0x1U;
+    tcram2REG->RAMTHRESHOLD = 0x1U;
+
+    /* allow SERR to be reported to ESM */
+    tcram1REG->RAMINTCTRL = 0x1U;
+    tcram2REG->RAMINTCTRL = 0x1U;
+
+    /* cause a 1-bit ECC error */
+    _coreDisableRamEcc_();
+    tcramA1bitError ^= 0x1U;
+    _coreEnableRamEcc_();
+
+    /* disable writes to ECC RAM */
+    tcram1REG->RAMCTRL = 0x0005000AU;
+    tcram2REG->RAMCTRL = 0x0005000AU;
+
+    /* read from location with 1-bit ECC error */
+    ramread = tcramA1bit;
+
+	/* Check for error status */
+	tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x1U;
+	tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x1U;
+	/*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
+	/*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
+    if((tcram1ErrStat == 0U) && (tcram2ErrStat == 0U))
+    {
+        /* TCRAM module does not reflect 1-bit error reported by CPU */
+        selftestFailNotification(CHECKB0RAMECC_FAIL1);
+    }
+    else
+    {
+        /* clear SERR flag */
+        tcram1REG->RAMERRSTATUS = 0x1U;
+        tcram2REG->RAMERRSTATUS = 0x1U;
+
+        /* clear status flags for ESM group1 channels 26 and 28 */
+        esmREG->SR1[0U] = 0x14000000U;
+    }
+
+    /* enable writes to ECC RAM, enable ECC error response */
+    tcram1REG->RAMCTRL = 0x0005010AU;
+    tcram2REG->RAMCTRL = 0x0005010AU;
+
+    /* cause a 2-bit ECC error */
+    _coreDisableRamEcc_();
+    tcramA2bitError ^= 0x3U;
+    _coreEnableRamEcc_();
+
+    /* read from location with 2-bit ECC error this will cause a data abort to be generated */
+    ramread = tcramA2bit;
+
+    /* delay before restoring the ram value */
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+    for(i=0U;i<10U;i++)
+    {
+    }/* Wait */
+
+    regread = tcram1REG->RAMUERRADDR;
+    regread = tcram2REG->RAMUERRADDR;
+
+    /* disable writes to ECC RAM */
+    tcram1REG->RAMCTRL = 0x0005000AU;
+    tcram2REG->RAMCTRL = 0x0005000AU;
+
+    /* Compute correct ECC */
+    tcramA1bit = tcramA1_bk;
+    tcramA2bit = tcramA2_bk;
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+}
+
+/** @fn void checkB1RAMECC(void)
+*   @brief Check TCRAM2 ECC error detection logic.
+*
+*   This function checks TCRAM2 ECC error detection logic.
+*/
+/* SourceId : SELFTEST_SourceId_018 */
+/* DesignId : SELFTEST_DesignId_019 */
+/* Requirements : HL_SR408 */
+void checkB1RAMECC(void)
+{
+    volatile uint64 ramread = 0U;
+	volatile uint32 regread = 0U;
+	uint32 tcram1ErrStat, tcram2ErrStat = 0U;
+
+    uint64 tcramB1_bk = tcramB1bit;
+    uint64 tcramB2_bk = tcramB2bit;
+    volatile uint32 i;
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+
+    /* enable writes to ECC RAM, enable ECC error response */
+    tcram1REG->RAMCTRL = 0x0005010AU;
+    tcram2REG->RAMCTRL = 0x0005010AU;
+
+    /* the first 1-bit error will cause an error response */
+    tcram1REG->RAMTHRESHOLD = 0x1U;
+    tcram2REG->RAMTHRESHOLD = 0x1U;
+
+    /* allow SERR to be reported to ESM */
+    tcram1REG->RAMINTCTRL = 0x1U;
+    tcram2REG->RAMINTCTRL = 0x1U;
+
+    /* cause a 1-bit ECC error */
+    _coreDisableRamEcc_();
+    tcramB1bitError ^= 0x1U;
+    _coreEnableRamEcc_();
+
+    /* disable writes to ECC RAM */
+    tcram1REG->RAMCTRL = 0x0005000AU;
+    tcram2REG->RAMCTRL = 0x0005000AU;
+
+    /* read from location with 1-bit ECC error */
+    ramread = tcramB1bit;
+
+	/* Check for error status */
+	tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x1U;
+	tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x1U;
+	/*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
+	/*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
+    if((tcram1ErrStat == 0U) && (tcram2ErrStat == 0U))
+    {
+        /* TCRAM module does not reflect 1-bit error reported by CPU */
+        selftestFailNotification(CHECKB1RAMECC_FAIL1);
+    }
+    else
+    {
+        /* clear SERR flag */
+        tcram1REG->RAMERRSTATUS = 0x1U;
+        tcram2REG->RAMERRSTATUS = 0x1U;
+
+        /* clear status flags for ESM group1 channels 26 and 28 */
+        esmREG->SR1[0U] = 0x14000000U;
+    }
+
+    /* enable writes to ECC RAM, enable ECC error response */
+    tcram1REG->RAMCTRL = 0x0005010AU;
+    tcram2REG->RAMCTRL = 0x0005010AU;
+
+    /* cause a 2-bit ECC error */
+    _coreDisableRamEcc_();
+    tcramB2bitError ^= 0x3U;
+    _coreEnableRamEcc_();
+
+    /* read from location with 2-bit ECC error this will cause a data abort to be generated */
+    ramread = tcramB2bit;
+
+    /* delay before restoring the ram value */
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+	for(i=0U;i<10U;i++)
+    {
+    }/* Wait */
+
+    regread = tcram1REG->RAMUERRADDR;
+    regread = tcram2REG->RAMUERRADDR;
+
+    /* disable writes to ECC RAM */
+    tcram1REG->RAMCTRL = 0x0005000AU;
+    tcram2REG->RAMCTRL = 0x0005000AU;
+
+    /* Compute correct ECC */
+    tcramB1bit = tcramB1_bk;
+    tcramB2bit = tcramB2_bk;
+
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+}
+
+/** @fn void checkFlashECC(void)
+*   @brief Check Flash ECC error detection logic.
+*
+*   This function checks Flash ECC error detection logic.
+*/
+/* SourceId : SELFTEST_SourceId_019 */
+/* DesignId : SELFTEST_DesignId_020 */
+/* Requirements : HL_SR405 */
+void checkFlashECC(void)
+{
+    /* Routine to check operation of ECC logic inside CPU for accesses to program flash */
+    volatile uint32 flashread = 0U;
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+
+    /* Flash Module ECC Response enabled */
+    flashWREG->FEDACCTRL1 = 0x000A060AU;
+
+    /* Enable diagnostic mode and select diag mode 7 */
+    flashWREG->FDIAGCTRL = 0x00050007U;
+
+    /* Select ECC diagnostic mode, single-bit to be corrupted */
+    flashWREG->FPAROVR = 0x00005A01U;
+
+    /* Set the trigger for the diagnostic mode */
+    flashWREG->FDIAGCTRL |= 0x01000000U;
+
+    /* read a flash location from the mirrored memory map */
+    flashread = flashBadECC1;
+
+    /* disable diagnostic mode */
+    flashWREG->FDIAGCTRL = 0x000A0007U;
+
+    /* this will have caused a single-bit error to be generated and corrected by CPU */
+    /* single-bit error not captured in flash module */
+    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+    if ((flashWREG->FEDACSTATUS & 0x2U) == 0U)
+    {
+        selftestFailNotification(CHECKFLASHECC_FAIL1);
+    }
+    else
+    {
+        /* clear single-bit error flag */
+        flashWREG->FEDACSTATUS = 0x2U;
+
+        /* clear ESM flag */
+        esmREG->SR1[0U] = 0x40U;
+
+        /* Enable diagnostic mode and select diag mode 7 */
+        flashWREG->FDIAGCTRL = 0x00050007U;
+
+        /* Select ECC diagnostic mode, two bits of ECC to be corrupted */
+        flashWREG->FPAROVR = 0x00005A03U;
+
+        /* Set the trigger for the diagnostic mode */
+        flashWREG->FDIAGCTRL |= 0x01000000U;
+
+        /* read from flash location from mirrored memory map this will cause a data abort */
+        flashread = flashBadECC2;
+
+        /* Read FUNCERRADD register */
+        flashread = flashWREG->FUNCERRADD;
+
+        /* disable diagnostic mode */
+        flashWREG->FDIAGCTRL = 0x000A0007U;
+    }
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+}
+
+/** @fn void custom_dabort(void)
+*   @brief Custom Data abort routine for the application.
+*
+*   Custom Data abort routine for the application.
+*/
+void custom_dabort(void)
+{
+    /* Need custom data abort handler here.
+     * This data abort is not caused due to diagnostic checks of flash and TCRAM ECC logic.
+     */
+/* USER CODE BEGIN (42) */
+/* USER CODE END */
+}
+
+/** @fn void stcSelfCheckFail(void)
+*   @brief STC Self test check fail service routine
+*
+*   This function is called if STC Self test check fail.
+*/
+void stcSelfCheckFail(void)
+{
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+    /* CPU self-test controller's own self-test failed.
+     * It is not possible to verify that STC is capable of indicating a CPU self-test error.
+     * It is not recommended to continue operation.
+     */
+
+    /* User can add small piece of code to take system to Safe state using user code section.
+     * Note: Just removing the for(;;) will take the system to unknown state under ST failure,
+     * since it is not handled by HALCoGen driver */
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+    /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    for(;;)
+    {
+    }/* Wait */
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+}
+
+/** @fn void cpuSelfTestFail(void)
+*   @brief CPU Self test check fail service routine
+*
+*   This function is called if CPU Self test check fail.
+*/
+void cpuSelfTestFail(void)
+{
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+    /* CPU self-test has failed.
+     * CPU operation is not reliable.
+     */
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+    /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    for(;;)
+    {
+    }/* Wait */
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+}
+
+
+/** @fn void vimParityCheck(void)
+*   @brief Routine to check VIM RAM parity error detection and signaling mechanism
+*
+*   Routine to check VIM RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_020 */
+/* DesignId : SELFTEST_DesignId_021 */
+/* Requirements : HL_SR385 */
+void vimParityCheck(void)
+{
+    volatile uint32 vimramread = 0U;
+    uint32 vimparctl_bk = VIM_PARCTL;
+
+/* USER CODE BEGIN (49) */
+/* USER CODE END */
+
+    /* Enable parity checking and parity test mode */
+    VIM_PARCTL = 0x0000010AU;
+
+    /* flip a bit in the VIM RAM parity location */
+    VIMRAMPARLOC ^= 0x1U;
+
+    /* disable parity test mode */
+    VIM_PARCTL = 0x0000000AU;
+
+    /* cause parity error */
+    vimramread = VIMRAMLOC;
+
+    /* check if ESM group1 channel 15 is flagged */
+    if ((esmREG->SR1[0U] & 0x8000U) ==0U)
+    {
+        /* VIM RAM parity error was not flagged to ESM. */
+        selftestFailNotification(VIMPARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear VIM RAM parity error flag in VIM */
+        VIM_PARFLG = 0x1U;
+
+        /* clear ESM group1 channel 15 flag */
+        esmREG->SR1[0U] = 0x8000U;
+
+        /* Enable parity checking and parity test mode */
+        VIM_PARCTL = 0x0000010AU;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        VIMRAMPARLOC ^= 0x1U;
+    }
+
+    /* Restore Parity Control register */
+    VIM_PARCTL = vimparctl_bk;
+
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+}
+
+
+/** @fn void dmaParityCheck(void)
+*   @brief Routine to check DMA control packet RAM parity error detection and signaling mechanism
+*
+*   Routine to check DMA control packet RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_021 */
+/* DesignId : SELFTEST_DesignId_022 */
+/* Requirements : HL_SR388 */
+void dmaParityCheck(void)
+{
+    volatile uint32 dmaread = 0U;
+    uint32 dmaparcr_bk = DMA_PARCR;
+
+/* USER CODE BEGIN (51) */
+/* USER CODE END */
+
+    /* Enable parity checking and parity test mode */
+    DMA_PARCR = 0x0000010AU;
+
+    /* Flip a bit in DMA RAM parity location */
+    DMARAMPARLOC ^= 0x1U;
+
+    /* Disable parity test mode */
+    DMA_PARCR = 0x0000000AU;
+
+    /* Cause parity error */
+    dmaread = DMARAMLOC;
+
+    /* Check if ESM group1 channel 3 is flagged */
+    if ((esmREG->SR1[0U] & 0x8U) == 0U)
+    {
+        /* DMA RAM parity error was not flagged to ESM. */
+        selftestFailNotification(DMAPARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear DMA parity error flag in DMA */
+        DMA_PARADDR = 0x01000000U;
+
+        /* clear ESM group1 channel 3 flag */
+        esmREG->SR1[0U] = 0x8U;
+
+        /* Enable parity checking and parity test mode */
+        DMA_PARCR = 0x0000010AU;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        DMARAMPARLOC ^= 0x1U;
+    }
+
+    /* Restrore Parity Control register */
+    DMA_PARCR = dmaparcr_bk;
+
+/* USER CODE BEGIN (52) */
+/* USER CODE END */
+}
+
+
+/** @fn void het1ParityCheck(void)
+*   @brief Routine to check HET1 RAM parity error detection and signaling mechanism
+*
+*   Routine to check HET1 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_022 */
+/* DesignId : SELFTEST_DesignId_024 */
+/* Requirements : HL_SR389 */
+void het1ParityCheck(void)
+{
+    volatile uint32 nhetread = 0U;
+    uint32 hetpcr_bk = hetREG1->PCR;
+
+/* USER CODE BEGIN (53) */
+/* USER CODE END */
+
+    /* Set TEST mode and enable parity checking */
+    hetREG1->PCR = 0x0000010AU;
+
+    /* flip parity bit */
+    NHET1RAMPARLOC ^= 0x1U;
+
+    /* Disable TEST mode */
+    hetREG1->PCR = 0x0000000AU;
+
+    /* read to cause parity error */
+    nhetread = NHET1RAMLOC;
+
+    /* check if ESM group1 channel 7 is flagged */
+    if ((esmREG->SR1[0U] & 0x80U) ==0U)
+    {
+        /* NHET1 RAM parity error was not flagged to ESM. */
+        selftestFailNotification(HET1PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear ESM group1 channel 7 flag */
+        esmREG->SR1[0U] = 0x80U;
+
+        /* Set TEST mode and enable parity checking */
+        hetREG1->PCR = 0x0000010AU;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        NHET1RAMPARLOC ^= 0x1U;
+    }
+
+    /* Restore Parity comtrol register */
+    hetREG1->PCR = hetpcr_bk;
+
+/* USER CODE BEGIN (54) */
+/* USER CODE END */
+}
+
+
+/** @fn void htu1ParityCheck(void)
+*   @brief Routine to check HTU1 RAM parity error detection and signaling mechanism
+*
+*   Routine to check HTU1 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_023 */
+/* DesignId : SELFTEST_DesignId_025 */
+/* Requirements : HL_SR390 */
+void htu1ParityCheck(void)
+{
+    volatile uint32 hturead = 0U;
+    uint32 htupcr_bk = htuREG1->PCR;
+
+/* USER CODE BEGIN (55) */
+/* USER CODE END */
+
+    /* Enable parity and TEST mode */
+    htuREG1->PCR = 0x0000010AU;
+
+    /* flip parity bit */
+    HTU1PARLOC ^= 0x1U;
+
+    /* Disable parity RAM test mode */
+    htuREG1->PCR = 0x0000000AU;
+
+    /* read to cause parity error */
+    hturead = HTU1RAMLOC;
+
+    /* check if ESM group1 channel 8 is flagged */
+    if ((esmREG->SR1[0U] & 0x100U) == 0U)
+    {
+        /* HTU1 RAM parity error was not flagged to ESM. */
+        selftestFailNotification(HTU1PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* Clear HTU parity error flag */
+        htuREG1->PAR = 0x00010000U;
+        esmREG->SR1[0U] = 0x100U;
+
+        /* Enable parity and TEST mode */
+        htuREG1->PCR = 0x0000010AU;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        HTU1PARLOC ^= 0x1U;
+    }
+
+    /* Restore Parity control register */
+    htuREG1->PCR = htupcr_bk;
+
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
+
+}
+
+
+/** @fn void het2ParityCheck(void)
+*   @brief Routine to check HET2 RAM parity error detection and signaling mechanism
+*
+*   Routine to check HET2 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_024 */
+/* DesignId : SELFTEST_DesignId_024 */
+/* Requirements : HL_SR389 */
+void het2ParityCheck(void)
+{
+    volatile uint32 nhetread = 0U;
+    uint32 hetpcr_bk = hetREG2->PCR;
+	uint32 esmCh7Stat, esmCh34Stat = 0U;
+	
+/* USER CODE BEGIN (57) */
+/* USER CODE END */
+
+    /* Set TEST mode and enable parity checking */
+    hetREG2->PCR = 0x0000010AU;
+
+    /* flip parity bit */
+    NHET2RAMPARLOC ^= 0x1U;
+
+    /* Disable TEST mode */
+    hetREG2->PCR = 0x0000000AU;
+
+    /* read to cause parity error */
+    nhetread = NHET2RAMLOC;
+
+    /* check if ESM group1 channel 7 or 34 (If not reserved) is flagged */
+	esmCh7Stat  = esmREG->SR1[0U] & 0x80U;
+	esmCh34Stat = esmREG->SR4[0U] & 0x4U;
+    if ((esmCh7Stat == 0U) && (esmCh34Stat ==0U))
+    {
+        /* NHET2 RAM parity error was not flagged to ESM. */
+        selftestFailNotification(HET2PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear ESM group1 channel 7 flag */
+        esmREG->SR1[0U] = 0x80U;
+
+        /* clear ESM group1 channel 34 flag */
+        esmREG->SR4[0U] = 0x4U;
+
+        /* Set TEST mode and enable parity checking */
+        hetREG2->PCR = 0x0000010AU;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        NHET2RAMPARLOC ^= 0x1U;
+    }
+
+    /* Restore parity control register */
+    hetREG2->PCR = hetpcr_bk;
+
+/* USER CODE BEGIN (58) */
+/* USER CODE END */
+}
+
+
+/** @fn void htu2ParityCheck(void)
+*   @brief Routine to check HTU2 RAM parity error detection and signaling mechanism
+*
+*   Routine to check HTU2 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_025 */
+/* DesignId : SELFTEST_DesignId_025 */
+/* Requirements : HL_SR390 */
+void htu2ParityCheck(void)
+{
+    volatile uint32 hturead = 0U;
+    uint32 htupcr_bk = htuREG2->PCR;
+
+/* USER CODE BEGIN (59) */
+/* USER CODE END */
+
+    /* Enable parity and TEST mode */
+    htuREG2->PCR = 0x0000010AU;
+
+    /* flip parity bit */
+    HTU2PARLOC ^= 0x1U;
+
+    /* Disable parity RAM test mode */
+    htuREG2->PCR = 0x0000000AU;
+
+    /* read to cause parity error */
+    hturead = HTU2RAMLOC;
+
+    /* check if ESM group1 channel 8 is flagged */
+    if ((esmREG->SR1[0U] & 0x100U) == 0U)
+    {
+        /* HTU2 RAM parity error was not flagged to ESM. */
+        selftestFailNotification(HTU2PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* Clear HTU parity error flag */
+        htuREG2->PAR = 0x00010000U;
+        esmREG->SR1[0U] = 0x100U;
+
+        /* Enable parity and TEST mode */
+        htuREG2->PCR = 0x0000010AU;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        HTU2PARLOC ^= 0x1U;
+    }
+
+    /* Restore parity control register*/
+    htuREG2->PCR = htupcr_bk;
+
+/* USER CODE BEGIN (60) */
+/* USER CODE END */
+}
+
+
+/** @fn void adc1ParityCheck(void)
+*   @brief Routine to check ADC1 RAM parity error detection and signaling mechanism
+*
+*   Routine to check ADC1 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_026 */
+/* DesignId : SELFTEST_DesignId_023 */
+/* Requirements : HL_SR387 */
+void adc1ParityCheck(void)
+{
+    volatile uint32 adcramread = 0U;
+    uint32 adcparcr_bk = adcREG1->PARCR;
+
+/* USER CODE BEGIN (61) */
+/* USER CODE END */
+
+    /* Set the TEST bit in the PARCR and enable parity checking */
+    adcREG1->PARCR = 0x10AU;
+
+    /* Invert the parity bits inside the ADC1 RAM's first location */
+    adcPARRAM1 = ~(adcPARRAM1);
+
+    /* clear the TEST bit */
+    adcREG1->PARCR = 0x00AU;
+
+    /* This read is expected to trigger a parity error */
+    adcramread = adcRAM1;
+
+    /* Check for ESM group1 channel 19 to be flagged */
+    if ((esmREG->SR1[0U] & 0x80000U) ==0U)
+    {
+        /* no ADC1 RAM parity error was flagged to ESM */
+        selftestFailNotification(ADC1PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear ADC1 RAM parity error flag */
+        esmREG->SR1[0U] = 0x80000U;
+
+        /* Set the TEST bit in the PARCR and enable parity checking */
+        adcREG1->PARCR = 0x10AU;
+
+        /* Revert back the parity bits to correct data */
+        adcPARRAM1 = ~(adcPARRAM1);
+    }
+
+    /* Restore parity control register */
+    adcREG1->PARCR = adcparcr_bk;
+
+/* USER CODE BEGIN (62) */
+/* USER CODE END */
+}
+
+
+/** @fn void adc2ParityCheck(void)
+*   @brief Routine to check ADC2 RAM parity error detection and signaling mechanism
+*
+*   Routine to check ADC2 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_027 */
+/* DesignId : SELFTEST_DesignId_023 */
+/* Requirements : HL_SR387 */
+void adc2ParityCheck(void)
+{
+    volatile uint32 adcramread = 0U;
+    uint32 adcparcr_bk = adcREG2->PARCR;
+
+/* USER CODE BEGIN (63) */
+/* USER CODE END */
+
+    /* Set the TEST bit in the PARCR and enable parity checking */
+    adcREG2->PARCR = 0x10AU;
+
+    /* Invert the parity bits inside the ADC2 RAM's first location */
+    adcPARRAM2 = ~(adcPARRAM2);
+
+    /* clear the TEST bit */
+    adcREG2->PARCR = 0x00AU;
+
+    /* This read is expected to trigger a parity error */
+    adcramread = adcRAM2;
+
+    /* Check for ESM group1 channel 1 to be flagged */
+    if ((esmREG->SR1[0U] & 0x2U) == 0U)
+    {
+        /* no ADC2 RAM parity error was flagged to ESM */
+        selftestFailNotification(ADC2PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear ADC2 RAM parity error flag */
+        esmREG->SR1[0U] = 0x2U;
+
+        /* Set the TEST bit in the PARCR and enable parity checking */
+        adcREG2->PARCR = 0x10AU;
+
+        /* Revert back the parity bits to correct data */
+        adcPARRAM2 = ~(adcPARRAM2);
+    }
+
+    /* Restore parity control register*/
+    adcREG2->PARCR = adcparcr_bk;
+
+/* USER CODE BEGIN (64) */
+/* USER CODE END */
+}
+
+/** @fn void can1ParityCheck(void)
+*   @brief Routine to check CAN1 RAM parity error detection and signaling mechanism
+*
+*   Routine to check CAN1 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_028 */
+/* DesignId : SELFTEST_DesignId_026 */
+/* Requirements : HL_SR393 */
+void can1ParityCheck(void)
+{
+    volatile uint32 canread = 0U;
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    uint32 canctl_bk =  canREG1->CTL;
+
+/* USER CODE BEGIN (65) */
+/* USER CODE END */
+
+    /* Disable parity, init mode, TEST mode */
+    canREG1->CTL = 0x00001481U;
+
+    /* Enable RAM Direct Access mode */
+    canREG1->TEST = 0x00000200U;
+
+    /* flip the parity bit */
+    canPARRAM1 ^= 0x00001000U;
+
+    /* Enable parity, disable init, still TEST mode */
+    canREG1->CTL = 0x00002880U;
+
+    /* Read location with parity error */
+    canread = canRAM1;
+
+    /* check if ESM group1 channel 21 is flagged */
+    if ((esmREG->SR1[0U] & 0x00200000U) == 0U)
+    {
+        /* No DCAN1 RAM parity error was flagged to ESM */
+        selftestFailNotification(CAN1PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear ESM group1 channel 21 flag */
+        esmREG->SR1[0U] = 0x00200000U;
+
+        /* Disable parity, init mode, TEST mode */
+        canREG1->CTL = 0x00001481U;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        canPARRAM1 ^= 0x00001000U;
+    }
+
+    /* Disable RAM Direct Access mode */
+    canREG1->TEST = 0x00000000U;
+
+    /* Restore CTL register */
+    canREG1->CTL = canctl_bk;
+
+    /* Read Error and Status register to clear Parity Error bit */
+    canread = canREG1->ES;
+
+/* USER CODE BEGIN (66) */
+/* USER CODE END */
+}
+
+
+/** @fn void can2ParityCheck(void)
+*   @brief Routine to check CAN2 RAM parity error detection and signaling mechanism
+*
+*   Routine to check CAN2 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_029 */
+/* DesignId : SELFTEST_DesignId_026 */
+/* Requirements : HL_SR393 */
+void can2ParityCheck(void)
+{
+    volatile uint32 canread = 0U;
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    uint32 canctl_bk = canREG2->CTL;
+
+/* USER CODE BEGIN (67) */
+/* USER CODE END */
+
+    /* Disable parity, init mode, TEST mode */
+    canREG2->CTL = 0x00001481U;
+
+    /* Enable RAM Direct Access mode */
+    canREG2->TEST = 0x00000200U;
+
+    /* flip the parity bit */
+    canPARRAM2 ^= 0x00001000U;
+
+    /* Enable parity, disable init, still TEST mode */
+    canREG2->CTL = 0x00002880U;
+
+    /* Read location with parity error */
+    canread = canRAM2;
+
+    /* check if ESM group1 channel 23 is flagged */
+    if ((esmREG->SR1[0U] & 0x00800000U) == 0U)
+    {
+        /* No DCAN2 RAM parity error was flagged to ESM */
+        selftestFailNotification(CAN2PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear ESM group1 channel 23 flag */
+        esmREG->SR1[0U] = 0x00800000U;
+
+        /* Disable parity, init mode, TEST mode */
+        canREG2->CTL = 0x00001481U;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        canPARRAM2 ^= 0x00001000U;
+    }
+
+    /* Disable RAM Direct Access mode */
+    canREG2->TEST = 0x00000000U;
+
+    /* disable TEST mode */
+    canREG2->CTL = canctl_bk;
+
+    /* Read Error and Status register to clear Parity Error bit */
+    canread = canREG2->ES;
+
+/* USER CODE BEGIN (68) */
+/* USER CODE END */
+}
+
+
+/** @fn void can3ParityCheck(void)
+*   @brief Routine to check CAN3 RAM parity error detection and signaling mechanism
+*
+*   Routine to check CAN3 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_030 */
+/* DesignId : SELFTEST_DesignId_026 */
+/* Requirements : HL_SR393 */
+void can3ParityCheck(void)
+{
+    volatile uint32 canread = 0U;
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    uint32 canctl_bk = canREG3->CTL;
+
+/* USER CODE BEGIN (69) */
+/* USER CODE END */
+
+    /* Disable parity, init mode, TEST mode */
+    canREG3->CTL = 0x00001481U;
+
+    /* Enable RAM Direct Access mode */
+    canREG3->TEST = 0x00000200U;
+
+    /* flip the parity bit */
+    canPARRAM3 ^= 0x00001000U;
+
+    /* Enable parity, disable init, still TEST mode */
+    canREG3->CTL = 0x00002880U;
+
+    /* Read location with parity error */
+    canread = canRAM3;
+
+    /* check if ESM group1 channel 22 is flagged */
+    if ((esmREG->SR1[0U] & 0x00400000U) == 0U)
+    {
+        /* No DCAN3 RAM parity error was flagged to ESM */
+        selftestFailNotification(CAN3PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear ESM group1 channel 22 flag */
+        esmREG->SR1[0U] = 0x00400000U;
+
+        /* Disable parity, init mode, TEST mode */
+        canREG3->CTL = 0x00001481U;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        canPARRAM3 ^= 0x00001000U;
+    }
+
+    /* Disable RAM Direct Access mode */
+    canREG3->TEST = 0x00000000U;
+
+    /* disable TEST mode */
+    canREG3->CTL = canctl_bk;
+
+    /* Read Error and Status register to clear Parity Error bit */
+    canread = canREG3->ES;
+
+/* USER CODE BEGIN (70) */
+/* USER CODE END */
+}
+
+
+/** @fn void mibspi1ParityCheck(void)
+*   @brief Routine to check MIBSPI1 RAM parity error detection and signaling mechanism
+*
+*   Routine to check MIBSPI1 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_031 */
+/* DesignId : SELFTEST_DesignId_027 */
+/* Requirements : HL_SR386 */
+void mibspi1ParityCheck(void)
+{
+    volatile uint32 spiread = 0U;
+    uint32 mibspie_bk = mibspiREG1->MIBSPIE;
+    uint32 mibspictl_bk = mibspiREG1->UERRCTRL;
+
+/* USER CODE BEGIN (71) */
+/* USER CODE END */
+
+    /* enable multi-buffered mode */
+    mibspiREG1->MIBSPIE = 0x1U;
+
+    /* enable parity error detection */
+    mibspiREG1->UERRCTRL = (mibspiREG1->UERRCTRL & 0xFFFFFFF0U) | (0xAU);
+
+    /* enable parity test mode */
+    mibspiREG1->UERRCTRL |= 0x00000100U;
+
+    /* flip bit 0 of the parity location */
+    mibspiPARRAM1 ^= 0x1U;
+
+    /* disable parity test mode */
+    mibspiREG1->UERRCTRL &= 0xFFFFFEFFU;
+
+    /* read from MibSPI1 RAM to cause parity error */
+    spiread = MIBSPI1RAMLOC;
+
+    /* check if ESM group1 channel 17 is flagged */
+    if ((esmREG->SR1[0U] & 0x20000U) == 0U)
+    {
+        /* No MibSPI1 RAM parity error was flagged to ESM. */
+        selftestFailNotification(MIBSPI1PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear parity error flags */
+        mibspiREG1->UERRSTAT = 0x3U;
+
+        /* clear ESM group1 channel 17 flag */
+        esmREG->SR1[0U] = 0x20000U;
+
+        /* enable parity test mode */
+        mibspiREG1->UERRCTRL |= 0x00000100U;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        mibspiPARRAM1 ^= 0x1U;
+    }
+
+    /* Restore MIBSPI control registers */
+    mibspiREG1->UERRCTRL = mibspictl_bk;
+    mibspiREG1->MIBSPIE = mibspie_bk;
+
+/* USER CODE BEGIN (72) */
+/* USER CODE END */
+}
+
+/** @fn void mibspi3ParityCheck(void)
+*   @brief Routine to check MIBSPI3 RAM parity error detection and signaling mechanism
+*
+*   Routine to check MIBSPI3 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_032 */
+/* DesignId : SELFTEST_DesignId_027 */
+/* Requirements : HL_SR386 */
+void mibspi3ParityCheck(void)
+{
+    volatile uint32 spiread = 0U;
+    uint32 mibspie_bk = mibspiREG3->MIBSPIE;
+    uint32 mibspictl_bk = mibspiREG3->UERRCTRL;
+
+/* USER CODE BEGIN (73) */
+/* USER CODE END */
+
+    /* enable multi-buffered mode */
+    mibspiREG3->MIBSPIE = 0x1U;
+
+    /* enable parity test mode */
+    mibspiREG3->UERRCTRL |= 0x00000100U;
+
+    /* flip bit 0 of the parity location */
+    mibspiPARRAM3 ^= 0x1U;
+
+    /* enable parity error detection */
+    mibspiREG3->UERRCTRL = (mibspiREG3->UERRCTRL & 0xFFFFFFF0U) | (0xAU);
+
+    /* disable parity test mode */
+    mibspiREG3->UERRCTRL &= 0xFFFFFEFFU;
+
+    /* read from MibSPI3 RAM to cause parity error */
+    spiread = MIBSPI3RAMLOC;
+
+    /* check if ESM group1 channel 18 is flagged */
+    if ((esmREG->SR1[0U] & 0x40000U) == 0U)
+    {
+        /* No MibSPI3 RAM parity error was flagged to ESM. */
+        selftestFailNotification(MIBSPI3PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear parity error flags */
+        mibspiREG3->UERRSTAT = 0x3U;
+
+        /* clear ESM group1 channel 18 flag */
+        esmREG->SR1[0U] = 0x40000U;
+
+        /* enable parity test mode */
+        mibspiREG3->UERRCTRL |= 0x00000100U;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        mibspiPARRAM3 ^= 0x1U;
+    }
+
+    /* Restore MIBSPI control registers */
+    mibspiREG3->UERRCTRL = mibspictl_bk;
+    mibspiREG3->MIBSPIE = mibspie_bk;
+
+/* USER CODE BEGIN (74) */
+/* USER CODE END */
+}
+
+/** @fn void mibspi5ParityCheck(void)
+*   @brief Routine to check MIBSPI5 RAM parity error detection and signaling mechanism
+*
+*   Routine to check MIBSPI5 RAM parity error detection and signaling mechanism
+*/
+/* SourceId : SELFTEST_SourceId_033 */
+/* DesignId : SELFTEST_DesignId_027 */
+/* Requirements : HL_SR386 */
+void mibspi5ParityCheck(void)
+{
+    volatile uint32 spiread = 0U;
+    uint32 mibspie_bk = mibspiREG5->MIBSPIE;
+    uint32 mibspictl_bk = mibspiREG5->UERRCTRL;
+
+/* USER CODE BEGIN (75) */
+/* USER CODE END */
+
+    /* enable multi-buffered mode */
+    mibspiREG5->MIBSPIE = 0x1U;
+
+    /* enable parity test mode */
+    mibspiREG5->UERRCTRL |= 0x00000100U;
+
+    /* flip bit 0 of the parity location */
+    mibspiPARRAM5 ^= 0x1U;
+
+    /* enable parity error detection */
+    mibspiREG5->UERRCTRL = (mibspiREG5->UERRCTRL & 0xFFFFFFF0U) | (0xAU);
+
+    /* disable parity test mode */
+    mibspiREG5->UERRCTRL &= 0xFFFFFEFFU;
+
+    /* read from MibSPI5 RAM to cause parity error */
+    spiread = MIBSPI5RAMLOC;
+
+    /* check if ESM group1 channel 24 is flagged */
+    if ((esmREG->SR1[0U] & 0x01000000U) == 0U)
+    {
+        /* No MibSPI5 RAM parity error was flagged to ESM. */
+        selftestFailNotification(MIBSPI5PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear parity error flags */
+        mibspiREG5->UERRSTAT = 0x3U;
+
+        /* clear ESM group1 channel 24 flag */
+        esmREG->SR1[0U] = 0x01000000U;
+
+        /* enable parity test mode */
+        mibspiREG5->UERRCTRL |= 0x00000100U;
+
+        /* Revert back to correct data, flip bit 0 of the parity location */
+        mibspiPARRAM5 ^= 0x1U;
+    }
+
+    /* Restore MIBSPI control registers */
+    mibspiREG5->UERRCTRL = mibspictl_bk;
+    mibspiREG5->MIBSPIE = mibspie_bk;
+
+/* USER CODE BEGIN (76) */
+/* USER CODE END */
+}
+
+/** @fn void checkRAMECC(void)
+*   @brief Check TCRAM ECC error detection logic.
+*
+*   This function checks TCRAM ECC error detection logic.
+*/
+/* SourceId : SELFTEST_SourceId_034 */
+/* DesignId : SELFTEST_DesignId_019 */
+/* Requirements : HL_SR408 */
+void checkRAMECC(void)
+{
+    volatile uint64 ramread = 0U;
+	volatile uint32 regread = 0U;
+	uint32 tcram1ErrStat, tcram2ErrStat = 0U;
+	
+    uint64 tcramA1_bk = tcramA1bit;
+    uint64 tcramB1_bk = tcramB1bit;
+    uint64 tcramA2_bk = tcramA2bit;
+    uint64 tcramB2_bk = tcramB2bit;
+
+    /* Clear RAMOCUUR before setting RAMTHRESHOLD register */
+    tcram1REG->RAMOCCUR = 0U;
+    tcram2REG->RAMOCCUR = 0U;
+
+    /* Set Single-bit Error Threshold Count as 1 */
+    tcram1REG->RAMTHRESHOLD = 1U;
+    tcram2REG->RAMTHRESHOLD = 1U;
+
+    /* Enable single bit error generation */
+    tcram1REG->RAMINTCTRL = 1U;
+    tcram2REG->RAMINTCTRL = 1U;
+
+    /* Enable writes to ECC RAM, enable ECC error response */
+    tcram1REG->RAMCTRL = 0x0005010AU;
+    tcram2REG->RAMCTRL = 0x0005010AU;
+
+    /* Force a single bit error in both the banks */
+    _coreDisableRamEcc_();
+    tcramA1bitError ^= 1U;
+    tcramB1bitError ^= 1U;
+    _coreEnableRamEcc_();
+
+    /* Read the corrupted data to generate single bit error */
+    ramread = tcramA1bit;
+    ramread = tcramB1bit;
+
+	/* Check for error status */
+	tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x1U;
+	tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x1U;
+	/*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
+	/*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
+    if((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U))
+    {
+        /* TCRAM module does not reflect 1-bit error reported by CPU */
+        selftestFailNotification(CHECKRAMECC_FAIL1);
+    }
+    else
+    {
+        if((esmREG->SR1[0U] & 0x14000000U) != 0x14000000U)
+        {
+            /* TCRAM 1-bit error not flagged in ESM */
+            selftestFailNotification(CHECKRAMECC_FAIL2);
+        }
+        else
+        {
+            /* Clear single bit error flag in TCRAM module */
+            tcram1REG->RAMERRSTATUS = 0x1U;
+            tcram2REG->RAMERRSTATUS = 0x1U;
+
+            /* Clear ESM status */
+            esmREG->SR1[0U] = 0x14000000U;
+        }
+    }
+
+    /* Force a double bit error in both the banks */
+    _coreDisableRamEcc_();
+    tcramA2bitError ^= 3U;
+    tcramB2bitError ^= 3U;
+    _coreEnableRamEcc_();
+
+    /* Read the corrupted data to generate double bit error */
+    ramread = tcramA2bit;
+    ramread = tcramB2bit;
+
+    regread = tcram1REG->RAMUERRADDR;
+    regread = tcram2REG->RAMUERRADDR;
+
+    /* disable writes to ECC RAM */
+    tcram1REG->RAMCTRL = 0x0005000AU;
+    tcram2REG->RAMCTRL = 0x0005000AU;
+
+    /* Compute correct ECC */
+    tcramA1bit = tcramA1_bk;
+    tcramB1bit = tcramB1_bk;
+    tcramA2bit = tcramA2_bk;
+    tcramB2bit = tcramB2_bk;
+}
+
+/** @fn void checkClockMonitor(void)
+*   @brief Check clock monitor failure detection logic.
+*
+*   This function checks clock monitor failure detection logic.
+*/
+/* SourceId : SELFTEST_SourceId_035 */
+/* DesignId : SELFTEST_DesignId_028 */
+/* Requirements : HL_SR394 */
+void checkClockMonitor(void)
+{
+    uint32 ghvsrc_bk;
+
+    /* Enable clock monitor range detection circuitry */
+    systemREG1->CLKTEST |= 0x03000000U;
+
+    /* Backup register GHVSRC */
+    ghvsrc_bk = systemREG1->GHVSRC;
+
+    /* Switch all clock domains to HF LPO */
+    systemREG1->GHVSRC = 0x05050005U;
+
+    /* Disable oscillator to cause a oscillator fail */
+    systemREG1->CSDISSET = 0x1U;
+
+    /* Wait till oscillator fail flag is set */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while((systemREG1->GBLSTAT & 0x1U) == 0U)
+    {
+    } /* Wait */
+
+    if((esmREG->SR1[0U] & 0x800U) != 0x800U)
+    {
+        selftestFailNotification(CHECKCLOCKMONITOR_FAIL1);
+    }
+    else
+    {
+        /* Clear ESM flag */
+        esmREG->SR1[0U] = 0x800U;
+
+        /* Disable clock monitor range detection circuitry */
+        systemREG1->CLKTEST &= ~(0x03000000U);
+
+        /* Enable oscillator */
+        systemREG1->CSDISCLR = 0x1U;
+
+        /* Wait until oscillator is enabled */
+        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+        while((systemREG1->CSVSTAT & 0x3U) == 0U)
+        {
+        } /* Wait */
+
+        /* Clear oscillator fail flag and PLL slip flag if any*/
+        systemREG1->GBLSTAT = 0x301U;
+
+        /* Switch back all clock domains */
+        systemREG1->GHVSRC = ghvsrc_bk;
+    }
+}
+
+/** @fn void checkFlashEEPROMECC(void)
+*   @brief Check Flash EEPROM ECC error detection logic.
+*
+*   This function checks Flash EEPROM ECC error detection logic.
+*/
+/* SourceId : SELFTEST_SourceId_036 */
+/* DesignId : SELFTEST_DesignId_029 */
+/* Requirements : HL_SR406 */
+void checkFlashEEPROMECC(void)
+{
+    uint32 ecc;
+    volatile uint32 regread;
+
+    /* Set Single Error Correction Threshold as 1 */
+    flashWREG->EECTRL2 |= 1U;
+
+    /* Enable EEPROM Emulation Error Profiling */
+    flashWREG->EECTRL1 |= 0x00000100U;
+
+    /* Load FEMU_XX regs in order to generate ECC */
+    flashWREG->FEMUADDR = 0xF0200000U;
+    flashWREG->FEMUDMSW = 0U;
+    flashWREG->FEMUDLSW = 0U;
+
+    /* ECC for the correct data*/
+    ecc = flashWREG->FEMUECC;
+
+    /* Load data with 1 bit error */
+    flashWREG->FEMUDMSW = 0U;
+    flashWREG->FEMUDLSW = 1U;
+
+    /* Enable Diagnostic ECC data correction mode and select FEE SECDED for diagnostic testing */
+    flashWREG->FDIAGCTRL = 0x00055001U;
+
+    flashWREG->FEMUECC = ecc;
+
+    /* Diagnostic trigger */
+    flashWREG->FDIAGCTRL |= 0x01000000U;
+
+    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+    if((flashWREG->EESTATUS & 0x1U) != 0x1U)
+    {
+        /* No single bit error was detected */
+        selftestFailNotification(CHECKFLASHEEPROMECC_FAIL1);
+    }
+    else
+    {
+        if((esmREG->SR4[0U] & 0x8U) != 0x8U)
+        {
+            /* EEPROM single bit error not captured in ESM */
+            selftestFailNotification(CHECKFLASHEEPROMECC_FAIL2);
+        }
+        else
+        {
+            /* Clear single bit error flag in flash wrapper */
+            flashWREG->EESTATUS = 0xFU;
+
+            /* Clear ESM flag */
+            esmREG->SR4[0U] = 0x8U;
+        }
+    }
+
+    /* Load data with 2 bit error */
+    flashWREG->FEMUDMSW = 0U;
+    flashWREG->FEMUDLSW = 3U;
+
+    /* Enable Diagnostic ECC data correction mode and select FEE SECDED for diagnostic testing */
+    flashWREG->FDIAGCTRL = 0x00055001U;
+
+    flashWREG->FEMUECC = ecc;
+
+    /* Diagnostic trigger */
+    flashWREG->FDIAGCTRL |= 0x01000000U;
+
+    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+    if((flashWREG->EESTATUS & 0x100U) != 0x100U)
+    {
+        /* No double bit error was detected */
+        selftestFailNotification(CHECKFLASHEEPROMECC_FAIL3);
+    }
+    else
+    {
+        if((esmREG->SR4[0U] & 0x10U) != 0x10U)
+        {
+            /* EEPROM double bit error not captured in ESM */
+            selftestFailNotification(CHECKFLASHEEPROMECC_FAIL4);
+        }
+        else
+        {
+            /* Clear uncorrectable error flag in flash wrapper */
+            flashWREG->EESTATUS = 0x1100U;
+
+            /* Read EEUNCERRADD register */
+            regread = flashWREG->EEUNCERRADD;
+
+            /* Clear ESM flag */
+            esmREG->SR4[0U] = 0x10U;
+
+
+        }
+    }
+}
+
+/** @fn void checkPLL1Slip(void)
+*   @brief Check PLL1 Slip detection logic.
+*
+*   This function checks PLL1 Slip detection logic.
+*/
+/* SourceId : SELFTEST_SourceId_037 */
+/* DesignId : SELFTEST_DesignId_030 */
+/* Requirements : HL_SR384 */
+void checkPLL1Slip(void)
+{
+    uint32 ghvsrc_bk, pllctl1_bk;
+
+    /* Back up the the registers GHVSRC and PLLCTRL1 */
+    ghvsrc_bk = systemREG1->GHVSRC;
+    pllctl1_bk = systemREG1->PLLCTL1;
+
+    /* Switch all clock domains to oscillator */
+    systemREG1->GHVSRC = 0x00000000U;
+
+    /* Disable Reset on PLL Slip and enable Bypass on PLL slip */
+    systemREG1->PLLCTL1 &= 0x1FFFFFFFU;
+
+    /* Force a PLL Slip */
+    systemREG1->PLLCTL1 ^= 0x8000U;
+
+    /* Wait till PLL slip flag is set */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while((systemREG1->GBLSTAT & 0x300U) == 0U)
+    {
+    } /* Wait */
+
+    if((esmREG->SR1[0U] & 0x400U) != 0x400U)
+    {
+        /* ESM flag not set */
+        selftestFailNotification(CHECKPLL1SLIP_FAIL1);
+    }
+    else
+    {
+        /* Disable PLL1 */
+        systemREG1->CSDISSET = 0x2U;
+
+        /* Wait till PLL1 is disabled */
+        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+        while((systemREG1->CSDIS & 0x2U) == 0U)
+        {
+        } /* Wait */
+
+        /* Restore the PLL multiplier value */
+        systemREG1->PLLCTL1 ^= 0x8000U;
+
+        /* Enable PLL1 */
+        systemREG1->CSDISCLR = 0x2U;
+
+        /* Wait till PLL1 is disabled */
+        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+        while((systemREG1->CSDIS & 0x2U) != 0U)
+        {
+        } /* Wait */
+
+        /* Switch back to the initial clock source */
+        systemREG1->GHVSRC = ghvsrc_bk;
+
+        /* Clear PLL slip flag */
+        systemREG1->GBLSTAT = 0x300U;
+
+        /* Clear ESM flag */
+        esmREG->SR1[0U] = 0x400U;
+
+        /* Restore the PLLCTL1 register */
+        systemREG1->PLLCTL1 = pllctl1_bk;
+    }
+}
+
+/** @fn void checkPLL2Slip(void)
+*   @brief Check PLL2 Slip detection logic.
+*
+*   This function checks PLL2 Slip detection logic.
+*/
+/* SourceId : SELFTEST_SourceId_038 */
+/* DesignId : SELFTEST_DesignId_031 */
+/* Requirements : HL_SR384 */
+void checkPLL2Slip(void)
+{
+    uint32 ghvsrc_bk;
+
+    /* Back up the the register GHVSRC */
+    ghvsrc_bk = systemREG1->GHVSRC;
+
+    /* Switch all clock domains to oscillator */
+    systemREG1->GHVSRC = 0x00000000U;
+	
+    /* Force a PLL2 Slip */
+    systemREG2->PLLCTL3 ^= 0x8000U;
+
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while((esmREG->SR4[0U] & 0x400U) != 0x400U)
+    {
+        /* Wait till ESM flag is set */
+    }
+
+    /* Disable PLL2 */
+    systemREG1->CSDISSET = 0x40U;
+
+    /* Wait till PLL2 is disabled */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while((systemREG1->CSDIS & 0x40U) == 0U)
+    {
+    } /* Wait */
+
+    /* Restore the PLL 2 multiplier value */
+    systemREG2->PLLCTL3 ^= 0x8000U;
+
+    /* Enable PLL2 */
+    systemREG1->CSDISCLR = 0x40U;
+
+    /* Wait till PLL2 is disabled */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while((systemREG1->CSDIS & 0x40U) != 0U)
+    {
+    } /* Wait */
+
+    /* Switch back to the initial clock source */
+    systemREG1->GHVSRC = ghvsrc_bk;
+
+    /* Clear PLL slip flag */
+    systemREG1->GBLSTAT = 0x300U;
+
+    /* Clear ESM flag */
+    esmREG->SR4[0U] = 0x400U;
+}
+
+
+/** @fn void checkRAMAddrParity(void)
+*   @brief Check TCRAM Address parity error detection and signaling mechanism.
+*
+*   This function TCRAM Address parity error detection and signaling mechanism.
+*/
+/* SourceId : SELFTEST_SourceId_039 */
+/* DesignId : SELFTEST_DesignId_032 */
+/* Requirements : HL_SR409 */
+void checkRAMAddrParity(void)
+{
+    register uint64 ramread;
+	volatile uint32 regread;
+	uint32 tcram1ErrStat, tcram2ErrStat;
+	
+    /* Invert Address parity scheme */
+    tcram1REG->RAMCTRL = 0x0D05000AU;
+    tcram2REG->RAMCTRL = 0x0D05000AU;
+
+    /* Read from both RAM banks */
+    ramread = tcramA1bit;
+    ramread = ramread | tcramB1bit; /* XOR-ing with ramread to avoid warnings */
+
+    /* Switch back to Address parity scheme */
+    tcram1REG->RAMCTRL = 0x0005000AU;
+    tcram2REG->RAMCTRL = 0x0005000AU;
+
+	/* Check for error status */
+	tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x100U;
+	tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x100U;
+	/*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
+	/*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
+    if((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U))
+    {
+        /* No Address parity error detected */
+        selftestFailNotification(CHECKRAMADDRPARITY_FAIL1);
+    }
+    else
+    {
+        if((esmREG->SR1[1U] & 0x1400U) != 0x1400U)
+        {
+            /* Address parity error not reported to ESM */
+            selftestFailNotification(CHECKRAMADDRPARITY_FAIL2);
+        }
+        else
+        {
+            /* Clear Address parity error flag */
+            tcram1REG->RAMERRSTATUS = 0x300U;
+            tcram2REG->RAMERRSTATUS = 0x300U;
+
+            /* Clear ESM flag */
+            esmREG->SR1[1U] = 0x1400U;
+
+            /* The nERROR pin will become inactive once the LTC counter expires */
+            esmREG->EKR = 0x5U;
+
+            regread = tcram1REG->RAMPERADDR;
+            regread = tcram2REG->RAMPERADDR;
+        }
+    }
+}
+
+/** @fn void checkRAMUERRTest(void)
+*   @brief Run RAM test
+*
+*   This function runs RAM test to test the redundant address decode and compare logic.
+*/
+/* SourceId : SELFTEST_SourceId_040 */
+/* DesignId : SELFTEST_DesignId_033 */
+/* Requirements : HL_SR410 */
+void checkRAMUERRTest(void)
+{
+    uint32 tcram1ErrStat, tcram2ErrStat = 0U;
+
+    /* Trigger equality check */
+    tcram1REG->RAMTEST = 0x018AU;
+    tcram2REG->RAMTEST = 0x018AU;
+
+    /* Wait till test is completed */
+    while(tcram1REG->RAMTEST != 0x008AU)
+    {
+    } /* Wait */
+    while(tcram2REG->RAMTEST != 0x008AU)
+    {
+    } /* Wait */
+
+    /* Check for error status */
+    tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x10U;
+    tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x10U;
+    if((tcram1ErrStat == 0x10U) || (tcram2ErrStat == 0x10U))
+    {
+        /* test failed */
+        selftestFailNotification(CHECKRAMUERRTEST_FAIL1);
+    }
+
+    /* Trigger inequality check */
+    tcram1REG->RAMTEST = 0x014AU;
+    tcram2REG->RAMTEST = 0x014AU;
+
+    /* Wait till test is completed */
+    while(tcram1REG->RAMTEST != 0x004AU)
+    {
+    }/* Wait */
+    while(tcram2REG->RAMTEST != 0x004AU)
+    {
+    }/* Wait */
+
+    tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x10U;
+    tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x10U;
+    if((tcram1ErrStat == 0x10U) || (tcram2ErrStat == 0x10U))
+    {
+        /* test failed */
+        selftestFailNotification(CHECKRAMUERRTEST_FAIL2);
+    }
+    else
+    {
+        tcram1REG->RAMERRSTATUS = 0x4U;
+        tcram2REG->RAMERRSTATUS = 0x4U;
+
+        /* Clear ESM flag */
+        esmREG->SR1[1U] = 0x140U;
+        esmREG->SSR2 = 0x140U;
+        esmREG->EKR = 0x5U;
+    }
+
+    /* Disable RAM test mode */
+    tcram1REG->RAMTEST = 0x5U;
+    tcram2REG->RAMTEST = 0x5U;
+}
+
+/* SourceId : SELFTEST_SourceId_041 */
+/* DesignId : SELFTEST_DesignId_018 */
+/* Requirements : HL_SR407 */
+void fmcBus1ParityCheck(void)
+{
+    uint32 regBkupFparOvr,regBckupFdiagctrl;
+    volatile uint32 flashread = 0U;
+
+    /* Backup registers */
+    regBkupFparOvr = flashWREG->FPAROVR;
+    regBckupFdiagctrl = flashWREG->FDIAGCTRL;
+
+    /* Read to unfreeze the error address registers */
+    flashread = flashWREG->FUNCERRADD;
+
+    /* clear status register */
+    flashWREG->FEDACSTATUS = 0x400U;
+
+    /* Enable Parity Error */
+    flashWREG->FPAROVR  = (uint32)((uint32)0x5U << 9U)
+	                    | (uint32)((uint32)0x5U << 12U);
+
+    /* set Diag test mode */
+    flashWREG->FDIAGCTRL = 0x00050000U | 0x00000007U;
+
+    /* Add parity */
+    flashWREG->FPAROVR |= 0x00000100U;
+
+    /* Start Test */
+    flashWREG->FDIAGCTRL |= 0x1000000U;
+
+    /* Wait until test done */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+    while((flashWREG->FDIAGCTRL & 0x1000000U) == 0x1000000U)
+    {
+    }/* Wait */
+
+    /* Check address Error */
+    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+    if((flashWREG->FEDACSTATUS & 0x400U) != 0x400U)
+    {
+        selftestFailNotification(FMCBUS1PARITYCHECK_FAIL1);
+    }
+    else
+    {
+        /* clear status register */
+        flashWREG->FEDACSTATUS = 0x400U;
+
+        /* check if ESM is flagged */
+        /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+        if((esmREG->SR1[1U] & 0x0000010U) == 0U)
+        {
+            selftestFailNotification(FMCBUS1PARITYCHECK_FAIL2);
+        }
+        else
+        {
+            /* clear ESM flag */
+            esmREG->SR1[1U] |= 0x0000010U;
+            esmREG->SSR2 |= 0x0000010U;
+            esmREG->EKR = 0x5U;
+
+            /* Stop Diag test mode */
+            flashWREG->FDIAGCTRL = regBckupFdiagctrl;
+            flashWREG->FPAROVR     = regBkupFparOvr;
+        }
+    }
+
+    /* Read to unfreeze the error address registers */
+    flashread = flashWREG->FUNCERRADD;
+}
+
+/* SourceId : SELFTEST_SourceId_042 */
+/* DesignId : SELFTEST_DesignId_011 */
+/* Requirements : HL_SR401 */
+void pbistFail(void)
+{
+    uint32 PBIST_RAMT, PBIST_FSRA0, PBIST_FSRDL0;
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    PBIST_RAMT = pbistREG->RAMT;
+    PBIST_FSRA0 = pbistREG->FSRA0;
+    PBIST_FSRDL0 = pbistREG->FSRDL0;
+
+    if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE)
+    {
+        memoryPort0TestFailNotification((uint32)((PBIST_RAMT & 0xFF000000U) >> 24U), (uint32)((PBIST_RAMT & 0x00FF0000U) >> 16U),(uint32)PBIST_FSRA0, (uint32)PBIST_FSRDL0);
+    }
+    else
+    {
+/* USER CODE BEGIN (77) */
+/* USER CODE END */
+/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+        for(;;)
+        {
+        }/* Wait */
+
+/* USER CODE BEGIN (78) */
+/* USER CODE END */
+    }
+}
+
+/** @fn void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*    @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*    @param[in] type:     whether initial or current value of the configuration registers need to be stored
+*                        - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*                        - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : SELFTEST_SourceId_043 */
+/* DesignId : SELFTEST_DesignId_034 */
+/* Requirements : HL_SR506 */
+void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_RAMT = PBIST_RAMT_CONFIGVALUE;
+        config_reg->CONFIG_DLR = PBIST_DLR_CONFIGVALUE;
+        config_reg->CONFIG_PACT = PBIST_PACT_CONFIGVALUE;
+        config_reg->CONFIG_PBISTID = PBIST_PBISTID_CONFIGVALUE;
+        config_reg->CONFIG_OVER = PBIST_OVER_CONFIGVALUE;
+        config_reg->CONFIG_FSRDL1 = PBIST_FSRDL1_CONFIGVALUE;
+        config_reg->CONFIG_ROM = PBIST_ROM_CONFIGVALUE;
+        config_reg->CONFIG_ALGO = PBIST_ALGO_CONFIGVALUE;
+        config_reg->CONFIG_RINFOL = PBIST_RINFOL_CONFIGVALUE;
+        config_reg->CONFIG_RINFOU = PBIST_RINFOU_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_RAMT = pbistREG->RAMT;
+        config_reg->CONFIG_DLR = pbistREG->DLR;
+        config_reg->CONFIG_PACT = pbistREG->PACT;
+        config_reg->CONFIG_PBISTID = pbistREG->PBISTID;
+        config_reg->CONFIG_OVER = pbistREG->OVER;
+        config_reg->CONFIG_FSRDL1 = pbistREG->FSRDL1;
+        config_reg->CONFIG_ROM = pbistREG->ROM;
+        config_reg->CONFIG_ALGO = pbistREG->ALGO;
+        config_reg->CONFIG_RINFOL = pbistREG->RINFOL;
+        config_reg->CONFIG_RINFOU = pbistREG->RINFOU;
+    }
+}
+
+/** @fn void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*    @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*    @param[in] type:     whether initial or current value of the configuration registers need to be stored
+*                        - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*                        - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : SELFTEST_SourceId_044 */
+/* DesignId : SELFTEST_DesignId_035 */
+/* Requirements : HL_SR506 */
+void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_STCGCR0 = STC_STCGCR0_CONFIGVALUE;
+        config_reg->CONFIG_STCGCR1 = STC_STCGCR1_CONFIGVALUE;
+        config_reg->CONFIG_STCTPR = STC_STCTPR_CONFIGVALUE;
+        config_reg->CONFIG_STCSCSCR = STC_STCSCSCR_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_STCGCR0 = stcREG->STCGCR0;
+        config_reg->CONFIG_STCGCR1 = stcREG->STCGCR1;
+        config_reg->CONFIG_STCTPR = stcREG->STCTPR;
+        config_reg->CONFIG_STCSCSCR = stcREG->STCSCSCR;
+    }
+}
+
+
+/** @fn void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*    @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*    @param[in] type:     whether initial or current value of the configuration registers need to be stored
+*                        - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*                        - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : SELFTEST_SourceId_045 */
+/* DesignId : SELFTEST_DesignId_036 */
+/* Requirements : HL_SR506 */
+void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_BOUNDARY = EFC_BOUNDARY_CONFIGVALUE;
+        config_reg->CONFIG_PINS = EFC_PINS_CONFIGVALUE;
+        config_reg->CONFIG_SELFTESTCYCLES = EFC_SELFTESTCYCLES_CONFIGVALUE;
+        config_reg->CONFIG_SELFTESTSIGN = EFC_SELFTESTSIGN_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_BOUNDARY = efcREG->BOUNDARY;
+        config_reg->CONFIG_PINS = efcREG->PINS;
+        config_reg->CONFIG_SELFTESTCYCLES = efcREG->SELF_TEST_CYCLES;
+        config_reg->CONFIG_SELFTESTSIGN = efcREG->SELF_TEST_SIGN;
+    }
+}
+
+
+/** @fn void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*    @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*    @param[in] type:     whether initial or current value of the configuration registers need to be stored
+*                        - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*                        - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : SELFTEST_SourceId_046 */
+/* DesignId : SELFTEST_DesignId_037 */
+/* Requirements : HL_SR506 */
+void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_CCMKEYR = CCMR4_CCMKEYR_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_CCMKEYR = CCMKEYR;
+    }
+}
+
+
+/** @fn void errata_PBIST_4(void)
+*   @brief Workaround for the Errata PBIST#4.
+*
+*   This function is workaround for Errata PBIST#4.
+*   This function is designed to initialize the ROMs using the PBIST controller.
+*   The CPU will configure the PBIST controller to test the PBIST ROM and STC ROM.
+*   This function should be called at startup after system init before using the ROMs.
+*
+*   @note : This Function uses register's which are not exposed to users through
+*   TRM , to run custom algorithm. User can use this function as Black box. 
+*
+*/
+void errata_PBIST_4(void)
+{
+    volatile uint32 i = 0U;
+    uint8 ROM_count;
+    sint32 PBIST_wait_done_loop;
+    uint32 pmuCalibration, pmuCount;
+
+    /* PMU calibration */
+    _pmuEnableCountersGlobal_();
+    _pmuResetCounters_();
+    _pmuStartCounters_(pmuCYCLE_COUNTER);
+    _pmuStopCounters_(pmuCYCLE_COUNTER);
+    pmuCalibration=_pmuGetCycleCount_();
+
+    /* ROM_init Setup using special reserved registers as part of errata fix */
+    /* (Only to be used in this function) */
+    *(volatile uint32 *)0xFFFF0400U = 0x0000000AU;
+    *(volatile uint32 *)0xFFFF040CU = 0x0000EE0AU;
+
+    /* Loop for Executing PBIST ROM and STC ROM */
+    for (ROM_count = 0U; ROM_count < 2U; ROM_count++)
+    {
+        PBIST_wait_done_loop = 0;
+    
+        /* Disable PBIST clocks and ROM clock */
+        pbistREG->PACT = 0x0U;
+        
+        /* PBIST Clocks did not disable */
+        if(pbistREG->PACT != 0x0U ) 
+        {
+            selftestFailNotification(PBISTSELFCHECK_FAIL3);
+        }
+        else
+        {
+            /* PBIST ROM clock frequency = HCLK frequency /2 */
+            /* Disable memory self controller */
+            systemREG1->MSTGCR = 0x00000105U;
+            
+            /* Disable Memory Initialization controller */
+            systemREG1->MINITGCR = 0x5U;
+
+            /* Enable memory self controller */
+            systemREG1->MSTGCR = 0x0000010AU;                               
+
+            /* Clear PBIST Done */
+            systemREG1->MSTCGSTAT = 0x1U;
+            
+            /* Enable PBIST controller */
+            systemREG1->MSINENA = 0x1U;
+
+			/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+	        /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */	
+            /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+            for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ }
+
+            /* Enable PBIST clocks and ROM clock */
+            pbistREG->PACT = 0x3U;
+
+            /* CPU control of PBIST */
+            pbistREG->DLR = 0x10U;
+
+            /* Load PBIST ALGO to initialize the ROMs */
+            *(volatile uint32 *)0xFFFFE400U = 0x00000001U;
+            *(volatile uint32 *)0xFFFFE440U = 0x00000025U;
+            *(volatile uint32 *)0xFFFFE404U = 0x62400001U;
+            *(volatile uint32 *)0xFFFFE444U = 0x00000004U;
+            *(volatile uint32 *)0xFFFFE408U = 0x00068003U;
+            *(volatile uint32 *)0xFFFFE448U = 0x00000000U;
+            *(volatile uint32 *)0xFFFFE40CU = 0x00000004U;
+            *(volatile uint32 *)0xFFFFE44CU = 0x00006860U;
+            *(volatile uint32 *)0xFFFFE410U = 0x00000000U;
+            *(volatile uint32 *)0xFFFFE450U = 0x00000001U;
+            *(volatile uint32 *)0xFFFFE540U = 0x000003E8U;
+            *(volatile uint32 *)0xFFFFE550U = 0x00000001U;
+            *(volatile uint32 *)0xFFFFE530U = 0x00000000U;
+            
+			/* SELECT ROM */
+            if (ROM_count == 1U)
+            {   
+                /* SELECT PBIST ROM */          
+                *(volatile uint32 *)0xFFFFE520U = 0x00000002U;
+                *(volatile uint32 *)0xFFFFE524U = 0x00000000U;
+                pbistREG->RAMT                  = 0x01002008U;
+            } 
+            else
+            {               
+                /* SELECT STC ROM */    
+                *(volatile uint32 *)0xFFFFE520U = 0xFFF0007CU;
+                *(volatile uint32 *)0xFFFFE524U = 0x0A63FFFFU;
+                pbistREG->RAMT                  = 0x02002008U;
+            }
+
+            /*  Setup using special reserved registers as part of errata fix */
+            /*      (Only to be used in this function) */
+            pbistREG->rsvd1[4U]    = 1U;
+            pbistREG->rsvd1[0U]    = 3U;
+
+            /* Start PMU counter */
+			_pmuResetCounters_();
+            _pmuStartCounters_(pmuCYCLE_COUNTER);
+
+            /* PBIST_RUN */
+            pbistREG->rsvd1[1U]    = 1U;
+
+            /* wait until memory self-test done is indicated */
+            /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+            while ((systemREG1->MSTCGSTAT & 0x1U) != 0x1U) 
+            {
+            }/* Wait */
+
+			/* Stop PMU counter */
+            _pmuStopCounters_(pmuCYCLE_COUNTER);
+			
+			/* Get CPU cycle count */
+            pmuCount =_pmuGetCycleCount_();
+			
+			/* Calculate PBIST test complete time in ROM Clock */
+			/* 2 - Divide value ( Default is 2 in HALCoGen) */
+			/* 1000 = 0x3E8 - Test Loop count in ROM Algorithm */
+			pmuCount = pmuCount - pmuCalibration;
+            PBIST_wait_done_loop = ((sint32)pmuCount/2) - 1000;
+
+            /* Check PBIST status results (Address, Status, Count, etc...) */
+            if ((pbistREG->FSRA0 | pbistREG->FSRA1 | pbistREG->FSRDL0 | pbistREG->rsvd3 |
+                 pbistREG->FSRDL1 | pbistREG->rsvd4[0U] | pbistREG->rsvd4[1U]) != 0U)
+            {
+                /* PBIST Failure for the Algorithm chosen above */
+                selftestFailNotification(PBISTSELFCHECK_FAIL1);
+            }
+
+            /* Check that the algorithm executed in the expected amount of time. */
+            /* This time is dependent on the ROMCLKDIV selected */
+            if ((PBIST_wait_done_loop <= 20) || (PBIST_wait_done_loop >= 200) )
+            {
+                selftestFailNotification(PBISTSELFCHECK_FAIL2);
+            }
+
+            /* Disable PBIST clocks and ROM clock */
+            pbistREG->PACT = 0x0U;
+
+            /* Disable PBIST */
+            systemREG1->MSTGCR &= 0xFFFFFFF0U;
+            systemREG1->MSTGCR |= 0x5U;
+        }
+    } /* ROM Loop */
+
+    /* ROM restore default setup */
+    /* (must be completed before continuing) */
+    *(volatile uint32 *)0xFFFF040CU = 0x0000AA0AU;
+    *(volatile uint32 *)0xFFFF040CU = 0x0000AA05U;
+	*(volatile uint32 *)0xFFFF0400U = 0x00000005U;
+
+	_pmuDisableCountersGlobal_();
+}
+
+
+/** @fn void enableParity(void)
+*   @brief Enable peripheral RAM parity
+*
+*   This function enables RAM parity for all peripherals for which RAM parity check is enabled.
+*   This function is called before memoryInit in the startup
+*
+*/
+#pragma WEAK(enableParity)
+void enableParity(void)
+{
+    DMA_PARCR = 0xAU;                      /* Enable DMA RAM parity */
+    VIM_PARCTL = 0xAU;                     /* Enable VIM RAM parity */
+    canREG1->CTL = ((uint32)0xAU << 10U) | 1U;    /* Enable CAN1 RAM parity */
+    canREG2->CTL = ((uint32)0xAU << 10U) | 1U;    /* Enable CAN2 RAM parity */
+    canREG3->CTL = ((uint32)0xAU << 10U) | 1U;    /* Enable CAN3 RAM parity */
+    adcREG1->PARCR = 0xAU;                 /* Enable ADC1 RAM parity */
+    adcREG2->PARCR = 0xAU;                 /* Enable ADC2 RAM parity */
+    hetREG1->PCR = 0xAU;                   /* Enable HET1 RAM parity */
+    htuREG1->PCR = 0xAU;                   /* Enable HTU1 RAM parity */
+    hetREG2->PCR = 0xAU;                   /* Enable HET2 RAM parity */
+    htuREG2->PCR = 0xAU;                   /* Enable HTU2 RAM parity */
+}
+
+/** @fn void disableParity(void)
+*   @brief Disable peripheral RAM parity
+*
+*   This function disables RAM parity for all peripherals for which RAM parity check is enabled.
+*   This function is called after memoryInit in the startup
+*
+*/
+#pragma WEAK(disableParity)
+void disableParity(void)
+{
+    DMA_PARCR = 0x5U;                      /* Disable DMA RAM parity */
+    VIM_PARCTL = 0x5U;                     /* Disable VIM RAM parity */
+    canREG1->CTL = ((uint32)0x5U << 10U) | 1U;    /* Disable CAN1 RAM parity */
+    canREG2->CTL = ((uint32)0x5U << 10U) | 1U;    /* Disable CAN2 RAM parity */
+    canREG3->CTL = ((uint32)0x5U << 10U) | 1U;    /* Disable CAN3 RAM parity */
+    adcREG1->PARCR = 0x5U;                 /* Disable ADC1 RAM parity */
+    adcREG2->PARCR = 0x5U;                 /* Disable ADC2 RAM parity */
+    hetREG1->PCR = 0x5U;                   /* Disable HET1 RAM parity */
+    htuREG1->PCR = 0x5U;                   /* Disable HTU1 RAM parity */
+    hetREG2->PCR = 0x5U;                   /* Disable HET2 RAM parity */
+    htuREG2->PCR = 0x5U;                   /* Disable HTU2 RAM parity */
+}
diff --git a/src/arch/rm46l8lp/halcogen/sys_startup.c b/src/arch/rm46l8lp/halcogen/sys_startup.c
new file mode 100644
index 0000000..49f312b
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_startup.c
@@ -0,0 +1,699 @@
+/** @file sys_startup.c 
+*   @brief Startup Source File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file contains:
+*   - Include Files
+*   - Type Definitions
+*   - External Functions
+*   - VIM RAM Setup
+*   - Startup Routine
+*   .
+*   which are relevant for the Startup.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* Include Files */
+
+#include "sys_common.h"
+#include "system.h"
+#include "sys_vim.h"
+#include "sys_core.h"
+#include "sys_selftest.h"
+#include "esm.h"
+#include "mibspi.h"
+
+#include "errata_SSWF021_45.h"
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+/* External Functions */
+/*SAFETYMCUSW 218 S MR:20.2 <APPROVED> "Functions from library" */
+extern void __TI_auto_init(void);
+/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(main should be declared by the user)" */
+extern int main(void);
+/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
+/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(Extern declaration present in the library)" */
+extern void exit(int _status);
+
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+void handlePLLLockFail(void);
+/* Startup Routine */
+void _c_int00(void);
+#define PLL_RETRIES 5U
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+#pragma CODE_STATE(_c_int00, 32)
+#pragma INTERRUPT(_c_int00, RESET)
+#pragma WEAK(_c_int00)
+
+/* SourceId : STARTUP_SourceId_001 */
+/* DesignId : STARTUP_DesignId_001 */
+/* Requirements : HL_SR508 */
+void _c_int00(void)
+{    
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+    /* Initialize Core Registers to avoid CCM Error */
+    _coreInitRegisters_();
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+    /* Initialize Stack Pointers */
+    _coreInitStackPointer_();
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+    /* Enable CPU Event Export */
+    /* This allows the CPU to signal any single-bit or double-bit errors detected
+     * by its ECC logic for accesses to program flash or data RAM.
+     */
+    _coreEnableEventBusExport_();
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+    /* Enable response to ECC errors indicated by CPU for accesses to flash */
+    flashWREG->FEDACCTRL1 = 0x000A060AU;
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+    /* Enable CPU ECC checking for ATCM (flash accesses) */
+    _coreEnableFlashEcc_();
+	
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+        /* Workaround for Errata CORTEXR4 66 */
+        _errata_CORTEXR4_66_();
+    
+        /* Workaround for Errata CORTEXR4 57 */ 
+        _errata_CORTEXR4_57_();
+
+    /* Reset handler: the following instructions read from the system exception status register
+     * to identify the cause of the CPU reset.
+     */
+
+    /* check for power-on reset condition */
+    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+    if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
+    {		
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+        /* Add condition to check whether PLL can be started successfully */
+        if (_errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U)
+        {
+            /* Put system in a safe state */
+			handlePLLLockFail();
+        }
+        /* clear all reset status flags */
+        SYS_EXCEPTION = 0xFFFFU;
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+      /* continue with normal start-up sequence */
+    }
+    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+    else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
+    {
+        /* Reset caused due to oscillator failure.
+        Add user code here to handle oscillator failure */
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+    }
+    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+    else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
+    {
+        /* Reset caused due 
+         *  1) windowed watchdog violation - Add user code here to handle watchdog violation.
+         *  2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
+         */
+        /* Check the WatchDog Status register */
+        if(WATCHDOG_STATUS != 0U)
+        {
+            /* Add user code here to handle watchdog violation. */ 
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+            /* Clear the Watchdog reset flag in Exception Status register */ 
+            SYS_EXCEPTION = WATCHDOG_RESET;
+        
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+        }
+        else
+        {
+            /* Clear the ICEPICK reset flag in Exception Status register */ 
+            SYS_EXCEPTION = ICEPICK_RESET;
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+		}
+    }
+    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+    else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
+    {
+        /* Reset caused due to CPU reset.
+        CPU reset can be caused by CPU self-test completion, or
+        by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+        /* clear all reset status flags */
+        SYS_EXCEPTION = CPU_RESET;
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+    }
+    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+    else if ((SYS_EXCEPTION & SW_RESET) != 0U)
+    {
+        /* Reset caused due to software reset.
+        Add user code to handle software reset. */
+		
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+	}
+    else
+    {
+        /* Reset caused by nRST being driven low externally.
+        Add user code to handle external reset. */
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+	}
+
+    /* Check if there were ESM group3 errors during power-up.
+     * These could occur during eFuse auto-load or during reads from flash OTP
+     * during power-up. Device operation is not reliable and not recommended
+     * in this case.
+     * An ESM group3 error only drives the nERROR pin low. An external circuit
+     * that monitors the nERROR pin must take the appropriate action to ensure that
+     * the system is placed in a safe state, as determined by the application.
+     */
+    if ((esmREG->SR1[2]) != 0U)
+    {
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+    /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+        for(;;)
+        { 
+        }/* Wait */                 
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+    }
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+    /* Initialize System - Clock, Flash settings with Efuse self check */
+    systemInit();
+    
+    /* Workaround for Errata PBIST#4 */
+    errata_PBIST_4();
+	
+    /* Run a diagnostic check on the memory self-test controller.
+     * This function chooses a RAM test algorithm and runs it on an on-chip ROM.
+     * The memory self-test is expected to fail. The function ensures that the PBIST controller
+     * is capable of detecting and indicating a memory self-test failure.
+     */
+    pbistSelfCheck();	
+	
+	/* Run PBIST on STC ROM */
+    pbistRun((uint32)STC_ROM_PBIST_RAM_GROUP,
+             ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
+    
+    /* Wait for PBIST for STC ROM to be completed */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while(pbistIsTestCompleted() != TRUE)
+    { 
+    }/* Wait */ 
+    
+    /* Check if PBIST on STC ROM passed the self-test */
+    if( pbistIsTestPassed() != TRUE)
+    {
+        /* PBIST and STC ROM failed the self-test.
+         * Need custom handler to check the memory failure
+         * and to take the appropriate next step.
+         */
+         
+        pbistFail();
+
+    }   
+	
+    /* Disable PBIST clocks and disable memory self-test mode */
+    pbistStop();
+
+	/* Run PBIST on PBIST ROM */
+    pbistRun((uint32)PBIST_ROM_PBIST_RAM_GROUP,
+             ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
+    
+    /* Wait for PBIST for PBIST ROM to be completed */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while(pbistIsTestCompleted() != TRUE)
+    { 
+    }/* Wait */ 
+    
+    /* Check if PBIST ROM passed the self-test */
+    if( pbistIsTestPassed() != TRUE)
+    {
+        /* PBIST and STC ROM failed the self-test.
+         * Need custom handler to check the memory failure
+         * and to take the appropriate next step.
+         */
+         
+        pbistFail();
+
+    } 
+	
+    /* Disable PBIST clocks and disable memory self-test mode */
+    pbistStop();	
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+    /* Disable RAM ECC before doing PBIST for Main RAM */
+    _coreDisableRamEcc_();
+    
+    /* Run PBIST on CPU RAM.
+     * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
+     * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
+     * device datasheet.
+     */
+    pbistRun(0x00300020U, /* ESRAM Single Port PBIST */
+             (uint32)PBIST_March13N_SP);
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+    /* Wait for PBIST for CPU RAM to be completed */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while(pbistIsTestCompleted() != TRUE)
+    { 
+    }/* Wait */                 
+    
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+    
+    /* Check if CPU RAM passed the self-test */
+    if( pbistIsTestPassed() != TRUE)
+    {
+        /* CPU RAM failed the self-test.
+         * Need custom handler to check the memory failure
+         * and to take the appropriate next step.
+         */
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+         
+        pbistFail();
+        
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+    }
+
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+    /* Disable PBIST clocks and disable memory self-test mode */
+    pbistStop();
+
+    
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+
+
+    /* Initialize CPU RAM.
+     * This function uses the system module's hardware for auto-initialization of memories and their
+     * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
+     * Hence the value 0x1 passed to the function.
+     * This function will initialize the entire CPU RAM and the corresponding ECC locations.
+     */
+    memoryInit(0x1U);
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+    
+    /* Enable ECC checking for TCRAM accesses.
+     * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
+     */
+    _coreEnableRamEcc_();
+
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+
+    /* Start PBIST on all dual-port memories */
+    /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories.
+       PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
+     */
+    pbistRun(  (uint32)0x00000000U    /* EMAC RAM */
+             | (uint32)0x00000000U    /* USB RAM */  
+             | (uint32)0x00000800U    /* DMA RAM */
+             | (uint32)0x00000200U    /* VIM RAM */
+             | (uint32)0x00000040U    /* MIBSPI1 RAM */
+             | (uint32)0x00000080U    /* MIBSPI3 RAM */
+             | (uint32)0x00000100U    /* MIBSPI5 RAM */
+             | (uint32)0x00000004U    /* CAN1 RAM */
+             | (uint32)0x00000008U    /* CAN2 RAM */
+             | (uint32)0x00000010U    /* CAN3 RAM */
+             | (uint32)0x00000400U    /* ADC1 RAM */
+             | (uint32)0x00020000U    /* ADC2 RAM */
+             | (uint32)0x00001000U    /* HET1 RAM */
+             | (uint32)0x00040000U    /* HET2 RAM */
+             | (uint32)0x00002000U    /* HTU1 RAM */
+             | (uint32)0x00080000U    /* HTU2 RAM */
+             | (uint32)0x00000000U    /* RTP RAM */
+             | (uint32)0x00000000U    /* FRAY RAM */
+             ,(uint32) PBIST_March13N_DP);
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+
+    /* Test the CPU ECC mechanism for RAM accesses.
+     * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
+     * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
+     * in the ECC causes a data abort exception. The data abort handler is written to look for
+     * deliberately caused exception and to return the code execution to the instruction
+     * following the one that caused the abort.
+     */
+    checkRAMECC();
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+
+    /* Test the CPU ECC mechanism for Flash accesses.
+     * The checkFlashECC function uses the flash interface module's diagnostic mode 7
+     * to create single-bit and double-bit errors in CPU accesses to the flash. A double-bit
+     * error on reading from flash causes a data abort exception.
+     * The data abort handler is written to look for deliberately caused exception and
+     * to return the code execution to the instruction following the one that was aborted.
+     *
+     */
+    checkFlashECC();
+    flashWREG->FDIAGCTRL = 0x000A0007U;                    /* disable flash diagnostic mode */
+
+/* USER CODE BEGIN (42) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+
+    /* Wait for PBIST for CPU RAM to be completed */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while(pbistIsTestCompleted() != TRUE)
+    { 
+    }/* Wait */                 
+    
+
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+
+    /* Check if CPU RAM passed the self-test */
+    if( pbistIsTestPassed() != TRUE)
+    {
+
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+
+        /* CPU RAM failed the self-test.
+         * Need custom handler to check the memory failure
+         * and to take the appropriate next step.
+         */
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+         
+        pbistFail();
+        
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+    }
+
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+
+    /* Disable PBIST clocks and disable memory self-test mode */
+    pbistStop();
+    
+/* USER CODE BEGIN (55) */
+/* USER CODE END */
+
+    /* Release the MibSPI1 modules from local reset.
+     * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
+     */
+     mibspiREG1->GCR0 = 0x1U;
+     
+    /* Release the MibSPI3 modules from local reset.
+     * This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
+     */
+    mibspiREG3->GCR0 = 0x1U;
+    
+    /* Release the MibSPI5 modules from local reset.
+     * This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
+     */
+    mibspiREG5->GCR0 = 0x1U;
+    
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
+
+    /* Enable parity on selected RAMs */
+    enableParity();
+    
+    /* Initialize all on-chip SRAMs except for MibSPIx RAMs
+     * The MibSPIx modules have their own auto-initialization mechanism which is triggered
+     * as soon as the modules are brought out of local reset.
+     */
+    /* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
+     */
+    /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
+              Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
+     */
+    memoryInit( (uint32)((uint32)1U << 1U)    /* DMA RAM */
+              | (uint32)((uint32)1U << 2U)    /* VIM RAM */
+              | (uint32)((uint32)1U << 5U)    /* CAN1 RAM */
+              | (uint32)((uint32)1U << 6U)    /* CAN2 RAM */
+              | (uint32)((uint32)1U << 10U)   /* CAN3 RAM */
+              | (uint32)((uint32)1U << 8U)    /* ADC1 RAM */
+              | (uint32)((uint32)1U << 14U)   /* ADC2 RAM */
+              | (uint32)((uint32)1U << 3U)    /* HET1 RAM */
+              | (uint32)((uint32)1U << 4U)    /* HTU1 RAM */
+              | (uint32)((uint32)1U << 15U)   /* HET2 RAM */
+              | (uint32)((uint32)1U << 16U)   /* HTU2 RAM */
+              );
+
+    /* Disable parity */
+    disableParity();
+    
+    /* Test the parity protection mechanism for peripheral RAMs
+       NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
+                 Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
+    */
+
+/* USER CODE BEGIN (57) */
+/* USER CODE END */
+     
+    het1ParityCheck();
+    
+/* USER CODE BEGIN (58) */
+/* USER CODE END */
+
+    htu1ParityCheck();
+    
+/* USER CODE BEGIN (59) */
+/* USER CODE END */
+
+    het2ParityCheck();
+    
+/* USER CODE BEGIN (60) */
+/* USER CODE END */
+
+    htu2ParityCheck();
+    
+/* USER CODE BEGIN (61) */
+/* USER CODE END */
+
+    adc1ParityCheck();
+    
+/* USER CODE BEGIN (62) */
+/* USER CODE END */
+
+    adc2ParityCheck();
+    
+/* USER CODE BEGIN (63) */
+/* USER CODE END */
+
+    can1ParityCheck();
+    
+/* USER CODE BEGIN (64) */
+/* USER CODE END */
+
+    can2ParityCheck();
+    
+/* USER CODE BEGIN (65) */
+/* USER CODE END */
+
+    can3ParityCheck();
+    
+/* USER CODE BEGIN (66) */
+/* USER CODE END */
+
+    vimParityCheck();
+    
+/* USER CODE BEGIN (67) */
+/* USER CODE END */
+
+    dmaParityCheck();
+
+
+/* USER CODE BEGIN (68) */
+/* USER CODE END */
+
+/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
+    { 
+    }/* Wait */                 
+    /* wait for MibSPI1 RAM to complete initialization */
+/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
+    { 
+    }/* Wait */                 
+    /* wait for MibSPI3 RAM to complete initialization */ 
+/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
+    { 
+    }/* Wait */                 
+    /* wait for MibSPI5 RAM to complete initialization */
+
+/* USER CODE BEGIN (69) */
+/* USER CODE END */
+
+    mibspi1ParityCheck();
+    
+/* USER CODE BEGIN (70) */
+/* USER CODE END */
+
+    mibspi3ParityCheck();
+    
+/* USER CODE BEGIN (71) */
+/* USER CODE END */
+    
+    mibspi5ParityCheck();
+    
+
+/* USER CODE BEGIN (72) */
+/* USER CODE END */
+    
+    /* Enable IRQ offset via Vic controller */
+    _coreEnableIrqVicOffset_();
+    
+
+/* USER CODE BEGIN (73) */
+/* USER CODE END */
+
+    /* Initialize VIM table */
+    vimInit();    
+
+/* USER CODE BEGIN (74) */
+/* USER CODE END */
+
+    /* Configure system response to error conditions signaled to the ESM group1 */
+    /* This function can be configured from the ESM tab of HALCoGen */
+    esmInit();
+    /* initialize copy table */
+    __TI_auto_init();
+/* USER CODE BEGIN (75) */
+/* USER CODE END */
+    
+    /* call the application */
+/*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
+/*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
+/*SAFETYMCUSW 60 D MR:8.8 <APPROVED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
+    main();
+
+/* USER CODE BEGIN (76) */
+/* USER CODE END */
+/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
+    exit(0);
+
+/* USER CODE BEGIN (77) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (78) */
+/* USER CODE END */
+/** @fn void handlePLLLockFail(void)
+*   @brief This function handles PLL lock fail.
+*/
+void handlePLLLockFail(void)
+{
+/* USER CODE BEGIN (79) */
+/* USER CODE END */
+	while(1)
+	{
+		
+	}
+/* USER CODE BEGIN (80) */
+/* USER CODE END */
+}
+/* USER CODE BEGIN (81) */
+/* USER CODE END */
diff --git a/src/arch/rm46l8lp/halcogen/sys_vim.c b/src/arch/rm46l8lp/halcogen/sys_vim.c
new file mode 100644
index 0000000..ef45422
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/sys_vim.c
@@ -0,0 +1,835 @@
+/** @file sys_vim.c 
+*   @brief VIM Driver Implementation File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#include "sys_vim.h"
+#include "system.h"
+#include "esm.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Vim Ram Definition */
+/** @struct vimRam
+*   @brief Vim Ram Definition
+*
+*   This type is used to access the Vim Ram.
+*/
+/** @typedef vimRAM_t
+*   @brief Vim Ram Type Definition
+*
+*   This type is used to access the Vim Ram.
+*/
+typedef volatile struct vimRam
+{
+    t_isrFuncPTR ISR[VIM_CHANNELS];
+} vimRAM_t;
+
+#define vimRAM ((vimRAM_t *)0xFFF82000U)
+
+static const t_isrFuncPTR s_vim_init[128U] =
+{
+    &phantomInterrupt,
+    &esmHighInterrupt,            /* Channel 0 */
+    &phantomInterrupt,            /* Channel 1 */
+    &rtiCompare0Interrupt,            /* Channel 2 */
+    &rtiCompare1Interrupt,            /* Channel 3 */
+    &rtiCompare2Interrupt,            /* Channel 4 */
+    &rtiCompare3Interrupt,            /* Channel 5 */
+    &phantomInterrupt,            /* Channel 6 */
+    &phantomInterrupt,            /* Channel 7 */
+    &phantomInterrupt,            /* Channel 8 */
+    &phantomInterrupt,            /* Channel 9 */
+    &phantomInterrupt,            /* Channel 10 */
+    &phantomInterrupt,            /* Channel 11 */
+    &phantomInterrupt,            /* Channel 12 */
+    &phantomInterrupt,            /* Channel 13 */
+    &phantomInterrupt,            /* Channel 14 */
+    &phantomInterrupt,            /* Channel 15 */
+    &phantomInterrupt,            /* Channel 16 */
+    &phantomInterrupt,            /* Channel 17 */
+    &phantomInterrupt,            /* Channel 18 */
+    &phantomInterrupt,            /* Channel 19 */
+    &esmLowInterrupt,            /* Channel 20 */
+    &phantomInterrupt,            /* Channel 21 */
+    &phantomInterrupt,            /* Channel 22 */
+    &phantomInterrupt,            /* Channel 23 */
+    &phantomInterrupt,            /* Channel 24 */
+    &phantomInterrupt,            /* Channel 25 */
+    &phantomInterrupt,            /* Channel 26 */
+    &phantomInterrupt,            /* Channel 27 */
+    &phantomInterrupt,            /* Channel 28 */
+    &phantomInterrupt,            /* Channel 29 */
+    &phantomInterrupt,            /* Channel 30 */
+    &phantomInterrupt,            /* Channel 31 */
+    &phantomInterrupt,            /* Channel 32 */
+    &phantomInterrupt,            /* Channel 33 */
+    &phantomInterrupt,            /* Channel 34 */
+    &phantomInterrupt,            /* Channel 35 */
+    &phantomInterrupt,            /* Channel 36 */
+    &phantomInterrupt,            /* Channel 37 */
+    &phantomInterrupt,            /* Channel 38 */
+    &phantomInterrupt,            /* Channel 39 */
+    &phantomInterrupt,            /* Channel 40 */
+    &phantomInterrupt,            /* Channel 41 */
+    &phantomInterrupt,            /* Channel 42 */
+    &phantomInterrupt,            /* Channel 43 */
+    &phantomInterrupt,            /* Channel 44 */
+    &phantomInterrupt,            /* Channel 45 */
+    &phantomInterrupt,            /* Channel 46 */
+    &phantomInterrupt,            /* Channel 47 */
+    &phantomInterrupt,            /* Channel 48 */
+    &phantomInterrupt,            /* Channel 49 */
+    &phantomInterrupt,            /* Channel 50 */
+    &phantomInterrupt,            /* Channel 51 */
+    &phantomInterrupt,            /* Channel 52 */
+    &phantomInterrupt,            /* Channel 53 */
+    &phantomInterrupt,            /* Channel 54 */
+    &phantomInterrupt,            /* Channel 55 */
+    &phantomInterrupt,            /* Channel 56 */
+    &phantomInterrupt,            /* Channel 57 */
+    &phantomInterrupt,            /* Channel 58 */
+    &phantomInterrupt,            /* Channel 59 */
+    &phantomInterrupt,            /* Channel 60 */
+    &phantomInterrupt,            /* Channel 61 */
+    &phantomInterrupt,            /* Channel 62 */
+    &phantomInterrupt,            /* Channel 63 */
+    &phantomInterrupt,            /* Channel 64 */
+    &phantomInterrupt,            /* Channel 65 */
+    &phantomInterrupt,            /* Channel 66 */
+    &phantomInterrupt,            /* Channel 67 */
+    &phantomInterrupt,            /* Channel 68 */
+    &phantomInterrupt,            /* Channel 69 */
+    &phantomInterrupt,            /* Channel 70 */
+    &phantomInterrupt,            /* Channel 71 */
+    &phantomInterrupt,            /* Channel 72 */
+    &phantomInterrupt,            /* Channel 73 */
+    &phantomInterrupt,            /* Channel 74 */
+    &phantomInterrupt,            /* Channel 75 */
+    &phantomInterrupt,            /* Channel 76 */
+    &phantomInterrupt,            /* Channel 77 */
+    &phantomInterrupt,            /* Channel 78 */
+    &phantomInterrupt,            /* Channel 79 */
+    &phantomInterrupt,            /* Channel 80 */
+    &phantomInterrupt,            /* Channel 81 */
+    &phantomInterrupt,            /* Channel 82 */
+    &phantomInterrupt,            /* Channel 83 */
+    &phantomInterrupt,            /* Channel 84 */
+    &phantomInterrupt,            /* Channel 85 */
+    &phantomInterrupt,            /* Channel 86 */
+    &phantomInterrupt,            /* Channel 87 */
+    &phantomInterrupt,            /* Channel 88 */
+    &phantomInterrupt,            /* Channel 89 */
+    &phantomInterrupt,            /* Channel 90 */
+    &phantomInterrupt,            /* Channel 91 */
+    &phantomInterrupt,            /* Channel 92 */
+    &phantomInterrupt,            /* Channel 93 */
+    &phantomInterrupt,            /* Channel 94 */
+    &phantomInterrupt,            /* Channel 95 */
+    &phantomInterrupt,            /* Channel 96 */
+    &phantomInterrupt,            /* Channel 97 */
+    &phantomInterrupt,            /* Channel 98 */
+    &phantomInterrupt,            /* Channel 99 */
+    &phantomInterrupt,            /* Channel 100 */
+    &phantomInterrupt,            /* Channel 101 */
+    &phantomInterrupt,            /* Channel 102 */
+    &phantomInterrupt,            /* Channel 103 */
+    &phantomInterrupt,            /* Channel 104 */
+    &phantomInterrupt,            /* Channel 105 */
+    &phantomInterrupt,            /* Channel 106 */
+    &phantomInterrupt,            /* Channel 107 */
+    &phantomInterrupt,            /* Channel 108 */
+    &phantomInterrupt,            /* Channel 109 */
+    &phantomInterrupt,            /* Channel 110 */
+    &phantomInterrupt,            /* Channel 111 */
+    &phantomInterrupt,            /* Channel 112 */
+    &phantomInterrupt,            /* Channel 113 */
+    &phantomInterrupt,            /* Channel 114 */
+    &phantomInterrupt,            /* Channel 115 */
+    &phantomInterrupt,            /* Channel 116 */
+    &phantomInterrupt,            /* Channel 117 */
+    &phantomInterrupt,            /* Channel 118 */
+    &phantomInterrupt,            /* Channel 119 */
+    &phantomInterrupt,            /* Channel 120 */
+    &phantomInterrupt,            /* Channel 121 */
+    &phantomInterrupt,            /* Channel 122 */
+    &phantomInterrupt,            /* Channel 123 */
+    &phantomInterrupt,            /* Channel 124 */
+    &phantomInterrupt,            /* Channel 125 */
+    &phantomInterrupt,            /* Channel 126 */
+};
+void vimParityErrorHandler(void);
+
+/** @fn void vimInit(void)
+*   @brief Initializes VIM module
+*
+*   This function initializes VIM RAM and registers
+*/
+/* SourceId : VIM_SourceId_001 */
+/* DesignId : VIM_DesignId_001 */
+/* Requirements : HL_SR100 */
+void vimInit(void)
+{
+	/* VIM RAM Parity Enable */
+	VIM_PARCTL = 0xAU;
+	
+	/* Initialize VIM table */
+    {
+        uint32 i;
+
+        for (i = 0U; i < VIM_CHANNELS; i++)
+        {
+            vimRAM->ISR[i] = s_vim_init[i];
+        }
+    }
+    
+    /* Set Fall-Back Address Parity Error Register */
+	/*SAFETYMCUSW 439 S MR:11.3 <APPROVED> " Need to store the address of a function in a 32 bit register - Advisory as per MISRA" */
+    VIM_FBPARERR = (uint32)&vimParityErrorHandler;
+
+    /* set IRQ/FIQ priorities */
+    vimREG->FIRQPR0 = (uint32)((uint32)SYS_FIQ << 0U)
+                    | (uint32)((uint32)SYS_FIQ << 1U)
+                    | (uint32)((uint32)SYS_IRQ << 2U)
+                    | (uint32)((uint32)SYS_IRQ << 3U)
+                    | (uint32)((uint32)SYS_IRQ << 4U)
+                    | (uint32)((uint32)SYS_IRQ << 5U)
+                    | (uint32)((uint32)SYS_IRQ << 6U)
+                    | (uint32)((uint32)SYS_IRQ << 7U)
+                    | (uint32)((uint32)SYS_IRQ << 8U)
+                    | (uint32)((uint32)SYS_IRQ << 9U)
+                    | (uint32)((uint32)SYS_IRQ << 10U)
+                    | (uint32)((uint32)SYS_IRQ << 11U)
+                    | (uint32)((uint32)SYS_IRQ << 12U)
+                    | (uint32)((uint32)SYS_IRQ << 13U)
+                    | (uint32)((uint32)SYS_IRQ << 14U)
+                    | (uint32)((uint32)SYS_IRQ << 15U)
+                    | (uint32)((uint32)SYS_IRQ << 16U)
+                    | (uint32)((uint32)SYS_IRQ << 17U)
+                    | (uint32)((uint32)SYS_IRQ << 18U)
+                    | (uint32)((uint32)SYS_IRQ << 19U)
+                    | (uint32)((uint32)SYS_IRQ << 20U)
+                    | (uint32)((uint32)SYS_IRQ << 21U)
+                    | (uint32)((uint32)SYS_IRQ << 22U)
+                    | (uint32)((uint32)SYS_IRQ << 23U)
+                    | (uint32)((uint32)SYS_IRQ << 24U)
+                    | (uint32)((uint32)SYS_IRQ << 25U)
+                    | (uint32)((uint32)SYS_IRQ << 26U)
+                    | (uint32)((uint32)SYS_IRQ << 27U)
+                    | (uint32)((uint32)SYS_IRQ << 28U)
+                    | (uint32)((uint32)SYS_IRQ << 29U)
+                    | (uint32)((uint32)SYS_IRQ << 30U)
+                    | (uint32)((uint32)SYS_IRQ << 31U);
+
+    vimREG->FIRQPR1 = (uint32)((uint32)SYS_IRQ << 0U)
+                    | (uint32)((uint32)SYS_IRQ << 1U)
+                    | (uint32)((uint32)SYS_IRQ << 2U)
+                    | (uint32)((uint32)SYS_IRQ << 3U)
+                    | (uint32)((uint32)SYS_IRQ << 4U)
+                    | (uint32)((uint32)SYS_IRQ << 5U)
+                    | (uint32)((uint32)SYS_IRQ << 6U)
+                    | (uint32)((uint32)SYS_IRQ << 7U)
+                    | (uint32)((uint32)SYS_IRQ << 8U)
+                    | (uint32)((uint32)SYS_IRQ << 9U)
+                    | (uint32)((uint32)SYS_IRQ << 10U)
+                    | (uint32)((uint32)SYS_IRQ << 11U)
+                    | (uint32)((uint32)SYS_IRQ << 12U)
+                    | (uint32)((uint32)SYS_IRQ << 13U)
+                    | (uint32)((uint32)SYS_IRQ << 14U)
+                    | (uint32)((uint32)SYS_IRQ << 15U)
+                    | (uint32)((uint32)SYS_IRQ << 16U)
+                    | (uint32)((uint32)SYS_IRQ << 17U)
+                    | (uint32)((uint32)SYS_IRQ << 18U)
+                    | (uint32)((uint32)SYS_IRQ << 19U)
+                    | (uint32)((uint32)SYS_IRQ << 20U)
+                    | (uint32)((uint32)SYS_IRQ << 21U)
+                    | (uint32)((uint32)SYS_IRQ << 22U)
+                    | (uint32)((uint32)SYS_IRQ << 23U)
+                    | (uint32)((uint32)SYS_IRQ << 24U)
+                    | (uint32)((uint32)SYS_IRQ << 25U)
+                    | (uint32)((uint32)SYS_IRQ << 26U)
+                    | (uint32)((uint32)SYS_IRQ << 27U)
+                    | (uint32)((uint32)SYS_IRQ << 28U)
+                    | (uint32)((uint32)SYS_IRQ << 29U)
+                    | (uint32)((uint32)SYS_IRQ << 30U)
+                    | (uint32)((uint32)SYS_IRQ << 31U);
+
+
+    vimREG->FIRQPR2 = (uint32)((uint32)SYS_IRQ << 0U)
+                    | (uint32)((uint32)SYS_IRQ << 1U)
+                    | (uint32)((uint32)SYS_IRQ << 2U)
+                    | (uint32)((uint32)SYS_IRQ << 3U)
+                    | (uint32)((uint32)SYS_IRQ << 4U)
+                    | (uint32)((uint32)SYS_IRQ << 5U)
+                    | (uint32)((uint32)SYS_IRQ << 6U)
+                    | (uint32)((uint32)SYS_IRQ << 7U)
+                    | (uint32)((uint32)SYS_IRQ << 8U)
+                    | (uint32)((uint32)SYS_IRQ << 9U)
+                    | (uint32)((uint32)SYS_IRQ << 10U)
+                    | (uint32)((uint32)SYS_IRQ << 11U)
+                    | (uint32)((uint32)SYS_IRQ << 12U)
+                    | (uint32)((uint32)SYS_IRQ << 13U)
+                    | (uint32)((uint32)SYS_IRQ << 14U)
+                    | (uint32)((uint32)SYS_IRQ << 15U)
+                    | (uint32)((uint32)SYS_IRQ << 16U)
+                    | (uint32)((uint32)SYS_IRQ << 17U)
+                    | (uint32)((uint32)SYS_IRQ << 18U)
+                    | (uint32)((uint32)SYS_IRQ << 19U)
+                    | (uint32)((uint32)SYS_IRQ << 20U)
+                    | (uint32)((uint32)SYS_IRQ << 21U)
+                    | (uint32)((uint32)SYS_IRQ << 22U)
+                    | (uint32)((uint32)SYS_IRQ << 23U)
+                    | (uint32)((uint32)SYS_IRQ << 24U)
+                    | (uint32)((uint32)SYS_IRQ << 25U)
+                    | (uint32)((uint32)SYS_IRQ << 26U)
+                    | (uint32)((uint32)SYS_IRQ << 27U)
+                    | (uint32)((uint32)SYS_IRQ << 28U)
+                    | (uint32)((uint32)SYS_IRQ << 29U)
+                    | (uint32)((uint32)SYS_IRQ << 30U)
+                    | (uint32)((uint32)SYS_IRQ << 31U);
+
+    vimREG->FIRQPR3 = (uint32)((uint32)SYS_IRQ << 0U)
+                    | (uint32)((uint32)SYS_IRQ << 1U)
+                    | (uint32)((uint32)SYS_IRQ << 2U)
+                    | (uint32)((uint32)SYS_IRQ << 3U)
+                    | (uint32)((uint32)SYS_IRQ << 4U)
+                    | (uint32)((uint32)SYS_IRQ << 5U)
+                    | (uint32)((uint32)SYS_IRQ << 6U)
+                    | (uint32)((uint32)SYS_IRQ << 7U)
+                    | (uint32)((uint32)SYS_IRQ << 8U)
+                    | (uint32)((uint32)SYS_IRQ << 9U)
+                    | (uint32)((uint32)SYS_IRQ << 10U)
+                    | (uint32)((uint32)SYS_IRQ << 11U)
+                    | (uint32)((uint32)SYS_IRQ << 12U)
+                    | (uint32)((uint32)SYS_IRQ << 13U)
+                    | (uint32)((uint32)SYS_IRQ << 14U)
+                    | (uint32)((uint32)SYS_IRQ << 15U)
+                    | (uint32)((uint32)SYS_IRQ << 16U)
+                    | (uint32)((uint32)SYS_IRQ << 17U)
+                    | (uint32)((uint32)SYS_IRQ << 18U)
+                    | (uint32)((uint32)SYS_IRQ << 19U)
+                    | (uint32)((uint32)SYS_IRQ << 20U)
+                    | (uint32)((uint32)SYS_IRQ << 21U)
+                    | (uint32)((uint32)SYS_IRQ << 22U)
+                    | (uint32)((uint32)SYS_IRQ << 23U)
+                    | (uint32)((uint32)SYS_IRQ << 24U)
+                    | (uint32)((uint32)SYS_IRQ << 25U)
+                    | (uint32)((uint32)SYS_IRQ << 26U)
+                    | (uint32)((uint32)SYS_IRQ << 27U)
+                    | (uint32)((uint32)SYS_IRQ << 28U)
+                    | (uint32)((uint32)SYS_IRQ << 29U)
+                    | (uint32)((uint32)SYS_IRQ << 30U)
+                    | (uint32)((uint32)SYS_IRQ << 31U);
+
+                    
+    /* enable interrupts */
+    vimREG->REQMASKSET0 = (uint32)((uint32)1U << 0U)
+                        | (uint32)((uint32)1U << 1U)
+                        | (uint32)((uint32)1U << 2U)
+                        | (uint32)((uint32)1U << 3U)
+                        | (uint32)((uint32)1U << 4U)
+                        | (uint32)((uint32)1U << 5U)
+                        | (uint32)((uint32)0U << 6U)
+                        | (uint32)((uint32)0U << 7U)
+                        | (uint32)((uint32)0U << 8U)
+                        | (uint32)((uint32)0U << 9U)
+                        | (uint32)((uint32)0U << 10U)
+                        | (uint32)((uint32)0U << 11U)
+                        | (uint32)((uint32)0U << 12U)
+                        | (uint32)((uint32)0U << 13U)
+                        | (uint32)((uint32)0U << 14U)
+                        | (uint32)((uint32)0U << 15U)
+                        | (uint32)((uint32)0U << 16U)
+                        | (uint32)((uint32)0U << 17U)
+                        | (uint32)((uint32)0U << 18U)
+                        | (uint32)((uint32)0U << 19U)
+                        | (uint32)((uint32)1U << 20U)
+                        | (uint32)((uint32)0U << 21U)
+                        | (uint32)((uint32)0U << 22U)
+                        | (uint32)((uint32)0U << 23U)
+                        | (uint32)((uint32)0U << 24U)
+                        | (uint32)((uint32)0U << 25U)
+                        | (uint32)((uint32)0U << 26U)
+                        | (uint32)((uint32)0U << 27U)
+                        | (uint32)((uint32)0U << 28U)
+                        | (uint32)((uint32)0U << 29U)
+                        | (uint32)((uint32)0U << 30U)
+                        | (uint32)((uint32)0U << 31U);
+
+    vimREG->REQMASKSET1 = (uint32)((uint32)0U << 0U)
+                        | (uint32)((uint32)0U << 1U)
+                        | (uint32)((uint32)0U << 2U)
+                        | (uint32)((uint32)0U << 3U)
+                        | (uint32)((uint32)0U << 4U)
+                        | (uint32)((uint32)0U << 5U)
+                        | (uint32)((uint32)0U << 6U)
+                        | (uint32)((uint32)0U << 7U)
+                        | (uint32)((uint32)0U << 8U)
+                        | (uint32)((uint32)0U << 9U)
+                        | (uint32)((uint32)0U << 10U)
+                        | (uint32)((uint32)0U << 11U)
+                        | (uint32)((uint32)0U << 12U)
+                        | (uint32)((uint32)0U << 13U)
+                        | (uint32)((uint32)0U << 14U)
+                        | (uint32)((uint32)0U << 15U)
+                        | (uint32)((uint32)0U << 16U)
+                        | (uint32)((uint32)0U << 17U)
+                        | (uint32)((uint32)0U << 18U)
+                        | (uint32)((uint32)0U << 19U)
+                        | (uint32)((uint32)0U << 20U)
+                        | (uint32)((uint32)0U << 21U)
+                        | (uint32)((uint32)0U << 22U)
+                        | (uint32)((uint32)0U << 23U)
+                        | (uint32)((uint32)0U << 24U)
+                        | (uint32)((uint32)0U << 25U)
+                        | (uint32)((uint32)0U << 26U)
+                        | (uint32)((uint32)0U << 27U)
+                        | (uint32)((uint32)0U << 28U)
+                        | (uint32)((uint32)0U << 29U)
+                        | (uint32)((uint32)0U << 30U)
+                        | (uint32)((uint32)0U << 31U);
+
+    vimREG->REQMASKSET2 = (uint32)((uint32)0U << 0U)
+                        | (uint32)((uint32)0U << 1U)
+                        | (uint32)((uint32)0U << 2U)
+                        | (uint32)((uint32)0U << 3U)
+                        | (uint32)((uint32)0U << 4U)
+                        | (uint32)((uint32)0U << 5U)
+                        | (uint32)((uint32)0U << 6U)
+                        | (uint32)((uint32)0U << 7U)
+                        | (uint32)((uint32)0U << 8U)
+                        | (uint32)((uint32)0U << 9U)
+                        | (uint32)((uint32)0U << 10U)
+                        | (uint32)((uint32)0U << 11U)
+                        | (uint32)((uint32)0U << 12U)
+                        | (uint32)((uint32)0U << 13U)
+                        | (uint32)((uint32)0U << 14U)
+                        | (uint32)((uint32)0U << 15U)
+                        | (uint32)((uint32)0U << 16U)
+                        | (uint32)((uint32)0U << 17U)
+                        | (uint32)((uint32)0U << 18U)
+                        | (uint32)((uint32)0U << 19U)
+                        | (uint32)((uint32)0U << 20U)
+                        | (uint32)((uint32)0U << 21U)
+                        | (uint32)((uint32)0U << 22U)
+                        | (uint32)((uint32)0U << 23U)
+                        | (uint32)((uint32)0U << 24U)
+                        | (uint32)((uint32)0U << 25U)
+                        | (uint32)((uint32)0U << 26U)
+                        | (uint32)((uint32)0U << 27U)
+                        | (uint32)((uint32)0U << 28U)
+                        | (uint32)((uint32)0U << 29U)
+                        | (uint32)((uint32)0U << 30U)
+                        | (uint32)((uint32)0U << 31U);
+                        
+    vimREG->REQMASKSET3 = (uint32)((uint32)0U << 0U)
+                        | (uint32)((uint32)0U << 1U)
+                        | (uint32)((uint32)0U << 2U)
+                        | (uint32)((uint32)0U << 3U)
+                        | (uint32)((uint32)0U << 4U)
+                        | (uint32)((uint32)0U << 5U)
+                        | (uint32)((uint32)0U << 6U)
+                        | (uint32)((uint32)0U << 7U)
+                        | (uint32)((uint32)0U << 8U)
+                        | (uint32)((uint32)0U << 9U)
+                        | (uint32)((uint32)0U << 10U)
+                        | (uint32)((uint32)0U << 11U)
+                        | (uint32)((uint32)0U << 12U)
+                        | (uint32)((uint32)0U << 13U)
+                        | (uint32)((uint32)0U << 14U)
+                        | (uint32)((uint32)0U << 15U)
+                        | (uint32)((uint32)0U << 16U)
+                        | (uint32)((uint32)0U << 17U)
+                        | (uint32)((uint32)0U << 18U)
+                        | (uint32)((uint32)0U << 19U)
+                        | (uint32)((uint32)0U << 20U)
+                        | (uint32)((uint32)0U << 21U)
+                        | (uint32)((uint32)0U << 22U)
+                        | (uint32)((uint32)0U << 23U)
+                        | (uint32)((uint32)0U << 24U)
+                        | (uint32)((uint32)0U << 25U)
+                        | (uint32)((uint32)0U << 26U)
+                        | (uint32)((uint32)0U << 27U)
+                        | (uint32)((uint32)0U << 28U)
+                        | (uint32)((uint32)0U << 29U)
+                        | (uint32)((uint32)0U << 30U)
+                        | (uint32)((uint32)0U << 31U);    
+
+    /* Set Capture event sources */
+	vimREG->CAPEVT = ((uint32)((uint32)0U << 0U)
+	                 |(uint32)((uint32)0U << 16U));
+}
+
+/** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
+*   @brief Map selected interrupt request to the selected channel
+*
+*    @param[in] request: Interrupt request number 2..127
+*    @param[in] channel: VIM Channel number 2..127
+*    @param[in] handler: Address of the interrupt handler
+*
+*   This function will map selected interrupt request to the selected channel.
+*
+*/
+/* SourceId : VIM_SourceId_002 */
+/* DesignId : VIM_DesignId_002 */
+/* Requirements : HL_SR101 */
+void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
+{
+    uint32 i,j;
+    i = channel >> 2U;              /* Find the register to configure */
+    j = channel - (i << 2U);        /* Find the offset of the type    */
+    j = 3U - j;                     /* reverse the byte order         */
+    j = j << 3U;                    /* find the bit location          */
+
+    /*Mapping the required interrupt request to the required channel*/
+    vimREG->CHANCTRL[i] &= ~(uint32)((uint32)0xFFU << j);
+    vimREG->CHANCTRL[i] |= (request << j);
+
+    /*Updating VIMRAM*/
+    vimRAM->ISR[channel + 1U] = handler;
+}
+
+/** @fn void vimEnableInterrupt(uint32 channel, boolean inttype)
+*   @brief Enable interrupt for the the selected channel
+*
+*    @param[in] channel: VIM Channel number 2..127
+*    @param[in] inttype: Interrupt type
+*                        - SYS_IRQ: Selected channel will be enabled as IRQ
+*                        - SYS_FIQ: Selected channel will be enabled as FIQ
+*
+*   This function will enable interrupt for the selected channel.
+*
+*/
+/* SourceId : VIM_SourceId_003 */
+/* DesignId : VIM_DesignId_003 */
+/* Requirements : HL_SR102 */
+void vimEnableInterrupt(uint32 channel, systemInterrupt_t inttype)
+{
+	if (channel >= 96U)
+    {
+        if(inttype == SYS_IRQ)
+        {
+            vimREG->FIRQPR3 &= ~(uint32)((uint32)1U << (channel-96U));
+        }
+        else
+        {
+            vimREG->FIRQPR3 |= ((uint32)1U << (channel-96U));
+        }
+        vimREG->REQMASKSET3 = (uint32)1U << (channel-96U);
+    }
+    else if (channel >= 64U)
+    {
+        if(inttype == SYS_IRQ)
+        {
+            vimREG->FIRQPR2 &= ~(uint32)((uint32)1U << (channel-64U));
+        }
+        else
+        {
+            vimREG->FIRQPR2 |= ((uint32)1U << (channel-64U));
+        }
+        vimREG->REQMASKSET2 = (uint32)1U << (channel-64U);
+    }
+    else if (channel >= 32U)
+    {
+        if(inttype == SYS_IRQ)
+        {
+            vimREG->FIRQPR1 &= ~(uint32)((uint32)1U << (channel-32U));
+        }
+        else
+        {
+            vimREG->FIRQPR1 |= ((uint32)1U << (channel-32U));
+        }
+        vimREG->REQMASKSET1 = (uint32)1U << (channel-32U);
+    }
+    else if (channel >= 2U)
+    {
+        if(inttype == SYS_IRQ)
+        {
+            vimREG->FIRQPR0 &= ~(uint32)((uint32)1U << channel);
+        }
+        else
+        {
+            vimREG->FIRQPR0 |= ((uint32)1U << channel);
+        }
+        vimREG->REQMASKSET0 = (uint32)1U << channel;
+    }
+    else
+    {
+		/* Empty */
+    }
+}
+
+/** @fn void vimDisableInterrupt(uint32 channel)
+*   @brief Disable interrupt for the the selected channel
+*
+*    @param[in] channel: VIM Channel number 2..127
+*
+*   This function will disable interrupt for the selected channel.
+*
+*/
+/* SourceId : VIM_SourceId_004 */
+/* DesignId : VIM_DesignId_004 */
+/* Requirements : HL_SR103 */
+void vimDisableInterrupt(uint32 channel)
+{
+    if (channel >= 96U)
+    {
+        vimREG->REQMASKCLR3 = (uint32)1U << (channel-96U);
+    }
+    else if (channel >= 64U)
+    {
+        vimREG->REQMASKCLR2 = (uint32)1U << (channel-64U);
+    }
+    else if (channel >=32U)
+    {
+        vimREG->REQMASKCLR1 = (uint32)1U << (channel-32U);
+    }
+    else if (channel >= 2U)
+    {
+        vimREG->REQMASKCLR0 = (uint32)1U << channel;
+    }
+    else
+    {
+		/* Empty */
+    }
+}
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*    @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*    @param[in] type:     whether initial or current value of the configuration registers need to be stored
+*                        - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*                        - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration 
+*   registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : VIM_SourceId_005 */
+/* DesignId : VIM_DesignId_005 */
+/* Requirements : HL_SR104 */
+void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
+{  
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE;
+        config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE;
+        config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE;
+        config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE;
+        config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE;
+        config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE;
+        config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE;
+        config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE;
+        config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE;
+        config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE;
+        config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE;
+        config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE;
+        config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[0U] = VIM_CHANCTRL0_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[1U] = VIM_CHANCTRL1_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[2U] = VIM_CHANCTRL2_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[3U] = VIM_CHANCTRL3_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[4U] = VIM_CHANCTRL4_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[5U] = VIM_CHANCTRL5_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[6U] = VIM_CHANCTRL6_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[7U] = VIM_CHANCTRL7_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[8U] = VIM_CHANCTRL8_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[9U] = VIM_CHANCTRL9_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[10U] = VIM_CHANCTRL10_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[11U] = VIM_CHANCTRL11_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[12U] = VIM_CHANCTRL12_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[13U] = VIM_CHANCTRL13_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[14U] = VIM_CHANCTRL14_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[15U] = VIM_CHANCTRL15_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[16U] = VIM_CHANCTRL16_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[17U] = VIM_CHANCTRL17_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[18U] = VIM_CHANCTRL18_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[19U] = VIM_CHANCTRL19_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[20U] = VIM_CHANCTRL20_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[21U] = VIM_CHANCTRL21_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[22U] = VIM_CHANCTRL22_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[23U] = VIM_CHANCTRL23_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[24U] = VIM_CHANCTRL24_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[25U] = VIM_CHANCTRL25_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[26U] = VIM_CHANCTRL26_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[27U] = VIM_CHANCTRL27_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[28U] = VIM_CHANCTRL28_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[29U] = VIM_CHANCTRL29_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[30U] = VIM_CHANCTRL30_CONFIGVALUE;
+		config_reg->CONFIG_CHANCTRL[31U] = VIM_CHANCTRL31_CONFIGVALUE;
+    }
+    else
+    {
+	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0;
+        config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1;
+        config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2;
+        config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3;
+        config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0;
+        config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1;
+        config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2;
+        config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3;
+        config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0;
+        config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1;
+        config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2;
+        config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3;
+        config_reg->CONFIG_CAPEVT = vimREG->CAPEVT;
+		config_reg->CONFIG_CHANCTRL[0U] = vimREG->CHANCTRL[0U];
+		config_reg->CONFIG_CHANCTRL[1U] = vimREG->CHANCTRL[1U];
+		config_reg->CONFIG_CHANCTRL[2U] = vimREG->CHANCTRL[2U];
+		config_reg->CONFIG_CHANCTRL[3U] = vimREG->CHANCTRL[3U];
+		config_reg->CONFIG_CHANCTRL[4U] = vimREG->CHANCTRL[4U];
+		config_reg->CONFIG_CHANCTRL[5U] = vimREG->CHANCTRL[5U];
+		config_reg->CONFIG_CHANCTRL[6U] = vimREG->CHANCTRL[6U];
+		config_reg->CONFIG_CHANCTRL[7U] = vimREG->CHANCTRL[7U];
+		config_reg->CONFIG_CHANCTRL[8U] = vimREG->CHANCTRL[8U];
+		config_reg->CONFIG_CHANCTRL[9U] = vimREG->CHANCTRL[9U];
+		config_reg->CONFIG_CHANCTRL[10U] = vimREG->CHANCTRL[10U];
+		config_reg->CONFIG_CHANCTRL[11U] = vimREG->CHANCTRL[11U];
+		config_reg->CONFIG_CHANCTRL[12U] = vimREG->CHANCTRL[12U];
+		config_reg->CONFIG_CHANCTRL[13U] = vimREG->CHANCTRL[13U];
+		config_reg->CONFIG_CHANCTRL[14U] = vimREG->CHANCTRL[14U];
+		config_reg->CONFIG_CHANCTRL[15U] = vimREG->CHANCTRL[15U];
+		config_reg->CONFIG_CHANCTRL[16U] = vimREG->CHANCTRL[16U];
+		config_reg->CONFIG_CHANCTRL[17U] = vimREG->CHANCTRL[17U];
+		config_reg->CONFIG_CHANCTRL[18U] = vimREG->CHANCTRL[18U];
+		config_reg->CONFIG_CHANCTRL[19U] = vimREG->CHANCTRL[19U];
+		config_reg->CONFIG_CHANCTRL[20U] = vimREG->CHANCTRL[20U];
+		config_reg->CONFIG_CHANCTRL[21U] = vimREG->CHANCTRL[21U];
+		config_reg->CONFIG_CHANCTRL[22U] = vimREG->CHANCTRL[22U];
+		config_reg->CONFIG_CHANCTRL[23U] = vimREG->CHANCTRL[23U];
+		config_reg->CONFIG_CHANCTRL[24U] = vimREG->CHANCTRL[24U];
+		config_reg->CONFIG_CHANCTRL[25U] = vimREG->CHANCTRL[25U];
+		config_reg->CONFIG_CHANCTRL[26U] = vimREG->CHANCTRL[26U];
+		config_reg->CONFIG_CHANCTRL[27U] = vimREG->CHANCTRL[27U];
+		config_reg->CONFIG_CHANCTRL[28U] = vimREG->CHANCTRL[28U];
+		config_reg->CONFIG_CHANCTRL[29U] = vimREG->CHANCTRL[29U];
+		config_reg->CONFIG_CHANCTRL[30U] = vimREG->CHANCTRL[30U];
+		config_reg->CONFIG_CHANCTRL[31U] = vimREG->CHANCTRL[31U];
+    }
+}
+
+
+#pragma CODE_STATE(vimParityErrorHandler, 32)
+#pragma INTERRUPT(vimParityErrorHandler, IRQ)
+#pragma WEAK(vimParityErrorHandler)
+
+/* SourceId : VIM_SourceId_006 */
+/* DesignId : VIM_DesignId_006 */
+/* Requirements : HL_SR105 */
+void vimParityErrorHandler(void)
+{
+    uint32 vec;
+    
+    /* Identify the corrupted address */
+    uint32 error_addr = VIM_ADDERR;
+
+    /* Identify the channel number */
+    uint32 error_channel = ((error_addr & 0x1FFU) >> 2U);
+
+    /* Correct the corrupted location */
+    vimRAM->ISR[error_channel] = s_vim_init[error_channel];
+
+    /* Clear Parity Error Flag */
+    VIM_PARFLG = 1U;
+
+    /* Disable and enable the highest priority pending channel */
+    if (vimREG->FIQINDEX != 0U)
+    {
+        vec = vimREG->FIQINDEX - 1U;
+    }
+    else 
+    {
+	   /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Read 32 bit volatile register" */
+        vec = vimREG->IRQINDEX - 1U;
+    }
+    if(vec == 0U)
+    {
+        vimREG->INTREQ0 = 1U;
+	    vec = esmREG->IOFFHR - 1U;
+		
+        if (vec < 32U)
+        {
+            esmREG->SR1[0U] = (uint32)1U << vec;
+            esmGroup1Notification(vec);
+        }
+        else if (vec < 64U)
+        {
+            esmREG->SR1[1U] = (uint32)1U << (vec-32U);
+            esmGroup2Notification(vec-32U);
+        }
+        else if (vec < 96U)
+        {
+            esmREG->SR4[0U] = (uint32)1U << (vec-64U);
+            esmGroup1Notification(vec-32U);
+        }
+        else
+        {
+            esmREG->SR4[1U] = (uint32)1U << (vec-96U);
+            esmGroup2Notification(vec-64U);
+        }
+    }
+    else if (vec < 32U)
+    {
+        vimREG->REQMASKCLR0 = (uint32)1U << vec;
+        vimREG->REQMASKSET0 = (uint32)1U << vec;
+    }
+    else if (vec < 64U)
+    {
+        vimREG->REQMASKCLR1 = (uint32)1U << (vec-32U);
+        vimREG->REQMASKSET1 = (uint32)1U << (vec-32U);
+    }
+    else if(vec < 96U)
+    {
+        vimREG->REQMASKCLR2 = (uint32)1U << (vec-64U);
+        vimREG->REQMASKSET2 = (uint32)1U << (vec-64U);
+    }
+	else
+	{
+	    vimREG->REQMASKCLR3 = (uint32)1U << (vec-96U);
+        vimREG->REQMASKSET3 = (uint32)1U << (vec-96U);
+	}
+}
diff --git a/src/arch/rm46l8lp/halcogen/system.c b/src/arch/rm46l8lp/halcogen/system.c
new file mode 100644
index 0000000..94e976d
--- /dev/null
+++ b/src/arch/rm46l8lp/halcogen/system.c
@@ -0,0 +1,681 @@
+/** @file system.c
+*   @brief System Driver Source File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file contains:
+*   - API Functions
+*   .
+*   which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* Include Files */
+
+#include "system.h"
+#include "sys_selftest.h"
+#include "sys_pcr.h"
+#include "pinmux.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void systemInit(void)
+*   @brief Initializes System Driver
+*
+*   This function initializes the System driver.
+*
+*/
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/* SourceId : SYSTEM_SourceId_001 */
+/* DesignId : SYSTEM_DesignId_001 */
+/* Requirements : HL_SR451 */
+void setupPLL(void)
+{
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+    /* Disable PLL1 and PLL2 */
+    systemREG1->CSDISSET = 0x00000002U | 0x00000040U;
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while((systemREG1->CSDIS & 0x42U) != 0x42U)
+    {
+    /* Wait */
+    }
+
+    /* Clear Global Status Register */
+    systemREG1->GBLSTAT = 0x301U;
+
+    /** - Configure PLL control registers */
+    /** @b Initialize @b Pll1: */
+
+    /**   - Setup pll control register 1:
+    *     - Setup reset on oscillator slip
+    *     - Setup bypass on pll slip
+    *     - setup Pll output clock divider to max before Lock (0x1f + 1 == 32)
+    *     - Setup reset on oscillator fail
+    *     - Setup reference clock divider (5 + 1 == 6)
+    *     - Setup Pll multiplier (0x77 + 1 == 120)
+    */
+    systemREG1->PLLCTL1 =  (uint32)0x00000000U
+                        |  (uint32)0x20000000U
+                        |  (uint32)((uint32)0x1FU << 24U)
+                        |  (uint32)0x00000000U
+                        |  (uint32)((uint32)(6U - 1U)<< 16U)
+                        |  (uint32)(0x7700U);
+
+    /**   - Setup pll control register 2
+    *     - Setup spreading rate
+    *     - Setup bandwidth adjustment
+    *     - Setup internal Pll output divider (1+1 == 2)
+    *     - Setup spreading amount
+    */
+    systemREG1->PLLCTL2 =  (uint32)((uint32)255U << 22U)
+                        |  (uint32)((uint32)7U << 12U)
+                        |  (uint32)((uint32)(2U - 1U) << 9U)
+                        |  (uint32)61U;
+
+    /** @b Initialize @b Pll2: */
+
+    /**   - Setup pll2 control register :
+    *     - setup Pll output clock divider to max before Lock
+    *     - Setup reference clock divider
+    *     - Setup internal Pll output divider
+    *     - Setup Pll multiplier
+    */
+    systemREG2->PLLCTL3 = (uint32)((uint32)(2U - 1U) << 29U)
+                        | (uint32)((uint32)0x1FU << 24U)
+                        | (uint32)((uint32)(6U - 1U)<< 16U)
+                        | (uint32)(0x7700U);
+
+    /** - Enable PLL(s) to start up or Lock */
+    systemREG1->CSDIS = 0x00000000U
+                      | 0x00000000U
+                      | 0x00000008U
+                      | 0x00000080U
+                      | 0x00000000U
+                      | 0x00000000U
+                      | 0x00000000U;  
+
+    // PLL1 output at this point == (oscin / 6) * 120 / (2 * 32) == oscin * 0.3125
+}
+
+/** @fn void trimLPO(void)
+*   @brief Initialize LPO trim values
+*   
+*	Load TRIM values from OTP if present else call customTrimLPO() function   
+*
+*/
+/* SourceId : SYSTEM_SourceId_002 */
+/* DesignId : SYSTEM_DesignId_002 */
+/* Requirements : HL_SR468 */
+void trimLPO(void)
+{
+    uint32 u32clocktestConfig;
+    /* Save user clocktest register configuration */
+    u32clocktestConfig = systemREG1->CLKTEST;
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+    /*The TRM states OTP TRIM value should be stepped to avoid large changes in the HF LPO clock that would result in a LPOCLKMON fault. At issue is the TRM does not specify what the maximum step is so there is no metric to use for the SW implementation - the routine can temporarily disable the LPOCLKMON range check so the sudden change will not cause a fault.*/
+    /* Disable clock range detection*/
+    systemREG1->CLKTEST = (systemREG1->CLKTEST 
+                        | (uint32)((uint32)0x1U << 24U))
+                        & (uint32)(~((uint32)0x1U << 25U));
+    
+    /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+    if(LPO_TRIM_VALUE != 0xFFFFU)
+    {
+
+        systemREG1->LPOMONCTL  = (uint32)((uint32)1U << 24U)
+                               | (uint32)((uint32)LPO_TRIM_VALUE);
+    }
+    else
+    {
+    
+        customTrimLPO();
+        
+    }
+    
+    /* Restore the user clocktest register value configuration */
+    systemREG1->CLKTEST = u32clocktestConfig;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+}
+
+/* SourceId : SYSTEM_SourceId_003 */
+/* DesignId : SYSTEM_DesignId_003 */
+/* Requirements : HL_SR457 */
+void setupFlash(void)
+{
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+    /** - Setup flash read mode, address wait states and data wait states */
+    flashWREG->FRDCNTL =  0x00000000U
+                       | (uint32)((uint32)3U << 8U)
+                       | (uint32)((uint32)1U << 4U)
+                       |  1U;
+
+    /** - Setup flash access wait states for bank 7 */
+    FSM_WR_ENA_HL    = 0x5U;
+    EEPROM_CONFIG_HL = 0x00000002U
+                     | (uint32)((uint32)3U << 16U) ;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+    /** - Disable write access to flash state machine registers */
+    FSM_WR_ENA_HL    = 0xAU;
+
+    /** - Setup flash bank power modes */
+    flashWREG->FBFALLBACK = 0x00000000U
+                          | (uint32)((uint32)SYS_ACTIVE << 14U) /* BANK 7 */
+                          | (uint32)((uint32)SYS_ACTIVE << 2U)  /* BANK 1 */
+                          | (uint32)((uint32)SYS_ACTIVE << 0U); /* BANK 0 */
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+}
+
+/* SourceId : SYSTEM_SourceId_004 */
+/* DesignId : SYSTEM_DesignId_004 */
+/* Requirements : HL_SR470 */
+void periphInit(void)
+{
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+    /** - Disable Peripherals before peripheral powerup*/
+    systemREG1->CLKCNTL &= 0xFFFFFEFFU;
+
+    /** - Release peripherals from reset and enable clocks to all peripherals */
+    /** - Power-up all peripherals */
+    pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;
+    pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;
+    pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;
+    pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;
+
+    /** - Enable Peripherals */
+    systemREG1->CLKCNTL |= 0x00000100U;
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+}
+
+/* SourceId : SYSTEM_SourceId_005 */
+/* DesignId : SYSTEM_DesignId_005 */
+/* Requirements : HL_SR469 */
+void mapClocks(void)
+{
+    uint32 SYS_CSVSTAT, SYS_CSDIS;
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+    /** @b Initialize @b Clock @b Tree: */
+    /** - Disable / Enable clock domain */
+    systemREG1->CDDIS = (uint32)((uint32)0U << 4U ) /* AVCLK1 , 1 - OFF, 0 - ON */
+                      | (uint32)((uint32)0U << 5U ) /* AVCLK2 , 1 - OFF, 0 - ON */
+                      | (uint32)((uint32)0U << 8U ) /* VCLK3 , 1 - OFF, 0 - ON */
+                      | (uint32)((uint32)0U << 9U ) /* VCLK4 , 1 - OFF, 0 - ON */
+                      | (uint32)((uint32)1U << 10U) /* AVCLK3 , 1 - OFF, 0 - ON */
+                      | (uint32)((uint32)0U << 11U); /* AVCLK4 , 1 - OFF, 0 - ON */
+
+
+    /* Work Around for Errata SYS#46:
+     *
+     * Errata Description:
+     *            Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid
+     * Workaround:
+     *            Always check the CSDIS register to make sure the clock source is turned on and check
+     * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock.
+     */
+    /** - Wait for until clocks are locked */
+    SYS_CSVSTAT = systemREG1->CSVSTAT;
+    SYS_CSDIS = systemREG1->CSDIS;
+    while ((SYS_CSVSTAT & ((SYS_CSDIS ^ 0xFFU) & 0xFFU)) != ((SYS_CSDIS ^ 0xFFU) & 0xFFU))
+    {
+        SYS_CSVSTAT = systemREG1->CSVSTAT;
+        SYS_CSDIS = systemREG1->CSDIS;
+    } /* Wait */
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+    /** - Map device clock domains to desired sources and configure top-level dividers */
+    /** - All clock domains are working off the default clock sources until now */
+    /** - The below assignments can be easily modified using the HALCoGen GUI */
+
+    /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
+    systemREG1->GHVSRC = (uint32)((uint32)SYS_OSC << 24U)
+                       | (uint32)((uint32)SYS_OSC << 16U)
+                       | (uint32)((uint32)SYS_PLL1 << 0U);
+
+    /** - Setup RTICLK1 and RTICLK2 clocks */
+    systemREG1->RCLKSRC = (uint32)((uint32)1U << 24U)
+                        | (uint32)((uint32)SYS_VCLK << 16U)
+                        | (uint32)((uint32)1U << 8U)
+                        | (uint32)((uint32)SYS_VCLK << 0U);
+
+    /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
+    systemREG1->VCLKASRC = (uint32)((uint32)SYS_VCLK << 8U)
+                         | (uint32)((uint32)SYS_VCLK << 0U);
+
+    /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
+    systemREG1->CLKCNTL  = (systemREG1->CLKCNTL & 0xF0FFFFFFU)
+                         | (uint32)((uint32)1U << 24U);
+    systemREG1->CLKCNTL  = (systemREG1->CLKCNTL & 0xFFF0FFFFU)
+                         | (uint32)((uint32)1U << 16U);
+
+    systemREG2->CLK2CNTL = (systemREG2->CLK2CNTL & 0xFFFFF0F0U)
+                         | (uint32)((uint32)1U << 8U)
+                         | (uint32)((uint32)1U << 0U);
+
+    systemREG2->VCLKACON1 =  (uint32)((uint32)(1U - 1U) << 24U)
+                           | (uint32)((uint32)0U << 20U)
+                           | (uint32)((uint32)SYS_VCLK << 16U)
+                           | (uint32)((uint32)(1U - 1U) << 8U)
+                           | (uint32)((uint32)0U << 4U)
+                           | (uint32)((uint32)SYS_VCLK << 0U);
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+    /* Now the PLLs are locked and the PLL outputs can be sped up */
+    /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
+    systemREG1->PLLCTL1 = (systemREG1->PLLCTL1 & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U);
+    // R = 1 => PLL1 output == (oscin / 6) * 120 / (2 * 1) == oscin * 10
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+    systemREG2->PLLCTL3 = (systemREG2->PLLCTL3 & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U);
+
+    /* Enable/Disable Frequency modulation */
+    systemREG1->PLLCTL2 |= 0x00000000U;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+}
+
+/* SourceId : SYSTEM_SourceId_006 */
+/* DesignId : SYSTEM_DesignId_006 */
+/* Requirements : HL_SR471 */
+void systemInit(void)
+{
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+    /* Configure PLL control registers and enable PLLs.
+     * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
+     * This initialization sequence performs all the tasks that are not
+     * required to be done at full application speed while the PLL locks.
+     */
+    setupPLL();
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+    /* Enable clocks to peripherals and release peripheral reset */
+    periphInit();
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+    /* Configure device-level multiplexing and I/O multiplexing */
+    muxInit();
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+    /** - Set up flash address and data wait states based on the target CPU clock frequency
+     * The number of address and data wait states for the target CPU clock frequency are specified
+     * in the specific part's datasheet.
+     */
+    setupFlash();
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+    /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
+    trimLPO();
+
+
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+    /** - Wait for PLLs to start up and map clock domains to desired clock sources */
+    mapClocks();
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+    /** - set ECLK pins functional mode */
+    systemREG1->SYSPC1 = 0U;
+
+    /** - set ECLK pins default output value */
+    systemREG1->SYSPC4 = 0U;
+
+    /** - set ECLK pins output direction */
+    systemREG1->SYSPC2 = 1U;
+
+    /** - set ECLK pins open drain enable */
+    systemREG1->SYSPC7 = 0U;
+
+    /** - set ECLK pins pullup/pulldown enable */
+    systemREG1->SYSPC8 = 0U;
+
+    /** - set ECLK pins pullup/pulldown select */
+    systemREG1->SYSPC9 = 1U;
+
+    /** - Setup ECLK */
+    systemREG1->ECPCNTL = (uint32)((uint32)0U << 24U)
+                        | (uint32)((uint32)0U << 23U)
+                        | (uint32)((uint32)(8U - 1U) & 0xFFFFU);
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+}
+
+/* SourceId : SYSTEM_SourceId_007 */
+/* DesignId : SYSTEM_DesignId_007 */
+/* Requirements : HL_SR493 */
+void systemPowerDown(uint32 mode)
+{
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+    /* Disable clock sources */
+    systemREG1->CSDISSET = mode & 0x000000FFU;
+
+    /* Disable clock domains */
+    systemREG1->CDDIS = (mode >> 8U) & 0x00000FFFU;
+
+    /* Idle CPU */
+    _gotoCPUIdle_();
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+
+}
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+/** @fn void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*   @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*   @param[in] type:    whether initial or current value of the configuration registers need to be stored
+*                       - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*                       - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : SYSTEM_SourceId_008 */
+/* DesignId : SYSTEM_DesignId_008 */
+/* Requirements : HL_SR506 */
+void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_SYSPC1 = SYS_SYSPC1_CONFIGVALUE;
+        config_reg->CONFIG_SYSPC2 = SYS_SYSPC2_CONFIGVALUE;
+        config_reg->CONFIG_SYSPC7 = SYS_SYSPC7_CONFIGVALUE;
+        config_reg->CONFIG_SYSPC8 = SYS_SYSPC8_CONFIGVALUE;
+        config_reg->CONFIG_SYSPC9 = SYS_SYSPC9_CONFIGVALUE;
+        config_reg->CONFIG_CSDIS = SYS_CSDIS_CONFIGVALUE;
+        config_reg->CONFIG_CDDIS = SYS_CDDIS_CONFIGVALUE;
+        config_reg->CONFIG_GHVSRC = SYS_GHVSRC_CONFIGVALUE;
+        config_reg->CONFIG_VCLKASRC = SYS_VCLKASRC_CONFIGVALUE;
+        config_reg->CONFIG_RCLKSRC = SYS_RCLKSRC_CONFIGVALUE;
+        config_reg->CONFIG_MSTGCR = SYS_MSTGCR_CONFIGVALUE;
+        config_reg->CONFIG_MINITGCR = SYS_MINITGCR_CONFIGVALUE;
+        config_reg->CONFIG_MSINENA = SYS_MSINENA_CONFIGVALUE;
+        config_reg->CONFIG_PLLCTL1 = SYS_PLLCTL1_CONFIGVALUE_2;
+        config_reg->CONFIG_PLLCTL2 = SYS_PLLCTL2_CONFIGVALUE;
+        config_reg->CONFIG_UERFLAG = SYS_UERFLAG_CONFIGVALUE;
+        /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+        if(LPO_TRIM_VALUE != 0xFFFFU)
+        {
+            config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_1;
+        }
+        else
+        {
+            config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_2;
+        }
+        config_reg->CONFIG_CLKTEST = SYS_CLKTEST_CONFIGVALUE;
+        config_reg->CONFIG_DFTCTRLREG1 = SYS_DFTCTRLREG1_CONFIGVALUE;
+        config_reg->CONFIG_DFTCTRLREG2 = SYS_DFTCTRLREG2_CONFIGVALUE;
+        config_reg->CONFIG_GPREG1 = SYS_GPREG1_CONFIGVALUE;
+        config_reg->CONFIG_RAMGCR = SYS_RAMGCR_CONFIGVALUE;
+        config_reg->CONFIG_BMMCR1 = SYS_BMMCR1_CONFIGVALUE;
+        config_reg->CONFIG_MMUGCR = SYS_MMUGCR_CONFIGVALUE;
+        config_reg->CONFIG_CLKCNTL = SYS_CLKCNTL_CONFIGVALUE;
+        config_reg->CONFIG_ECPCNTL = SYS_ECPCNTL_CONFIGVALUE;
+        config_reg->CONFIG_DEVCR1 = SYS_DEVCR1_CONFIGVALUE;
+        config_reg->CONFIG_SYSECR = SYS_SYSECR_CONFIGVALUE;
+
+        config_reg->CONFIG_PLLCTL3 = SYS2_PLLCTL3_CONFIGVALUE_2;
+        config_reg->CONFIG_STCCLKDIV = SYS2_STCCLKDIV_CONFIGVALUE;
+        config_reg->CONFIG_CLK2CNTL = SYS2_CLK2CNTL_CONFIGVALUE;
+        config_reg->CONFIG_VCLKACON1 = SYS2_VCLKACON1_CONFIGVALUE;
+        config_reg->CONFIG_CLKSLIP = SYS2_CLKSLIP_CONFIGVALUE;
+        config_reg->CONFIG_EFC_CTLEN = SYS2_EFC_CTLEN_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_SYSPC1 = systemREG1->SYSPC1;
+        config_reg->CONFIG_SYSPC2 = systemREG1->SYSPC2;
+        config_reg->CONFIG_SYSPC7 = systemREG1->SYSPC7;
+        config_reg->CONFIG_SYSPC8 = systemREG1->SYSPC8;
+        config_reg->CONFIG_SYSPC9 = systemREG1->SYSPC9;
+        config_reg->CONFIG_CSDIS = systemREG1->CSDIS;
+        config_reg->CONFIG_CDDIS = systemREG1->CDDIS;
+        config_reg->CONFIG_GHVSRC = systemREG1->GHVSRC;
+        config_reg->CONFIG_VCLKASRC = systemREG1->VCLKASRC;
+        config_reg->CONFIG_RCLKSRC = systemREG1->RCLKSRC;
+        config_reg->CONFIG_MSTGCR = systemREG1->MSTGCR;
+        config_reg->CONFIG_MINITGCR = systemREG1->MINITGCR;
+        config_reg->CONFIG_MSINENA = systemREG1->MSINENA;
+        config_reg->CONFIG_PLLCTL1 = systemREG1->PLLCTL1;
+        config_reg->CONFIG_PLLCTL2 = systemREG1->PLLCTL2;
+        config_reg->CONFIG_UERFLAG = systemREG1->SYSPC10;
+        config_reg->CONFIG_LPOMONCTL = systemREG1->LPOMONCTL;
+        config_reg->CONFIG_CLKTEST = systemREG1->CLKTEST;
+        config_reg->CONFIG_DFTCTRLREG1 = systemREG1->DFTCTRLREG1;
+        config_reg->CONFIG_DFTCTRLREG2 = systemREG1->DFTCTRLREG2;
+        config_reg->CONFIG_GPREG1 = systemREG1->GPREG1;
+        config_reg->CONFIG_RAMGCR = systemREG1->RAMGCR;
+        config_reg->CONFIG_BMMCR1 = systemREG1->BMMCR1;
+        config_reg->CONFIG_MMUGCR = systemREG1->CPURSTCR;
+        config_reg->CONFIG_CLKCNTL = systemREG1->CLKCNTL;
+        config_reg->CONFIG_ECPCNTL = systemREG1->ECPCNTL;
+        config_reg->CONFIG_DEVCR1 = systemREG1->DEVCR1;
+        config_reg->CONFIG_SYSECR = systemREG1->SYSECR;
+
+        /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_PLLCTL3 = systemREG2->PLLCTL3;
+        config_reg->CONFIG_STCCLKDIV = systemREG2->STCCLKDIV;
+        config_reg->CONFIG_CLK2CNTL = systemREG2->CLK2CNTL;
+        config_reg->CONFIG_VCLKACON1 = systemREG2->VCLKACON1;
+        config_reg->CONFIG_CLKSLIP = systemREG2->CLKSLIP;
+        config_reg->CONFIG_EFC_CTLEN = systemREG2->EFC_CTLEN;
+    }
+}
+
+/** @fn void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*   @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*   @param[in] type:    whether initial or current value of the configuration registers need to be stored
+*                       - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*                       - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : SYSTEM_SourceId_009 */
+/* DesignId : SYSTEM_DesignId_009 */
+/* Requirements : HL_SR506 */
+void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_FRDCNTL = TCMFLASH_FRDCNTL_CONFIGVALUE;
+        config_reg->CONFIG_FEDACCTRL1 = TCMFLASH_FEDACCTRL1_CONFIGVALUE;
+        config_reg->CONFIG_FEDACCTRL2 = TCMFLASH_FEDACCTRL2_CONFIGVALUE;
+        config_reg->CONFIG_FEDACSDIS = TCMFLASH_FEDACSDIS_CONFIGVALUE;
+        config_reg->CONFIG_FBPROT = TCMFLASH_FBPROT_CONFIGVALUE;
+        config_reg->CONFIG_FBSE = TCMFLASH_FBSE_CONFIGVALUE;
+        config_reg->CONFIG_FBAC = TCMFLASH_FBAC_CONFIGVALUE;
+        config_reg->CONFIG_FBFALLBACK = TCMFLASH_FBFALLBACK_CONFIGVALUE;
+        config_reg->CONFIG_FPAC1 = TCMFLASH_FPAC1_CONFIGVALUE;
+        config_reg->CONFIG_FPAC2 = TCMFLASH_FPAC2_CONFIGVALUE;
+        config_reg->CONFIG_FMAC = TCMFLASH_FMAC_CONFIGVALUE;
+        config_reg->CONFIG_FLOCK = TCMFLASH_FLOCK_CONFIGVALUE;
+        config_reg->CONFIG_FDIAGCTRL = TCMFLASH_FDIAGCTRL_CONFIGVALUE;
+        config_reg->CONFIG_FEDACSDIS2 = TCMFLASH_FEDACSDIS2_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_FRDCNTL = flashWREG->FRDCNTL;
+        config_reg->CONFIG_FEDACCTRL1 = flashWREG->FEDACCTRL1;
+        config_reg->CONFIG_FEDACCTRL2 = flashWREG->FEDACCTRL2;
+        config_reg->CONFIG_FEDACSDIS = flashWREG->FEDACSDIS;
+        config_reg->CONFIG_FBPROT = flashWREG->FBPROT;
+        config_reg->CONFIG_FBSE = flashWREG->FBSE;
+        config_reg->CONFIG_FBAC = flashWREG->FBAC;
+        config_reg->CONFIG_FBFALLBACK = flashWREG->FBFALLBACK;
+        config_reg->CONFIG_FPAC1 = flashWREG->FPAC1;
+        config_reg->CONFIG_FPAC2 = flashWREG->FPAC2;
+        config_reg->CONFIG_FMAC = flashWREG->FMAC;
+        config_reg->CONFIG_FLOCK = flashWREG->FLOCK;
+        config_reg->CONFIG_FDIAGCTRL = flashWREG->FDIAGCTRL;
+        config_reg->CONFIG_FEDACSDIS2 = flashWREG->FEDACSDIS2;
+    }
+}
+
+
+
+/** @fn void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*   @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
+*   @param[in] type:    whether initial or current value of the configuration registers need to be stored
+*                       - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*                       - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : SYSTEM_SourceId_010 */
+/* DesignId : SYSTEM_DesignId_010 */
+/* Requirements : HL_SR506 */
+void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_RAMCTRL[0U] = SRAM_RAMCTRL_CONFIGVALUE;
+        config_reg->CONFIG_RAMTHRESHOLD[0U] = SRAM_RAMTHRESHOLD_CONFIGVALUE;
+        config_reg->CONFIG_RAMINTCTRL[0U] = SRAM_RAMINTCTRL_CONFIGVALUE;
+        config_reg->CONFIG_RAMTEST[0U] = SRAM_RAMTEST_CONFIGVALUE;
+        config_reg->CONFIG_RAMADDRDECVECT[0U] = SRAM_RAMADDRDECVECT_CONFIGVALUE;
+
+        config_reg->CONFIG_RAMCTRL[1U] = SRAM_RAMCTRL_CONFIGVALUE;
+        config_reg->CONFIG_RAMTHRESHOLD[1U] = SRAM_RAMTHRESHOLD_CONFIGVALUE;
+        config_reg->CONFIG_RAMINTCTRL[1U] = SRAM_RAMINTCTRL_CONFIGVALUE;
+        config_reg->CONFIG_RAMTEST[1U] = SRAM_RAMTEST_CONFIGVALUE;
+        config_reg->CONFIG_RAMADDRDECVECT[1U] = SRAM_RAMADDRDECVECT_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_RAMCTRL[0U] = tcram1REG->RAMCTRL;
+        config_reg->CONFIG_RAMTHRESHOLD[0U] = tcram1REG->RAMTHRESHOLD;
+        config_reg->CONFIG_RAMINTCTRL[0U] = tcram1REG->RAMINTCTRL;
+        config_reg->CONFIG_RAMTEST[0U] = tcram1REG->RAMTEST;
+        config_reg->CONFIG_RAMADDRDECVECT[0U] = tcram1REG->RAMADDRDECVECT;
+
+        /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_RAMCTRL[1U] = tcram2REG->RAMCTRL;
+        config_reg->CONFIG_RAMTHRESHOLD[1U] = tcram2REG->RAMTHRESHOLD;
+        config_reg->CONFIG_RAMINTCTRL[1U] = tcram2REG->RAMINTCTRL;
+        config_reg->CONFIG_RAMTEST[1U] = tcram2REG->RAMTEST;
+        config_reg->CONFIG_RAMADDRDECVECT[1U] = tcram2REG->RAMADDRDECVECT;
+    }
+}
+
+/** @fn customTrimLPO(void)
+*   @brief custom function to initilize LPO trim values
+*
+*   This function initializes default LPO trim values if OTP value is 0XFFFF,
+*   user can also write their own code to handle this case .
+*
+*/
+void customTrimLPO(void)
+{
+    /* User can write logic to handle the case where LPO trim is set to 0xFFFFu */
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+    
+    /* Load default trimLPO value */
+     systemREG1->LPOMONCTL   = (uint32)((uint32)1U << 24U)
+                             | (uint32)((uint32)16U << 8U)
+                             | (uint32)((uint32)16U);
+                                
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+}
diff --git a/src/arch/rm46l8lp/prompt b/src/arch/rm46l8lp/prompt
new file mode 100644
index 0000000..673d232
--- /dev/null
+++ b/src/arch/rm46l8lp/prompt
@@ -0,0 +1 @@
+Hercules RM46L8 Launchpad