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authorDaniel Friesel <derf@finalrewind.org>2018-08-08 14:59:02 +0200
committerDaniel Friesel <derf@finalrewind.org>2018-08-08 14:59:02 +0200
commite7f1024732ee9bac13fbf2e2439106f9f3577db7 (patch)
tree16e52dac6be007b3ca6b0f38f3226a12fb828bc7 /src/arch/blinkenrocket/arch.cc
parent4a2747f0c508cd5af830c14e43ffeaf3fe25e4e7 (diff)
Add Blinkenrocket arch
Diffstat (limited to 'src/arch/blinkenrocket/arch.cc')
-rw-r--r--src/arch/blinkenrocket/arch.cc85
1 files changed, 85 insertions, 0 deletions
diff --git a/src/arch/blinkenrocket/arch.cc b/src/arch/blinkenrocket/arch.cc
new file mode 100644
index 0000000..8042679
--- /dev/null
+++ b/src/arch/blinkenrocket/arch.cc
@@ -0,0 +1,85 @@
+#include "arch.h"
+#include <avr/io.h>
+#include <avr/interrupt.h>
+#include <util/delay.h>
+
+void Arch::setup(void)
+{
+#ifdef TIMER_CYCLES
+ TCCR0A = _BV(CS00);
+#endif
+
+#if defined(WITH_LOOP) || defined(TIMER_S)
+ TCCR1A = 0;
+ TCCR1B = _BV(WGM12) | _BV(CS12) | _BV(CS10); // /1024
+ OCR1A = F_CPU / 1024;
+ TIMSK1 = _BV(OCIE1A);
+#endif
+
+/*
+#ifdef TIMER_US
+ // 16MHz/8 -> 2MHz timer
+ TCCR1A = 0;
+ TCCR2B = _BV(CS21);
+#endif
+*/
+ sei();
+}
+
+#ifdef WITH_WAKEUP
+void wakeup();
+#endif
+
+#if defined(WITH_LOOP) || defined(TIMER_S)
+
+#include "driver/uptime.h"
+void loop();
+
+#endif
+
+void Arch::idle_loop(void)
+{
+ while (1) {
+ SMCR = _BV(SE);
+ asm("sleep");
+ SMCR = 0;
+ asm("wdr");
+#ifdef WITH_LOOP
+ loop();
+#endif
+#ifdef WITH_WAKEUP
+ wakeup();
+#endif
+#ifdef TIMER_S
+ uptime.tick_s();
+#endif
+ }
+}
+
+void Arch::idle(void)
+{
+ SMCR = _BV(SE);
+ asm("sleep");
+ SMCR = 0;
+ asm("wdr");
+}
+
+void Arch::delay_us(unsigned char const us)
+{
+ _delay_us(us);
+}
+
+void Arch::delay_ms(unsigned char const ms)
+{
+ _delay_ms(ms);
+}
+
+Arch arch;
+
+#if defined(WITH_LOOP) || defined(TIMER_S)
+
+ISR(TIMER1_COMPA_vect)
+{
+}
+
+#endif