diff options
Diffstat (limited to 'Microbenchmarks/MRAM-Latency/dpu/copy.c')
| -rw-r--r-- | Microbenchmarks/MRAM-Latency/dpu/copy.c | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/Microbenchmarks/MRAM-Latency/dpu/copy.c b/Microbenchmarks/MRAM-Latency/dpu/copy.c index 5cfd141..de9cca8 100644 --- a/Microbenchmarks/MRAM-Latency/dpu/copy.c +++ b/Microbenchmarks/MRAM-Latency/dpu/copy.c @@ -45,7 +45,9 @@ int main_kernel1() { uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T); dpu_results_t *result = &DPU_RESULTS[tasklet_id]; - result->cycles = 0; + result->count = 0; + result->r_cycles = 0; + result->w_cycles = 0; // Address of the current processing block in MRAM uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2)); @@ -57,27 +59,20 @@ int main_kernel1() { for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){ __mram_ptr void const* address_A = (__mram_ptr void const*)(mram_base_addr_A + byte_index); __mram_ptr void* address_B = (__mram_ptr void*)(mram_base_addr_B + byte_index); -#ifdef READ // Barrier timer_start(&cycles); // START TIMER -#endif // Load cache with current MRAM block mram_read(address_A, cache_A, BLOCK_SIZE); -#ifdef READ // Barrier - result->cycles += timer_stop(&cycles); // STOP TIMER -#endif + result->r_cycles += timer_stop(&cycles); // STOP TIMER -#ifdef WRITE // Barrier timer_start(&cycles); // START TIMER -#endif // Write cache to current MRAM block mram_write(cache_A, address_B, BLOCK_SIZE); -#ifdef WRITE // Barrier - result->cycles += timer_stop(&cycles); // STOP TIMER -#endif + result->w_cycles += timer_stop(&cycles); // STOP TIMER + result->count += 1; } return 0; |