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-rw-r--r--VA/dpu/task.c109
1 files changed, 62 insertions, 47 deletions
diff --git a/VA/dpu/task.c b/VA/dpu/task.c
index bb41303..9622911 100644
--- a/VA/dpu/task.c
+++ b/VA/dpu/task.c
@@ -15,10 +15,11 @@
__host dpu_arguments_t DPU_INPUT_ARGUMENTS;
// vector_addition: Computes the vector addition of a cached block
-static void vector_addition(T *bufferB, T *bufferA, unsigned int l_size) {
- for (unsigned int i = 0; i < l_size; i++){
- bufferB[i] += bufferA[i];
- }
+static void vector_addition(T *bufferB, T *bufferA, unsigned int l_size)
+{
+ for (unsigned int i = 0; i < l_size; i++) {
+ bufferB[i] += bufferA[i];
+ }
}
// Barrier
@@ -26,53 +27,67 @@ BARRIER_INIT(my_barrier, NR_TASKLETS);
extern int main_kernel1(void);
-int (*kernels[nr_kernels])(void) = {main_kernel1};
+int (*kernels[nr_kernels])(void) = { main_kernel1 };
-int main(void) {
- // Kernel
- return kernels[DPU_INPUT_ARGUMENTS.kernel]();
+int main(void)
+{
+ // Kernel
+ return kernels[DPU_INPUT_ARGUMENTS.kernel] ();
}
// main_kernel1
-int main_kernel1() {
- unsigned int tasklet_id = me();
+int main_kernel1()
+{
+ unsigned int tasklet_id = me();
#if PRINT
- printf("tasklet_id = %u\n", tasklet_id);
+ printf("tasklet_id = %u\n", tasklet_id);
#endif
- if (tasklet_id == 0){ // Initialize once the cycle counter
- mem_reset(); // Reset the heap
- }
- // Barrier
- barrier_wait(&my_barrier);
-
- uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes
- uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes
-
- // Address of the current processing block in MRAM
- uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;
- uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;
- uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);
-
- // Initialize a local cache to store the MRAM block
- T *cache_A = (T *) mem_alloc(BLOCK_SIZE);
- T *cache_B = (T *) mem_alloc(BLOCK_SIZE);
-
- for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){
-
- // Bound checking
- uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;
-
- // Load cache with current MRAM block
- mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);
- mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, l_size_bytes);
-
- // Computer vector addition
- vector_addition(cache_B, cache_A, l_size_bytes >> DIV);
-
- // Write cache to current MRAM block
- mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), l_size_bytes);
-
- }
-
- return 0;
+ if (tasklet_id == 0) { // Initialize once the cycle counter
+ mem_reset(); // Reset the heap
+ }
+ // Barrier
+ barrier_wait(&my_barrier);
+
+ uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes
+ uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes
+
+ // Address of the current processing block in MRAM
+ uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;
+ uint32_t mram_base_addr_A = (uint32_t) DPU_MRAM_HEAP_POINTER;
+ uint32_t mram_base_addr_B =
+ (uint32_t) (DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);
+
+ // Initialize a local cache to store the MRAM block
+ T *cache_A = (T *) mem_alloc(BLOCK_SIZE);
+ T *cache_B = (T *) mem_alloc(BLOCK_SIZE);
+
+ for (unsigned int byte_index = base_tasklet;
+ byte_index < input_size_dpu_bytes;
+ byte_index += BLOCK_SIZE * NR_TASKLETS) {
+
+ // Bound checking
+ uint32_t l_size_bytes =
+ (byte_index + BLOCK_SIZE >=
+ input_size_dpu_bytes) ? (input_size_dpu_bytes -
+ byte_index) : BLOCK_SIZE;
+
+ // Load cache with current MRAM block
+ mram_read((__mram_ptr void const *)(mram_base_addr_A +
+ byte_index), cache_A,
+ l_size_bytes);
+ mram_read((__mram_ptr void const *)(mram_base_addr_B +
+ byte_index), cache_B,
+ l_size_bytes);
+
+ // Computer vector addition
+ vector_addition(cache_B, cache_A, l_size_bytes >> DIV);
+
+ // Write cache to current MRAM block
+ mram_write(cache_B,
+ (__mram_ptr void *)(mram_base_addr_B + byte_index),
+ l_size_bytes);
+
+ }
+
+ return 0;
}