1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
|
#include <avr/io.h>
#include <avr/interrupt.h>
; Onewire iButton / SmartButton slave. Has the 64bit ID set below.
;
; Tested and working with a DS2482-100 and an IBL USB iButton reader. Should
; mostly adhere to the standard, but nothing is guaranteed.
; Set the 64bit ID (including 8bit CRC) here, in the order in which they are
; printed on the button (see
; <https://wiki.chaosdorf.de/images/f/fc/Smartbutton.jpg>).
; Note: The bytes are sent in reversed order. This has also been observed
; on off-the-shelf smartbuttons / iButtons.
#define ADDR1 0xC4
#define ADDR2 0x00
#define ADDR3 0x00
#define ADDR4 0x09
#define ADDR5 0x7d
#define ADDR6 0x79
#define ADDR7 0x04
#define ADDR8 0x01
; ==========================================================================
; You should not need to change things below, unless you're not using PD3
; as OWI data pin.
; ==========================================================================
; Register summary:
; r1: NULLREG - constant 0 (set up by avr-gcc)
; r16: temporary
; r20: LASTCMD
; r21: BUF
; r22: POS
; r23: APOS
; r24: BYTE
; r25: SEARCHSTEP
; The LCNT registers count how many microseconds have passed
; since the last low-to-high / high-to-low transition. In the main loop,
; only r28 and r29 (Y) are incremented (precisely once per microsecond).
; Note that this requires an AVR operating at 8MHz.
#define LCNTH r29
#define LCNTL r28
; The last complete command byte received from the master. Once this is
; set, we start writing data onto the bus. Reset at bus resets and once a
; command is done
#define LASTCMD r20
; command buffer, always initialized to 0
#define BUF r21
; bitmask for the current buffer (either BUF or BYTE) position.
; Left-shifted after each bit
#define POS r22
; Position in the 8-byte address sequence
#define APOS r23
; current byte in this sequence
#define BYTE r24
; the SEARCH ROM command consits of three steps: send a bit of our address,
; send the inverted bit of our address, receive the bit the master chose
; to proceed with. the current position in this cycle is stored here
#define SEARCHSTEP r25
#define CMD_READROM 0x33
#define CMD_SEARCHROM 0xf0
#define SEARCHSTEP_BIT 0
#define SEARCHSTEP_INV 1
#define SEARCHSTEP_DIRECTION 2
#define NULLREG r1
.text
.global main
main:
; watchdog reset after ~4 seconds
out _SFR_IO_ADDR(MCUSR), NULLREG
ldi r16, (_BV(WDCE) | _BV(WDE))
out _SFR_IO_ADDR(WDTCR), r16
ldi r16, (_BV(WDE) | _BV(WDP3))
out _SFR_IO_ADDR(WDTCR), r16
; rising edge for reset/presence signals and reading data,
; falling edge for writing.
ldi r16, _BV(ISC10)
out _SFR_IO_ADDR(MCUCR), r16
ldi r16, _BV(INT1)
out _SFR_IO_ADDR(GIMSK), r16
; disable Analog Comparator
sbi _SFR_IO_ADDR(ACSR), ACD
; disable USI / USART
sbi _SFR_IO_ADDR(PRR), PRUSI
sbi _SFR_IO_ADDR(PRR), PRUSART
clr POS
clr APOS
clr _SFR_IO_ADDR(DDRD)
clr _SFR_IO_ADDR(PORTD)
sbi _SFR_IO_ADDR(DDRB), PB2
cbi _SFR_IO_ADDR(PORTB), PB2
sei
clr LCNTL
clr LCNTH
; increment LCNT once per microsecond
loop:
adiw LCNTL, 1
wdr
nop
nop
nop
nop
rjmp loop
delay_short:
ldi r16, 15
wdr
wdr
wdr
wdr
subi r16, 1
cpi r16, 0
brne .-14
ret
delay_long:
ldi r16, 120
wdr
wdr
wdr
wdr
subi r16, 1
cpi r16, 0
brne .-14
ret
.global INT1_vect
INT1_vect:
sbis _SFR_IO_ADDR(PIND), PD3
rjmp check_cmd
; Read OWI command
cpi LCNTH, 0
breq check_lastcmd
; send presence signal
sbi _SFR_IO_ADDR(DDRD), PD3
rcall delay_long
cbi _SFR_IO_ADDR(DDRD), PD3
clr LASTCMD
clr BUF
ldi POS, 1
clr APOS
wdr
in r16, _SFR_IO_ADDR(GIFR)
ori r16, _BV(INTF1)
out _SFR_IO_ADDR(GIFR), r16
reti
check_lastcmd:
cpi LASTCMD, 0
brne check_lastcmd_nope
cpi LCNTL, 16
brsh check_lastcmd_lcntl_done
or BUF, POS
check_lastcmd_lcntl_done:
cpi POS, 0x80
breq command_received
lsl POS
check_lastcmd_nope:
reti
command_received:
mov LASTCMD, BUF
ldi POS, 1
clr APOS
ldi BYTE, ~ADDR8
ldi SEARCHSTEP, SEARCHSTEP_BIT
in r16, _SFR_IO_ADDR(GIFR)
ori r16, _BV(INTF1)
out _SFR_IO_ADDR(GIFR), r16
reti
check_cmd:
cpi LASTCMD, CMD_READROM
brne check_cmd_searchrom
; we got READ ROM
mov r16, BYTE
and r16, POS
breq pos_bit_is_null
; (BYTE & POS) is true -> ADDRx has a 0 bit, keep data low
sbi _SFR_IO_ADDR(DDRD), PD3
rcall delay_short
cbi _SFR_IO_ADDR(DDRD), PD3
wdr
in r16, _SFR_IO_ADDR(GIFR)
ori r16, _BV(INTF1)
out _SFR_IO_ADDR(GIFR), r16
pos_bit_is_null:
cpi POS, 0x80
breq pos_is_0x80
lsl POS
rjmp check_cmd_cleanup
pos_is_0x80:
ldi POS, 1
; (1)
; Put next ADDRx into BYTE or reset state if we sent all 8 bytes.
; APOS is checked for 1 / 2 / 3 /... in turn and the corresponding
; address set where appropriate. Since there are no shortcuts, this
; block has a constant execution time of ~4us
inc APOS ;APOS++
cpi APOS, 1
brne .+2 ; if (APOS == 1) {
ldi BYTE, ~ADDR7
cpi APOS, 2 ; }
brne .+2 ; if (APOS == 2) {
ldi BYTE, ~ADDR6
cpi APOS, 3 ; }
brne .+2 ; if (APOS == 3) {
ldi BYTE, ~ADDR5
cpi APOS, 4 ; }
brne .+2 ; if (APOS == 4) {
ldi BYTE, ~ADDR4
cpi APOS, 5 ; }
brne .+2 ; if (APOS == 5) {
ldi BYTE, ~ADDR3
cpi APOS, 6 ; }
brne .+2 ; if (APOS == 6) {
ldi BYTE, ~ADDR2
cpi APOS, 7 ; }
brne .+2 ; if (APOS == 7) {
ldi BYTE, ~ADDR1
cpi APOS, 8 ; }
brne .+4 ; if (APOS == 8) {
clr LASTCMD
clr BUF ; }
rjmp check_cmd_cleanup
check_cmd_searchrom:
cpi LASTCMD, CMD_SEARCHROM
brne check_cmd_cleanup
cpi SEARCHSTEP, SEARCHSTEP_BIT
brne check_searchstep_2
mov r16, BYTE
and r16, POS
brne check_searchstep_2
rjmp send_ack
check_searchstep_2:
cpi SEARCHSTEP, SEARCHSTEP_INV
brne check_search_lt_direction
mov r16, BYTE
and r16, POS
breq check_search_lt_direction
send_ack:
rcall delay_short
cbi _SFR_IO_ADDR(DDRD), PD3
wdr
in r16, _SFR_IO_ADDR(GIFR)
ori r16, _BV(INTF1)
out _SFR_IO_ADDR(GIFR), r16
check_search_lt_direction:
cpi SEARCHSTEP, SEARCHSTEP_DIRECTION
brge check_pos
inc SEARCHSTEP
check_pos:
cpi POS, 0x80
breq check_pos_else
lsl POS
ldi SEARCHSTEP, SEARCHSTEP_BIT
rjmp check_cmd_cleanup
check_pos_else:
ldi SEARCHSTEP, SEARCHSTEP_BIT
ldi POS, 1
; see (1)
inc APOS
cpi APOS, 1
brne .+2
ldi BYTE, ~ADDR7
cpi APOS, 2
brne .+2
ldi BYTE, ~ADDR6
cpi APOS, 3
brne .+2
ldi BYTE, ~ADDR5
cpi APOS, 4
brne .+2
ldi BYTE, ~ADDR4
cpi APOS, 5
brne .+2
ldi BYTE, ~ADDR3
cpi APOS, 6
brne .+2
ldi BYTE, ~ADDR2
cpi APOS, 7
brne .+2
ldi BYTE, ~ADDR1
cpi APOS, 8
brne .+4
clr LASTCMD
clr BUF
check_cmd_cleanup:
clr LCNTH
ldi LCNTL, 1
reti
|