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| author | Daniel Friesel <daniel.friesel@uos.de> | 2020-08-27 10:45:46 +0200 |
|---|---|---|
| committer | Daniel Friesel <daniel.friesel@uos.de> | 2020-08-27 10:45:46 +0200 |
| commit | a474830ceed996fd659fcbe21e2c5d903197fa0f (patch) | |
| tree | a88bfcdf33a1f8802f324a5b3368ab4a6a4e7efb | |
| parent | e64ec4bd8eef73af8051a0c833a8576ff610f51a (diff) | |
Show proper power plot if available
| -rwxr-xr-x | bin/dlog-viewer | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bin/dlog-viewer b/bin/dlog-viewer index a4f8ba8..8270705 100755 --- a/bin/dlog-viewer +++ b/bin/dlog-viewer @@ -283,7 +283,7 @@ def main(): export_csv(dlog, args.csv_export) if args.plot: - if dlog.all_data_slots_have_power() and False: + if dlog.all_data_slots_have_power(): show_power_plot(dlog) else: show_raw_plot(dlog) |