diff options
| author | Daniel Friesel <derf@finalrewind.org> | 2021-09-19 18:50:38 +0200 |
|---|---|---|
| committer | Daniel Friesel <derf@finalrewind.org> | 2021-09-19 18:50:38 +0200 |
| commit | 521a5fce744d89d2eee010c4d8f6bbf525b07de7 (patch) | |
| tree | 38592baabbb7e0cb0aa6b523dadcb09a71b51b42 /src/arch/lora32u4ii/driver/spi.cc | |
| parent | c59f87f58732bad349b05770ee7c6a43e6bb7258 (diff) | |
lora32u4ii spi: go back to 2MHz
Diffstat (limited to 'src/arch/lora32u4ii/driver/spi.cc')
| -rw-r--r-- | src/arch/lora32u4ii/driver/spi.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/lora32u4ii/driver/spi.cc b/src/arch/lora32u4ii/driver/spi.cc index 5c782c8..c2cad08 100644 --- a/src/arch/lora32u4ii/driver/spi.cc +++ b/src/arch/lora32u4ii/driver/spi.cc @@ -1,3 +1,8 @@ +/* + * Copyright 2021 Daniel Friesel + * + * SPDX-License-Identifier: BSD-2-Clause + */ #include "driver/spi.h" #include "driver/gpio.h" #include "arch.h" @@ -11,7 +16,7 @@ signed char SPI::setup() // Configure SCK and MOSI as output DDRB |= _BV(PB2) | _BV(PB1); // up to 2 MHz SPI clock - SPCR = _BV(SPE) | _BV(MSTR) | _BV(SPR0); + SPCR = _BV(SPE) | _BV(MSTR); } signed char SPI::xmit( |