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authorDaniel Friesel <daniel.friesel@uos.de>2019-06-21 11:09:42 +0200
committerDaniel Friesel <daniel.friesel@uos.de>2019-06-21 11:09:42 +0200
commit0dbe2001333b8f6a01e3082ce16e7326db801991 (patch)
treef35f2643372f94602566f5513555a68d0338f7ac /src/driver
parent6f9e50ca58623e551baa81fa635471b0b340f5af (diff)
add basic nRF24 driver
Diffstat (limited to 'src/driver')
-rw-r--r--src/driver/nrf24l01.cc95
1 files changed, 95 insertions, 0 deletions
diff --git a/src/driver/nrf24l01.cc b/src/driver/nrf24l01.cc
new file mode 100644
index 0000000..144158c
--- /dev/null
+++ b/src/driver/nrf24l01.cc
@@ -0,0 +1,95 @@
+/*
+ * Based on https://github.com/nRF24/RF24
+ */
+
+#include <stdlib.h>
+
+#include "driver/nrf24l01.h"
+#include "driver/nrf24l01/registers.h"
+#include "driver/spi_b.h"
+#include "driver/gpio.h"
+#include "arch.h"
+
+#ifndef NRF24L01_EN_PIN
+#error makeflag nrf24l01_en_pin required
+#endif
+
+#ifndef NRF24L01_CS_PIN
+#error makeflag nrf24l01_cs_pin required
+#endif
+
+void Nrf24l01::setup()
+{
+ spi.setup();
+ gpio.output(NRF24L01_EN_PIN);
+ gpio.output(NRF24L01_CS_PIN);
+ gpio.write(NRF24L01_EN_PIN, 0);
+ csnHigh();
+ arch.delay_ms(5);
+
+ // Reset NRF_CONFIG and enable 16-bit CRC.
+ writeRegister( NRF_CONFIG, 0b00001100 ) ;
+
+ // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
+ // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
+ // sizes must never be used. See documentation for a more complete explanation.
+ setRetries(5,15);
+
+ // Reset value is MAX
+ setPALevel( RF24_PA_MAX ) ;
+
+}
+
+void Nrf24l01::setRetries(uint8_t delay, uint8_t count)
+{
+ writeRegister(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
+}
+
+void Nrf24l01::setPALevel(uint8_t level)
+{
+ uint8_t setup = readRegister(RF_SETUP) & 0b11111000;
+
+ if(level > 3){ // If invalid level, go to max PA
+ level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit
+ }else{
+ level = (level << 1) + 1; // Else set level as requested
+ }
+
+ writeRegister( RF_SETUP, setup |= level ) ; // Write it to the chip
+}
+
+uint8_t Nrf24l01::getStatus()
+{
+ txbuf[0] = NOP;
+ beginTransaction();
+ spi.xmit(1, txbuf, 1, rxbuf);
+ endTransaction();
+
+ return rxbuf[0];
+}
+
+uint8_t Nrf24l01::readRegister(uint8_t reg)
+{
+ txbuf[0] = R_REGISTER | ( REGISTER_MASK & reg );
+ txbuf[1] = NOP;
+
+ beginTransaction();
+ spi.xmit(2, txbuf, 2, rxbuf);
+ endTransaction();
+
+ return rxbuf[1];
+}
+
+uint8_t Nrf24l01::writeRegister(uint8_t reg, uint8_t value)
+{
+ txbuf[0] = W_REGISTER | (REGISTER_MASK & reg);
+ txbuf[1] = value;
+
+ beginTransaction();
+ spi.xmit(2, txbuf, 1, rxbuf);
+ endTransaction();
+
+ return rxbuf[0];
+}
+
+Nrf24l01 nrf24l01;