diff options
| author | Birte Kristina Friesel <birte.friesel@uos.de> | 2023-12-15 15:09:15 +0100 |
|---|---|---|
| committer | Birte Kristina Friesel <birte.friesel@uos.de> | 2023-12-15 15:09:15 +0100 |
| commit | a3e2763c547352544b320aaab626d173680a6a15 (patch) | |
| tree | 097b81aed17b7e95516db05e61b5dbfebda43fd2 /Microbenchmarks/WRAM/dpu | |
| parent | 3341ff57ab4464a4c3d15504df228ddc779c9fd4 (diff) | |
WRAM copy: report latency and throughput
Diffstat (limited to 'Microbenchmarks/WRAM/dpu')
| -rw-r--r-- | Microbenchmarks/WRAM/dpu/task.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/Microbenchmarks/WRAM/dpu/task.c b/Microbenchmarks/WRAM/dpu/task.c index 9ded3da..6e54b0b 100644 --- a/Microbenchmarks/WRAM/dpu/task.c +++ b/Microbenchmarks/WRAM/dpu/task.c @@ -63,6 +63,7 @@ int main_kernel1() { dpu_results_t *result = &DPU_RESULTS[tasklet_id]; result->cycles = 0; + result->count = 0; const uint32_t A_SIZE = (BLOCK_SIZE >> DIV) << 2; // Address of the current processing block in MRAM @@ -81,7 +82,7 @@ int main_kernel1() { // Load cache with current MRAM block mram_read((__mram_ptr void const*)(mram_base_addr_A + A_byte_index), cache_A, A_SIZE); mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, BLOCK_SIZE); - mram_read((__mram_ptr void const*)(mram_base_addr_C + byte_index), cache_C, BLOCK_SIZE); // Clean cache_C + //mram_read((__mram_ptr void const*)(mram_base_addr_C + byte_index), cache_C, BLOCK_SIZE); // Clean cache_C #ifdef WRAM // Barrier @@ -102,6 +103,7 @@ int main_kernel1() { mram_write(cache_C, (__mram_ptr void*)(mram_base_addr_C + byte_index), BLOCK_SIZE); A_byte_index += A_SIZE * NR_TASKLETS; + result->count += 1; } #ifndef WRAM |