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authorJuan Gomez Luna <juan.gomez@safari.ethz.ch>2021-06-16 19:46:05 +0200
committerJuan Gomez Luna <juan.gomez@safari.ethz.ch>2021-06-16 19:46:05 +0200
commit3de4b495fb176eba9a0eb517a4ce05903cb67acb (patch)
treefc6776a94549d2d4039898f183dbbeb2ce013ba9 /VA/dpu/task.c
parentef5c3688c486b80a56d3c1cded25f2b2387f2668 (diff)
PrIM -- first commit
Diffstat (limited to 'VA/dpu/task.c')
-rw-r--r--VA/dpu/task.c78
1 files changed, 78 insertions, 0 deletions
diff --git a/VA/dpu/task.c b/VA/dpu/task.c
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+/*
+* Vector addition with multiple tasklets
+*
+*/
+#include <stdint.h>
+#include <stdio.h>
+#include <defs.h>
+#include <mram.h>
+#include <alloc.h>
+#include <perfcounter.h>
+#include <barrier.h>
+
+#include "../support/common.h"
+
+__host dpu_arguments_t DPU_INPUT_ARGUMENTS;
+
+// vector_addition: Computes the vector addition of a cached block
+static void vector_addition(T *bufferB, T *bufferA, unsigned int l_size) {
+ for (unsigned int i = 0; i < l_size; i++){
+ bufferB[i] += bufferA[i];
+ }
+}
+
+// Barrier
+BARRIER_INIT(my_barrier, NR_TASKLETS);
+
+extern int main_kernel1(void);
+
+int (*kernels[nr_kernels])(void) = {main_kernel1};
+
+int main(void) {
+ // Kernel
+ return kernels[DPU_INPUT_ARGUMENTS.kernel]();
+}
+
+// main_kernel1
+int main_kernel1() {
+ unsigned int tasklet_id = me();
+#if PRINT
+ printf("tasklet_id = %u\n", tasklet_id);
+#endif
+ if (tasklet_id == 0){ // Initialize once the cycle counter
+ mem_reset(); // Reset the heap
+ }
+ // Barrier
+ barrier_wait(&my_barrier);
+
+ uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes
+ uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes
+
+ // Address of the current processing block in MRAM
+ uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;
+ uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;
+ uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);
+
+ // Initialize a local cache to store the MRAM block
+ T *cache_A = (T *) mem_alloc(BLOCK_SIZE);
+ T *cache_B = (T *) mem_alloc(BLOCK_SIZE);
+
+ for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){
+
+ // Bound checking
+ uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;
+
+ // Load cache with current MRAM block
+ mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);
+ mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, l_size_bytes);
+
+ // Computer vector addition
+ vector_addition(cache_B, cache_A, l_size_bytes >> DIV);
+
+ // Write cache to current MRAM block
+ mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), l_size_bytes);
+
+ }
+
+ return 0;
+}