blob: 4247aac38d75877a7b3b203fc895018e81ae82a8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
|
/*
* STREAM Scale
*
*/
#include <stdint.h>
#include <stdio.h>
#include <defs.h>
#include <mram.h>
#include <alloc.h>
#include <perfcounter.h>
#include <barrier.h>
#include "../support/common.h"
#include "../support/cyclecount.h"
__host dpu_arguments_t DPU_INPUT_ARGUMENTS;
__host dpu_results_t DPU_RESULTS[NR_TASKLETS];
// Scale
static void scale_dpu(T *bufferB, T *bufferA, T scalar) {
#pragma unroll
for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++){
bufferB[i] = scalar * bufferA[i];
}
}
// Barrier
BARRIER_INIT(my_barrier, NR_TASKLETS);
extern int main_kernel1(void);
int (*kernels[nr_kernels])(void) = {main_kernel1};
int main(void) {
// Kernel
return kernels[DPU_INPUT_ARGUMENTS.kernel]();
}
// main_kernel1
int main_kernel1() {
unsigned int tasklet_id = me();
#if PRINT
printf("tasklet_id = %u\n", tasklet_id);
#endif
if (tasklet_id == 0){ // Initialize once the cycle counter
mem_reset(); // Reset the heap
perfcounter_config(COUNT_CYCLES, true);
}
perfcounter_cycles cycles;
// Barrier
barrier_wait(&my_barrier);
#ifndef WRAM
timer_start(&cycles); // START TIMER
#endif
uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);
T scalar = (T)input_size_dpu; // Simply use this number as a scalar
dpu_results_t *result = &DPU_RESULTS[tasklet_id];
result->cycles = 0;
// Address of the current processing block in MRAM
uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));
uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));
// Initialize a local cache to store the MRAM block
T *cache_A = (T *) mem_alloc(BLOCK_SIZE);
T *cache_B = (T *) mem_alloc(BLOCK_SIZE);
for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){
// Load cache with current MRAM block
mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);
#ifdef WRAM
// Barrier
barrier_wait(&my_barrier);
timer_start(&cycles); // START TIMER
#endif
// Scale
scale_dpu(cache_B, cache_A, scalar);
#ifdef WRAM
result->cycles += timer_stop(&cycles); // STOP TIMER
// Barrier
barrier_wait(&my_barrier);
#endif
// Write cache to current MRAM block
mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);
}
#ifndef WRAM
result->cycles = timer_stop(&cycles); // STOP TIMER
#endif
return 0;
}
|
