diff options
| author | Daniel Friesel <derf@finalrewind.org> | 2015-12-31 16:49:53 +0100 |
|---|---|---|
| committer | Daniel Friesel <derf@finalrewind.org> | 2015-12-31 16:49:53 +0100 |
| commit | 4eb3666312621fd982d46aff2e4ca110b30dac66 (patch) | |
| tree | 52b1cacb73229267517ce1e4017574883c2ddbd8 | |
| parent | c8e30d21f46c85c57cf7fc55a84bbbf627fd7b7c (diff) | |
vusb-i2c-tht layout: Add a missing wire
| -rw-r--r-- | circuit/vusb-i2c-tht.brd | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/circuit/vusb-i2c-tht.brd b/circuit/vusb-i2c-tht.brd index 1c480d5..a3f27fc 100644 --- a/circuit/vusb-i2c-tht.brd +++ b/circuit/vusb-i2c-tht.brd @@ -689,7 +689,7 @@ design rules under a new name.</description> <contactref element="Q1" pad="2"/> <wire x1="31.75" y1="10.795" x2="32.512" y2="10.795" width="0.4064" layer="16"/> <wire x1="32.512" y1="10.795" x2="36.83" y2="6.477" width="0.4064" layer="16"/> -<wire x1="36.83" y1="4.125" x2="36.83" y2="6.477" width="0" layer="19" extent="16-16"/> +<wire x1="36.83" y1="6.477" x2="36.83" y2="4.125" width="0.4064" layer="16"/> </signal> <signal name="AVRD+"> <contactref element="IC1" pad="6"/> |