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authorBirte Kristina Friesel <derf@finalrewind.org>2024-01-26 23:21:42 +0100
committerBirte Kristina Friesel <derf@finalrewind.org>2024-01-26 23:21:42 +0100
commit021e08eba3272e3e3f30b6175464e48792dff1d1 (patch)
tree83866ba4bf3dcaeb6bbe5191813a4bb105c0620a /src/arch/atmega2560/driver
parent218166456b68ca2266c8e7c77c1085ad4fc16e86 (diff)
atmega2560: provide one DMX driver per extra UART
Diffstat (limited to 'src/arch/atmega2560/driver')
-rw-r--r--src/arch/atmega2560/driver/dmx1.cc53
-rw-r--r--src/arch/atmega2560/driver/dmx2.cc53
-rw-r--r--src/arch/atmega2560/driver/dmx3.cc (renamed from src/arch/atmega2560/driver/dmx.cc)8
3 files changed, 110 insertions, 4 deletions
diff --git a/src/arch/atmega2560/driver/dmx1.cc b/src/arch/atmega2560/driver/dmx1.cc
new file mode 100644
index 0000000..1724591
--- /dev/null
+++ b/src/arch/atmega2560/driver/dmx1.cc
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2022 Birte Kristina Friesel
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#include <avr/io.h>
+#include "arch.h"
+#include "driver/dmx1.h"
+#include "driver/gpio.h"
+
+#undef BAUD
+#define BAUD 250000UL
+#include <util/setbaud.h>
+
+void DMX1::setup()
+{
+ UBRR1H = UBRRH_VALUE;
+ UBRR1L = UBRRL_VALUE;
+
+#if USE_2X
+ UCSR1A |= _BV(U2X1);
+#else
+ UCSR1A &= ~_BV(U2X1);
+#endif
+
+ UCSR1B = _BV(TXEN1);
+ UCSR1C = _BV(USBS1) | _BV(UCSZ11) | _BV(UCSZ10); // MSB first, 8 data bits, 2 stop bits, no parity
+}
+
+void DMX1::write()
+{
+ // Disable UART for reset and mark signals
+ UCSR1B &= ~_BV(TXEN1);
+ gpio.output(GPIO::pd3, 0);
+ arch.delay_us(88); // break / reset
+ gpio.output(GPIO::pd3, 1);
+ arch.delay_us(8); // mark
+ UCSR1B |= _BV(TXEN1); // causes line to go high
+ for (uint8_t i = 0; i < 32; i++) {
+ while (!(UCSR1A & _BV(UDRE1)));
+ UDR1 = frames[i];
+ }
+ for (uint8_t i = 0; i < 258 - num_frames; i++) {
+ while (!(UCSR1A & _BV(UDRE1)));
+ UDR1 = 0;
+ }
+ for (uint8_t i = 0; i < 255; i++) {
+ while (!(UCSR1A & _BV(UDRE1)));
+ UDR1 = 0;
+ }
+}
+
+DMX1 dmx1;
diff --git a/src/arch/atmega2560/driver/dmx2.cc b/src/arch/atmega2560/driver/dmx2.cc
new file mode 100644
index 0000000..9b5d35f
--- /dev/null
+++ b/src/arch/atmega2560/driver/dmx2.cc
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2022 Birte Kristina Friesel
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#include <avr/io.h>
+#include "arch.h"
+#include "driver/dmx2.h"
+#include "driver/gpio.h"
+
+#undef BAUD
+#define BAUD 250000UL
+#include <util/setbaud.h>
+
+void DMX2::setup()
+{
+ UBRR2H = UBRRH_VALUE;
+ UBRR2L = UBRRL_VALUE;
+
+#if USE_2X
+ UCSR2A |= _BV(U2X2);
+#else
+ UCSR2A &= ~_BV(U2X2);
+#endif
+
+ UCSR2B = _BV(TXEN2);
+ UCSR2C = _BV(USBS2) | _BV(UCSZ21) | _BV(UCSZ20); // MSB first, 8 data bits, 2 stop bits, no parity
+}
+
+void DMX2::write()
+{
+ // Disable UART for reset and mark signals
+ UCSR2B &= ~_BV(TXEN2);
+ gpio.output(GPIO::ph1, 0);
+ arch.delay_us(88); // break / reset
+ gpio.output(GPIO::ph1, 1);
+ arch.delay_us(8); // mark
+ UCSR2B |= _BV(TXEN2); // causes line to go high
+ for (uint8_t i = 0; i < 32; i++) {
+ while (!(UCSR2A & _BV(UDRE2)));
+ UDR2 = frames[i];
+ }
+ for (uint8_t i = 0; i < 258 - num_frames; i++) {
+ while (!(UCSR2A & _BV(UDRE2)));
+ UDR2 = 0;
+ }
+ for (uint8_t i = 0; i < 255; i++) {
+ while (!(UCSR2A & _BV(UDRE2)));
+ UDR2 = 0;
+ }
+}
+
+DMX2 dmx2;
diff --git a/src/arch/atmega2560/driver/dmx.cc b/src/arch/atmega2560/driver/dmx3.cc
index 894ef99..0f6db4e 100644
--- a/src/arch/atmega2560/driver/dmx.cc
+++ b/src/arch/atmega2560/driver/dmx3.cc
@@ -5,14 +5,14 @@
*/
#include <avr/io.h>
#include "arch.h"
-#include "driver/dmx.h"
+#include "driver/dmx3.h"
#include "driver/gpio.h"
#undef BAUD
#define BAUD 250000UL
#include <util/setbaud.h>
-void DMX::setup()
+void DMX3::setup()
{
UBRR3H = UBRRH_VALUE;
UBRR3L = UBRRL_VALUE;
@@ -27,7 +27,7 @@ void DMX::setup()
UCSR3C = _BV(USBS3) | _BV(UCSZ31) | _BV(UCSZ30); // MSB first, 8 data bits, 2 stop bits, no parity
}
-void DMX::write()
+void DMX3::write()
{
// Disable UART for reset and mark signals
UCSR3B &= ~_BV(TXEN3);
@@ -50,4 +50,4 @@ void DMX::write()
}
}
-DMX dmx;
+DMX3 dmx3;