diff options
author | Daniel Friesel <derf@finalrewind.org> | 2021-09-18 21:07:30 +0200 |
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committer | Daniel Friesel <derf@finalrewind.org> | 2021-09-18 21:07:30 +0200 |
commit | 4f6973b8500418abf83c2377d09396b8588f7746 (patch) | |
tree | 83862be273470ad25e492e62cf830cbc4ea4a9b5 /src/arch/lora32u4ii/arch.cc | |
parent | 65d563aa36e1367d4d3191ac838c6fb60ac4f481 (diff) |
New architecture: lora32u4ii
Very limited support at the moment. No I2C/SPI, no USB bootloader or USB UART.
Diffstat (limited to 'src/arch/lora32u4ii/arch.cc')
-rw-r--r-- | src/arch/lora32u4ii/arch.cc | 123 |
1 files changed, 123 insertions, 0 deletions
diff --git a/src/arch/lora32u4ii/arch.cc b/src/arch/lora32u4ii/arch.cc new file mode 100644 index 0000000..aa5c288 --- /dev/null +++ b/src/arch/lora32u4ii/arch.cc @@ -0,0 +1,123 @@ +#include "arch.h" +#include <avr/io.h> +#include <avr/interrupt.h> +#include <avr/wdt.h> +#include <util/delay.h> + +void Arch::setup(void) +{ + wdt_disable(); + +#if F_CPU == 8000000UL + /* default */ +#elif F_CPU == 4000000UL + CLKPR = _BV(CLKPCE); + CLKPR = _BV(CLKPS0); +#elif F_CPU == 2000000UL + CLKPR = _BV(CLKPCE); + CLKPR = _BV(CLKPS1); +#elif F_CPU == 1000000UL + CLKPR = _BV(CLKPCE); + CLKPR = _BV(CLKPS1) | _BV(CLKPS0); +#elif F_CPU == 500000UL + CLKPR = _BV(CLKPCE); + CLKPR = _BV(CLKPS2); +#elif F_CPU == 250000UL + CLKPR = _BV(CLKPCE); + CLKPR = _BV(CLKPS2) | _BV(CLKPS0); +#elif F_CPU == 125000UL + CLKPR = _BV(CLKPCE); + CLKPR = _BV(CLKPS2) | _BV(CLKPS1); +#elif F_CPU == 62500UL + CLKPR = _BV(CLKPCE); + CLKPR = _BV(CLKPS2) | _BV(CLKPS1) | _BV(CLKPS0); +#elif F_CPU == 32150UL + CLKPR = _BV(CLKPCE); + CLKPR = _BV(CLKPS3); +#else +#error Unsupported F_CPU +#endif + +#if defined(CONFIG_loop) || defined(TIMER_S) + TCCR1A = 0; + TCCR1B = _BV(WGM12) | _BV(CS12) | _BV(CS10); // CTC, /1024 + OCR1A = F_CPU / 1024; + TIMSK1 = _BV(OCIE1A); +#endif + + sei(); +} + +#ifdef CONFIG_wakeup +void wakeup(); +#endif + +#if defined(CONFIG_loop) || defined(TIMER_S) + +#include "driver/uptime.h" + +#endif + +#if defined(CONFIG_loop) +extern void loop(); +volatile char run_loop = 0; +#endif + +void Arch::idle_loop(void) +{ + while (1) { + SMCR = _BV(SE); + asm("sleep"); + SMCR = 0; + asm("wdr"); +#ifdef CONFIG_loop + if (run_loop) { + loop(); + run_loop = 0; + } +#endif +#ifdef CONFIG_wakeup + wakeup(); +#endif + } +} + +void Arch::idle(void) +{ + SMCR = _BV(SE); + asm("sleep"); + SMCR = 0; + asm("wdr"); +} + +void Arch::delay_us(unsigned int const us) +{ + for (unsigned int i = 0; i < us; i++) { + _delay_us(1); + } +} + +void Arch::delay_ms(unsigned int const ms) +{ + for (unsigned int i = 0; i < ms; i++) { + _delay_ms(1); + } +} + +Arch arch; + +#if defined(CONFIG_loop) || defined(TIMER_S) + +#ifndef __acweaving +ISR(TIMER1_COMPA_vect) +{ +#ifdef CONFIG_loop + run_loop = 1; +#endif +#ifdef TIMER_S + uptime.tick_s(); +#endif +} +#endif + +#endif |