diff options
author | Daniel Friesel <derf@finalrewind.org> | 2021-09-19 18:42:25 +0200 |
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committer | Daniel Friesel <derf@finalrewind.org> | 2021-09-19 18:42:25 +0200 |
commit | 0288997cc3eea0b252b748f8803171a0a4e986fc (patch) | |
tree | 0d43e68a4ab1d9e51b55c1a416851e29966b5086 /src/arch/lora32u4ii/driver | |
parent | b35dfb3f83116350eef8681c8e3db72618fdb70e (diff) |
lora32u4ii: add spi driver
Diffstat (limited to 'src/arch/lora32u4ii/driver')
-rw-r--r-- | src/arch/lora32u4ii/driver/spi.cc | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/arch/lora32u4ii/driver/spi.cc b/src/arch/lora32u4ii/driver/spi.cc new file mode 100644 index 0000000..f7cc29e --- /dev/null +++ b/src/arch/lora32u4ii/driver/spi.cc @@ -0,0 +1,39 @@ +#include "driver/spi.h" +#include "driver/gpio.h" +#include "arch.h" +#include <avr/io.h> + +signed char SPI::setup() +{ + // configure SS as output to avoid unintened switches to slave mode + gpio.output(GPIO::pb0, 0); + // MISO is automatically configured as input + // Configure SCK and MOSI as output + DDRB |= _BV(PB2) | _BV(PB1); + // up to 2 MHz SPI clock + SPCR = _BV(SPE) | _BV(MSTR) | _BV(SPR0); +} + +signed char SPI::xmit( + unsigned char tx_len, unsigned char *tx_buf, + unsigned char rx_len, unsigned char *rx_buf) +{ + unsigned char i = 0; + + while ((i < tx_len) || (i < rx_len)) { + if (i < tx_len) { + SPDR = tx_buf[i]; + } else { + SPDR = 0; + } + arch.delay_ms(1); + while (!(SPSR & _BV(SPIF))) ; + if (i < rx_len) { + rx_buf[i] = SPDR; + } + i++; + } + return 0; +} + +SPI spi; |