diff options
| author | Daniel Friesel <derf@finalrewind.org> | 2018-10-15 12:26:11 +0200 |
|---|---|---|
| committer | Daniel Friesel <derf@finalrewind.org> | 2018-10-15 12:26:11 +0200 |
| commit | 17831e691af5152e9e1bdd8588e150810c1836a6 (patch) | |
| tree | ccbc33b01f8bbe64d2bc8b8f5d04e9de6fa343f7 /src | |
| parent | 60cb80bde54265e1fdf3cc8d21e74292d5f769db (diff) | |
MSP430: Support several CPU speeds
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/msp430fr5969lp/arch.cc | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/src/arch/msp430fr5969lp/arch.cc b/src/arch/msp430fr5969lp/arch.cc index 04a52c9..7de978c 100644 --- a/src/arch/msp430fr5969lp/arch.cc +++ b/src/arch/msp430fr5969lp/arch.cc @@ -9,13 +9,34 @@ void Arch::setup(void) PM5CTL0 &= ~LOCKLPM5; - FRCTL0 = FWPW; - FRCTL0_L = 0x10; - FRCTL0_H = 0xff; + /* + * Note: arch drivers assume SMCLK freq == F_CPU + */ + +#if F_CPU == 16000000UL + FRCTL0 = FWPW; // unlock FRAM Control + FRCTL0_L = 0x10; // one wait state before FRAM access (required for 8MHz < F_CPU <= 16 MHz) + FRCTL0_H = 0xff; // lock FRAM control by writing an invalid password // 16MHz DCO CSCTL0_H = CSKEY >> 8; CSCTL1 = DCORSEL | DCOFSEL_4; +#elif F_CPU == 8000000UL + // 8MHz DCO + CSCTL0_H = CSKEY >> 8; + CSCTL1 = DCOFSEL_6; +#elif F_CPU == 4000000UL + // 8MHz DCO + CSCTL0_H = CSKEY >> 8; + CSCTL1 = DCOFSEL_3; +#elif F_CPU == 1000000UL + // 8MHz DCO + CSCTL0_H = CSKEY >> 8; + CSCTL1 = DCOFSEL_0; +#else +#error Unsupported F_CPU +#endif + #ifdef WITH_LOOP CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK; #else |