diff options
Diffstat (limited to 'src/arch')
34 files changed, 16897 insertions, 0 deletions
diff --git a/src/arch/rm46l8lp/Kconfig b/src/arch/rm46l8lp/Kconfig new file mode 100644 index 0000000..4b04f57 --- /dev/null +++ b/src/arch/rm46l8lp/Kconfig @@ -0,0 +1,10 @@ +# Copyright 2022 Daniel Friesel +# +# SPDX-License-Identifier: CC0-1.0 +config arch_rm46l8lp_driver_counter +bool "Cycle Counter" +select meta_driver_counter + +config arch_rm46l8lp_driver_uptime +bool "Uptime Counter" +select meta_driver_uptime diff --git a/src/arch/rm46l8lp/Makefile.inc b/src/arch/rm46l8lp/Makefile.inc new file mode 100644 index 0000000..415b1df --- /dev/null +++ b/src/arch/rm46l8lp/Makefile.inc @@ -0,0 +1,122 @@ +# vim:ft=make +# +# Copyright 2020 Daniel Friesel +# +# SPDX-License-Identifier: BSD-2-Clause + +SERIAL_PORT ?= ttyACM2 + +cpu_freq ?= 160000000 +counter_freq ?= 80000000 + +INCLUDES += --include_path=/home/derf/lib/local/ti/ccs1200/ccs/tools/compiler/ti-cgt-arm_20.2.6.LTS/include --include_path=include/arch/rm46l8lp/halcogen + +# this is not gcc +COMMON_FLAGS = +CFLAGS = +CXXFLAGS = + +COMMON_FLAGS += --preinclude=include/config.h +COMMON_FLAGS += -DF_CPU=${cpu_freq}UL +COMMON_FLAGS += -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --opt_for_speed=0 +COMMON_FLAGS += --define=_TMS570LS12x_ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi +#CXXFLAGS += --c++14 + +CC = /home/derf/lib/local/ti/ccs1200/ccs/tools/compiler/ti-cgt-arm_20.2.6.LTS/bin/armcl +CXX = ${CC} +SIZE = /home/derf/lib/local/ti/ccs1200/ccs/tools/compiler/ti-cgt-arm_20.2.6.LTS/bin/armsize + +ARCH_SHORTNAME = rm46l8 + +C_TARGETS += src/arch/rm46l8lp/halcogen/adc.c +C_TARGETS += src/arch/rm46l8lp/halcogen/errata_SSWF021_45.c +C_TARGETS += src/arch/rm46l8lp/halcogen/esm.c +C_TARGETS += src/arch/rm46l8lp/halcogen/gio.c +C_TARGETS += src/arch/rm46l8lp/halcogen/pinmux.c +C_TARGETS += src/arch/rm46l8lp/halcogen/notification.c +C_TARGETS += src/arch/rm46l8lp/halcogen/rti.c +C_TARGETS += src/arch/rm46l8lp/halcogen/sys_dma.c +C_TARGETS += src/arch/rm46l8lp/halcogen/sys_phantom.c +C_TARGETS += src/arch/rm46l8lp/halcogen/sci.c +C_TARGETS += src/arch/rm46l8lp/halcogen/sys_pcr.c +C_TARGETS += src/arch/rm46l8lp/halcogen/sys_pmm.c +C_TARGETS += src/arch/rm46l8lp/halcogen/sys_startup.c +C_TARGETS += src/arch/rm46l8lp/halcogen/system.c +C_TARGETS += src/arch/rm46l8lp/halcogen/sys_vim.c +C_TARGETS += src/arch/rm46l8lp/halcogen/sys_selftest.c +CXX_TARGETS += src/arch/rm46l8lp/arch.cc +CXX_TARGETS += src/arch/rm46l8lp/driver/gpio.cc +CXX_TARGETS += src/arch/rm46l8lp/driver/stdout.cc +ASM_TARGETS += src/arch/rm46l8lp/halcogen/dabort.asm +ASM_TARGETS += src/arch/rm46l8lp/halcogen/sys_core.asm +ASM_TARGETS += src/arch/rm46l8lp/halcogen/sys_intvecs.asm +ASM_TARGETS += src/arch/rm46l8lp/halcogen/sys_mpu.asm +ASM_TARGETS += src/arch/rm46l8lp/halcogen/sys_pmu.asm + +# special case for TI CC makefile +ifeq (${loop}, 1) + COMMON_FLAGS += -DCONFIG_loop +endif + +ifneq ($(findstring counter,${arch_drivers}), ) + CONFIG_arch_rm46l8lp_driver_counter = y +endif + +ifeq (${timer_s}, 1) + CONFIG_arch_rm46l8lp_driver_uptime = y +endif + +ifdef CONFIG_arch_rm46l8lp_driver_counter + CXX_TARGETS += src/arch/rm46l8lp/driver/counter.cc +endif + +ifdef CONFIG_arch_rm46l8lp_driver_uptime + COMMON_FLAGS += -DTIMER_S + CXX_TARGETS += src/arch/rm46l8lp/driver/uptime.cc +endif + +OBJECTS = ${CXX_TARGETS:.cc=.obj} ${C_TARGETS:.c=.obj} ${ASM_TARGETS:.asm=.obj} + +%.obj : %.cc | include/config.h + ${QUIET}${CXX} ${INCLUDES} ${COMMON_FLAGS} ${CXXFLAGS} --preproc_with_compile --obj_directory=$(dir $@) ${@:.obj=.cc} + +%.obj : %.c | include/config.h + ${QUIET}${CC} ${INCLUDES} ${COMMON_FLAGS} ${CFLAGS} --preproc_with_compile --obj_directory=$(dir $@) ${@:.obj=.c} + +%.obj : %.asm | include/config.h + ${QUIET}${CC} ${INCLUDES} ${COMMON_FLAGS} ${CFLAGS} --preproc_with_compile --obj_directory=$(dir $@) ${@:.obj=.asm} + +build/system.elf: ${OBJECTS} + ${QUIET}mkdir -p build + ${QUIET}${CXX} ${COMMON_FLAGS} ${CXXFLAGS} \ + -z --heap_size=0x1000 --stack_size=0x1000 \ + -i"/home/derf/lib/local/ti/ccs1200/ccs/tools/compiler/ti-cgt-arm_20.2.6.LTS/lib" \ + -i"/home/derf/lib/local/ti/ccs1200/ccs/tools/compiler/ti-cgt-arm_20.2.6.LTS/include" \ + --reread_libs --warn_sections --ecc=off --rom_model -o $@ \ + ${OBJECTS} src/arch/rm46l8lp/halcogen/sys_link.cmd \ + -lrtsv7R4_T_le_v3D16_eabi.lib + +program: build/system.elf + ${QUIET}/opt/ti/uniflash_7.2.0/dslite.sh -c src/arch/rm46l8lp/RM46L852.ccxml -f build/system.elf -u + +arch_clean: + ${QUIET}rm -f ${OBJECTS} + +monitor: + ${QUIET}screen /dev/${SERIAL_PORT} 19200 + +arch_help: + +arch_info: + @echo "CPU Freq: ${cpu_freq} Hz" + @echo "Count Freq: ${counter_freq} Hz" + @echo "Counter Overflow: 4294967296/4294967295" + @echo "Monitor: /dev/${SERIAL_PORT} 19200" + +attributes: build/system.elf + ${QUIET}script/size.py ${SIZE} text,data data,bss + +nfpvalues: build/system.elf + ${QUIET}script/nfpvalues.py ${SIZE} text,data data,bss + +.PHONY: arch_clean arch_help arch_info attributes cat monitor program diff --git a/src/arch/rm46l8lp/RM46L852.ccxml b/src/arch/rm46l8lp/RM46L852.ccxml new file mode 100644 index 0000000..582d900 --- /dev/null +++ b/src/arch/rm46l8lp/RM46L852.ccxml @@ -0,0 +1,19 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<configurations XML_version="1.2" id="configurations_0"> +<configuration XML_version="1.2" id="configuration_0"> + <instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/> + <connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe"> + + <instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/> + + <instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/> + + <instance XML_version="1.2" href="drivers/tixds510cortexR.xml" id="drivers" xml="tixds510cortexR.xml" xmlpath="drivers"/> + + + <platform XML_version="1.2" id="platform_0"> + <instance XML_version="1.2" desc="RM46L852" href="devices/rm46l852.xml" id="RM46L852" xml="rm46l852.xml" xmlpath="devices"/> + </platform> + </connection> + </configuration> +</configurations> diff --git a/src/arch/rm46l8lp/arch.cc b/src/arch/rm46l8lp/arch.cc new file mode 100644 index 0000000..e07e507 --- /dev/null +++ b/src/arch/rm46l8lp/arch.cc @@ -0,0 +1,126 @@ +/* + * Copyright 2020 Daniel Friesel + * + * SPDX-License-Identifier: BSD-2-Clause + */ +#include "arch.h" +#include "gio.h" +#include "rti.h" + +#ifdef __acweaving +#define __delay_cycles(x) +#endif + +void Arch::setup(void) +{ + gioInit(); + + // disable counter blocks + rtiREG1->GCTRL = 0; + + // internal clock, RTIUC0 -> RTIFRC0 + rtiREG1->TBCTRL = 0; + + // no capture sources + rtiREG1->CAPCTRL = 0; + + // input source: counter 0 -> compare 0/1, counter 1 -> compare 2/3 + rtiREG1->COMPCTRL = 0x00001100U; + + // reset up / free running counter 0 + rtiREG1->CNT[0].UCx = 0; + rtiREG1->CNT[0].FRCx = 0; + + // reset up / free running counter 1 + rtiREG1->CNT[1].UCx = 0; + rtiREG1->CNT[1].FRCx = 0; + + // free running counter 0 freq = RTICLK/2^32 + rtiREG1->CNT[0].CPUCx = 0xffffffffU; + + // free running counter 1 freq = RTICLK/2 ( == VCLK/4, see halcogen/system.c) + rtiREG1->CNT[1].CPUCx = 1; + + // one interrupt per second + rtiREG1->CMP[2].COMPx = F_CPU/4; + rtiREG1->CMP[2].UDCPx = F_CPU/4; + + // clear all pending interrupts + rtiREG1->INTFLAG = 0x0007000FU; + + // disable all interrupts + rtiREG1->CLEARINTENA = 0x00070F0FU; + +#if defined(CONFIG_loop) || defined(TIMER_S) + rtiEnableNotification(rtiNOTIFICATION_COMPARE2); +#endif + _enable_IRQ(); +#if defined(CONFIG_loop) || defined(TIMER_S) + rtiStartCounter(rtiCOUNTER_BLOCK1); +#endif +} + +#ifdef CONFIG_wakeup +extern void wakeup(); +#endif + +#if defined(CONFIG_loop) +extern void loop(); +volatile bool run_loop = 0; +#endif + +void Arch::delay_us(unsigned int const us) +{ + if (us < 10) { + for (unsigned int i = 0; i < us; i++) { + __delay_cycles(F_CPU / 4000000UL); + } + } else { + for (unsigned int i = 0; i < us/10; i++) { + __delay_cycles(F_CPU / 400000UL); + } + } +} +void Arch::delay_ms(unsigned int const ms) +{ + for (unsigned int i = 0; i < ms; i++) { + __delay_cycles(F_CPU / 4000UL); + } +} + + +void Arch::idle_loop(void) +{ + while (1) { +#if defined(CONFIG_loop) + if (run_loop) { + loop(); + run_loop = 0; + } +#endif + } +} + +void Arch::idle(void) +{ +#ifdef CONFIG_wakeup + wakeup(); +#endif +} + +#if defined(CONFIG_loop) || defined(TIMER_S) +#include "driver/uptime.h" +void rtiNotification(uint32 notification) +{ + if (notification == rtiNOTIFICATION_COMPARE2) { +#ifdef CONFIG_loop + run_loop = 1; +#endif +#ifdef TIMER_S + uptime.tick_s(); +#endif + } +} +#endif + +Arch arch; diff --git a/src/arch/rm46l8lp/driver/counter.cc b/src/arch/rm46l8lp/driver/counter.cc new file mode 100644 index 0000000..4e0bb92 --- /dev/null +++ b/src/arch/rm46l8lp/driver/counter.cc @@ -0,0 +1,8 @@ +/* + * Copyright 2022 Daniel Friesel + * + * SPDX-License-Identifier: BSD-2-Clause + */ +#include "driver/counter.h" + +Counter counter; diff --git a/src/arch/rm46l8lp/driver/gpio.cc b/src/arch/rm46l8lp/driver/gpio.cc new file mode 100644 index 0000000..148bcdb --- /dev/null +++ b/src/arch/rm46l8lp/driver/gpio.cc @@ -0,0 +1,8 @@ +/* + * Copyright 2020 Daniel Friesel + * + * SPDX-License-Identifier: BSD-2-Clause + */ +#include "driver/gpio.h" + +GPIO gpio; diff --git a/src/arch/rm46l8lp/driver/stdout.cc b/src/arch/rm46l8lp/driver/stdout.cc new file mode 100644 index 0000000..9d5403c --- /dev/null +++ b/src/arch/rm46l8lp/driver/stdout.cc @@ -0,0 +1,23 @@ +/* + * Copyright 2022 Daniel Friesel + * + * SPDX-License-Identifier: BSD-2-Clause + */ +#include "driver/stdout.h" +#include "sci.h" + +void StandardOutput::setup() +{ + sciInit(); +} + +void StandardOutput::put(char c) +{ + while ((scilinREG->FLR & 0x04) == 0x04); + sciSendByte(scilinREG, c); + if (c == '\n') { + put('\r'); + } +} + +StandardOutput kout; diff --git a/src/arch/rm46l8lp/driver/uptime.cc b/src/arch/rm46l8lp/driver/uptime.cc new file mode 100644 index 0000000..8aaff8f --- /dev/null +++ b/src/arch/rm46l8lp/driver/uptime.cc @@ -0,0 +1,8 @@ +/* + * Copyright 2022 Daniel Friesel + * + * SPDX-License-Identifier: BSD-2-Clause + */ +#include "driver/uptime.h" + +Uptime uptime; diff --git a/src/arch/rm46l8lp/halcogen/adc.c b/src/arch/rm46l8lp/halcogen/adc.c new file mode 100644 index 0000000..a888c19 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/adc.c @@ -0,0 +1,989 @@ +/** @file adc.c +* @brief ADC Driver Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - API Functions +* - Interrupt Handlers +* . +* which are relevant for the ADC driver. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "adc.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + +/** @fn void adcInit(void) +* @brief Initializes ADC Driver +* +* This function initializes the ADC driver. +* +*/ +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/* SourceId : ADC_SourceId_001 */ +/* DesignId : ADC_DesignId_001 */ +/* Requirements : HL_SR185 */ +void adcInit(void) +{ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + + /** @b Initialize @b ADC1: */ + + /** - Reset ADC module */ + adcREG1->RSTCR = 1U; + adcREG1->RSTCR = 0U; + + /** - Enable 12-BIT ADC */ + adcREG1->OPMODECR |= 0x80000000U; + + /** - Setup prescaler */ + adcREG1->CLOCKCR = 7U; + + /** - Setup memory boundaries */ + adcREG1->BNDCR = (uint32)((uint32)8U << 16U) | (8U + 8U); + adcREG1->BNDEND = (adcREG1->BNDEND & 0xFFFF0000U) | (2U); + + /** - Setup event group conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[0U] = (uint32)ADC_12_BIT + | (uint32)0x00000000U + | (uint32)0x00000000U; + + /** - Setup event group hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->EVSRC = (uint32)0x00000000U + | (uint32)ADC1_EVENT; + + /** - Setup event group sample window */ + adcREG1->EVSAMP = 1U; + + /** - Setup event group sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->EVSAMPDISEN = (uint32)((uint32)0U << 8U) + | (uint32)0x00000000U; + + /** - Setup group 1 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[1U] = (uint32)ADC_12_BIT + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U; + + /** - Setup group 1 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G1SRC = (uint32)0x00000000U + | (uint32)ADC1_EVENT; + + /** - Setup group 1 sample window */ + adcREG1->G1SAMP = 0U; + + /** - Setup group 1 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G1SAMPDISEN = (uint32)((uint32)0U << 8U) + | (uint32)0x00000000U; + + /** - Setup group 2 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[2U] = (uint32)ADC_12_BIT + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U; + + /** - Setup group 2 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G2SRC = (uint32)0x00000000U + | (uint32)ADC1_EVENT; + + /** - Setup group 2 sample window */ + adcREG1->G2SAMP = 1U; + + /** - Setup group 2 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G2SAMPDISEN = (uint32)((uint32)0U << 8U) + | (uint32)0x00000000U; + + /** - ADC1 EVT pin output value */ + adcREG1->EVTOUT = 0U; + + /** - ADC1 EVT pin direction */ + adcREG1->EVTDIR = 0U; + + /** - ADC1 EVT pin open drain enable */ + adcREG1->EVTPDR = 0U; + + /** - ADC1 EVT pin pullup / pulldown selection */ + adcREG1->EVTPSEL = 1U; + + /** - ADC1 EVT pin pullup / pulldown enable*/ + adcREG1->EVTDIS = 0U; + + /** - Enable ADC module */ + adcREG1->OPMODECR |= 0x80140001U; + + /** - Wait for buffer initialization complete */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while (((adcREG1->BNDEND & 0xFFFF0000U) >> 16U ) != 0U) + { + } /* Wait */ + + /** - Setup parity */ + adcREG1->PARCR = 0x00000005U; + + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + +/** - s_adcSelect is used as constant table for channel selection */ +static const uint32 s_adcSelect[2U][3U] = +{ + {0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U, + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000040U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U, + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U}, + {0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U , + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U, + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U} +}; + +/** - s_adcFiFoSize is used as constant table for channel selection */ +static const uint32 s_adcFiFoSize[2U][3U] = +{ + {16U, + 1U, + 16U}, + {16U, + 16U, + 16U} +}; + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +/** @fn void adcStartConversion(adcBASE_t *adc, uint32 group) +* @brief Starts an ADC conversion +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* +* This function starts a conversion of the ADC hardware group. +* +*/ +/* SourceId : ADC_SourceId_002 */ +/* DesignId : ADC_DesignId_002 */ +/* Requirements : HL_SR186 */ +void adcStartConversion(adcBASE_t *adc, uint32 group) +{ + uint32 index = (adc == adcREG1) ? 0U : 1U; + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + + /** - Setup FiFo size */ + adc->GxINTCR[group] = s_adcFiFoSize[index][group]; + + /** - Start Conversion */ + adc->GxSEL[group] = s_adcSelect[index][group]; + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (8) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + +/** @fn void adcStopConversion(adcBASE_t *adc, uint32 group) +* @brief Stops an ADC conversion +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* +* This function stops a conversion of the ADC hardware group. +* +*/ +/* SourceId : ADC_SourceId_003 */ +/* DesignId : ADC_DesignId_003 */ +/* Requirements : HL_SR187 */ +void adcStopConversion(adcBASE_t *adc, uint32 group) +{ +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + + /** - Stop Conversion */ + adc->GxSEL[group] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + + +/** @fn void adcResetFiFo(adcBASE_t *adc, uint32 group) +* @brief Resets FiFo read and write pointer. +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* +* This function resets the FiFo read and write pointers. +* +*/ +/* SourceId : ADC_SourceId_004 */ +/* DesignId : ADC_DesignId_004*/ +/* Requirements : HL_SR188 */ +void adcResetFiFo(adcBASE_t *adc, uint32 group) +{ +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + + /** - Reset FiFo */ + adc->GxFIFORESETCR[group] = 1U; + + /** @note The function adcInit has to be called before this function can be used.\n + * the conversion should be stopped before calling this function. + */ + +/* USER CODE BEGIN (14) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + + +/** @fn uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data) +* @brief Gets converted a ADC values +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* @param[out] data Pointer to store ADC converted data +* @return The function will return the number of converted values copied into data buffer: +* +* This function writes a ADC message into a ADC message box. +* +*/ +/* SourceId : ADC_SourceId_005 */ +/* DesignId : ADC_DesignId_005 */ +/* Requirements : HL_SR189 */ +uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data) +{ + uint32 i; + uint32 buf; + uint32 mode; + uint32 index = (adc == adcREG1) ? 0U : 1U; + + uint32 intcr_reg = adc->GxINTCR[group]; + uint32 count = (intcr_reg >= 256U) ? s_adcFiFoSize[index][group] : (s_adcFiFoSize[index][group] - (uint32)(intcr_reg & 0xFFU)); + adcData_t *ptr = data; + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + + mode = (adc->OPMODECR & ADC_12_BIT_MODE); + + if(mode == ADC_12_BIT_MODE) + { + /** - Get conversion data and channel/pin id */ + for (i = 0U; i < count; i++) + { + buf = adc->GxBUF[group].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + ptr->value = (uint16)(buf & 0xFFFU); + ptr->id = (uint32)((buf >> 16U) & 0x1FU); + /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */ + ptr++; + } + } + else + { + /** - Get conversion data and channel/pin id */ + for (i = 0U; i < count; i++) + { + buf = adc->GxBUF[group].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + ptr->value = (uint16)(buf & 0x3FFU); + ptr->id = (uint32)((buf >> 10U) & 0x1FU); + /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */ + ptr++; + } + } + + + adc->GxINTFLG[group] = 9U; + + /** @note The function adcInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + return count; +} + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + + +/** @fn uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group) +* @brief Checks if FiFo buffer is full +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* @return The function will return: +* - 0: When FiFo buffer is not full +* - 1: When FiFo buffer is full +* - 3: When FiFo buffer overflow occurred +* +* This function checks FiFo buffer status. +* +*/ +/* SourceId : ADC_SourceId_006 */ +/* DesignId : ADC_DesignId_006 */ +/* Requirements : HL_SR190 */ +uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group) +{ + uint32 flags; + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ + + /** - Read FiFo flags */ + flags = adc->GxINTFLG[group] & 3U; + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + + +/** @fn uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group) +* @brief Checks if Conversion is complete +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* @return The function will return: +* - 0: When is not finished +* - 8: When conversion is complete +* +* This function checks if conversion is complete. +* +*/ +/* SourceId : ADC_SourceId_007 */ +/* DesignId : ADC_DesignId_007 */ +/* Requirements : HL_SR191 */ +uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group) +{ + uint32 flags; + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ + + /** - Read conversion flags */ + flags = adc->GxINTFLG[group] & 8U; + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + +/** @fn void adcCalibration(adcBASE_t *adc) +* @brief Computes offset error using Calibration mode +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* This function computes offset error using Calibration mode +* +*/ +/* SourceId : ADC_SourceId_008 */ +/* DesignId : ADC_DesignId_010 */ +/* Requirements : HL_SR194 */ +void adcCalibration(adcBASE_t *adc) +{ +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + + uint32 conv_val[5U]={0U,0U,0U,0U,0U}; + uint32 loop_index=0U; + uint32 offset_error=0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[0U]=0x00U; + adc->GxSEL[1U]=0x00U; + adc->GxSEL[2U]=0x00U; + + for(loop_index=0U;loop_index<4U;loop_index++) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR=0x0U; + + switch(loop_index) + { + case 0U : /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR=0x0U; + break; + + case 1U : /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR=0x0100U; + break; + + case 2U : /* Test 1 : Bride En = 1 , HiLo =0 */ + adc->CALCR=0x0200U; + break; + + case 3U : /* Test 1 : Bride En = 1 , HiLo =1 */ + adc->CALCR=0x0300U; + break; + default : + break; + } + + /* Enable Calibration mode */ + adc->CALCR|=0x1U; + + /* Start calibration conversion */ + adc->CALCR|=0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((adc->CALCR & 0x00010000U)==0x00010000U) + { + } /* Wait */ + + /* Read converted value */ + conv_val[loop_index]= adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR=0x0U; + + /* Compute the Offset error correction value */ + conv_val[4U]=conv_val[0U]+ conv_val[1U] + conv_val[2U] + conv_val[3U]; + + conv_val[4U]=(conv_val[4U]/4U); + + offset_error=conv_val[4U]-0x7FFU; + + /*Write the offset error to the Calibration register */ + /* Load 2;s complement of the computed value to ADCALR register */ + offset_error=~offset_error; + offset_error=offset_error & 0xFFFU; + offset_error=offset_error+1U; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + /** @note The function adcInit has to be called before using this function. */ + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ +} + + +/** @fn void adcMidPointCalibration(adcBASE_t *adc) +* @brief Computes offset error using Mid Point Calibration mode +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @return This function will return offset error using Mid Point Calibration mode +* +* This function computes offset error using Mid Point Calibration mode +* +*/ +/* SourceId : ADC_SourceId_009 */ +/* DesignId : ADC_DesignId_011 */ +/* Requirements : HL_SR195 */ +uint32 adcMidPointCalibration(adcBASE_t *adc) +{ +/* USER CODE BEGIN (27) */ +/* USER CODE END */ + + uint32 conv_val[3U]={0U,0U,0U}; + uint32 loop_index=0U; + uint32 offset_error=0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[0U]=0x00U; + adc->GxSEL[1U]=0x00U; + adc->GxSEL[2U]=0x00U; + + for(loop_index=0U;loop_index<2U;loop_index++) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR=0x0U; + + switch(loop_index) + { + case 0U : /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR=0x0U; + break; + + case 1U : /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR=0x0100U; + break; + + default : + break; + + } + + /* Enable Calibration mode */ + adc->CALCR|=0x1U; + + /* Start calibration conversion */ + adc->CALCR|=0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((adc->CALCR & 0x00010000U)==0x00010000U) + { + } /* Wait */ + + /* Read converted value */ + conv_val[loop_index]= adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR=0x0U; + + /* Compute the Offset error correction value */ + conv_val[2U]=(conv_val[0U])+ (conv_val[1U]); + + conv_val[2U]=(conv_val[2U]/2U); + + offset_error=conv_val[2U]-0x7FFU; + + /* Write the offset error to the Calibration register */ + /* Load 2's complement of the computed value to ADCALR register */ + offset_error=~offset_error; + offset_error=offset_error+1U; + offset_error=offset_error & 0xFFFU; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + return(offset_error); + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + +/** @fn void adcEnableNotification(adcBASE_t *adc, uint32 group) +* @brief Enable notification +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* +* This function will enable the notification of a conversion. +* In single conversion mode for conversion complete and +* in continuous conversion mode when the FiFo buffer is full. +* +*/ +/* SourceId : ADC_SourceId_010 */ +/* DesignId : ADC_DesignId_008 */ +/* Requirements : HL_SR192 */ +void adcEnableNotification(adcBASE_t *adc, uint32 group) +{ + uint32 notif = (((uint32)(adc->GxMODECR[group]) & 2U) == 2U) ? 1U : 8U; + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + + adc->GxINTENA[group] = notif; + + /** @note The function adcInit has to be called before this function can be used.\n + * This function should be called before the conversion is started + */ + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + + +/** @fn void adcDisableNotification(adcBASE_t *adc, uint32 group) +* @brief Disable notification +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* +* This function will disable the notification of a conversion. +*/ +/* SourceId : ADC_SourceId_011 */ +/* DesignId : ADC_DesignId_009 */ +/* Requirements : HL_SR193 */ +void adcDisableNotification(adcBASE_t *adc, uint32 group) +{ +/* USER CODE BEGIN (33) */ +/* USER CODE END */ + + adc->GxINTENA[group] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (34) */ +/* USER CODE END */ +} + +/** @fn void adcSetEVTPin(adcBASE_t *adc, uint32 value) +* @brief Set ADCEVT pin +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* @param[in] value Value to be set: 0 or 1 +* +* This function will set the ADC EVT pin if configured as an output pin. +*/ +/* SourceId : ADC_SourceId_020 */ +/* DesignId : ADC_DesignId_014 */ +/* Requirements : HL_SR529 */ +void adcSetEVTPin(adcBASE_t *adc, uint32 value) +{ + adc->EVTOUT = value; +} + +/** @fn uint32 adcGetEVTPin(adcBASE_t *adc) +* @brief Set ADCEVT pin +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* @return Value of the ADC EVT pin: 0 or 1 +* +* This function will return the value of ADC EVT pin. +*/ +/* SourceId : ADC_SourceId_021 */ +/* DesignId : ADC_DesignId_015 */ +/* Requirements : HL_SR529 */ +uint32 adcGetEVTPin(adcBASE_t *adc) +{ + return adc->EVTIN; +} + +/** @fn void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ADC_SourceId_012 */ +/* DesignId : ADC_DesignId_012 */ +/* Requirements : HL_SR203 */ +void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_OPMODECR = ADC1_OPMODECR_CONFIGVALUE; + config_reg->CONFIG_CLOCKCR = ADC1_CLOCKCR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[0U] = ADC1_G0MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[1U] = ADC1_G1MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[2U] = ADC1_G2MODECR_CONFIGVALUE; + config_reg->CONFIG_G0SRC = ADC1_G0SRC_CONFIGVALUE; + config_reg->CONFIG_G1SRC = ADC1_G1SRC_CONFIGVALUE; + config_reg->CONFIG_G2SRC = ADC1_G2SRC_CONFIGVALUE; + config_reg->CONFIG_BNDCR = ADC1_BNDCR_CONFIGVALUE; + config_reg->CONFIG_BNDEND = ADC1_BNDEND_CONFIGVALUE; + config_reg->CONFIG_G0SAMP = ADC1_G0SAMP_CONFIGVALUE; + config_reg->CONFIG_G1SAMP = ADC1_G1SAMP_CONFIGVALUE; + config_reg->CONFIG_G2SAMP = ADC1_G2SAMP_CONFIGVALUE; + config_reg->CONFIG_G0SAMPDISEN = ADC1_G0SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G1SAMPDISEN = ADC1_G1SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G2SAMPDISEN = ADC1_G2SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_PARCR = ADC1_PARCR_CONFIGVALUE; + } + else + { + config_reg->CONFIG_OPMODECR = adcREG1->OPMODECR; + config_reg->CONFIG_CLOCKCR = adcREG1->CLOCKCR; + config_reg->CONFIG_GxMODECR[0U] = adcREG1->GxMODECR[0U]; + config_reg->CONFIG_GxMODECR[1U] = adcREG1->GxMODECR[1U]; + config_reg->CONFIG_GxMODECR[2U] = adcREG1->GxMODECR[2U]; + config_reg->CONFIG_G0SRC = adcREG1->EVSRC; + config_reg->CONFIG_G1SRC = adcREG1->G1SRC; + config_reg->CONFIG_G2SRC = adcREG1->G2SRC; + config_reg->CONFIG_BNDCR = adcREG1->BNDCR; + config_reg->CONFIG_BNDEND = adcREG1->BNDEND; + config_reg->CONFIG_G0SAMP = adcREG1->EVSAMP; + config_reg->CONFIG_G1SAMP = adcREG1->G1SAMP; + config_reg->CONFIG_G2SAMP = adcREG1->G2SAMP; + config_reg->CONFIG_G0SAMPDISEN = adcREG1->EVSAMPDISEN; + config_reg->CONFIG_G1SAMPDISEN = adcREG1->G1SAMPDISEN; + config_reg->CONFIG_G2SAMPDISEN = adcREG1->G2SAMPDISEN; + config_reg->CONFIG_PARCR = adcREG1->PARCR; + } +} + + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ + + + + + + diff --git a/src/arch/rm46l8lp/halcogen/dabort.asm b/src/arch/rm46l8lp/halcogen/dabort.asm new file mode 100644 index 0000000..89a4b8c --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/dabort.asm @@ -0,0 +1,146 @@ +;------------------------------------------------------------------------------- +; dabort.asm +; +; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +; +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; +; + + .text + .arm + + +;------------------------------------------------------------------------------- +; Run Memory Test + + .ref custom_dabort + .def _dabort + .asmfunc + +_dabort + stmfd r13!, {r0 - r12, lr}; push registers and link register on to stack + + ldr r12, esmsr3 ; ESM Group3 status register + ldr r0, [r12] + tst r0, #0x8 ; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM + bne ramErrorFound + tst r0, #0x20 ; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM + bne ramErrorFound2 + +noRAMerror + tst r0, #0x80 ; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM + bne flashErrorFound + + bl custom_dabort ; custom data abort handler required + ; If this custom handler is written in assembly, all registers used in the routine + ; and the link register must be saved on to the stack upon entry, and restored before + ; return from the routine. + + ldmfd r13!, {r0 - r12, lr}; pop registers and link register from stack + subs pc, lr, #8 ; restore state of CPU when abort occurred, and branch back to instruction that was aborted + +ramErrorFound + ldr r1, ramctrl ; RAM control register for B0TCM TCRAMW + ldr r2, [r1] + tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled + beq ramErrorReal + mov r2, #0x20 + str r2, [r1, #0x10] ; clear RAM error status register + + mov r2, #0x08 + str r2, [r12] ; clear ESM group3 channel3 flag for uncorrectable RAM ECC errors + mov r2, #5 + str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 ; branch to instruction after the one that caused the abort + ; this is the case because the data abort was caused intentionally + ; and we do not want to cause the same data abort again. + +ramErrorFound2 + ldr r1, ram2ctrl ; RAM control register for B1TCM TCRAMW + ldr r2, [r1] + tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled + beq ramErrorReal + mov r2, #0x20 + str r2, [r1, #0x10] ; clear RAM error status register + + mov r2, #0x20 + str r2, [r12] ; clear ESM group3 flags channel5 flag for uncorrectable RAM ECC errors + mov r2, #5 + str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 ; branch to instruction after the one that caused the abort + ; this is the case because the data abort was caused intentionally + ; and we do not want to cause the same data abort again. + + +ramErrorReal + b ramErrorReal ; branch here forever as continuing operation is not recommended + +flashErrorFound + ldr r1, flashbase + ldr r2, [r1, #0x6C] ; read FDIAGCTRL register + + mov r2, r2, lsr #16 + tst r2, #5 ; check if bits 19:16 are 5, this indicates diagnostic mode is enabled + beq flashErrorReal + mov r2, #1 + mov r2, r2, lsl #8 + + str r2, [r1, #0x1C] ; clear FEDACSTATUS error flag + + mov r2, #0x80 + str r2, [r12] ; clear ESM group3 flag for uncorrectable flash ECC error +; mov r2, #5 +; str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 ; branch to instruction after the one that caused the abort + ; this is the case because the data abort was caused intentionally + ; and we do not want to cause the same data abort again. + + +flashErrorReal + b flashErrorReal ; branch here forever as continuing operation is not recommended + +esmsr3 .word 0xFFFFF520 +ramctrl .word 0xFFFFF800 +ram2ctrl .word 0xFFFFF900 +ram1errstat .word 0xFFFFF810 +ram2errstat .word 0xFFFFF910 +flashbase .word 0xFFF87000 + + .endasmfunc + + diff --git a/src/arch/rm46l8lp/halcogen/errata_SSWF021_45.c b/src/arch/rm46l8lp/halcogen/errata_SSWF021_45.c new file mode 100644 index 0000000..36ff1ab --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/errata_SSWF021_45.c @@ -0,0 +1,358 @@ +/** @file errata_SSWF021_45.c +* @brief errata for PLLs +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ +#include "errata_SSWF021_45_defs.h" +#include "errata_SSWF021_45.h" + +static uint32 check_frequency(uint32 cnt1_clksrc); +static uint32 disable_plls(uint32 plls); + +/** @fn uint32 _errata_SSWF021_45_both_plls(uint32 count) +* @brief This handles the errata for PLL1 and PLL2. This function is called in device startup +* +* @param[in] count : Number of retries until both PLLs are locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason + is that a PLL is already being used as a clock source. This can be caused by the workaround function + being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_both_plls(uint32 count) +{ + uint32 failCode,retries,clkCntlSav; + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for(retries = 0U;(retries < count);retries++) + { + failCode = 0U; + /* Disable PLL1 and PLL2 */ + failCode = disable_plls(SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2); + if(failCode != 0U) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR1[0U] = ESM_SR1_PLL1SLIP; + esmREG->SR4[0U] = ESM_SR4_PLL2SLIP; + /* set both PLLs to OSCIN/1*27/(2*1) */ + systemREG1->PLLCTL1 = 0x20001A00U; + systemREG1->PLLCTL2 = 0x3FC0723DU; + systemREG2->PLLCTL3 = 0x20001A00U; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2; + /* Check for (PLL1 valid or PLL1 slip) and (PLL2 valid or PLL2 slip) */ + while ((((systemREG1->CSVSTAT & SYS_CLKSRC_PLL1) == 0U) && ((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) == 0U)) || + (((systemREG1->CSVSTAT & SYS_CLKSRC_PLL2) == 0U) && ((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) == 0U))) + { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if(((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U)) + { + failCode |= 1U; + } + else + { + failCode |= check_frequency(dcc1CNT1_CLKSRC_PLL1); + } + /* If PLL2 valid, check the frequency */ + if(((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U)) + { + failCode |= 2U; + } + else + { + failCode |= (check_frequency(dcc1CNT1_CLKSRC_PLL2) << 1U); + } + if (failCode == 0U) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls(SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = (clkCntlSav & 0x000F0100U); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 _errata_SSWF021_45_pll1(uint32 count) +* @brief This handles the errata for PLL1. This function is called in device startup +* +* @param[in] count : Number of retries until both PLL1 is locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason + is that a PLL is already being used as a clock source. This can be caused by the workaround function + being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_pll1(uint32 count) +{ + uint32 failCode,retries,clkCntlSav; + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for(retries = 0U;(retries < count);retries++) + { + failCode = 0U; + /* Disable PLL1 */ + failCode = disable_plls(SYS_CLKSRC_PLL1); + if(failCode != 0U) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR1[0U] = ESM_SR1_PLL1SLIP; + /* set PLL1 to OSCIN/1*27/(2*1) */ + systemREG1->PLLCTL1 = 0x20001A00U; + systemREG1->PLLCTL2 = 0x3FC0723DU; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL1; + /* Check for PLL1 valid or PLL1 slip*/ + while(((systemREG1->CSVSTAT & SYS_CLKSRC_PLL1) == 0U) && ((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) == 0U)) + { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if(((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U)) + { + failCode |= 1U; + } + else + { + failCode |= check_frequency(dcc1CNT1_CLKSRC_PLL1); + } + if (failCode == 0U) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls(SYS_CLKSRC_PLL1); + + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = (clkCntlSav & 0x000F0100U); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 _errata_SSWF021_45_pll2(uint32 count) +* @brief This handles the errata for PLL2. This function is called in device startup +* +* @param[in] count : Number of retries until PLL2 is locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason + is that a PLL is already being used as a clock source. This can be caused by the workaround function + being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_pll2(uint32 count) +{ + uint32 failCode,retries,clkCntlSav; + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for(retries = 0U;(retries < count);retries++) + { + failCode = 0U; + /* Disable PLL2 */ + failCode = disable_plls(SYS_CLKSRC_PLL2); + if(failCode != 0U) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR4[0U] = ESM_SR4_PLL2SLIP; + /* set PLL2 to OSCIN/1*27/(2*1) */ + systemREG2->PLLCTL3 = 0x20001A00U; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL2; + /* Check for PLL2 valid or PLL2 slip */ + while (((systemREG1->CSVSTAT & SYS_CLKSRC_PLL2) == 0U) && ((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) == 0U)) + { + /* Wait */ + } + /* If PLL2 valid, check the frequency */ + if(((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U)) + { + failCode |= 2U; + } + else + { + failCode |= (check_frequency(dcc1CNT1_CLKSRC_PLL2) << 1U); + } + if (failCode == 0U) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls(SYS_CLKSRC_PLL2); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = (clkCntlSav & 0x000F0100U); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 check_frequency(uint32 cnt1_clksrc) +* @brief This function checks for the PLL frequency. +* +* @param[in] cnt1_clksrc : Clock source for Counter1 +* 0U - PLL1 (clock source 0) +* 1U - PLL2 (clock source 1) +* +* @return DCC Error status +* 0 - DCC error has not occurred +* 1 - DCC error has occurred +*/ +static uint32 check_frequency(uint32 cnt1_clksrc) +{ + /* Setup DCC1 */ + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = (uint32)0x5U | /** Disable DCC1 */ + (uint32)((uint32)0x5U << 4U) | /** No Error Interrupt */ + (uint32)((uint32)0xAU << 8U) | /** Single Shot mode */ + (uint32)((uint32)0x5U << 12U); /** No Done Interrupt */ + /* Clear ERR and DONE bits */ + dccREG1->STAT = 3U; + /** DCC1 Clock0 Counter Seed value configuration */ + dccREG1->CNT0SEED = 68U; + /** DCC1 Clock0 Valid Counter Seed value configuration */ + dccREG1->VALID0SEED = 4U; + /** DCC1 Clock1 Counter Seed value configuration */ + dccREG1->CNT1SEED = 972U; + /** DCC1 Clock1 Source 1 Select */ + dccREG1->CNT1CLKSRC = (uint32)((uint32)10U << 12U) | /** DCC Enable / Disable Key */ + (uint32) cnt1_clksrc; /** DCC1 Clock Source 1 */ + + dccREG1->CNT0CLKSRC = (uint32)DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */ + + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = (uint32)0xAU | /** Enable DCC1 */ + (uint32)((uint32)0x5U << 4U) | /** No Error Interrupt */ + (uint32)((uint32)0xAU << 8U) | /** Single Shot mode */ + (uint32)((uint32)0x5U << 12U); /** No Done Interrupt */ + while(dccREG1->STAT == 0U) + { + /* Wait */ + } + return (dccREG1->STAT & 0x01U); +} +/** @fn uint32 disable_plls(uint32 plls) +* @brief This function disables plls and clears the respective ESM flags. +* +* @param[in] plls : Clock source for Counter1 +* 2U - PLL1 +* 40U - PLL2 +* +* @return failCode +* 0 = Success (the PLL or both PLLs have successfully locked and then been disabled) +* 4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason +* is that a PLL is already being used as a clock source. This can be caused by the workaround function +* being called from the wrong place in the code. +*/ +static uint32 disable_plls(uint32 plls) +{ + uint32 timeout,failCode; + + systemREG1->CSDISSET = plls; + failCode = 0U; + timeout = 0x10U; + timeout --; + while(((systemREG1->CSVSTAT & (plls)) != 0U) && (timeout != 0U)) + { + /* Clear ESM and GLBSTAT PLL slip flags */ + systemREG1->GBLSTAT = 0x00000300U; + + if ((plls & SYS_CLKSRC_PLL1) == SYS_CLKSRC_PLL1) + { + esmREG->SR1[0U] = ESM_SR1_PLL1SLIP; + } + if ((plls & SYS_CLKSRC_PLL2) == SYS_CLKSRC_PLL2) + { + esmREG->SR4[0U] = ESM_SR4_PLL2SLIP; + } + timeout --; + /* Wait */ + } + if(timeout == 0U) + { + failCode = 4U; + } + else + { + failCode = 0U; + } + return failCode; +} diff --git a/src/arch/rm46l8lp/halcogen/esm.c b/src/arch/rm46l8lp/halcogen/esm.c new file mode 100644 index 0000000..16c94cc --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/esm.c @@ -0,0 +1,844 @@ +/** @file esm.c +* @brief Esm Driver Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - API Functions +* . +* which are relevant for the Esm driver. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "esm.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + +/** @fn void esmInit(void) +* @brief Initializes Esm Driver +* +* This function initializes the Esm driver. +* +*/ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/* SourceId : ESM_SourceId_001 */ +/* DesignId : ESM_DesignId_001 */ +/* Requirements : HL_SR4 */ +void esmInit(void) +{ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + + /** - Disable error pin channels */ + esmREG->DEPAPR1 = 0xFFFFFFFFU; + esmREG->IEPCR4 = 0xFFFFFFFFU; + + /** - Disable interrupts */ + esmREG->IECR1 = 0xFFFFFFFFU; + esmREG->IECR4 = 0xFFFFFFFFU; + + /** - Clear error status flags */ + esmREG->SR1[0U] = 0xFFFFFFFFU; + esmREG->SR1[1U] = 0xFFFFFFFFU; + esmREG->SSR2 = 0xFFFFFFFFU; + esmREG->SR1[2U] = 0xFFFFFFFFU; + esmREG->SR4[0U] = 0xFFFFFFFFU; + + /** - Setup LPC preload */ + esmREG->LTCPR = 16384U - 1U; + + /** - Reset error pin */ + if (esmREG->EPSR == 0U) + { + esmREG->EKR = 0x00000005U; + } + else + { + esmREG->EKR = 0x00000000U; + } + + /** - Clear interrupt level */ + esmREG->ILCR1 = 0xFFFFFFFFU; + esmREG->ILCR4 = 0xFFFFFFFFU; + + /** - Set interrupt level */ + esmREG->ILSR1 = (uint32)((uint32)0U << 31U) + | (uint32)((uint32)0U << 30U) + | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)0U << 28U) + | (uint32)((uint32)0U << 27U) + | (uint32)((uint32)0U << 26U) + | (uint32)((uint32)0U << 25U) + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)0U << 22U) + | (uint32)((uint32)0U << 21U) + | (uint32)((uint32)0U << 20U) + | (uint32)((uint32)0U << 19U) + | (uint32)((uint32)0U << 18U) + | (uint32)((uint32)0U << 17U) + | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)0U << 15U) + | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)0U << 12U) + | (uint32)((uint32)0U << 11U) + | (uint32)((uint32)0U << 10U) + | (uint32)((uint32)0U << 9U) + | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)0U << 7U) + | (uint32)((uint32)0U << 6U) + | (uint32)((uint32)0U << 5U) + | (uint32)((uint32)0U << 4U) + | (uint32)((uint32)0U << 3U) + | (uint32)((uint32)0U << 2U) + | (uint32)((uint32)0U << 1U) + | (uint32)((uint32)0U << 0U); + + esmREG->ILSR4 = (uint32)((uint32)0U << 31U) + | (uint32)((uint32)0U << 30U) + | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)0U << 28U) + | (uint32)((uint32)0U << 27U) + | (uint32)((uint32)0U << 26U) + | (uint32)((uint32)0U << 25U) + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)0U << 22U) + | (uint32)((uint32)0U << 21U) + | (uint32)((uint32)0U << 20U) + | (uint32)((uint32)0U << 19U) + | (uint32)((uint32)0U << 18U) + | (uint32)((uint32)0U << 17U) + | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)0U << 15U) + | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)0U << 12U) + | (uint32)((uint32)0U << 11U) + | (uint32)((uint32)0U << 10U) + | (uint32)((uint32)0U << 9U) + | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)0U << 7U) + | (uint32)((uint32)0U << 6U) + | (uint32)((uint32)0U << 5U) + | (uint32)((uint32)0U << 4U) + | (uint32)((uint32)0U << 3U) + | (uint32)((uint32)0U << 2U) + | (uint32)((uint32)0U << 1U) + | (uint32)((uint32)0U << 0U); + + /** - Enable error pin channels */ + esmREG->EEPAPR1 = (uint32)((uint32)1U << 31U) + | (uint32)((uint32)0U << 30U) + | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)0U << 28U) + | (uint32)((uint32)0U << 27U) + | (uint32)((uint32)0U << 26U) + | (uint32)((uint32)0U << 25U) + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)0U << 22U) + | (uint32)((uint32)0U << 21U) + | (uint32)((uint32)0U << 20U) + | (uint32)((uint32)0U << 19U) + | (uint32)((uint32)0U << 18U) + | (uint32)((uint32)0U << 17U) + | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)0U << 15U) + | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)0U << 12U) + | (uint32)((uint32)1U << 11U) + | (uint32)((uint32)1U << 10U) + | (uint32)((uint32)0U << 9U) + | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)0U << 7U) + | (uint32)((uint32)0U << 6U) + | (uint32)((uint32)0U << 5U) + | (uint32)((uint32)0U << 4U) + | (uint32)((uint32)0U << 3U) + | (uint32)((uint32)0U << 2U) + | (uint32)((uint32)0U << 1U) + | (uint32)((uint32)0U << 0U); + + esmREG->IEPSR4 = (uint32)((uint32)0U << 31U) + | (uint32)((uint32)0U << 30U) + | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)0U << 28U) + | (uint32)((uint32)0U << 27U) + | (uint32)((uint32)0U << 26U) + | (uint32)((uint32)0U << 25U) + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)0U << 22U) + | (uint32)((uint32)0U << 21U) + | (uint32)((uint32)0U << 20U) + | (uint32)((uint32)0U << 19U) + | (uint32)((uint32)0U << 18U) + | (uint32)((uint32)0U << 17U) + | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)0U << 15U) + | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)0U << 12U) + | (uint32)((uint32)0U << 11U) + | (uint32)((uint32)0U << 10U) + | (uint32)((uint32)0U << 9U) + | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)0U << 7U) + | (uint32)((uint32)0U << 6U) + | (uint32)((uint32)0U << 5U) + | (uint32)((uint32)0U << 4U) + | (uint32)((uint32)0U << 3U) + | (uint32)((uint32)0U << 2U) + | (uint32)((uint32)0U << 1U) + | (uint32)((uint32)0U << 0U); + + /** - Enable interrupts */ + esmREG->IESR1 = (uint32)((uint32)1U << 31U) + | (uint32)((uint32)0U << 30U) + | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)1U << 28U) + | (uint32)((uint32)1U << 27U) + | (uint32)((uint32)1U << 26U) + | (uint32)((uint32)0U << 25U) + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)0U << 22U) + | (uint32)((uint32)0U << 21U) + | (uint32)((uint32)0U << 20U) + | (uint32)((uint32)0U << 19U) + | (uint32)((uint32)0U << 18U) + | (uint32)((uint32)0U << 17U) + | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)0U << 15U) + | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)0U << 12U) + | (uint32)((uint32)1U << 11U) + | (uint32)((uint32)1U << 10U) + | (uint32)((uint32)0U << 9U) + | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)0U << 7U) + | (uint32)((uint32)1U << 6U) + | (uint32)((uint32)0U << 5U) + | (uint32)((uint32)0U << 4U) + | (uint32)((uint32)0U << 3U) + | (uint32)((uint32)0U << 2U) + | (uint32)((uint32)0U << 1U) + | (uint32)((uint32)0U << 0U); + + esmREG->IESR4 = (uint32)((uint32)0U << 31U) + | (uint32)((uint32)0U << 30U) + | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)0U << 28U) + | (uint32)((uint32)0U << 27U) + | (uint32)((uint32)0U << 26U) + | (uint32)((uint32)0U << 25U) + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)0U << 22U) + | (uint32)((uint32)0U << 21U) + | (uint32)((uint32)0U << 20U) + | (uint32)((uint32)0U << 19U) + | (uint32)((uint32)0U << 18U) + | (uint32)((uint32)0U << 17U) + | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)0U << 15U) + | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)0U << 12U) + | (uint32)((uint32)0U << 11U) + | (uint32)((uint32)1U << 10U) + | (uint32)((uint32)1U << 9U) + | (uint32)((uint32)1U << 8U) + | (uint32)((uint32)0U << 7U) + | (uint32)((uint32)0U << 6U) + | (uint32)((uint32)0U << 5U) + | (uint32)((uint32)0U << 4U) + | (uint32)((uint32)0U << 3U) + | (uint32)((uint32)0U << 2U) + | (uint32)((uint32)0U << 1U) + | (uint32)((uint32)0U << 0U); + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ +} + + +/** @fn uint32 esmError(void) +* @brief Return Error status +* +* @return The error status +* +* Returns the error status. +*/ +/* SourceId : ESM_SourceId_002 */ +/* DesignId : ESM_DesignId_002 */ +/* Requirements : HL_SR5 */ +uint32 esmError(void) +{ + uint32 status; + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + status = esmREG->EPSR; + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + return status; +} + + +/** @fn void esmEnableError(uint64 channels) +* @brief Enable Group 1 Channels Error Signals propagation +* +* @param[in] channels - Channel mask +* +* Enable Group 1 Channels Error Signals propagation to the error pin. +*/ +/* SourceId : ESM_SourceId_003 */ +/* DesignId : ESM_DesignId_003 */ +/* Requirements : HL_SR6 */ +void esmEnableError(uint64 channels) +{ +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + + esmREG->IEPSR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU); + esmREG->EEPAPR1 = (uint32)(channels & 0xFFFFFFFFU); + +/* USER CODE BEGIN (8) */ +/* USER CODE END */ +} + + +/** @fn void esmDisableError(uint64 channels) +* @brief Disable Group 1 Channels Error Signals propagation +* +* @param[in] channels - Channel mask +* +* Disable Group 1 Channels Error Signals propagation to the error pin. +*/ +/* SourceId : ESM_SourceId_004 */ +/* DesignId : ESM_DesignId_004 */ +/* Requirements : HL_SR7 */ +void esmDisableError(uint64 channels) +{ +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + esmREG->IEPCR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU); + esmREG->DEPAPR1 = (uint32)(channels & 0xFFFFFFFFU); + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ +} + + +/** @fn void esmTriggerErrorPinReset(void) +* @brief Trigger error pin reset and switch back to normal operation +* +* Trigger error pin reset and switch back to normal operation. +*/ +/* SourceId : ESM_SourceId_005 */ +/* DesignId : ESM_DesignId_005 */ +/* Requirements : HL_SR8 */ +void esmTriggerErrorPinReset(void) +{ +/* USER CODE BEGIN (11) */ +/* USER CODE END */ + + esmREG->EKR = 5U; + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ +} + + +/** @fn void esmActivateNormalOperation(void) +* @brief Activate normal operation +* +* Activates normal operation mode. +*/ +/* SourceId : ESM_SourceId_006 */ +/* DesignId : ESM_DesignId_006 */ +/* Requirements : HL_SR9 */ +void esmActivateNormalOperation(void) +{ +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + + esmREG->EKR = 0U; + +/* USER CODE BEGIN (14) */ +/* USER CODE END */ +} + + +/** @fn void esmEnableInterrupt(uint64 channels) +* @brief Enable Group 1 Channels Interrupts +* +* @param[in] channels - Channel mask +* +* Enable Group 1 Channels Interrupts. +*/ +/* SourceId : ESM_SourceId_007 */ +/* DesignId : ESM_DesignId_007 */ +/* Requirements : HL_SR10 */ +void esmEnableInterrupt(uint64 channels) +{ +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + + esmREG->IESR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU); + esmREG->IESR1 = (uint32)(channels & 0xFFFFFFFFU); + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ +} + + +/** @fn void esmDisableInterrupt(uint64 channels) +* @brief Disable Group 1 Channels Interrupts +* +* @param[in] channels - Channel mask +* +* Disable Group 1 Channels Interrupts. +*/ +/* SourceId : ESM_SourceId_008 */ +/* DesignId : ESM_DesignId_008 */ +/* Requirements : HL_SR11 */ +void esmDisableInterrupt(uint64 channels) +{ +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + esmREG->IECR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU); + esmREG->IECR1 = (uint32)(channels & 0xFFFFFFFFU); + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ +} + + +/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags) +* @brief Set Group 1 Channels Interrupt Levels +* +* @param[in] channels - Channel mask +* @param[in] flags - Level mask: - 0: Low priority interrupt +* - 1: High priority interrupt +* +* Set Group 1 Channels Interrupts levels. +*/ +/* SourceId : ESM_SourceId_009 */ +/* DesignId : ESM_DesignId_009 */ +/* Requirements : HL_SR12 */ +void esmSetInterruptLevel(uint64 channels, uint64 flags) +{ +/* USER CODE BEGIN (19) */ +/* USER CODE END */ + + esmREG->ILCR4 = (uint32)(((channels & (~flags)) >> 32U) & 0xFFFFFFFFU); + esmREG->ILSR4 = (uint32)(((channels & flags) >> 32U) & 0xFFFFFFFFU); + esmREG->ILCR1 = (uint32)((channels & (~flags)) & 0xFFFFFFFFU); + esmREG->ILSR1 = (uint32)((channels & flags) & 0xFFFFFFFFU); + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ +} + + +/** @fn void esmClearStatus(uint32 group, uint64 channels) +* @brief Clear Group error status +* +* @param[in] group - Error group +* @param[in] channels - Channel mask +* +* Clear Group error status. +*/ +/* SourceId : ESM_SourceId_010 */ +/* DesignId : ESM_DesignId_010 */ +/* Requirements : HL_SR13 */ +void esmClearStatus(uint32 group, uint64 channels) +{ +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + + esmREG->SR1[group] = (uint32)(channels & 0xFFFFFFFFU); + if(group == 0U) + { + esmREG->SR4[group] = (uint32)((channels >> 32U) & 0xFFFFFFFFU); + } + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ +} + + +/** @fn void esmClearStatusBuffer(uint64 channels) +* @brief Clear Group 2 error status buffer +* +* @param[in] channels - Channel mask +* +* Clear Group 2 error status buffer. +*/ +/* SourceId : ESM_SourceId_011 */ +/* DesignId : ESM_DesignId_011 */ +/* Requirements : HL_SR14 */ +void esmClearStatusBuffer(uint64 channels) +{ +/* USER CODE BEGIN (23) */ +/* USER CODE END */ + + esmREG->SSR2 = (uint32)(channels & 0xFFFFFFFFU); + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ +} + + +/** @fn void esmSetCounterPreloadValue(uint32 value) +* @brief Set counter preload value +* +* @param[in] value - Counter preload value +* +* Set counter preload value. +*/ +/* SourceId : ESM_SourceId_012 */ +/* DesignId : ESM_DesignId_012 */ +/* Requirements : HL_SR15 */ +void esmSetCounterPreloadValue(uint32 value) +{ +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + + esmREG->LTCPR = value & 0xC000U; + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ +} + + +/** @fn uint64 esmGetStatus(uint32 group, uint64 channels) +* @brief Return Error status +* +* @param[in] group - Error group +* @param[in] channels - Error Channels +* +* @return The channels status of selected group +* +* Returns the channels status of selected group. +*/ +/* SourceId : ESM_SourceId_013 */ +/* DesignId : ESM_DesignId_013 */ +/* Requirements : HL_SR16 */ +uint64 esmGetStatus(uint32 group, uint64 channels) +{ + uint64 status; + uint32 ESM_ESTATUS4, ESM_ESTATUS1; + if(group == 0U) + { + ESM_ESTATUS4 = esmREG->SR4[group]; + } + else + { + ESM_ESTATUS4 = 0U; + } + ESM_ESTATUS1 = esmREG->SR1[group]; + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ + status = (((uint64)(ESM_ESTATUS4) << 32U) | (uint64)ESM_ESTATUS1) & channels; + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + + return status; +} + + +/** @fn uint64 esmGetStatusBuffer(uint64 channels) +* @brief Return Group 2 channel x Error status buffer +* +* @param[in] channels - Error Channels +* +* @return The channels status +* +* Returns the group 2 buffered status of selected channels. +*/ +/* SourceId : ESM_SourceId_014 */ +/* DesignId : ESM_DesignId_014 */ +/* Requirements : HL_SR17 */ +uint64 esmGetStatusBuffer(uint64 channels) +{ + uint64 status; + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + status = ((uint64)esmREG->SSR2) & channels; + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + + return status; +} + +/** @fn esmSelfTestFlag_t esmEnterSelfTest(void) +* @brief Return ESM Self test status +* +* @return ESM Self test status +* +* Returns the ESM Self test status. +*/ +/* SourceId : ESM_SourceId_015 */ +/* DesignId : ESM_DesignId_015 */ +/* Requirements : HL_SR19 */ +esmSelfTestFlag_t esmEnterSelfTest(void) +{ + esmSelfTestFlag_t status; + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + + uint32 errPinStat = esmREG->EPSR & 0x1U; + uint32 esmKeyReg = esmREG->EKR; + if((errPinStat == 0x0U) && (esmKeyReg == 0x0U)) + { + status = esmSelfTest_NotStarted; + } + else + { + esmREG->EKR = 0xAU; + status = esmSelfTest_Active; + if((esmREG->EPSR & 0x1U) != 0x0U) + { + status = esmSelfTest_Failed; + } + esmREG->EKR = 0x5U; + } + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + + return status; +} + +/** @fn esmSelfTestFlag_t esmSelfTestStatus(void) +* @brief Return ESM Self test status +* +* Returns the ESM Self test status. +*/ +/* SourceId : ESM_SourceId_016 */ +/* DesignId : ESM_DesignId_016 */ +/* Requirements : HL_SR18 */ +esmSelfTestFlag_t esmSelfTestStatus(void) +{ + esmSelfTestFlag_t status; + +/* USER CODE BEGIN (33) */ +/* USER CODE END */ + + if((esmREG->EPSR & 0x1U) == 0x0U) + { + if(esmREG->EKR == 0x5U) + { + status = esmSelfTest_Active; + } + else + { + status = esmSelfTest_Failed; + } + } + else + { + status = esmSelfTest_Passed; + } + +/* USER CODE BEGIN (34) */ +/* USER CODE END */ + + return status; +} + +/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ESM_SourceId_017 */ +/* DesignId : ESM_DesignId_017 */ +/* Requirements : HL_SR20, HL_SR24 */ +void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_EEPAPR1 = ESM_EEPAPR1_CONFIGVALUE; + config_reg->CONFIG_IESR1 = ESM_IESR1_CONFIGVALUE; + config_reg->CONFIG_ILSR1 = ESM_ILSR1_CONFIGVALUE; + config_reg->CONFIG_LTCPR = ESM_LTCPR_CONFIGVALUE; + config_reg->CONFIG_EKR = ESM_EKR_CONFIGVALUE; + config_reg->CONFIG_IEPSR4 = ESM_IEPSR4_CONFIGVALUE; + config_reg->CONFIG_IESR4 = ESM_IESR4_CONFIGVALUE; + config_reg->CONFIG_ILSR4 = ESM_ILSR4_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_EEPAPR1 = esmREG->EEPAPR1; + config_reg->CONFIG_IESR1 = esmREG->IESR1; + config_reg->CONFIG_ILSR1 = esmREG->ILSR1; + config_reg->CONFIG_LTCPR = esmREG->LTCPR; + config_reg->CONFIG_EKR = esmREG->EKR; + config_reg->CONFIG_IEPSR4 = esmREG->IEPSR4; + config_reg->CONFIG_IESR4 = esmREG->IESR4; + config_reg->CONFIG_ILSR4 = esmREG->ILSR4; + } +} + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ + +/** @fn void esmHighInterrupt(void) +* @brief High Level Interrupt for ESM +*/ +#pragma CODE_STATE(esmHighInterrupt, 32) +#pragma INTERRUPT(esmHighInterrupt, FIQ) +/* SourceId : ESM_SourceId_018 */ +/* DesignId : ESM_DesignId_018 */ +/* Requirements : HL_SR21, HL_SR22 */ +void esmHighInterrupt(void) +{ + uint32 vec = esmREG->IOFFHR - 1U; + +/* USER CODE BEGIN (36) */ +/* USER CODE END */ + + if (vec < 32U) + { + esmREG->SR1[0U] = (uint32)1U << vec; + esmGroup1Notification(vec); + } + else if (vec < 64U) + { + esmREG->SR1[1U] = (uint32)1U << (vec-32U); + esmGroup2Notification(vec-32U); + } + else if (vec < 96U) + { + esmREG->SR4[0U] = (uint32)1U << (vec-64U); + esmGroup1Notification(vec-32U); + } + else + { + esmREG->SR4[0U] = 0xFFFFFFFFU; + esmREG->SR1[1U] = 0xFFFFFFFFU; + esmREG->SR1[0U] = 0xFFFFFFFFU; + } + +/* USER CODE BEGIN (37) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (38) */ +/* USER CODE END */ + +/** @fn void esmLowInterrupt(void) +* @brief Low Level Interrupt for ESM +*/ +#pragma CODE_STATE(esmLowInterrupt, 32) +#pragma INTERRUPT(esmLowInterrupt, IRQ) +/* SourceId : ESM_SourceId_019 */ +/* DesignId : ESM_DesignId_018 */ +/* Requirements : HL_SR21, HL_SR22 */ +void esmLowInterrupt(void) +{ + + /* Note : Group 1 Error */ + /* 1 to 32 -> channel 0 to 31 */ + /* 65 to 96 -> channel 32 to 63 */ + + uint32 vec = esmREG->IOFFLR - 1U; + +/* USER CODE BEGIN (39) */ +/* USER CODE END */ + + if (vec < 32U) /* channel 0 to 31 */ + { + esmREG->SR1[0U] = (uint32)1U << vec; + esmGroup1Notification(vec); + } + else if ((vec >= 64U) && (vec < 96U)) /* channel 32 to 63 */ + { + esmREG->SR4[0U] = (uint32)1U << (vec-64U); + esmGroup1Notification(vec-32U); + } + else + { + esmREG->SR4[0U] = 0xFFFFFFFFU; + esmREG->SR1[0U] = 0xFFFFFFFFU; + } + +/* USER CODE BEGIN (40) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (41) */ +/* USER CODE END */ diff --git a/src/arch/rm46l8lp/halcogen/gio.c b/src/arch/rm46l8lp/halcogen/gio.c new file mode 100644 index 0000000..2365e18 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/gio.c @@ -0,0 +1,518 @@ +/** @file gio.c +* @brief GIO Driver Implementation File +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "gio.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void gioInit(void) +* @brief Initializes the GIO Driver +* +* This function initializes the GIO module and set the GIO ports +* to the initial values. +*/ +/* SourceId : GIO_SourceId_001 */ +/* DesignId : GIO_DesignId_001 */ +/* Requirements : HL_SR26 */ +void gioInit(void) +{ +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + + /** bring GIO module out of reset */ + gioREG->GCR0 = 1U; + gioREG->ENACLR = 0xFFU; + gioREG->LVLCLR = 0xFFU; + + /** @b initialize @b Port @b A */ + + /** - Port A output values */ + gioPORTA->DOUT = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)0U << 1U) /* Bit 1 */ + | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U); /* Bit 7 */ + + /** - Port A direction */ + gioPORTA->DIR = (uint32)((uint32)1U << 0U) /* Bit 0 */ + | (uint32)((uint32)1U << 1U) /* Bit 1 */ + | (uint32)((uint32)1U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U); /* Bit 7 */ + + /** - Port A open drain enable */ + gioPORTA->PDR = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)0U << 1U) /* Bit 1 */ + | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U); /* Bit 7 */ + + /** - Port A pullup / pulldown selection */ + gioPORTA->PSL = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)0U << 1U) /* Bit 1 */ + | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U); /* Bit 7 */ + + /** - Port A pullup / pulldown enable*/ + gioPORTA->PULDIS = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)0U << 1U) /* Bit 1 */ + | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U); /* Bit 7 */ + + /** @b initialize @b Port @b B */ + + /** - Port B output values */ + gioPORTB->DOUT = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)0U << 1U) /* Bit 1 */ + | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U); /* Bit 7 */ + + /** - Port B direction */ + gioPORTB->DIR = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)1U << 1U) /* Bit 1 */ + | (uint32)((uint32)1U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U); /* Bit 7 */ + + /** - Port B open drain enable */ + gioPORTB->PDR = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)0U << 1U) /* Bit 1 */ + | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U); /* Bit 7 */ + + /** - Port B pullup / pulldown selection */ + gioPORTB->PSL = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)0U << 1U) /* Bit 1 */ + | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U); /* Bit 7 */ + + /** - Port B pullup / pulldown enable*/ + gioPORTB->PULDIS = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)0U << 1U) /* Bit 1 */ + | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U); /* Bit 7 */ + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + + /** @b initialize @b interrupts */ + + /** - interrupt polarity */ + gioREG->POL = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)0U << 1U) /* Bit 1 */ + | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U) /* Bit 7 */ + | (uint32)((uint32)0U << 8U) /* Bit 8 */ + | (uint32)((uint32)0U << 9U) /* Bit 9 */ + | (uint32)((uint32)0U << 10U) /* Bit 10 */ + | (uint32)((uint32)0U << 11U) /* Bit 11 */ + | (uint32)((uint32)0U << 12U) /* Bit 12 */ + | (uint32)((uint32)0U << 13U) /* Bit 13 */ + | (uint32)((uint32)0U << 14U) /* Bit 14 */ + | (uint32)((uint32)0U << 15U); /* Bit 15 */ + + + /** - interrupt level */ + gioREG->LVLSET = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)0U << 1U) /* Bit 1 */ + | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U) /* Bit 7 */ + | (uint32)((uint32)0U << 8U) /* Bit 8 */ + | (uint32)((uint32)0U << 9U) /* Bit 9 */ + | (uint32)((uint32)0U << 10U) /* Bit 10 */ + | (uint32)((uint32)0U << 11U) /* Bit 11 */ + | (uint32)((uint32)0U << 12U) /* Bit 12 */ + | (uint32)((uint32)0U << 13U) /* Bit 13 */ + | (uint32)((uint32)0U << 14U) /* Bit 14 */ + | (uint32)((uint32)0U << 15U); /* Bit 15 */ + + + + + /** - clear all pending interrupts */ + gioREG->FLG = 0xFFU; + + /** - enable interrupts */ + gioREG->ENASET = (uint32)((uint32)0U << 0U) /* Bit 0 */ + | (uint32)((uint32)0U << 1U) /* Bit 1 */ + | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)0U << 4U) /* Bit 4 */ + | (uint32)((uint32)0U << 5U) /* Bit 5 */ + | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)0U << 7U) /* Bit 7 */ + | (uint32)((uint32)0U << 8U) /* Bit 8 */ + | (uint32)((uint32)0U << 9U) /* Bit 9 */ + | (uint32)((uint32)0U << 10U) /* Bit 10 */ + | (uint32)((uint32)0U << 11U) /* Bit 11 */ + | (uint32)((uint32)0U << 12U) /* Bit 12 */ + | (uint32)((uint32)0U << 13U) /* Bit 13 */ + | (uint32)((uint32)0U << 14U) /* Bit 14 */ + | (uint32)((uint32)0U << 15U); /* Bit 15 */ + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ +} + + +/** @fn void gioSetDirection(gioPORT_t *port, uint32 dir) +* @brief Set Port Direction +* @param[in] port pointer to GIO port: +* - gioPORTA: PortA pointer +* - gioPORTB: PortB pointer +* @param[in] dir value to write to DIR register +* +* Set the direction of GIO pins at runtime. +*/ +/* SourceId : GIO_SourceId_002 */ +/* DesignId : GIO_DesignId_002 */ +/* Requirements : HL_SR27 */ +void gioSetDirection(gioPORT_t *port, uint32 dir) +{ + port->DIR = dir; +} + + +/** @fn void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value) +* @brief Write Bit +* @param[in] port pointer to GIO port: +* - gioPORTA: PortA pointer +* - gioPORTB: PortB pointer +* @param[in] bit number 0-7 that specifies the bit to be written to. +* - 0: LSB +* - 7: MSB +* @param[in] value binary value to write to bit +* +* Writes a value to the specified pin of the given GIO port +*/ +/* SourceId : GIO_SourceId_003 */ +/* DesignId : GIO_DesignId_003 */ +/* Requirements : HL_SR28 */ +void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value) +{ +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + if (value != 0U) + { + port->DSET = (uint32)1U << bit; + } + else + { + port->DCLR = (uint32)1U << bit; + } +} + + +/** @fn void gioSetPort(gioPORT_t *port, uint32 value) +* @brief Write Port Value +* @param[in] port pointer to GIO port: +* - gioPORTA: PortA pointer +* - gioPORTB: PortB pointer +* @param[in] value value to write to port +* +* Writes a value to all pin of a given GIO port +*/ +/* SourceId : GIO_SourceId_004 */ +/* DesignId : GIO_DesignId_004 */ +/* Requirements : HL_SR29 */ +void gioSetPort(gioPORT_t *port, uint32 value) +{ +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + port->DOUT = value; + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + +} + + +/** @fn uint32 gioGetBit(gioPORT_t *port, uint32 bit) +* @brief Read Bit +* @param[in] port pointer to GIO port: +* - gioPORTA: PortA pointer +* - gioPORTB: PortB pointer +* @param[in] bit number 0-7 that specifies the bit to be written to. +* - 0: LSB +* - 7: MSB +* +* Reads a the current value from the specified pin of the given GIO port +*/ +/* SourceId : GIO_SourceId_005 */ +/* DesignId : GIO_DesignId_005 */ +/* Requirements : HL_SR30 */ +uint32 gioGetBit(gioPORT_t *port, uint32 bit) +{ +/* USER CODE BEGIN (8) */ +/* USER CODE END */ + + return (port->DIN >> bit) & 1U; +} + + +/** @fn uint32 gioGetPort(gioPORT_t *port) +* @brief Read Port Value +* @param[in] port pointer to GIO port: +* - gioPORTA: PortA pointer +* - gioPORTB: PortB pointer +* +* Reads a the current value of a given GIO port +*/ +/* SourceId : GIO_SourceId_006 */ +/* DesignId : GIO_DesignId_006 */ +/* Requirements : HL_SR31 */ +uint32 gioGetPort(gioPORT_t *port) +{ +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + return port->DIN; +} + +/** @fn void gioToggleBit(gioPORT_t *port, uint32 bit) +* @brief Write Bit +* @param[in] port pointer to GIO port: +* - gioPORTA: PortA pointer +* - gioPORTB: PortB pointer +* @param[in] bit number 0-7 that specifies the bit to be written to. +* - 0: LSB +* - 7: MSB +* +* Toggle a value to the specified pin of the given GIO port +*/ +/* SourceId : GIO_SourceId_007 */ +/* DesignId : GIO_DesignId_007 */ +/* Requirements : HL_SR32 */ +void gioToggleBit(gioPORT_t *port, uint32 bit) +{ +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + + if ((port->DIN & (uint32)((uint32)1U << bit)) != 0U) + { + port->DCLR = (uint32)1U << bit; + } + else + { + port->DSET = (uint32)1U << bit; + } +} + +/** @fn void gioEnableNotification(uint32 bit) +* @brief Enable Interrupt +* @param[in] port pointer to GIO port: +* - gioPORTA: PortA pointer +* - gioPORTB: PortB pointer +* @param[in] bit interrupt pin to enable +* - 0: LSB +* - 7: MSB +* +* Enables an interrupt pin of selected port +*/ +/* SourceId : GIO_SourceId_008 */ +/* DesignId : GIO_DesignId_008 */ +/* Requirements : HL_SR33 */ +void gioEnableNotification(gioPORT_t *port, uint32 bit) +{ +/* USER CODE BEGIN (11) */ +/* USER CODE END */ + + if (port == gioPORTA) + { + gioREG->ENASET = (uint32)1U << bit; + } + else if (port == gioPORTB) + { + gioREG->ENASET = (uint32)1U << (bit + 8U); + } + else + { + /* Empty */ + } +} + + +/** @fn void gioDisableNotification(uint32 bit) +* @brief Disable Interrupt +* @param[in] port pointer to GIO port: +* - gioPORTA: PortA pointer +* - gioPORTB: PortB pointer +* @param[in] bit interrupt pin to enable +* - 0: LSB +* - 7: MSB +* +* Disables an interrupt pin of selected port +*/ +/* SourceId : GIO_SourceId_009 */ +/* DesignId : GIO_DesignId_009 */ +/* Requirements : HL_SR34 */ +void gioDisableNotification(gioPORT_t *port, uint32 bit) +{ +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + + if (port == gioPORTA) + { + gioREG->ENACLR = (uint32)1U << bit; + } + else if (port == gioPORTB) + { + gioREG->ENACLR = (uint32)1U << (bit + 8U); + } + else + { + /* Empty */ + } +} + +/** @fn void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : GIO_SourceId_010 */ +/* DesignId : GIO_DesignId_010 */ +/* Requirements : HL_SR37 */ +void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_INTDET = GIO_INTDET_CONFIGVALUE; + config_reg->CONFIG_POL = GIO_POL_CONFIGVALUE; + config_reg->CONFIG_INTENASET = GIO_INTENASET_CONFIGVALUE; + config_reg->CONFIG_LVLSET = GIO_LVLSET_CONFIGVALUE; + + config_reg->CONFIG_PORTADIR = GIO_PORTADIR_CONFIGVALUE; + config_reg->CONFIG_PORTAPDR = GIO_PORTAPDR_CONFIGVALUE; + config_reg->CONFIG_PORTAPSL = GIO_PORTAPSL_CONFIGVALUE; + config_reg->CONFIG_PORTAPULDIS = GIO_PORTAPULDIS_CONFIGVALUE; + + config_reg->CONFIG_PORTBDIR = GIO_PORTBDIR_CONFIGVALUE; + config_reg->CONFIG_PORTBPDR = GIO_PORTBPDR_CONFIGVALUE; + config_reg->CONFIG_PORTBPSL = GIO_PORTBPSL_CONFIGVALUE; + config_reg->CONFIG_PORTBPULDIS = GIO_PORTBPULDIS_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_INTDET = gioREG->INTDET; + config_reg->CONFIG_POL = gioREG->POL; + config_reg->CONFIG_INTENASET = gioREG->ENASET; + config_reg->CONFIG_LVLSET = gioREG->LVLSET; + + config_reg->CONFIG_PORTADIR = gioPORTA->DIR; + config_reg->CONFIG_PORTAPDR = gioPORTA->PDR; + config_reg->CONFIG_PORTAPSL = gioPORTA->PSL; + config_reg->CONFIG_PORTAPULDIS = gioPORTA->PULDIS; + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_PORTBDIR = gioPORTB->DIR; + config_reg->CONFIG_PORTBPDR = gioPORTB->PDR; + config_reg->CONFIG_PORTBPSL = gioPORTB->PSL; + config_reg->CONFIG_PORTBPULDIS = gioPORTB->PULDIS; + } +} + + + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ diff --git a/src/arch/rm46l8lp/halcogen/het.c b/src/arch/rm46l8lp/halcogen/het.c new file mode 100644 index 0000000..b83fab4 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/het.c @@ -0,0 +1,1936 @@ +/** @file het.c +* @brief HET Driver Implementation File +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +#include "het.h" +#include "sys_vim.h" +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/*----------------------------------------------------------------------------*/ +/* Global variables */ + +static const uint32 s_het1pwmPolarity[8U] = +{ + 3U, + 3U, + 3U, + 3U, + 3U, + 3U, + 3U, + 3U, +}; + + +/*----------------------------------------------------------------------------*/ +/* Default Program */ + +/** @var static const hetINSTRUCTION_t het1PROGRAM[58] +* @brief Default Program +* +* Het program running after initialization. +*/ + +static const hetINSTRUCTION_t het1PROGRAM[58U] = +{ + /* CNT: Timebase + * - Instruction = 0 + * - Next instruction = 1 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { + /* Program */ + 0x00002C80U, + /* Control */ + 0x01FFFFFFU, + /* Data */ + 0xFFFFFF80U, + /* Reserved */ + 0x00000000U + }, + /* PWCNT: PWM 0 -> Duty Cycle + * - Instruction = 1 + * - Next instruction = 2 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { + /* Program */ + 0x000055C0U, + /* Control */ + (0x00004006U | (uint32)((uint32)8U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* DJZ: PWM 0 -> Period + * - Instruction = 2 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { + /* Program */ + 0x00007480U, + /* Control */ + 0x00052006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PWCNT: PWM 1 -> Duty Cycle + * - Instruction = 3 + * - Next instruction = 4 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { + /* Program */ + 0x000095C0U, + /* Control */ + (0x00008006U | (uint32)((uint32)10U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* DJZ: PWM 1 -> Period + * - Instruction = 4 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { + /* Program */ + 0x0000B480U, + /* Control */ + 0x00056006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PWCNT: PWM 2 -> Duty Cycle + * - Instruction = 5 + * - Next instruction = 6 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { + /* Program */ + 0x0000D5C0U, + /* Control */ + (0x0000C006U | (uint32)((uint32)12U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* DJZ: PWM 2 -> Period + * - Instruction = 6 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { + /* Program */ + 0x0000F480U, + /* Control */ + 0x0005A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PWCNT: PWM 3 -> Duty Cycle + * - Instruction = 7 + * - Next instruction = 8 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { + /* Program */ + 0x000115C0U, + /* Control */ + (0x00010006U | (uint32)((uint32)14U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* DJZ: PWM 3 -> Period + * - Instruction = 8 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { + /* Program */ + 0x00013480U, + /* Control */ + 0x0005E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PWCNT: PWM 4 -> Duty Cycle + * - Instruction = 9 + * - Next instruction = 10 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { + /* Program */ + 0x000155C0U, + /* Control */ + (0x00014006U | (uint32)((uint32)16U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* DJZ: PWM 4 -> Period + * - Instruction = 10 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { + /* Program */ + 0x00017480U, + /* Control */ + 0x00062006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PWCNT: PWM 5 -> Duty Cycle + * - Instruction = 11 + * - Next instruction = 12 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { + /* Program */ + 0x000195C0U, + /* Control */ + (0x00018006U | (uint32)((uint32)17U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* DJZ: PWM 5 -> Period + * - Instruction = 12 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { + /* Program */ + 0x0001B480U, + /* Control */ + 0x00066006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PWCNT: PWM 6 -> Duty Cycle + * - Instruction = 13 + * - Next instruction = 14 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { + /* Program */ + 0x0001D5C0U, + /* Control */ + (0x0001C006U | (uint32)((uint32)18U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* DJZ: PWM 6 -> Period + * - Instruction = 14 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { + /* Program */ + 0x0001F480U, + /* Control */ + 0x0006A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PWCNT: PWM 7 -> Duty Cycle + * - Instruction = 15 + * - Next instruction = 16 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { + /* Program */ + 0x000215C0U, + /* Control */ + (0x00020006U | (uint32)((uint32)19U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* DJZ: PWM 7 -> Period + * - Instruction = 16 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { + /* Program */ + 0x00023480U, + /* Control */ + 0x0006E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* ECNT: CCU Edge 0 + * - Instruction = 17 + * - Next instruction = 18 + * - Conditional next instruction = 18 + * - Interrupt = 17 + * - Pin = 9 + */ + { + /* Program */ + 0x00025440U, + /* Control */ + (0x00024007U | (uint32)((uint32)9U << 8U) | (uint32)((uint32)1U << 4U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* ECNT: CCU Edge 1 + * - Instruction = 18 + * - Next instruction = 19 + * - Conditional next instruction = 19 + * - Interrupt = 18 + * - Pin = 11 + */ + { + /* Program */ + 0x00027440U, + /* Control */ + (0x00026007U | (uint32)((uint32)11U << 8U) | (uint32)((uint32)1U << 4U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* ECNT: CCU Edge 2 + * - Instruction = 19 + * - Next instruction = 20 + * - Conditional next instruction = 20 + * - Interrupt = 19 + * - Pin = 13 + */ + { + /* Program */ + 0x00029440U, + /* Control */ + (0x00028007U | (uint32)((uint32)13U << 8U) | (uint32)((uint32)1U << 4U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* ECNT: CCU Edge 3 + * - Instruction = 20 + * - Next instruction = 21 + * - Conditional next instruction = 21 + * - Interrupt = 20 + * - Pin = 15 + */ + { + /* Program */ + 0x0002B440U, + /* Control */ + (0x0002A007U | (uint32)((uint32)15U << 8U) | (uint32)((uint32)1U << 4U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* ECNT: CCU Edge 4 + * - Instruction = 21 + * - Next instruction = 22 + * - Conditional next instruction = 22 + * - Interrupt = 21 + * - Pin = 20 + */ + { + /* Program */ + 0x0002D440U, + /* Control */ + (0x0002C007U | (uint32)((uint32)20U << 8U) | (uint32)((uint32)1U << 4U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* ECNT: CCU Edge 5 + * - Instruction = 22 + * - Next instruction = 23 + * - Conditional next instruction = 23 + * - Interrupt = 22 + * - Pin = 21 + */ + { + /* Program */ + 0x0002F440U, + /* Control */ + (0x0002E007U | (uint32)((uint32)21U << 8U) | (uint32)((uint32)1U << 4U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* ECNT: CCU Edge 6 + * - Instruction = 23 + * - Next instruction = 24 + * - Conditional next instruction = 24 + * - Interrupt = 23 + * - Pin = 22 + */ + { + /* Program */ + 0x00031440U, + /* Control */ + (0x00030007U | (uint32)((uint32)22U << 8U) | (uint32)((uint32)1U << 4U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* ECNT: CCU Edge 7 + * - Instruction = 24 + * - Next instruction = 25 + * - Conditional next instruction = 25 + * - Interrupt = 24 + * - Pin = 23 + */ + { + /* Program */ + 0x00033440U, + /* Control */ + (0x00032007U | (uint32)((uint32)23U << 8U) | (uint32)((uint32)1U << 4U)), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Duty 0 + * - Instruction = 25 + * - Next instruction = 26 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + */ + { + /* Program */ + 0x00034E00U | (uint32)((uint32)0U << 6U) | (uint32)(0U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Period 0 + * - Instruction = 26 + * - Next instruction = 27 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + 1 + */ + { + /* Program */ + 0x00036E80U | (uint32)((uint32)0U << 6U) | (uint32)((0U) + 1U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Duty 1 + * - Instruction = 27 + * - Next instruction = 28 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + */ + { + /* Program */ + 0x00038E00U | (uint32)((uint32)0U << 6U) | (uint32)(2U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Period 1 + * - Instruction = 28 + * - Next instruction = 29 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + 1 + */ + { + /* Program */ + 0x0003AE80U | (uint32)((uint32)0U << 6U) | (uint32)((2U) + 1U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Duty 2 + * - Instruction = 29 + * - Next instruction = 30 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + */ + { + /* Program */ + 0x0003CE00U | (uint32)((uint32)0U << 6U) | (uint32)(4U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Period 2 + * - Instruction = 30 + * - Next instruction = 31 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + 1 + */ + { + /* Program */ + 0x0003EE80U | (uint32)((uint32)0U << 6U) | (uint32)((4U) + 1U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Duty 3 + * - Instruction = 31 + * - Next instruction = 32 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + */ + { + /* Program */ + 0x00040E00U | (uint32)((uint32)0U << 6U) | (uint32)(6U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Period 3 + * - Instruction = 32 + * - Next instruction = 33 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + 1 + */ + { + /* Program */ + 0x00042E80U | (uint32)((uint32)0U << 6U) | (uint32)((6U) + 1U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Duty 4 + * - Instruction = 33 + * - Next instruction = 34 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + */ + { + /* Program */ + 0x00044E00U | (uint32)((uint32)0U << 6U) | (uint32)(24U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Period 4 + * - Instruction = 34 + * - Next instruction = 35 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + 1 + */ + { + /* Program */ + 0x00046E80U | (uint32)((uint32)0U << 6U) | (uint32)((24U) + 1U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Duty 5 + * - Instruction = 35 + * - Next instruction = 36 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + */ + { + /* Program */ + 0x00048E00U | (uint32)((uint32)0U << 6U) | (uint32)(26U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Period 5 + * - Instruction = 36 + * - Next instruction = 37 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + 1 + */ + { + /* Program */ + 0x0004AE80U | (uint32)((uint32)0U << 6U) | (uint32)((26U) + 1U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Duty 6 + * - Instruction = 37 + * - Next instruction = 38 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + */ + { + /* Program */ + 0x0004CE00U | (uint32)((uint32)0U << 6U) | (uint32)(28U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Period 6 + * - Instruction = 38 + * - Next instruction = 39 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + 1 + */ + { + /* Program */ + 0x0004EE80U | (uint32)((uint32)0U << 6U) | (uint32)((28U) + 1U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Duty 7 + * - Instruction = 39 + * - Next instruction = 40 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + */ + { + /* Program */ + 0x00050E00U | (uint32)((uint32)0U << 6U) | (uint32)(30U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* PCNT: Capture Period 7 + * - Instruction = 40 + * - Next instruction = 57 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + 1 + */ + { + /* Program */ + 0x00072E80U | (uint32)((uint32)0U << 6U) | (uint32)((30U) + 1U), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 0 -> Duty Cycle Update + * - Instruction = 41 + * - Next instruction = 42 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { + /* Program */ + 0x00054201U, + /* Control */ + (0x00004007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)8U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 80128U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 0 -> Period Update + * - Instruction = 42 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { + /* Program */ + 0x00006202U, + /* Control */ + (0x00052007U), + /* Data */ + 159872U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 1 -> Duty Cycle Update + * - Instruction = 43 + * - Next instruction = 44 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { + /* Program */ + 0x00058203U, + /* Control */ + (0x00008007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)10U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 80128U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 1 -> Period Update + * - Instruction = 44 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { + /* Program */ + 0x0000A204U, + /* Control */ + (0x00056007U), + /* Data */ + 159872U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 2 -> Duty Cycle Update + * - Instruction = 45 + * - Next instruction = 46 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { + /* Program */ + 0x0005C205U, + /* Control */ + (0x0000C007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)12U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 80128U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 2 -> Period Update + * - Instruction = 46 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { + /* Program */ + 0x0000E206U, + /* Control */ + (0x0005A007U), + /* Data */ + 159872U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 3 -> Duty Cycle Update + * - Instruction = 47 + * - Next instruction = 48 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { + /* Program */ + 0x00060207U, + /* Control */ + (0x00010007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)14U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 80128U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 3 -> Period Update + * - Instruction = 48 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { + /* Program */ + 0x00012208U, + /* Control */ + (0x0005E007U), + /* Data */ + 159872U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 4 -> Duty Cycle Update + * - Instruction = 49 + * - Next instruction = 50 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { + /* Program */ + 0x00064209U, + /* Control */ + (0x00014007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)16U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 80128U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 4 -> Period Update + * - Instruction = 50 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { + /* Program */ + 0x0001620AU, + /* Control */ + (0x00062007U), + /* Data */ + 159872U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 5 -> Duty Cycle Update + * - Instruction = 51 + * - Next instruction = 52 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { + /* Program */ + 0x0006820BU, + /* Control */ + (0x00018007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)17U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 80128U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 5 -> Period Update + * - Instruction = 52 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { + /* Program */ + 0x0001A20CU, + /* Control */ + (0x00066007U), + /* Data */ + 159872U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 6 -> Duty Cycle Update + * - Instruction = 53 + * - Next instruction = 54 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { + /* Program */ + 0x0006C20DU, + /* Control */ + (0x0001C007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)18U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 80128U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 6 -> Period Update + * - Instruction = 54 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { + /* Program */ + 0x0001E20EU, + /* Control */ + (0x0006A007U), + /* Data */ + 159872U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 7 -> Duty Cycle Update + * - Instruction = 55 + * - Next instruction = 56 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { + /* Program */ + 0x0007020FU, + /* Control */ + (0x00020007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)19U << 8U) | (uint32)((uint32)3U << 3U)), + /* Data */ + 80128U, + /* Reserved */ + 0x00000000U + }, + /* MOV64: PWM 7 -> Period Update + * - Instruction = 56 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { + /* Program */ + 0x00022210U, + /* Control */ + (0x0006E007U), + /* Data */ + 159872U, + /* Reserved */ + 0x00000000U + }, + /* WCAP: Capture timestamp + * - Instruction = 57 + * - Next instruction = 0 + * - Conditional next instruction = 0 + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { + /* Program */ + 0x00001600U, + /* Control */ + (0x00000004U), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U + }, +}; + + + +/** @fn void hetInit(void) +* @brief Initializes the het Driver +* +* This function initializes the het 1 module. +*/ +/* SourceId : HET_SourceId_001 */ +/* DesignId : HET_DesignId_001 */ +/* Requirements : HL_SR363 */ +void hetInit(void) +{ + /** @b initialize @b HET */ + + /** - Set HET pins default output value */ + hetREG1->DOUT = (uint32)((uint32)0U << 31U) + | (uint32)((uint32)0U << 30U) + | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)0U << 28U) + | (uint32)((uint32)0U << 27U) + | (uint32)((uint32)0U << 26U) + | (uint32)((uint32)0U << 25U) + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)0U << 22U) + | (uint32)((uint32)0U << 21U) + | (uint32)((uint32)0U << 20U) + | (uint32)((uint32)0U << 19U) + | (uint32)((uint32)0U << 18U) + | (uint32)((uint32)0U << 17U) + | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)0U << 15U) + | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)0U << 12U) + | (uint32)((uint32)0U << 11U) + | (uint32)((uint32)0U << 10U) + | (uint32)((uint32)0U << 9U) + | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)0U << 7U) + | (uint32)((uint32)0U << 6U) + | (uint32)((uint32)0U << 5U) + | (uint32)((uint32)0U << 4U) + | (uint32)((uint32)0U << 3U) + | (uint32)((uint32)0U << 2U) + | (uint32)((uint32)0U << 1U) + | (uint32)((uint32)0U << 0U); + + /** - Set HET pins direction */ + hetREG1->DIR = (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U; + + /** - Set HET pins open drain enable */ + hetREG1->PDR = (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00008000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U; + + /** - Set HET pins pullup/down enable */ + hetREG1->PULDIS = (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U; + + /** - Set HET pins pullup/down select */ + hetREG1->PSL = (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00008000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U; + + /** - Set HET pins high resolution share */ + hetREG1->HRSH = (uint32) 0x00008000U + | (uint32) 0x00004000U + | (uint32) 0x00002000U + | (uint32) 0x00001000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000008U + | (uint32) 0x00000004U + | (uint32) 0x00000002U + | (uint32) 0x00000001U; + + /** - Set HET pins AND share */ + hetREG1->AND = (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U; + + /** - Set HET pins XOR share */ + hetREG1->XOR = (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG1->PFR = (uint32)((uint32) 6U << 8U) + | ((uint32) 0U); + + + /** - Parity control register + * - Enable/Disable Parity check + */ + hetREG1->PCR = (uint32) 0x00000005U; + + /** - Fill HET RAM with opcodes and Data */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 <APPROVED> "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 <APPROVED> "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 <APPROVED> "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 <APPROVED> "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */ + (void)memcpy((void *)hetRAM1, (const void *)het1PROGRAM, sizeof(het1PROGRAM)); + + /** - Setup interrupt priority level + * - PWM 0 end of duty level + * - PWM 0 end of period level + * - PWM 1 end of duty level + * - PWM 1 end of period level + * - PWM 2 end of duty level + * - PWM 2 end of period level + * - PWM 3 end of duty level + * - PWM 3 end of period level + * - PWM 4 end of duty level + * - PWM 4 end of period level + * - PWM 5 end of duty level + * - PWM 5 end of period level + * - PWM 6 end of duty level + * - PWM 6 end of period level + * - PWM 7 end of duty level + * - PWM 7 end of period level + + * - CCU Edge Detection 0 level + * - CCU Edge Detection 1 level + * - CCU Edge Detection 2 level + * - CCU Edge Detection 3 level + * - CCU Edge Detection 4 level + * - CCU Edge Detection 5 level + * - CCU Edge Detection 6 level + * - CCU Edge Detection 7 level + */ + hetREG1->PRY = (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U; + + /** - Enable interrupts + * - PWM 0 end of duty + * - PWM 0 end of period + * - PWM 1 end of duty + * - PWM 1 end of period + * - PWM 2 end of duty + * - PWM 2 end of period + * - PWM 3 end of duty + * - PWM 3 end of period + * - PWM 4 end of duty + * - PWM 4 end of period + * - PWM 5 end of duty + * - PWM 5 end of period + * - PWM 6 end of duty + * - PWM 6 end of period + * - PWM 7 end of duty + * - PWM 7 end of period + * - CCU Edge Detection 0 + * - CCU Edge Detection 1 + * - CCU Edge Detection 2 + * - CCU Edge Detection 3 + * - CCU Edge Detection 4 + * - CCU Edge Detection 5 + * - CCU Edge Detection 6 + * - CCU Edge Detection 7 + */ + hetREG1->INTENAC = 0xFFFFFFFFU; + hetREG1->INTENAS = (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U + | (uint32) 0x00000000U; + + + /** - Setup control register + * - Enable output buffers + * - Ignore software breakpoints + * - Master or Slave Clock Mode + * - Enable HET + */ + hetREG1->GCR = ( 0x00000001U + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)1U << 16U) + | (0x00020000U)); + + +} +/** @fn void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm) +* @brief Start pwm signal +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* @param[in] pwm Pwm signal: +* - pwm0: Pwm 0 +* - pwm1: Pwm 1 +* - pwm2: Pwm 2 +* - pwm3: Pwm 3 +* - pwm4: Pwm 4 +* - pwm5: Pwm 5 +* - pwm6: Pwm 6 +* - pwm7: Pwm 7 +* +* Start the given pwm signal +*/ +/* SourceId : HET_SourceId_002 */ +/* DesignId : HET_DesignId_002 */ +/* Requirements : HL_SR364 */ +void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm) +{ + + hetRAM->Instruction[(pwm << 1U) + 41U].Control |= 0x00400000U; +} + + +/** @fn void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm) +* @brief Stop pwm signal +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* @param[in] pwm Pwm signal: +* - pwm0: Pwm 0 +* - pwm1: Pwm 1 +* - pwm2: Pwm 2 +* - pwm3: Pwm 3 +* - pwm4: Pwm 4 +* - pwm5: Pwm 5 +* - pwm6: Pwm 6 +* - pwm7: Pwm 7 +* +* Stop the given pwm signal +*/ +/* SourceId : HET_SourceId_003 */ +/* DesignId : HET_DesignId_003 */ +/* Requirements : HL_SR365 */ +void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm) +{ + hetRAM->Instruction[(pwm << 1U) + 41U].Control &= ~(uint32)0x00400000U; +} + + +/** @fn void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty) +* @brief Set duty cycle +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* @param[in] pwm Pwm signal: +* - pwm0: Pwm 0 +* - pwm1: Pwm 1 +* - pwm2: Pwm 2 +* - pwm3: Pwm 3 +* - pwm4: Pwm 4 +* - pwm5: Pwm 5 +* - pwm6: Pwm 6 +* - pwm7: Pwm 7 +* @param[in] pwmDuty duty cycle in %. +* +* Sets a new duty cycle on the given pwm signal +*/ +/* SourceId : HET_SourceId_004 */ +/* DesignId : HET_DesignId_004 */ +/* Requirements : HL_SR366 */ +void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty) +{ + uint32 action; + uint32 pwmPolarity =0U; + uint32 pwmPeriod = hetRAM->Instruction[(pwm << 1U) + 42U].Data + 128U; + pwmPeriod = pwmPeriod >> 7U; + + if(hetRAM == hetRAM1) + { + pwmPolarity = s_het1pwmPolarity[pwm]; + } + else + { + } + if (pwmDuty == 0U) + { + action = (pwmPolarity == 3U) ? 0U : 2U; + } + else if (pwmDuty >= 100U) + { + action = (pwmPolarity == 3U) ? 2U : 0U; + } + else + { + action = pwmPolarity; + } + + hetRAM->Instruction[(pwm << 1U) + 41U].Control = ((hetRAM->Instruction[(pwm << 1U) + 41U].Control) & (~(uint32)(0x00000018U))) | (action << 3U); + hetRAM->Instruction[(pwm << 1U) + 41U].Data = (((pwmPeriod * pwmDuty) / 100U) << 7U) + 128U; +} + + +/** @fn void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal) +* @brief Set period +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* @param[in] pwm Pwm signal: +* - pwm0: Pwm 0 +* - pwm1: Pwm 1 +* - pwm2: Pwm 2 +* - pwm3: Pwm 3 +* - pwm4: Pwm 4 +* - pwm5: Pwm 5 +* - pwm6: Pwm 6 +* - pwm7: Pwm 7 +* @param[in] signal signal + - duty cycle in %. +* - period period in us. +* +* Sets a new pwm signal +*/ +/* SourceId : HET_SourceId_005 */ +/* DesignId : HET_DesignId_005 */ +/* Requirements : HL_SR367 */ +void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal) +{ + uint32 action; + uint32 pwmPolarity = 0U; + float64 pwmPeriod = 0.0F; + + if(hetRAM == hetRAM1) + { + pwmPeriod = (signal.period * 1000.0F) / 800.000F; + pwmPolarity = s_het1pwmPolarity[pwm]; + } + else + { + } + if (signal.duty == 0U) + { + action = (pwmPolarity == 3U) ? 0U : 2U; + } + else if (signal.duty >= 100U) + { + action = (pwmPolarity == 3U) ? 2U : 0U; + } + else + { + action = pwmPolarity; + } + + hetRAM->Instruction[(pwm << 1U) + 41U].Control = ((hetRAM->Instruction[(pwm << 1U) + 41U].Control) & (~(uint32)(0x00000018U))) | (action << 3U); + hetRAM->Instruction[(pwm << 1U) + 41U].Data = ((((uint32)pwmPeriod * signal.duty) / 100U) << 7U ) + 128U; + hetRAM->Instruction[(pwm << 1U) + 42U].Data = ((uint32)pwmPeriod << 7U) - 128U; + +} + + +/** @fn void pwmGetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal) +* @brief Get duty cycle +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* @param[in] pwm Pwm signal: +* - pwm0: Pwm 0 +* - pwm1: Pwm 1 +* - pwm2: Pwm 2 +* - pwm3: Pwm 3 +* - pwm4: Pwm 4 +* - pwm5: Pwm 5 +* - pwm6: Pwm 6 +* - pwm7: Pwm 7 +* @param[in] signal signal +* - duty cycle in %. +* - period period in us. +* +* Gets current signal of the given pwm signal. +*/ +/* SourceId : HET_SourceId_006 */ +/* DesignId : HET_DesignId_006 */ +/* Requirements : HL_SR368 */ +void pwmGetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t* signal) +{ + uint32 pwmDuty = (hetRAM->Instruction[(pwm << 1U) + 41U].Data - 128U) >> 7U; + uint32 pwmPeriod = (hetRAM->Instruction[(pwm << 1U) + 42U].Data + 128U) >> 7U; + + signal->duty = (pwmDuty * 100U) / pwmPeriod; + + if(hetRAM == hetRAM1) + { + signal->period = ((float64)pwmPeriod * 800.000F) / 1000.0F; + } + else + { + signal->period = ((float64)pwmPeriod * 800.000F) / 1000.0F; + } +} + +/** @fn void pwmEnableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) +* @brief Enable pwm notification +* @param[in] hetREG Pointer to HET Module: +* - hetREG1: HET1 Module pointer +* - hetREG2: HET2 Module pointer +* @param[in] pwm Pwm signal: +* - pwm0: Pwm 0 +* - pwm1: Pwm 1 +* - pwm2: Pwm 2 +* - pwm3: Pwm 3 +* - pwm4: Pwm 4 +* - pwm5: Pwm 5 +* - pwm6: Pwm 6 +* - pwm7: Pwm 7 +* @param[in] notification Pwm notification: +* - pwmEND_OF_DUTY: Notification on end of duty +* - pwmEND_OF_PERIOD: Notification on end of end period +* - pwmEND_OF_BOTH: Notification on end of both duty and period +*/ +/* SourceId : HET_SourceId_007 */ +/* DesignId : HET_DesignId_007 */ +/* Requirements : HL_SR369 */ +void pwmEnableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) +{ + hetREG->FLG = notification << (pwm << 1U); + hetREG->INTENAS = notification << (pwm << 1U); +} + + +/** @fn void pwmDisableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) +* @brief Enable pwm notification +* @param[in] hetREG Pointer to HET Module: +* - hetREG1: HET1 Module pointer +* - hetREG2: HET2 Module pointer +* @param[in] pwm Pwm signal: +* - pwm0: Pwm 0 +* - pwm1: Pwm 1 +* - pwm2: Pwm 2 +* - pwm3: Pwm 3 +* - pwm4: Pwm 4 +* - pwm5: Pwm 5 +* - pwm6: Pwm 6 +* - pwm7: Pwm 7 +* @param[in] notification Pwm notification: +* - pwmEND_OF_DUTY: Notification on end of duty +* - pwmEND_OF_PERIOD: Notification on end of end period +* - pwmEND_OF_BOTH: Notification on end of both duty and period +*/ +/* SourceId : HET_SourceId_008 */ +/* DesignId : HET_DesignId_008 */ +/* Requirements : HL_SR370 */ +void pwmDisableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) +{ + hetREG->INTENAC = notification << (pwm << 1U); +} + + +/** @fn void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32 edge) +* @brief Resets edge counter to 0 +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* @param[in] edge Edge signal: +* - edge0: Edge 0 +* - edge1: Edge 1 +* - edge2: Edge 2 +* - edge3: Edge 3 +* - edge4: Edge 4 +* - edge5: Edge 5 +* - edge6: Edge 6 +* - edge7: Edge 7 +* +* Reset edge counter to 0. +*/ +/* SourceId : HET_SourceId_009 */ +/* DesignId : HET_DesignId_009 */ +/* Requirements : HL_SR372 */ +void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32 edge) +{ + hetRAM->Instruction[edge + 17U].Data = 0U; +} + + +/** @fn uint32 edgeGetCounter(hetRAMBASE_t * hetRAM, uint32 edge) +* @brief Get current edge counter value +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* @param[in] edge Edge signal: +* - edge0: Edge 0 +* - edge1: Edge 1 +* - edge2: Edge 2 +* - edge3: Edge 3 +* - edge4: Edge 4 +* - edge5: Edge 5 +* - edge6: Edge 6 +* - edge7: Edge 7 +* +* Gets current edge counter value. +*/ +/* SourceId : HET_SourceId_010 */ +/* DesignId : HET_DesignId_010 */ +/* Requirements : HL_SR373 */ +uint32 edgeGetCounter(hetRAMBASE_t * hetRAM, uint32 edge) +{ + return hetRAM->Instruction[edge + 17U].Data >> 7U; +} + + +/** @fn void edgeEnableNotification(hetBASE_t * hetREG, uint32 edge) +* @brief Enable edge notification +* @param[in] hetREG Pointer to HET Module: +* - hetREG1: HET1 Module pointer +* - hetREG2: HET2 Module pointer +* @param[in] edge Edge signal: +* - edge0: Edge 0 +* - edge1: Edge 1 +* - edge2: Edge 2 +* - edge3: Edge 3 +* - edge4: Edge 4 +* - edge5: Edge 5 +* - edge6: Edge 6 +* - edge7: Edge 7 +*/ +/* SourceId : HET_SourceId_011 */ +/* DesignId : HET_DesignId_011 */ +/* Requirements : HL_SR374 */ +void edgeEnableNotification(hetBASE_t * hetREG, uint32 edge) +{ + hetREG->FLG = (uint32)0x20000U << edge; + hetREG->INTENAS = (uint32)0x20000U << edge; +} + + +/** @fn void edgeDisableNotification(hetBASE_t * hetREG, uint32 edge) +* @brief Enable edge notification +* @param[in] hetREG Pointer to HET Module: +* - hetREG1: HET1 Module pointer +* - hetREG2: HET2 Module pointer +* @param[in] edge Edge signal: +* - edge0: Edge 0 +* - edge1: Edge 1 +* - edge2: Edge 2 +* - edge3: Edge 3 +* - edge4: Edge 4 +* - edge5: Edge 5 +* - edge6: Edge 6 +* - edge7: Edge 7 +*/ +/* SourceId : HET_SourceId_012 */ +/* DesignId : HET_DesignId_012 */ +/* Requirements : HL_SR375 */ +void edgeDisableNotification(hetBASE_t * hetREG, uint32 edge) +{ + hetREG->INTENAC = (uint32)0x20000U << edge; +} + + +/** @fn void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t signal) +* @brief Get capture signal +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* @param[in] cap captured signal: +* - cap0: Captured signal 0 +* - cap1: Captured signal 1 +* - cap2: Captured signal 2 +* - cap3: Captured signal 3 +* - cap4: Captured signal 4 +* - cap5: Captured signal 5 +* - cap6: Captured signal 6 +* - cap7: Captured signal 7 +* @param[in] signal signal +* - duty cycle in %. +* - period period in us. +* +* Gets current signal of the given capture signal. +*/ +/* SourceId : HET_SourceId_013 */ +/* DesignId : HET_DesignId_013 */ +/* Requirements : HL_SR377 */ +void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t *signal) +{ + uint32 pwmDuty = (hetRAM->Instruction[(cap << 1U) + 25U].Data) >> 7U; + uint32 pwmPeriod = (hetRAM->Instruction[(cap << 1U) + 26U].Data) >> 7U; + + signal->duty = (pwmDuty * 100U) / pwmPeriod; + + if( hetRAM == hetRAM1) + { + signal->period = ((float64)pwmPeriod * 800.000F) / 1000.0F; + } + else + { + signal->period = ((float64)pwmPeriod * 800.000F) / 1000.0F; + } +} + + +/** @fn void hetResetTimestamp(hetRAMBASE_t *hetRAM) +* @brief Resets timestamp +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* +* Resets loop count based timestamp. +*/ +/* SourceId : HET_SourceId_014 */ +/* DesignId : HET_DesignId_014 */ +/* Requirements : HL_SR378 */ +void hetResetTimestamp(hetRAMBASE_t * hetRAM) +{ + hetRAM->Instruction[0U].Data = 0U; +} + + +/** @fn uint32 hetGetTimestamp(hetRAMBASE_t *hetRAM) +* @brief Returns timestamp +* +* Returns loop count based timestamp. +*/ +/* SourceId : HET_SourceId_015 */ +/* DesignId : HET_DesignId_015 */ +/* Requirements : HL_SR379 */ +uint32 hetGetTimestamp(hetRAMBASE_t * hetRAM) +{ + return hetRAM->Instruction[57U].Data; +} + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + + +/** @fn void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the HET1 configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : HET_SourceId_016 */ +/* DesignId : HET_DesignId_016 */ +/* Requirements : HL_SR379 */ +void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_GCR = HET1_GCR_CONFIGVALUE; + config_reg->CONFIG_PFR = HET1_PFR_CONFIGVALUE; + config_reg->CONFIG_INTENAS = HET1_INTENAS_CONFIGVALUE; + config_reg->CONFIG_INTENAC = HET1_INTENAC_CONFIGVALUE; + config_reg->CONFIG_PRY = HET1_PRY_CONFIGVALUE; + config_reg->CONFIG_AND = HET1_AND_CONFIGVALUE; + config_reg->CONFIG_HRSH = HET1_HRSH_CONFIGVALUE; + config_reg->CONFIG_XOR = HET1_XOR_CONFIGVALUE; + config_reg->CONFIG_DIR = HET1_DIR_CONFIGVALUE; + config_reg->CONFIG_PDR = HET1_PDR_CONFIGVALUE; + config_reg->CONFIG_PULDIS = HET1_PULDIS_CONFIGVALUE; + config_reg->CONFIG_PSL = HET1_PSL_CONFIGVALUE; + config_reg->CONFIG_PCR = HET1_PCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_GCR = hetREG1->GCR; + config_reg->CONFIG_PFR = hetREG1->PFR; + config_reg->CONFIG_INTENAS = hetREG1->INTENAS; + config_reg->CONFIG_INTENAC = hetREG1->INTENAC; + config_reg->CONFIG_PRY = hetREG1->PRY; + config_reg->CONFIG_AND = hetREG1->AND; + config_reg->CONFIG_HRSH = hetREG1->HRSH; + config_reg->CONFIG_XOR = hetREG1->XOR; + config_reg->CONFIG_DIR = hetREG1->DIR; + config_reg->CONFIG_PDR = hetREG1->PDR; + config_reg->CONFIG_PULDIS = hetREG1->PULDIS; + config_reg->CONFIG_PSL = hetREG1->PSL; + config_reg->CONFIG_PCR = hetREG1->PCR; + } +} + + + diff --git a/src/arch/rm46l8lp/halcogen/mibspi.c b/src/arch/rm46l8lp/halcogen/mibspi.c new file mode 100644 index 0000000..c8adcef --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/mibspi.c @@ -0,0 +1,922 @@ +/** @file mibspi.c +* @brief MIBSPI Driver Implementation File +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "mibspi.h" +#include "sys_vim.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void mibspiInit(void) +* @brief Initializes the MIBSPI Driver +* +* This function initializes the MIBSPI module. +*/ +/* SourceId : MIBSPI_SourceId_001 */ +/* DesignId : MIBSPI_DesignId_001 */ +/* Requirements : HL_SR153 */ +void mibspiInit(void) +{ +uint32 i ; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + + + + /** @b initialize @b MIBSPI3 */ + + /** bring MIBSPI out of reset */ + mibspiREG3->GCR0 = 0U; + mibspiREG3->GCR0 = 1U; + + /** enable MIBSPI3 multibuffered mode and enable buffer RAM */ + mibspiREG3->MIBSPIE = (mibspiREG3->MIBSPIE & 0xFFFFFFFEU) | 1U; + + /** MIBSPI3 master mode and clock configuration */ + mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */ + | 1U); /* MASTER */ + + /** MIBSPI3 enable pin configuration */ + mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */ + + /** - Delays */ + mibspiREG3->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */ + | (uint32)((uint32)0U << 16U) /* T2CDELAY */ + | (uint32)((uint32)0U << 8U) /* T2EDELAY */ + | (uint32)((uint32)0U << 0U); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG3->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)79U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 1 */ + mibspiREG3->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)79U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 2 */ + mibspiREG3->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)79U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 3 */ + mibspiREG3->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)79U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Default Chip Select */ + mibspiREG3->DEF = (uint32)(0xFFU); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ((mibspiREG3->FLG & 0x01000000U) != 0U) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG3->UERRCTRL = (mibspiREG3->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U); + + /** - initialize transfer groups */ + mibspiREG3->TGCTRL[0U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)0U << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[1U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)8U << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + + + mibspiREG3->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U; + + mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U); + + /** - initialize buffer ram */ + { + i = 0U; + +#if (8U > 0U) + { + +#if (8U > 1U) + + while (i < (8U-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG3->LVL = (uint32)((uint32)0U << 9U) /* TXINT */ + | (uint32)((uint32)0U << 8U) /* RXINT */ + | (uint32)((uint32)0U << 6U) /* OVRNINT */ + | (uint32)((uint32)0U << 4U) /* BITERR */ + | (uint32)((uint32)0U << 3U) /* DESYNC */ + | (uint32)((uint32)0U << 2U) /* PARERR */ + | (uint32)((uint32)0U << 1U) /* TIMEOUT */ + | (uint32)((uint32)0U << 0U); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG3->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U) + | (uint32)((uint32)0U << 9U) /* TXINT */ + | (uint32)((uint32)0U << 8U) /* RXINT */ + | (uint32)((uint32)0U << 6U) /* OVRNINT */ + | (uint32)((uint32)0U << 4U) /* BITERR */ + | (uint32)((uint32)0U << 3U) /* DESYNC */ + | (uint32)((uint32)0U << 2U) /* PARERR */ + | (uint32)((uint32)0U << 1U) /* TIMEOUT */ + | (uint32)((uint32)0U << 0U); /* DLENERR */ + + /** @b initialize @b MIBSPI3 @b Port */ + + /** - MIBSPI3 Port output values */ + mibspiREG3->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + /** - MIBSPI3 Port direction */ + mibspiREG3->PC1 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + /** - MIBSPI3 Port open drain enable */ + mibspiREG3->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + + /** - MIBSPI3 Port pullup / pulldown selection */ + mibspiREG3->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO */ + | (uint32)((uint32)1U << 11U); /* SOMI */ + + + /** - MIBSPI3 Port pullup / pulldown enable*/ + mibspiREG3->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + + /* MIBSPI3 set all pins to functional */ + mibspiREG3->PC0 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO */ + | (uint32)((uint32)1U << 11U); /* SOMI */ + + /** - Finally start MIBSPI3 */ + mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFEFFFFFFU) | 0x01000000U; + + + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +} + + +/** @fn void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port) +* @brief Change functional behavior of pins at runtime. +* @param[in] mibspi - mibspi module base address +* @param[in] port - Value to write to PC0 register +* +* Change the value of the PC0 register at runtime, this allows to +* dynamically change the functionality of the MIBSPI pins between functional +* and GIO mode. +*/ +/* SourceId : MIBSPI_SourceId_002 */ +/* DesignId : MIBSPI_DesignId_002 */ +/* Requirements : HL_SR154 */ +void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port) +{ +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + + mibspi->PC0 = port; + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ +} + + +/** @fn void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) +* @brief Set Buffer Data +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* @param[in] data - new data for transfer group +* +* This function updates the data for the specified transfer group, +* the length of the data must match the length of the transfer group. +*/ +/* SourceId : MIBSPI_SourceId_003 */ +/* DesignId : MIBSPI_DesignId_003 */ +/* Requirements : HL_SR155 */ +void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) +{ +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + mibspiRAM_t *ram = (mibspi == mibspiREG1) ? mibspiRAM1 : ((mibspi == mibspiREG3) ? mibspiRAM3 : mibspiRAM5); + uint32 start = (mibspi->TGCTRL[group] >> 8U) & 0xFFU; + uint32 end = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU); + + if (end == 0U) {end = 128U;} + + while (start < end) + { + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + ram->tx[start].data = *data; + /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */ + data++; + start++; + } +/* USER CODE BEGIN (7) */ +/* USER CODE END */ +} + + +/** @fn void mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) +* @brief Retrieves Buffer Data from receive buffer +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* @param[out] data - pointer to data array +* +* @return error flags from data buffer, if there was a receive error on +* one of the buffers this will be reflected in the return value. +* +* This function transfers the data from the specified transfer group receive +* buffers to the data array, the length of the data must match the length +* of the transfer group. +*/ +/* SourceId : MIBSPI_SourceId_004 */ +/* DesignId : MIBSPI_DesignId_004 */ +/* Requirements : HL_SR156 */ +uint32 mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) +{ +/* USER CODE BEGIN (8) */ +/* USER CODE END */ + + mibspiRAM_t *ram = (mibspi == mibspiREG1) ? mibspiRAM1 : ((mibspi == mibspiREG3) ? mibspiRAM3 : mibspiRAM5); + uint32 start = (mibspi->TGCTRL[group] >> 8U) & 0xFFU; + uint32 end = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU); + uint16 mibspiFlags = 0U; + uint32 ret; + if (end == 0U) {end = 128U;} + + while (start < end) + { + mibspiFlags |= ram->rx[start].flags; + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + *data = ram->rx[start].data; + /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */ + data++; + start++; + } + + ret = ((uint32)mibspiFlags >> 8U) & 0x5FU; +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + return ret; +} + + +/** @fn void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group) +* @brief Transmit Transfer Group +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* +* Initiates a transfer for the specified transfer group. +*/ +/* SourceId : MIBSPI_SourceId_005 */ +/* DesignId : MIBSPI_DesignId_005 */ +/* Requirements : HL_SR157 */ +void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group) +{ +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + + mibspi->TGCTRL[group] |= 0x80000000U; + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +} + + +/** @fn boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group) +* @brief Check for Transfer Group Ready +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* +* @return TRUE is transfer complete, otherwise FALSE. +* +* Checks to see if the transfer for the specified transfer group +* has finished. +*/ +/* SourceId : MIBSPI_SourceId_006 */ +/* DesignId : MIBSPI_DesignId_006 */ +/* Requirements : HL_SR158 */ +boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group) +{ + boolean status; + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + + if(((((mibspi->TGINTFLG & 0xFFFF0000U) >> 16U)>> group) & 1U) == 1U) + { + mibspi->TGINTFLG = (mibspi->TGINTFLG & 0x0000FFFFU) | ((uint32)((uint32)1U << group) << 16U); + status = TRUE; + } + else + { + status = FALSE; + } + +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + + return (status); +} + + +/** @fn void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype) +* @brief Enable Loopback mode for self test +* @param[in] mibspi - Mibspi module base address +* @param[in] Loopbacktype - Digital or Analog +* +* This function enables the Loopback mode for self test. +*/ +/* SourceId : MIBSPI_SourceId_007 */ +/* DesignId : MIBSPI_DesignId_009 */ +/* Requirements : HL_SR161 */ +void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype) +{ +/* USER CODE BEGIN (14) */ +/* USER CODE END */ + + /* Clear Loopback incase enabled already */ + mibspi->IOLPKTSTCR = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + mibspi->IOLPKTSTCR = (uint32)0x00000A00U + | (uint32)((uint32)Loopbacktype << 1U); + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ +} + +/** @fn void mibspiDisableLoopback(mibspiBASE_t *mibspi) +* @brief Enable Loopback mode for self test +* @param[in] mibspi - Mibspi module base address +* +* This function disable the Loopback mode. +*/ +/* SourceId : MIBSPI_SourceId_008 */ +/* DesignId : MIBSPI_DesignId_010 */ +/* Requirements : HL_SR162 */ +void mibspiDisableLoopback(mibspiBASE_t *mibspi) +{ +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + + /* Disable Loopback Mode */ + mibspi->IOLPKTSTCR = 0x00000500U; + +/* USER CODE BEGIN (17) */ +/* USER CODE END */ +} + +/** @fn void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT) +* @brief Set the Pmode for the selected Data Format register +* @param[in] mibspi - Mibspi module base address +* @param[in] Pmode - Mibspi Parellel mode +* PMODE_NORMAL +* PMODE_2_DATALINE +* PMODE_4_DATALINE +* PMODE_8_DATALINE +* @param[in] DFMT - Mibspi Data Format register +* DATA_FORMAT0 +* DATA_FORMAT1 +* DATA_FORMAT2 +* DATA_FORMAT3 +* +* This function sets the Pmode for the selected Data Format register. +*/ +/* SourceId : MIBSPI_SourceId_009 */ +/* DesignId : MIBSPI_DesignId_011 */ +/* Requirements : HL_SR524 */ +void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT) +{ + uint32 pmctrl_reg; + /* Set the Pmode for the selected Data Format register */ + pmctrl_reg = (mibspi->PMCTRL & (~(uint32)((uint32)0xFFU << (8U * DFMT)))); + mibspi->PMCTRL = (pmctrl_reg | (uint32)((uint32)Pmode << ((8U * DFMT)))); + +} + +/** @fn void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level) +* @brief Enable Transfer Group interrupt +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* @param[in] level - Interrupt level +* +* This function enables the transfer group finished interrupt. +*/ +/* SourceId : MIBSPI_SourceId_010 */ +/* DesignId : MIBSPI_DesignId_007 */ +/* Requirements : HL_SR159 */ +void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level) +{ +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + + if (level != 0U) + { + mibspi->TGITLVST = (mibspi->TGITLVST & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U); + } + else + { + mibspi->TGITLVCR = (mibspi->TGITLVCR & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U); + } + mibspi->TGITENST = (mibspi->TGITENST & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U); + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ +} + + +/** @fn void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group) +* @brief Disable Transfer Group interrupt +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* +* This function disables the transfer group finished interrupt. +*/ +/* SourceId : MIBSPI_SourceId_011 */ +/* DesignId : MIBSPI_DesignId_008 */ +/* Requirements : HL_SR160 */ +void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group) +{ +/* USER CODE BEGIN (20) */ +/* USER CODE END */ + + mibspi->TGITENCR = (mibspi->TGITENCR & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U); + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ +} + + +/** @fn void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : MIBSPI_SourceId_013 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : HL_SR166 */ +void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_GCR1 = MIBSPI3_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI3_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI3_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI3_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI3_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI3_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI3_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI3_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI3_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI3_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI3_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI3_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI3_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI3_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI3_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[0U] = MIBSPI3_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[1U] = MIBSPI3_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[2U] = MIBSPI3_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[3U] = MIBSPI3_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[4U] = MIBSPI3_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[5U] = MIBSPI3_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[6U] = MIBSPI3_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[7U] = MIBSPI3_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_UERRCTRL = MIBSPI3_UERRCTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_GCR1 = mibspiREG3->GCR1; + config_reg->CONFIG_INT0 = mibspiREG3->INT0; + config_reg->CONFIG_LVL = mibspiREG3->LVL; + config_reg->CONFIG_PCFUN = mibspiREG3->PC0; + config_reg->CONFIG_PCDIR = mibspiREG3->PC1; + config_reg->CONFIG_PCPDR = mibspiREG3->PC6; + config_reg->CONFIG_PCDIS = mibspiREG3->PC7; + config_reg->CONFIG_PCPSL = mibspiREG3->PC8; + config_reg->CONFIG_DELAY = mibspiREG3->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG3->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG3->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG3->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG3->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG3->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG3->LTGPEND; + config_reg->CONFIG_TGCTRL[0U] = mibspiREG3->TGCTRL[0U]; + config_reg->CONFIG_TGCTRL[1U] = mibspiREG3->TGCTRL[1U]; + config_reg->CONFIG_TGCTRL[2U] = mibspiREG3->TGCTRL[2U]; + config_reg->CONFIG_TGCTRL[3U] = mibspiREG3->TGCTRL[3U]; + config_reg->CONFIG_TGCTRL[4U] = mibspiREG3->TGCTRL[4U]; + config_reg->CONFIG_TGCTRL[5U] = mibspiREG3->TGCTRL[5U]; + config_reg->CONFIG_TGCTRL[6U] = mibspiREG3->TGCTRL[6U]; + config_reg->CONFIG_TGCTRL[7U] = mibspiREG3->TGCTRL[7U]; + config_reg->CONFIG_UERRCTRL = mibspiREG3->UERRCTRL; + } +} + + + + + + diff --git a/src/arch/rm46l8lp/halcogen/notification.c b/src/arch/rm46l8lp/halcogen/notification.c new file mode 100644 index 0000000..3371143 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/notification.c @@ -0,0 +1,228 @@ +/** @file notification.c +* @brief User Notification Definition File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file defines empty notification routines to avoid +* linker errors, Driver expects user to define the notification. +* The user needs to either remove this file and use their custom +* notification function or place their code sequence in this file +* between the provided USER CODE BEGIN and USER CODE END. +* +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* Include Files */ + +#include "esm.h" +#include "sys_selftest.h" +#include "adc.h" +#include "gio.h" +#include "mibspi.h" +#include "sci.h" +#include "het.h" +#include "rti.h" +#include "sys_dma.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ +#pragma WEAK(esmGroup1Notification) +void esmGroup1Notification(uint32 channel) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (1) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +#pragma WEAK(esmGroup2Notification) +void esmGroup2Notification(uint32 channel) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ +#pragma WEAK(memoryPort0TestFailNotification) +void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (5) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ +#pragma WEAK(memoryPort1TestFailNotification) +void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (7) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (8) */ +/* USER CODE END */ +#pragma WEAK(rtiNotification) +void rtiNotification(uint32 notification) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (9) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ +#pragma WEAK(adcNotification) +void adcNotification(adcBASE_t *adc, uint32 group) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ +#pragma WEAK(gioNotification) +void gioNotification(gioPORT_t *port, uint32 bit) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (19) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ +#pragma WEAK(mibspiNotification) +void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (25) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ +#pragma WEAK(mibspiGroupNotification) +void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (27) */ +/* USER CODE END */ +} +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + +#pragma WEAK(sciNotification) +void sciNotification(sciBASE_t *sci, uint32 flags) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (29) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + +#pragma WEAK(pwmNotification) +void pwmNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (35) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (36) */ +/* USER CODE END */ +#pragma WEAK(edgeNotification) +void edgeNotification(hetBASE_t * hetREG,uint32 edge) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (37) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (38) */ +/* USER CODE END */ +#pragma WEAK(hetNotification) +void hetNotification(hetBASE_t *het, uint32 offset) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (39) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (40) */ +/* USER CODE END */ + + +/* USER CODE BEGIN (43) */ +/* USER CODE END */ + + +/* USER CODE BEGIN (47) */ +/* USER CODE END */ + + +/* USER CODE BEGIN (50) */ +/* USER CODE END */ + + +/* USER CODE BEGIN (53) */ +/* USER CODE END */ + +#pragma WEAK(dmaGroupANotification) +void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (54) */ +/* USER CODE END */ +} +/* USER CODE BEGIN (55) */ +/* USER CODE END */ + +/* USER CODE BEGIN (56) */ +/* USER CODE END */ + +/* USER CODE BEGIN (58) */ +/* USER CODE END */ + +/* USER CODE BEGIN (60) */ +/* USER CODE END */ diff --git a/src/arch/rm46l8lp/halcogen/pinmux.c b/src/arch/rm46l8lp/halcogen/pinmux.c new file mode 100644 index 0000000..aa37535 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/pinmux.c @@ -0,0 +1,367 @@ +/** @file pinmux.c +* @brief PINMUX Driver Implementation File +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* Include Files */ + +#include "pinmux.h" + +/*LDRA_INSPECTWINDOW 50 */ +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +#define PINMUX_SET(REG, PINNUM, MUX) \ + (pinMuxReg->PINMMR##REG = (pinMuxReg->PINMMR##REG & PINMUX_PIN_##PINNUM##_MASK) | (PINMUX_PIN_##PINNUM##_##MUX)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_GATE_EMIF_CLK_ENABLE(state) \ + (pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | (PINMUX_GATE_EMIF_CLK_##state)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \ + (pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \ + (pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETHERNET_SELECT(interface) \ + (pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM1_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM1_MASK) | (PINMUX_ETPWM1_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM2_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM2_MASK) | (PINMUX_ETPWM2_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM3_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM3_MASK) | (PINMUX_ETPWM3_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM4_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM4_MASK) | (PINMUX_ETPWM4_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM5_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR42 = (pinMuxReg->PINMMR42 & PINMUX_ETPWM5_MASK) | (PINMUX_ETPWM5_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM6_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR42 = (pinMuxReg->PINMMR42 & PINMUX_ETPWM6_MASK) | (PINMUX_ETPWM6_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM7_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR42 = (pinMuxReg->PINMMR42 & PINMUX_ETPWM7_MASK) | (PINMUX_ETPWM7_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TZ1_ENABLE(interface) \ + (pinMuxReg->PINMMR46 = (pinMuxReg->PINMMR46 & PINMUX_TZ1_SHIFT) | (PINMUX_TZ1_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TZ2_ENABLE(interface) \ + (pinMuxReg->PINMMR46 = (pinMuxReg->PINMMR46 & PINMUX_TZ2_SHIFT) | (PINMUX_TZ2_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TZ3_ENABLE(interface) \ + (pinMuxReg->PINMMR47 = (pinMuxReg->PINMMR47 & PINMUX_TZ3_SHIFT) | (PINMUX_TZ3_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_EPWM1SYNCI_ENABLE(interface) \ + (pinMuxReg->PINMMR47 = (pinMuxReg->PINMMR47 & PINMUX_EPWM1SYNCI_SHIFT) | (PINMUX_EPWM1SYNCI_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE(state) \ + (pinMuxReg->PINMMR36 = (pinMuxReg->PINMMR36 & PINMUX_ETPWM_TIME_BASE_SYNC_MASK) | (PINMUX_ETPWM_TIME_BASE_SYNC_##state)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TBCLK_SYNC_ENABLE(state) \ + (pinMuxReg->PINMMR37 = (pinMuxReg->PINMMR37 & PINMUX_ETPWM_TBCLK_SYNC_MASK) | (PINMUX_ETPWM_TBCLK_SYNC_##state)) + + + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* SourceId : PINMUX_SourceId_001 */ +/* DesignId : PINMUX_DesignId_001 */ +/* Requirements : HL_SR325 */ +void muxInit(void){ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + /* Enable Pin Muxing */ + kickerReg->KICKER0 = 0x83E70B13U; + kickerReg->KICKER1 = 0x95A4F1E0U; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + + pinMuxReg->PINMMR0 = PINMUX_PIN_1_GIOB_3 | PINMUX_PIN_2_GIOA_0 | PINMUX_PIN_3_HET1_29 | PINMUX_PIN_4_HET1_27; + + pinMuxReg->PINMMR1 = PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_HET1_11; + + pinMuxReg->PINMMR2 = PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_GIOA_5; + + pinMuxReg->PINMMR3 = PINMUX_PIN_15_HET1_22 | PINMUX_PIN_16_GIOA_6; + + pinMuxReg->PINMMR4 = PINMUX_PIN_22_GIOA_7 | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03; + + pinMuxReg->PINMMR5 = PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_HET1_02 | PINMUX_PIN_31_HET1_05; + + pinMuxReg->PINMMR6 = PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_HET1_09; + + pinMuxReg->PINMMR7 = PINMUX_PIN_37_HET1_25 | PINMUX_PIN_38_HET1_06; + + pinMuxReg->PINMMR8 = PINMUX_PIN_39_HET1_13 | PINMUX_PIN_40_HET1_19 | PINMUX_PIN_41_HET1_15; + + pinMuxReg->PINMMR9 = ((~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_PIN_54_HET1_31 | PINMUX_PIN_55_MIBSPI3NCS_0; + + pinMuxReg->PINMMR10 = PINMUX_PIN_86_AD1EVT; + + pinMuxReg->PINMMR11 = PINMUX_PIN_91_HET1_24; + + pinMuxReg->PINMMR12 = PINMUX_PIN_92_HET1_26 | PINMUX_PIN_96_HET1_23 | PINMUX_PIN_97_MIBSPI5NENA; + + pinMuxReg->PINMMR13 = PINMUX_PIN_98_MIBSPI5SOMI_0 | PINMUX_PIN_99_MIBSPI5SIMO_0 | PINMUX_PIN_100_MIBSPI5CLK | PINMUX_PIN_105_MIBSPI1NCS_0; + + pinMuxReg->PINMMR14 = PINMUX_PIN_106_HET1_08 | PINMUX_PIN_107_HET1_28; + + pinMuxReg->PINMMR15 = 0x01010101U; + + pinMuxReg->PINMMR16 = 0x01010101U; + + pinMuxReg->PINMMR17 = PINMUX_PIN_118_HET1_10 | PINMUX_PIN_124_HET1_12; + + pinMuxReg->PINMMR18 = PINMUX_PIN_125_HET1_14 | PINMUX_PIN_126_GIOB_0; + + pinMuxReg->PINMMR19 = PINMUX_PIN_127_HET1_30; + + pinMuxReg->PINMMR20 = PINMUX_PIN_130_HET1_17; + + pinMuxReg->PINMMR21 = PINMUX_PIN_133_GIOB_1; + + pinMuxReg->PINMMR22 = 0x01010101U; + + pinMuxReg->PINMMR23 = ((~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U); + + pinMuxReg->PINMMR24 = ((~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U); + + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + pinMuxReg->PINMMR25 = ((~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U); + + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + pinMuxReg->PINMMR26 = ((~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U); + + pinMuxReg->PINMMR27 = PINMUX_PIN_32_MIBSPI5NCS_0; + + pinMuxReg->PINMMR29 = 0x01010101U; + + pinMuxReg->PINMMR30 = 0x01010100U; + + pinMuxReg->PINMMR31 = 0x01010101U; + + pinMuxReg->PINMMR32 = 0x00010101U; + + pinMuxReg->PINMMR33 = PINMUX_PIN_36_HET1_04 | PINMUX_PIN_51_ECAP2 | PINMUX_PIN_52_MIBSPI3SIMO | PINMUX_PIN_53_MIBSPI3CLK; + + pinMuxReg->PINMMR34 = PINMUX_PIN_139_HET1_16 | PINMUX_PIN_140_HET1_18 | PINMUX_PIN_141_HET1_20; + + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + + PINMUX_GATE_EMIF_CLK_ENABLE(OFF); + PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF); + PINMUX_ALT_ADC_TRIGGER_SELECT(1); + PINMUX_ETHERNET_SELECT(RMII); + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + PINMUX_SET(0,1,GIOB_3); + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + PINMUX_SET(0,2,GIOA_0); + PINMUX_SET(1,5,GIOA_1); + PINMUX_SET(3,15,HET1_22); + PINMUX_SET(18,125,HET1_14); + PINMUX_SET(18,126,GIOB_0); + PINMUX_SET(21,133,GIOB_1); + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + PINMUX_ETPWM1_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM2_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM3_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM4_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM5_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM6_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM7_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE(OFF); + PINMUX_ETPWM_TZ1_ENABLE(ASYNC); + PINMUX_ETPWM_TZ2_ENABLE(ASYNC); + PINMUX_ETPWM_TZ3_ENABLE(ASYNC); + PINMUX_ETPWM_EPWM1SYNCI_ENABLE(ASYNC); + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + /* Disable Pin Muxing */ + kickerReg->KICKER0 = 0x00000000U; + kickerReg->KICKER1 = 0x00000000U; + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ +} + +/** @fn void pinmuxGetConfigValue(pinmux_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : PINMUX_SourceId_002 */ +/* DesignId : PINMUX_DesignId_002 */ +/* Requirements : HL_SR328 */ +void pinmuxGetConfigValue(pinmux_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + {/* Do not pass Initial Value as parameter */ + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_PINMMR0 = pinMuxReg->PINMMR0; + config_reg->CONFIG_PINMMR1 = pinMuxReg->PINMMR1; + config_reg->CONFIG_PINMMR2 = pinMuxReg->PINMMR2; + config_reg->CONFIG_PINMMR3 = pinMuxReg->PINMMR3; + config_reg->CONFIG_PINMMR4 = pinMuxReg->PINMMR4; + config_reg->CONFIG_PINMMR5 = pinMuxReg->PINMMR5; + config_reg->CONFIG_PINMMR6 = pinMuxReg->PINMMR6; + config_reg->CONFIG_PINMMR7 = pinMuxReg->PINMMR7; + config_reg->CONFIG_PINMMR8 = pinMuxReg->PINMMR8; + config_reg->CONFIG_PINMMR9 = pinMuxReg->PINMMR9; + config_reg->CONFIG_PINMMR10 = pinMuxReg->PINMMR10; + config_reg->CONFIG_PINMMR11 = pinMuxReg->PINMMR11; + config_reg->CONFIG_PINMMR12 = pinMuxReg->PINMMR12; + config_reg->CONFIG_PINMMR13 = pinMuxReg->PINMMR13; + config_reg->CONFIG_PINMMR14 = pinMuxReg->PINMMR14; + config_reg->CONFIG_PINMMR15 = pinMuxReg->PINMMR15; + config_reg->CONFIG_PINMMR16 = pinMuxReg->PINMMR16; + config_reg->CONFIG_PINMMR17 = pinMuxReg->PINMMR17; + config_reg->CONFIG_PINMMR18 = pinMuxReg->PINMMR18; + config_reg->CONFIG_PINMMR19 = pinMuxReg->PINMMR19; + config_reg->CONFIG_PINMMR20 = pinMuxReg->PINMMR20; + config_reg->CONFIG_PINMMR21 = pinMuxReg->PINMMR21; + config_reg->CONFIG_PINMMR22 = pinMuxReg->PINMMR22; + config_reg->CONFIG_PINMMR23 = pinMuxReg->PINMMR23; + config_reg->CONFIG_PINMMR24 = pinMuxReg->PINMMR24; + config_reg->CONFIG_PINMMR25 = pinMuxReg->PINMMR25; + config_reg->CONFIG_PINMMR26 = pinMuxReg->PINMMR26; + config_reg->CONFIG_PINMMR27 = pinMuxReg->PINMMR27; + config_reg->CONFIG_PINMMR28 = pinMuxReg->PINMMR28; + config_reg->CONFIG_PINMMR29 = pinMuxReg->PINMMR29; + config_reg->CONFIG_PINMMR30 = pinMuxReg->PINMMR30; + config_reg->CONFIG_PINMMR32 = pinMuxReg->PINMMR32; + config_reg->CONFIG_PINMMR33 = pinMuxReg->PINMMR33; + config_reg->CONFIG_PINMMR34 = pinMuxReg->PINMMR34; + config_reg->CONFIG_PINMMR35 = pinMuxReg->PINMMR35; + config_reg->CONFIG_PINMMR36 = pinMuxReg->PINMMR36; + config_reg->CONFIG_PINMMR37 = pinMuxReg->PINMMR37; + config_reg->CONFIG_PINMMR38 = pinMuxReg->PINMMR38; + config_reg->CONFIG_PINMMR39 = pinMuxReg->PINMMR39; + config_reg->CONFIG_PINMMR40 = pinMuxReg->PINMMR40; + config_reg->CONFIG_PINMMR41 = pinMuxReg->PINMMR41; + config_reg->CONFIG_PINMMR42 = pinMuxReg->PINMMR42; + config_reg->CONFIG_PINMMR43 = pinMuxReg->PINMMR43; + config_reg->CONFIG_PINMMR44 = pinMuxReg->PINMMR44; + config_reg->CONFIG_PINMMR45 = pinMuxReg->PINMMR45; + config_reg->CONFIG_PINMMR46 = pinMuxReg->PINMMR46; + config_reg->CONFIG_PINMMR47 = pinMuxReg->PINMMR47; + } +} + +/* USER CODE BEGIN (8) */ +/* USER CODE END */ diff --git a/src/arch/rm46l8lp/halcogen/rti.c b/src/arch/rm46l8lp/halcogen/rti.c new file mode 100644 index 0000000..a7298cf --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/rti.c @@ -0,0 +1,959 @@ +/** @file rti.c +* @brief RTI Driver Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - API Functions +* - Interrupt Handlers +* . +* which are relevant for the RTI driver. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "rti.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + +/** @fn void rtiInit(void) +* @brief Initializes RTI Driver +* +* This function initializes the RTI driver. +* +*/ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* SourceId : RTI_SourceId_001 */ +/* DesignId : RTI_DesignId_001 */ +/* Requirements : HL_SR76 */ +void rtiInit(void) +{ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + /** @b Initialize @b RTI1: */ + + /** - Setup NTU source, debug options and disable both counter blocks */ + rtiREG1->GCTRL = (uint32)((uint32)0x0U << 16U) | 0x00000000U; + + /** - Setup timebase for free running counter 0 */ + rtiREG1->TBCTRL = 0x00000000U; + + /** - Enable/Disable capture event sources for both counter blocks */ + rtiREG1->CAPCTRL = 0U | 0U; + + /** - Setup input source compare 0-3 */ + rtiREG1->COMPCTRL = 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U; + + /** - Reset up counter 0 */ + rtiREG1->CNT[0U].UCx = 0x00000000U; + + /** - Reset free running counter 0 */ + rtiREG1->CNT[0U].FRCx = 0x00000000U; + + /** - Setup up counter 0 compare value + * - 0x00000000: Divide by 2^32 + * - 0x00000001-0xFFFFFFFF: Divide by (CPUC0 + 1) + */ + rtiREG1->CNT[0U].CPUCx = 7U; + + /** - Reset up counter 1 */ + rtiREG1->CNT[1U].UCx = 0x00000000U; + + /** - Reset free running counter 1 */ + rtiREG1->CNT[1U].FRCx = 0x00000000U; + + /** - Setup up counter 1 compare value + * - 0x00000000: Divide by 2^32 + * - 0x00000001-0xFFFFFFFF: Divide by (CPUC1 + 1) + */ + rtiREG1->CNT[1U].CPUCx = 7U; + + /** - Setup compare 0 value. This value is compared with selected free running counter. */ + rtiREG1->CMP[0U].COMPx = 50000U; + + /** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */ + rtiREG1->CMP[0U].UDCPx = 50000U; + + /** - Setup compare 1 value. This value is compared with selected free running counter. */ + rtiREG1->CMP[1U].COMPx = 50000000U; + + /** - Setup update compare 1 value. This value is added to the compare 1 value on each compare match. */ + rtiREG1->CMP[1U].UDCPx = 50000000U; + + /** - Setup compare 2 value. This value is compared with selected free running counter. */ + rtiREG1->CMP[2U].COMPx = 5000000U; + + /** - Setup update compare 2 value. This value is added to the compare 2 value on each compare match. */ + rtiREG1->CMP[2U].UDCPx = 5000000U; + + /** - Setup compare 3 value. This value is compared with selected free running counter. */ + rtiREG1->CMP[3U].COMPx = 50000000U; + + /** - Setup update compare 3 value. This value is added to the compare 3 value on each compare match. */ + rtiREG1->CMP[3U].UDCPx = 50000000U; + + /** - Clear all pending interrupts */ + rtiREG1->INTFLAG = 0x0007000FU; + + /** - Disable all interrupts */ + rtiREG1->CLEARINTENA = 0x00070F0FU; + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + * This function does not start the counters. + */ + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + +/** @fn void rtiStartCounter(uint32 counter) +* @brief Starts RTI Counter block +* @param[in] counter Select counter block to be started: +* - rtiCOUNTER_BLOCK0: RTI counter block 0 will be started +* - rtiCOUNTER_BLOCK1: RTI counter block 1 will be started +* +* This function starts selected counter block of the selected RTI module. +*/ + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ +/* SourceId : RTI_SourceId_002 */ +/* DesignId : RTI_DesignId_002 */ +/* Requirements : HL_SR77 */ +void rtiStartCounter(uint32 counter) +{ +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + + rtiREG1->GCTRL |= ((uint32)1U << (counter & 3U)); + + /** @note The function rtiInit has to be called before this function can be used.\n + * This function has to be executed in privileged mode. + */ + +/* USER CODE BEGIN (8) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + +/** @fn void rtiStopCounter(uint32 counter) +* @brief Stops RTI Counter block +* @param[in] counter Select counter to be stopped: +* - rtiCOUNTER_BLOCK0: RTI counter block 0 will be stopped +* - rtiCOUNTER_BLOCK1: RTI counter block 1 will be stopped +* +* This function stops selected counter block of the selected RTI module. +*/ + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ +/* SourceId : RTI_SourceId_003 */ +/* DesignId : RTI_DesignId_003 */ +/* Requirements : HL_SR78 */ +void rtiStopCounter(uint32 counter) +{ +/* USER CODE BEGIN (11) */ +/* USER CODE END */ + + rtiREG1->GCTRL &= ~(uint32)((uint32)1U << (counter & 3U)); + + /** @note The function rtiInit has to be called before this function can be used.\n + * This function has to be executed in privileged mode. + */ + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + + +/** @fn uint32 rtiResetCounter(uint32 counter) +* @brief Reset RTI Counter block +* @param[in] counter Select counter block to be reset: +* - rtiCOUNTER_BLOCK0: RTI counter block 0 will be reset +* - rtiCOUNTER_BLOCK1: RTI counter block 1 will be reset +* @return The function will return: +* - 0: When the counter reset wasn't successful +* - 1: When the counter reset was successful +* +* This function resets selected counter block of the selected RTI module. +*/ + +/* USER CODE BEGIN (14) */ +/* USER CODE END */ +/* SourceId : RTI_SourceId_004 */ +/* DesignId : RTI_DesignId_004 */ +/* Requirements : HL_SR79 */ +uint32 rtiResetCounter(uint32 counter) +{ + uint32 success = 0U; + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + if ((rtiREG1->GCTRL & (uint32)((uint32)1U << (counter & 3U))) == 0U) + { + rtiREG1->CNT[counter].UCx = 0x00000000U; + rtiREG1->CNT[counter].FRCx = 0x00000000U; + + success = 1U; + } + + /** @note The function rtiInit has to be called before this function can be used.\n + * This function has to be executed in privileged mode.\n + * The selected counter block has to be stopped before it can reset. + */ + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + + return success; +} + +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + +/** @fn void rtiSetPeriod(uint32 compare, uint32 period) +* @brief Set new period of RTI compare +* @param[in] compare Select compare to change period: +* - rtiCOMPARE0: RTI compare 0 will change the period +* - rtiCOMPARE1: RTI compare 1 will change the period +* - rtiCOMPARE2: RTI compare 2 will change the period +* - rtiCOMPARE3: RTI compare 3 will change the period +* @param[in] period new period in [ticks - 1]: +* - 0x00000000: Divide by 1 +* - n: Divide by n + 1 +* +* This function will change the period of the selected compare. +*/ + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ +/* SourceId : RTI_SourceId_005 */ +/* DesignId : RTI_DesignId_005 */ +/* Requirements : HL_SR80 */ +void rtiSetPeriod(uint32 compare, uint32 period) +{ +/* USER CODE BEGIN (19) */ +/* USER CODE END */ + + rtiREG1->CMP[compare].UDCPx = period; + + /** @note The function rtiInit has to be called before this function can be used.\n + * This function has to be executed in privileged mode.\n + * When the corresponding counter block is not stopped,\n + * the period will change on the next compare match of the old period. + */ + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + + +/** @fn uint32 rtiGetPeriod(uint32 compare) +* @brief Get current period of RTI compare +* @param[in] compare Select compare to return the current period: +* - rtiCOMPARE0: RTI compare 0 will return the current period +* - rtiCOMPARE1: RTI compare 1 will return the current period +* - rtiCOMPARE2: RTI compare 2 will return the current period +* - rtiCOMPARE3: RTI compare 3 will return the current period +* @return Current period of selected compare in [ticks - 1]: +* - 0x00000000: Divide by 1 +* - n: Divide by n + 1 +* +* This function will return the period of the selected compare. +*/ + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ +/* SourceId : RTI_SourceId_006 */ +/* DesignId : RTI_DesignId_006 */ +/* Requirements : HL_SR81 */ +uint32 rtiGetPeriod(uint32 compare) +{ + uint32 period; + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ + + period = rtiREG1->CMP[compare].UDCPx; + + /** @note The function rtiInit has to be called before this function can be used. + */ + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + + return period; +} + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + + +/** @fn uint32 rtiGetCurrentTick(uint32 compare) +* @brief Get current tick of RTI compare +* @param[in] compare Select compare to return the current tick: +* - rtiCOMPARE0: RTI compare 0 will return the current tick +* - rtiCOMPARE1: RTI compare 1 will return the current tick +* - rtiCOMPARE2: RTI compare 2 will return the current tick +* - rtiCOMPARE3: RTI compare 3 will return the current tick +* @return Current tick of selected compare +* +* This function will return the current tick of the selected compare. +*/ + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ +/* SourceId : RTI_SourceId_007 */ +/* DesignId : RTI_DesignId_007 */ +/* Requirements : HL_SR82 */ +uint32 rtiGetCurrentTick(uint32 compare) +{ + uint32 tick; + uint32 counter = ((rtiREG1->COMPCTRL & (uint32)((uint32)1U << (compare << 2U))) != 0U ) ? 1U : 0U; + uint32 RTI_CNT_FRCx = rtiREG1->CNT[counter].FRCx; + uint32 RTI_CMP_COMPx = rtiREG1->CMP[compare].COMPx; + uint32 RTI_CMP_UDCPx = rtiREG1->CMP[compare].UDCPx; + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ + + tick = RTI_CNT_FRCx - (RTI_CMP_COMPx - RTI_CMP_UDCPx); + + /** @note The function rtiInit has to be called before this function can be used. + */ + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + + return tick; +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + +/** @fn void dwdInit(uint16 dwdPreload) +* @brief Initialize DWD Expiration Period +* @param[in] dwdPreload DWD Preload value for expiration time. +* - Texp = (dwdPreload +1) / RTICLK +* - n: Divide by n + 1 +* +* This function can be called to set the DWD expiration +* +*/ +/* SourceId : RTI_SourceId_008 */ +/* DesignId : RTI_DesignId_010 */ +/* Requirements : HL_SR85 */ +void dwdInit(uint16 dwdPreload) +{ +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + + /* Clear the violations if already present */ + rtiREG1->WDSTATUS = 0xFFU; + + rtiREG1->DWDPRLD = dwdPreload; + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + +/** @fn void dwwdInit(dwwdReaction_t Reaction, uint16 dwdPreload, dwwdWindowSize_t Window_Size) +* @brief Initialize DWD Expiration Period +* @param[in] Reaction DWWD reaction if the watchdog is serviced outside the time window. +* - Generate_Reset +* - Generate_NMI +* @param[in] dwdPreload DWWD Preload value for the watchdog expiration time. +* - Texp = (dwdPreload +1) / RTICLK +* - n: Divide by n + 1 +* @param[in] Window_Size DWWD time window size +* - Size_100_Percent +* - Size_50_Percent +* - Size_25_Percent +* - Size_12_5_Percent +* - Size_6_25_Percent +* - Size_3_125_Percent +* +* This function can be called to set the DWD expiration +* +*/ +/* SourceId : RTI_SourceId_009 */ +/* DesignId : RTI_DesignId_011 */ +/* Requirements : HL_SR86 */ +void dwwdInit(dwwdReaction_t Reaction, uint16 dwdPreload, dwwdWindowSize_t Window_Size) +{ +/* USER CODE BEGIN (33) */ +/* USER CODE END */ + + /* Clear the violations if already present */ + rtiREG1->WDSTATUS = 0xFFU; + + rtiREG1->WWDSIZECTRL = (uint32) Window_Size; + rtiREG1->DWDPRLD = (uint32) dwdPreload; + rtiREG1->WWDRXNCTRL = (uint32) Reaction; + +/* USER CODE BEGIN (34) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ + +/** @fn uint32 dwwdGetCurrentDownCounter(void) +* @brief Get the current DWWD Down Counter +* @return Current tick of selected compare +* +* This function will get the current DWWD down counter value. +* +*/ +/* SourceId : RTI_SourceId_010 */ +/* DesignId : RTI_DesignId_012 */ +/* Requirements : HL_SR87 */ +uint32 dwwdGetCurrentDownCounter(void) +{ +/* USER CODE BEGIN (36) */ +/* USER CODE END */ + + return (rtiREG1->DWDCNTR); + +/* USER CODE BEGIN (37) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (38) */ +/* USER CODE END */ + +/** @fn void dwdCounterEnable(void) +* @brief Enable DWD +* +* This function will Enable the DWD counter. +* +*/ +/* SourceId : RTI_SourceId_011 */ +/* DesignId : RTI_DesignId_013 */ +/* Requirements : HL_SR88 */ +void dwdCounterEnable(void) +{ +/* USER CODE BEGIN (39) */ +/* USER CODE END */ + + rtiREG1->DWDCTRL = 0xA98559DAU; + +/* USER CODE BEGIN (40) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (41) */ +/* USER CODE END */ + +/* USER CODE BEGIN (42) */ +/* USER CODE END */ +/* USER CODE BEGIN (43) */ +/* USER CODE END */ +/* USER CODE BEGIN (44) */ +/* USER CODE END */ +/** @fn void dwdSetPreload(uint16 dwdPreload) +* @brief Initialize DWD Expiration Period +* @param[in] dwdPreload DWD Preload value for the watchdog expiration time. +* - Texp = (dwdPreload +1) / RTICLK +* - n: Divide by n + 1 +* +* This function can be called to set the Preload value for the watchdog expiration time. +* +*/ +/* SourceId : RTI_SourceId_012 */ +/* DesignId : RTI_DesignId_014 */ +/* Requirements : HL_SR85 */ +void dwdSetPreload(uint16 dwdPreload) +{ +/* USER CODE BEGIN (45) */ +/* USER CODE END */ + rtiREG1->DWDPRLD = dwdPreload; +/* USER CODE BEGIN (46) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (47) */ +/* USER CODE END */ + +/** @fn void dwdReset(void) +* @brief Reset Digital Watchdog +* +* This function can be called to reset Digital Watchdog. +* +*/ +/* SourceId : RTI_SourceId_013 */ +/* DesignId : RTI_DesignId_015 */ +/* Requirements : HL_SR89 */ +void dwdReset(void) +{ +/* USER CODE BEGIN (48) */ +/* USER CODE END */ + rtiREG1->WDKEY = 0x0000E51AU; + rtiREG1->WDKEY = 0x0000A35CU; +/* USER CODE BEGIN (49) */ +/* USER CODE END */ +} + +/** @fn void dwdGenerateSysReset(void) +* @brief Generate System Reset through DWD +* +* This function can be called to generate system reset using DWD. +* +*/ +/* SourceId : RTI_SourceId_014 */ +/* DesignId : RTI_DesignId_016 */ +/* Requirements : HL_SR90 */ +void dwdGenerateSysReset(void) +{ +/* USER CODE BEGIN (50) */ +/* USER CODE END */ + rtiREG1->WDKEY = 0x0000E51AU; + rtiREG1->WDKEY = 0x00002345U; +/* USER CODE BEGIN (51) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (52) */ +/* USER CODE END */ + +/** @fn boolean IsdwdKeySequenceCorrect(void) +* @brief Check if DWD Key sequence correct. +* @return The function will return: +* - TRUE: When the DWD key sequence is written correctly. +* - FALSE: When the DWD key sequence is written incorrectly / not written. +* +* This function will get status of the DWD Key sequence. +* +*/ +/* SourceId : RTI_SourceId_015 */ +/* DesignId : RTI_DesignId_017 */ +/* Requirements : HL_SR91 */ +boolean IsdwdKeySequenceCorrect(void) +{ + boolean Status; + +/* USER CODE BEGIN (53) */ +/* USER CODE END */ + + if((rtiREG1->WDSTATUS & 0x4U) == 0x4U) + { + Status = FALSE; + } + else + { + Status = TRUE; + } + +/* USER CODE BEGIN (54) */ +/* USER CODE END */ + + return Status; +} + +/* USER CODE BEGIN (55) */ +/* USER CODE END */ + +/** @fn dwdResetStatus_t dwdGetStatus(void) +* @brief Check if Reset is generated due to DWD. +* @return The function will return: +* - Reset_Generated: When the Reset is generated due to DWD. +* - No_Reset_Generated: No Reset is generated due to DWD. +* +* This function will get dwd Reset status. +* +*/ +/* SourceId : RTI_SourceId_016 */ +/* DesignId : RTI_DesignId_018 */ +/* Requirements : HL_SR92 */ +dwdResetStatus_t dwdGetStatus(void) +{ +/* USER CODE BEGIN (56) */ +/* USER CODE END */ + dwdResetStatus_t Reset_Status; + if((rtiREG1->WDSTATUS & 0x2U) == 0x2U) + { + Reset_Status = Reset_Generated; + } + else + { + Reset_Status = No_Reset_Generated; + } + +/* USER CODE BEGIN (57) */ +/* USER CODE END */ + return Reset_Status; +} + +/* USER CODE BEGIN (58) */ +/* USER CODE END */ + +/** @fn void dwdClearFlag(void) +* @brief Clear the DWD violation flag. +* +* This function will clear dwd status register. +* +*/ +/* SourceId : RTI_SourceId_017 */ +/* DesignId : RTI_DesignId_020 */ +/* Requirements : HL_SR94 */ +void dwdClearFlag(void) +{ +/* USER CODE BEGIN (59) */ +/* USER CODE END */ + + rtiREG1->WDSTATUS = 0xFFU; + +/* USER CODE BEGIN (60) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (61) */ +/* USER CODE END */ + +/** @fn dwdViolation_t dwdGetViolationStatus(void) +* @brief Check the status of the DWD or DWWD violation happened. +* @return The function will return one of following violations occured: +* - NoTime_Violation +* - Key_Seq_Violation +* - Time_Window_Violation +* - EndTime_Window_Violation +* - StartTime_Window_Violation +* +* This function will get status of the DWD or DWWD violation status. +* +*/ +/* SourceId : RTI_SourceId_018 */ +/* DesignId : RTI_DesignId_019 */ +/* Requirements : HL_SR93 */ +dwdViolation_t dwdGetViolationStatus(void) +{ +/* USER CODE BEGIN (62) */ +/* USER CODE END */ + dwdViolation_t Violation_Status; + + if ((rtiREG1->WDSTATUS & 0x04U) == 0x04U) + { + Violation_Status = Key_Seq_Violation; + } + else if((rtiREG1->WDSTATUS & 0x8U) == 0x8U) + { + Violation_Status = StartTime_Window_Violation; + } + else if ((rtiREG1->WDSTATUS & 0x10U) == 0x10U) + { + Violation_Status = EndTime_Window_Violation; + } + else if ((rtiREG1->WDSTATUS & 0x20U) == 0x20U) + { + Violation_Status = Time_Window_Violation; + } + else + { + Violation_Status = NoTime_Violation; + } + +/* USER CODE BEGIN (63) */ +/* USER CODE END */ + + return Violation_Status; +} + +/* USER CODE BEGIN (64) */ +/* USER CODE END */ + +/** @fn void rtiEnableNotification(uint32 notification) +* @brief Enable notification of RTI module +* @param[in] notification Select notification of RTI module: +* - rtiNOTIFICATION_COMPARE0: RTI compare 0 notification +* - rtiNOTIFICATION_COMPARE1: RTI compare 1 notification +* - rtiNOTIFICATION_COMPARE2: RTI compare 2 notification +* - rtiNOTIFICATION_COMPARE3: RTI compare 3 notification +* - rtiNOTIFICATION_TIMEBASE: RTI Timebase notification +* - rtiNOTIFICATION_COUNTER0: RTI counter 0 overflow notification +* - rtiNOTIFICATION_COUNTER1: RTI counter 1 overflow notification +* +* This function will enable the selected notification of a RTI module. +* It is possible to enable multiple notifications masked. +*/ + +/* USER CODE BEGIN (65) */ +/* USER CODE END */ +/* SourceId : RTI_SourceId_019 */ +/* DesignId : RTI_DesignId_008 */ +/* Requirements : HL_SR83 */ +void rtiEnableNotification(uint32 notification) +{ +/* USER CODE BEGIN (66) */ +/* USER CODE END */ + + rtiREG1->INTFLAG = notification; + rtiREG1->SETINTENA = notification; + + /** @note The function rtiInit has to be called before this function can be used.\n + * This function has to be executed in privileged mode. + */ + +/* USER CODE BEGIN (67) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (68) */ +/* USER CODE END */ + +/** @fn void rtiDisableNotification(uint32 notification) +* @brief Disable notification of RTI module +* @param[in] notification Select notification of RTI module: +* - rtiNOTIFICATION_COMPARE0: RTI compare 0 notification +* - rtiNOTIFICATION_COMPARE1: RTI compare 1 notification +* - rtiNOTIFICATION_COMPARE2: RTI compare 2 notification +* - rtiNOTIFICATION_COMPARE3: RTI compare 3 notification +* - rtiNOTIFICATION_TIMEBASE: RTI Timebase notification +* - rtiNOTIFICATION_COUNTER0: RTI counter 0 overflow notification +* - rtiNOTIFICATION_COUNTER1: RTI counter 1 overflow notification +* +* This function will disable the selected notification of a RTI module. +* It is possible to disable multiple notifications masked. +*/ + +/* USER CODE BEGIN (69) */ +/* USER CODE END */ +/* SourceId : RTI_SourceId_020 */ +/* DesignId : RTI_DesignId_009 */ +/* Requirements : HL_SR84 */ +void rtiDisableNotification(uint32 notification) +{ +/* USER CODE BEGIN (70) */ +/* USER CODE END */ + + rtiREG1->CLEARINTENA = notification; + + /** @note The function rtiInit has to be called before this function can be used.\n + * This function has to be executed in privileged mode. + */ + +/* USER CODE BEGIN (71) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (72) */ +/* USER CODE END */ + +/** @fn void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') of the configuration +* registers to the struct pointed by config_reg +* +*/ +/* SourceId : RTI_SourceId_021 */ +/* DesignId : RTI_DesignId_021 */ +/* Requirements : HL_SR97 */ +void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_GCTRL = RTI_GCTRL_CONFIGVALUE; + config_reg->CONFIG_TBCTRL = RTI_TBCTRL_CONFIGVALUE; + config_reg->CONFIG_CAPCTRL = RTI_CAPCTRL_CONFIGVALUE; + config_reg->CONFIG_COMPCTRL = RTI_COMPCTRL_CONFIGVALUE; + config_reg->CONFIG_UDCP0 = RTI_UDCP0_CONFIGVALUE; + config_reg->CONFIG_UDCP1 = RTI_UDCP1_CONFIGVALUE; + config_reg->CONFIG_UDCP2 = RTI_UDCP2_CONFIGVALUE; + config_reg->CONFIG_UDCP3 = RTI_UDCP3_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_GCTRL = rtiREG1->GCTRL; + config_reg->CONFIG_TBCTRL = rtiREG1->TBCTRL; + config_reg->CONFIG_CAPCTRL = rtiREG1->CAPCTRL; + config_reg->CONFIG_COMPCTRL = rtiREG1->COMPCTRL; + config_reg->CONFIG_UDCP0 = rtiREG1->CMP[0U].UDCPx; + config_reg->CONFIG_UDCP1 = rtiREG1->CMP[1U].UDCPx; + config_reg->CONFIG_UDCP2 = rtiREG1->CMP[2U].UDCPx; + config_reg->CONFIG_UDCP3 = rtiREG1->CMP[3U].UDCPx; + } +} + +/* USER CODE BEGIN (73) */ +/* USER CODE END */ + +/** @fn void rtiCompare0Interrupt(void) +* @brief RTI1 Compare 0 Interrupt Handler +* +* RTI1 Compare 0 interrupt handler +* +*/ +#pragma CODE_STATE(rtiCompare0Interrupt, 32) +#pragma INTERRUPT(rtiCompare0Interrupt, IRQ) + +/* SourceId : RTI_SourceId_022 */ +/* DesignId : RTI_DesignId_022 */ +/* Requirements : HL_SR95 */ +void rtiCompare0Interrupt(void) +{ +/* USER CODE BEGIN (74) */ +/* USER CODE END */ + + rtiREG1->INTFLAG = 1U; + rtiNotification(rtiNOTIFICATION_COMPARE0); + +/* USER CODE BEGIN (75) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (76) */ +/* USER CODE END */ + +/** @fn void rtiCompare1Interrupt(void) +* @brief RTI1 Compare 1 Interrupt Handler +* +* RTI1 Compare 1 interrupt handler +* +*/ +#pragma CODE_STATE(rtiCompare1Interrupt, 32) +#pragma INTERRUPT(rtiCompare1Interrupt, IRQ) + +/* SourceId : RTI_SourceId_023 */ +/* DesignId : RTI_DesignId_022 */ +/* Requirements : HL_SR95 */ +void rtiCompare1Interrupt(void) +{ +/* USER CODE BEGIN (77) */ +/* USER CODE END */ + + rtiREG1->INTFLAG = 2U; + rtiNotification(rtiNOTIFICATION_COMPARE1); + +/* USER CODE BEGIN (78) */ +/* USER CODE END */ +} + + +/* USER CODE BEGIN (79) */ +/* USER CODE END */ + +/** @fn void rtiCompare2Interrupt(void) +* @brief RTI1 Compare 2 Interrupt Handler +* +* RTI1 Compare 2 interrupt handler +* +*/ +#pragma CODE_STATE(rtiCompare2Interrupt, 32) +#pragma INTERRUPT(rtiCompare2Interrupt, IRQ) + +/* SourceId : RTI_SourceId_024 */ +/* DesignId : RTI_DesignId_022 */ +/* Requirements : HL_SR95 */ +void rtiCompare2Interrupt(void) +{ +/* USER CODE BEGIN (80) */ +/* USER CODE END */ + + rtiREG1->INTFLAG = 4U; + rtiNotification(rtiNOTIFICATION_COMPARE2); + +/* USER CODE BEGIN (81) */ +/* USER CODE END */ +} + + +/* USER CODE BEGIN (82) */ +/* USER CODE END */ + +/** @fn void rtiCompare3Interrupt(void) +* @brief RTI1 Compare 3 Interrupt Handler +* +* RTI1 Compare 3 interrupt handler +* +*/ +#pragma CODE_STATE(rtiCompare3Interrupt, 32) +#pragma INTERRUPT(rtiCompare3Interrupt, IRQ) + +/* SourceId : RTI_SourceId_025 */ +/* DesignId : RTI_DesignId_022 */ +/* Requirements : HL_SR95 */ +void rtiCompare3Interrupt(void) +{ +/* USER CODE BEGIN (83) */ +/* USER CODE END */ + + rtiREG1->INTFLAG = 8U; + rtiNotification(rtiNOTIFICATION_COMPARE3); + +/* USER CODE BEGIN (84) */ +/* USER CODE END */ +} + + + + diff --git a/src/arch/rm46l8lp/halcogen/sci.c b/src/arch/rm46l8lp/halcogen/sci.c new file mode 100644 index 0000000..10d3590 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sci.c @@ -0,0 +1,673 @@ +/** @file sci.c +* @brief SCI Driver Implementation File +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sci.h" +#include "sys_vim.h" +#include "math.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ +/** @struct g_sciTransfer +* @brief Interrupt mode globals +* +*/ +static volatile struct g_sciTransfer +{ + uint32 mode; /* Used to check for TX interrupt Enable */ + uint32 tx_length; /* Transmit data length in number of Bytes */ + uint32 rx_length; /* Receive data length in number of Bytes */ + uint8 * tx_data; /* Transmit data pointer */ + uint8 * rx_data; /* Receive data pointer */ +} g_sciTransfer_t[2U]; + + +/** @fn void sciInit(void) +* @brief Initializes the SCI Driver +* +* This function initializes the SCI module. +*/ +/* SourceId : SCI_SourceId_001 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : HL_SR230 */ +void sciInit(void) +{ +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + + + /** @b initialize @b SCILIN */ + + /** - bring SCI out of reset */ + scilinREG->GCR0 = 0U; + scilinREG->GCR0 = 1U; + + /** - Disable all interrupts */ + scilinREG->CLEARINT = 0xFFFFFFFFU; + scilinREG->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + scilinREG->GCR1 = (uint32)((uint32)1U << 25U) /* enable transmit */ + | (uint32)((uint32)1U << 24U) /* enable receive */ + | (uint32)((uint32)1U << 5U) /* internal clock (device has no clock pin) */ + | (uint32)((uint32)(2U-1U) << 4U) /* number of stop bits */ + | (uint32)((uint32)0U << 3U) /* even parity, otherwise odd */ + | (uint32)((uint32)0U << 2U) /* enable parity */ + | (uint32)((uint32)1U << 1U); /* asynchronous timing mode */ + + /** - set baudrate */ + scilinREG->BRS = 259U; /* baudrate */ + + /** - transmission length */ + scilinREG->FORMAT = 8U - 1U; /* length */ + + /** - set SCI pins functional mode */ + scilinREG->PIO0 = (uint32)((uint32)1U << 2U) /* tx pin */ + | (uint32)((uint32)1U << 1U); /* rx pin */ + + + /** - set SCI pins default output value */ + scilinREG->PIO3 = (uint32)((uint32)0U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + + /** - set SCI pins output direction */ + scilinREG->PIO1 = (uint32)((uint32)0U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + + /** - set SCI pins open drain enable */ + scilinREG->PIO6 = (uint32)((uint32)0U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + + /** - set SCI pins pullup/pulldown enable */ + scilinREG->PIO7 = (uint32)((uint32)0U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + + /** - set SCI pins pullup/pulldown select */ + scilinREG->PIO8 = (uint32)((uint32)1U << 2U) /* tx pin */ + | (uint32)((uint32)1U << 1U); /* rx pin */ + + + /** - set interrupt level */ + scilinREG->SETINTLVL = (uint32)((uint32)0U << 26U) /* Framing error */ + | (uint32)((uint32)0U << 25U) /* Overrun error */ + | (uint32)((uint32)0U << 24U) /* Parity error */ + | (uint32)((uint32)0U << 9U) /* Receive */ + | (uint32)((uint32)0U << 8U) /* Transmit */ + | (uint32)((uint32)0U << 1U) /* Wakeup */ + | (uint32)((uint32)0U); /* Break detect */ + + /** - set interrupt enable */ + scilinREG->SETINT = (uint32)((uint32)0U << 26U) /* Framing error */ + | (uint32)((uint32)0U << 25U) /* Overrun error */ + | (uint32)((uint32)0U << 24U) /* Parity error */ + | (uint32)((uint32)0U << 9U) /* Receive */ + | (uint32)((uint32)0U << 1U) /* Wakeup */ + | (uint32)((uint32)0U); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[1U].mode = (uint32)0U << 8U; + g_sciTransfer_t[1U].tx_length = 0U; + g_sciTransfer_t[1U].rx_length = 0U; + + /** - Finaly start SCILIN */ + scilinREG->GCR1 |= 0x80U; + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +} + + +/** @fn void sciSetFunctional(sciBASE_t *sci, uint32 port) +* @brief Change functional behavior of pins at runtime. +* @param[in] sci - sci module base address +* @param[in] port - Value to write to PIO0 register +* +* Change the value of the PCPIO0 register at runtime, this allows to +* dynamically change the functionality of the SCI pins between functional +* and GIO mode. +*/ +/* SourceId : SCI_SourceId_002 */ +/* DesignId : SCI_DesignId_002 */ +/* Requirements : HL_SR231 */ +void sciSetFunctional(sciBASE_t *sci, uint32 port) +{ +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + + sci->PIO0 = port; + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ +} + + +/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32 baud) +* @brief Change baudrate at runtime. +* @param[in] sci - sci module base address +* @param[in] baud - baudrate in Hz +* +* Change the SCI baudrate at runtime. +*/ +/* SourceId : SCI_SourceId_003 */ +/* DesignId : SCI_DesignId_003 */ +/* Requirements : HL_SR232 */ +void sciSetBaudrate(sciBASE_t *sci, uint32 baud) +{ + float64 vclk = 80.000 * 1000000.0; + uint32 f = ((sci->GCR1 & 2U) == 2U) ? 16U : 1U; + uint32 temp; + float64 temp2; +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + /*SAFETYMCUSW 96 S MR:6.1 <APPROVED> "Calculations including int and float cannot be avoided" */ + temp = (f*(baud)); + temp2 = ((vclk)/((float64)temp))-1U; + temp2 = floor(temp2 + 0.5); /* Rounding-off to the closest integer */ + sci->BRS = (uint32)((uint32)temp2 & 0x00FFFFFFU); + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ +} + + +/** @fn uint32 sciIsTxReady(sciBASE_t *sci) +* @brief Check if Tx buffer empty +* @param[in] sci - sci module base address +* +* @return The TX ready flag +* +* Checks to see if the Tx buffer ready flag is set, returns +* 0 is flags not set otherwise will return the Tx flag itself. +*/ +/* SourceId : SCI_SourceId_004 */ +/* DesignId : SCI_DesignId_004 */ +/* Requirements : HL_SR233 */ +uint32 sciIsTxReady(sciBASE_t *sci) +{ +/* USER CODE BEGIN (8) */ +/* USER CODE END */ + + return sci->FLR & (uint32)SCI_TX_INT; +} + + +/** @fn void sciSendByte(sciBASE_t *sci, uint8 byte) +* @brief Send Byte +* @param[in] sci - sci module base address +* @param[in] byte - byte to transfer +* +* Sends a single byte in polling mode, will wait in the +* routine until the transmit buffer is empty before sending +* the byte. Use sciIsTxReady to check for Tx buffer empty +* before calling sciSendByte to avoid waiting. +*/ +/* SourceId : SCI_SourceId_005 */ +/* DesignId : SCI_DesignId_005 */ +/* Requirements : HL_SR234 */ +void sciSendByte(sciBASE_t *sci, uint8 byte) +{ +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((sci->FLR & (uint32)SCI_TX_INT) == 0U) + { + } /* Wait */ + sci->TD = byte; + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ +} + + +/** @fn void sciSend(sciBASE_t *sci, uint32 length, uint8 * data) +* @brief Send Data +* @param[in] sci - sci module base address +* @param[in] length - number of data words to transfer +* @param[in] data - pointer to data to send +* +* Send a block of data pointed to by 'data' and 'length' bytes +* long. If interrupts have been enabled the data is sent using +* interrupt mode, otherwise polling mode is used. In interrupt +* mode transmission of the first byte is started and the routine +* returns immediately, sciSend must not be called again until the +* transfer is complete, when the sciNotification callback will +* be called. In polling mode, sciSend will not return until +* the transfer is complete. +* +* @note if data word is less than 8 bits, then the data must be left +* aligned in the data byte. +*/ +/* SourceId : SCI_SourceId_006 */ +/* DesignId : SCI_DesignId_006 */ +/* Requirements : HL_SR235 */ +void sciSend(sciBASE_t *sci, uint32 length, uint8 * data) +{ + uint32 index = (sci == sciREG) ? 0U : 1U; + uint8 txdata; + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Mode variable is configured in sciEnableNotification()" */ + if ((g_sciTransfer_t[index].mode & (uint32)SCI_TX_INT) != 0U) + { + /* we are in interrupt mode */ + + g_sciTransfer_t[index].tx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + g_sciTransfer_t[index].tx_data = data; + + /* start transmit by sending first byte */ + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + txdata = *g_sciTransfer_t[index].tx_data; + sci->TD = (uint32)(txdata); + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */ + g_sciTransfer_t[index].tx_data++; + sci->SETINT = (uint32)SCI_TX_INT; + } + else + { + /* send the data */ + while (length > 0U) + { + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((sci->FLR & (uint32)SCI_TX_INT) == 0U) + { + } /* Wait */ + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + txdata = *data; + sci->TD = (uint32)(txdata); + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */ + data++; + length--; + } + } + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ +} + + +/** @fn uint32 sciIsRxReady(sciBASE_t *sci) +* @brief Check if Rx buffer full +* @param[in] sci - sci module base address +* +* @return The Rx ready flag +* +* Checks to see if the Rx buffer full flag is set, returns +* 0 is flags not set otherwise will return the Rx flag itself. +*/ +/* SourceId : SCI_SourceId_007 */ +/* DesignId : SCI_DesignId_007 */ +/* Requirements : HL_SR236 */ +uint32 sciIsRxReady(sciBASE_t *sci) +{ +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + + return sci->FLR & (uint32)SCI_RX_INT; +} + +/** @fn uint32 sciIsIdleDetected(sciBASE_t *sci) +* @brief Check if Idle Period is Detected +* @param[in] sci - sci module base address +* +* @return The Idle flag +* +* Checks to see if the SCI Idle flag is set, returns 0 if idle +* period has been detected and SCI is ready to receive, otherwise returns the Idle flag itself. +*/ +/* SourceId : SCI_SourceId_008 */ +/* DesignId : SCI_DesignId_008 */ +/* Requirements : HL_SR237 */ +uint32 sciIsIdleDetected(sciBASE_t *sci) +{ +/* USER CODE BEGIN (14) */ +/* USER CODE END */ + + return sci->FLR & (uint32)SCI_IDLE; +} + + +/** @fn uint32 sciRxError(sciBASE_t *sci) +* @brief Return Rx Error flags +* @param[in] sci - sci module base address +* +* @return The Rx error flags +* +* Returns the Rx framing, overrun and parity errors flags, +* also clears the error flags before returning. +*/ +/* SourceId : SCI_SourceId_009 */ +/* DesignId : SCI_DesignId_009 */ +/* Requirements : HL_SR238 */ +uint32 sciRxError(sciBASE_t *sci) +{ + uint32 status = (sci->FLR & ((uint32)SCI_FE_INT | (uint32)SCI_OE_INT |(uint32)SCI_PE_INT)); + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + + sci->FLR = ((uint32)SCI_FE_INT | (uint32)SCI_OE_INT | (uint32)SCI_PE_INT); + return status; +} + + +/** @fn uint32 sciReceiveByte(sciBASE_t *sci) +* @brief Receive Byte +* @param[in] sci - sci module base address +* +* @return Received byte +* +* Receives a single byte in polling mode. If there is +* not a byte in the receive buffer the routine will wait +* until one is received. Use sciIsRxReady to check to +* see if the buffer is full to avoid waiting. +*/ +/* SourceId : SCI_SourceId_010 */ +/* DesignId : SCI_DesignId_010 */ +/* Requirements : HL_SR239 */ +uint32 sciReceiveByte(sciBASE_t *sci) +{ +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((sci->FLR & (uint32)SCI_RX_INT) == 0U) + { + } /* Wait */ + + return (sci->RD & (uint32)0x000000FFU); +} + + +/** @fn void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data) +* @brief Receive Data +* @param[in] sci - sci module base address +* @param[in] length - number of data words to transfer +* @param[in] data - pointer to data buffer to receive data +* +* Receive a block of 'length' bytes long and place it into the +* data buffer pointed to by 'data'. If interrupts have been +* enabled the data is received using interrupt mode, otherwise +* polling mode is used. In interrupt mode receive is setup and +* the routine returns immediately, sciReceive must not be called +* again until the transfer is complete, when the sciNotification +* callback will be called. In polling mode, sciReceive will not +* return until the transfer is complete. +*/ +/* SourceId : SCI_SourceId_011 */ +/* DesignId : SCI_DesignId_011 */ +/* Requirements : HL_SR240 */ +void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data) +{ +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + if ((sci->SETINT & (uint32)SCI_RX_INT) == (uint32)SCI_RX_INT) + { + /* we are in interrupt mode */ + uint32 index = (sci == sciREG) ? 0U : 1U; + + /* clear error flags */ + sci->FLR = ((uint32) SCI_FE_INT | (uint32) SCI_OE_INT | (uint32) SCI_PE_INT); + + g_sciTransfer_t[index].rx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + g_sciTransfer_t[index].rx_data = data; + } + else + { + while (length > 0U) + { + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((sci->FLR & (uint32)SCI_RX_INT) == 0U) + { + } /* Wait */ + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + *data = (uint8)(sci->RD & 0x000000FFU); + /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */ + data++; + length--; + } + } +/* USER CODE BEGIN (18) */ +/* USER CODE END */ +} + +/** @fn void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype) +* @brief Enable Loopback mode for self test +* @param[in] sci - sci module base address +* @param[in] Loopbacktype - Digital or Analog +* +* This function enables the Loopback mode for self test. +*/ +/* SourceId : SCI_SourceId_012 */ +/* DesignId : SCI_DesignId_014 */ +/* Requirements : HL_SR243 */ +void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype) +{ +/* USER CODE BEGIN (19) */ +/* USER CODE END */ + + /* Clear Loopback incase enabled already */ + sci->IODFTCTRL = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + sci->IODFTCTRL = (uint32)0x00000A00U + | (uint32)((uint32)Loopbacktype << 1U); + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ +} + +/** @fn void sciDisableLoopback(sciBASE_t *sci) +* @brief Enable Loopback mode for self test +* @param[in] sci - sci module base address +* +* This function disable the Loopback mode. +*/ +/* SourceId : SCI_SourceId_013 */ +/* DesignId : SCI_DesignId_015 */ +/* Requirements : HL_SR244 */ +void sciDisableLoopback(sciBASE_t *sci) +{ +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + + /* Disable Loopback Mode */ + sci->IODFTCTRL = 0x00000500U; + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ +} + +/** @fn sciEnableNotification(sciBASE_t *sci, uint32 flags) +* @brief Enable interrupts +* @param[in] sci - sci module base address +* @param[in] flags - Interrupts to be enabled, can be ored value of: +* SCI_FE_INT - framing error, +* SCI_OE_INT - overrun error, +* SCI_PE_INT - parity error, +* SCI_RX_INT - receive buffer ready, +* SCI_TX_INT - transmit buffer ready, +* SCI_WAKE_INT - wakeup, +* SCI_BREAK_INT - break detect +*/ +/* SourceId : SCI_SourceId_014 */ +/* DesignId : SCI_DesignId_012 */ +/* Requirements : HL_SR241 */ +void sciEnableNotification(sciBASE_t *sci, uint32 flags) +{ + uint32 index = (sci == sciREG) ? 0U : 1U; + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ + + g_sciTransfer_t[index].mode |= (flags & (uint32)SCI_TX_INT); + sci->SETINT = (flags & (uint32)(~(uint32)(SCI_TX_INT))); + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ +} + + +/** @fn sciDisableNotification(sciBASE_t *sci, uint32 flags) +* @brief Disable interrupts +* @param[in] sci - sci module base address +* @param[in] flags - Interrupts to be disabled, can be ored value of: +* SCI_FE_INT - framing error, +* SCI_OE_INT - overrun error, +* SCI_PE_INT - parity error, +* SCI_RX_INT - receive buffer ready, +* SCI_TX_INT - transmit buffer ready, +* SCI_WAKE_INT - wakeup, +* SCI_BREAK_INT - break detect +*/ +/* SourceId : SCI_SourceId_015 */ +/* DesignId : SCI_DesignId_013 */ +/* Requirements : HL_SR242 */ +void sciDisableNotification(sciBASE_t *sci, uint32 flags) +{ + uint32 index = (sci == sciREG) ? 0U : 1U; + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + + g_sciTransfer_t[index].mode &= (uint32)(~(flags & (uint32)SCI_TX_INT)); + sci->CLEARINT = (flags & (uint32)(~(uint32)(SCI_TX_INT))); + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ +} + +/** @fn sciEnterResetState(sciBASE_t *sci) +* @brief Enter reset state +* @param[in] sci - sci module base address +* @note The SCI should only be configured while in reset state +*/ +/* SourceId : SCI_SourceId_022 */ +/* DesignId : SCI_DesignId_018 */ +/* Requirements : HL_SR548 */ +void sciEnterResetState(sciBASE_t *sci) +{ + sci->GCR1 &= 0xFFFFFF7FU; +} + +/** @fn scixitResetState(sciBASE_t *sci) +* @brief Exit reset state +* @param[in] sci - sci module base address +* @note The SCI should only be configured while in reset state +*/ +/* SourceId : SCI_SourceId_023 */ +/* DesignId : SCI_DesignId_018 */ +/* Requirements : HL_SR548 */ +void sciExitResetState(sciBASE_t *sci) +{ + sci->GCR1 |= 0x00000080U; +} + + +/** @fn void scilinGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the SCILIN ( SCI2) configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : SCI_SourceId_017 */ +/* DesignId : SCI_DesignId_016 */ +/* Requirements : HL_SR247 */ +void scilinGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_GCR0 = SCILIN_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = SCILIN_GCR1_CONFIGVALUE; + config_reg->CONFIG_SETINT = SCILIN_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = SCILIN_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = SCILIN_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRS = SCILIN_BRS_CONFIGVALUE; + config_reg->CONFIG_PIO0 = SCILIN_PIO0_CONFIGVALUE; + config_reg->CONFIG_PIO1 = SCILIN_PIO1_CONFIGVALUE; + config_reg->CONFIG_PIO6 = SCILIN_PIO6_CONFIGVALUE; + config_reg->CONFIG_PIO7 = SCILIN_PIO7_CONFIGVALUE; + config_reg->CONFIG_PIO8 = SCILIN_PIO8_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_GCR0 = scilinREG->GCR0; + config_reg->CONFIG_GCR1 = scilinREG->GCR1; + config_reg->CONFIG_SETINT = scilinREG->SETINT; + config_reg->CONFIG_SETINTLVL = scilinREG->SETINTLVL; + config_reg->CONFIG_FORMAT = scilinREG->FORMAT; + config_reg->CONFIG_BRS = scilinREG->BRS; + config_reg->CONFIG_PIO0 = scilinREG->PIO0; + config_reg->CONFIG_PIO1 = scilinREG->PIO1; + config_reg->CONFIG_PIO6 = scilinREG->PIO6; + config_reg->CONFIG_PIO7 = scilinREG->PIO7; + config_reg->CONFIG_PIO8 = scilinREG->PIO8; + } +} + +/* USER CODE BEGIN (37) */ +/* USER CODE END */ + diff --git a/src/arch/rm46l8lp/halcogen/sys_core.asm b/src/arch/rm46l8lp/halcogen/sys_core.asm new file mode 100644 index 0000000..f02616e --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_core.asm @@ -0,0 +1,734 @@ +;------------------------------------------------------------------------------- +; sys_core.asm +; +; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +; +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; +; + + .text + .arm + +;------------------------------------------------------------------------------- +; Initialize CPU Registers +; SourceId : CORE_SourceId_001 +; DesignId : CORE_DesignId_001 +; Requirements: HL_SR477, HL_SR476, HL_SR492 + + .def _coreInitRegisters_ + .asmfunc + + +_coreInitRegisters_ + + + ; After reset, the CPU is in the Supervisor mode (M = 10011) + mov r0, lr + mov r1, #0x0000 + mov r2, #0x0000 + mov r3, #0x0000 + mov r4, #0x0000 + mov r5, #0x0000 + mov r6, #0x0000 + mov r7, #0x0000 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mov r13, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + ; Switch to FIQ mode (M = 10001) + cps #17 + mov lr, r0 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + ; Switch to IRQ mode (M = 10010) + cps #18 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + ; Switch to Abort mode (M = 10111) + cps #23 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + ; Switch to Undefined Instruction Mode (M = 11011) + cps #27 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + ; Switch to System Mode ( Shares User Mode registers ) (M = 11111) + cps #31 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + + + mrc p15, #0x00, r2, c1, c0, #0x02 + orr r2, r2, #0xF00000 + mcr p15, #0x00, r2, c1, c0, #0x02 + mov r2, #0x40000000 + fmxr fpexc, r2 + + fmdrr d0, r1, r1 + fmdrr d1, r1, r1 + fmdrr d2, r1, r1 + fmdrr d3, r1, r1 + fmdrr d4, r1, r1 + fmdrr d5, r1, r1 + fmdrr d6, r1, r1 + fmdrr d7, r1, r1 + fmdrr d8, r1, r1 + fmdrr d9, r1, r1 + fmdrr d10, r1, r1 + fmdrr d11, r1, r1 + fmdrr d12, r1, r1 + fmdrr d13, r1, r1 + fmdrr d14, r1, r1 + fmdrr d15, r1, r1 + bl next1 +next1 + bl next2 +next2 + bl next3 +next3 + bl next4 +next4 + bx r0 + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Initialize Stack Pointers +; SourceId : CORE_SourceId_002 +; DesignId : CORE_DesignId_002 +; Requirements: HL_SR478 + + .def _coreInitStackPointer_ + .asmfunc + +_coreInitStackPointer_ + + cps #17 + ldr sp, fiqSp + cps #18 + ldr sp, irqSp + cps #19 + ldr sp, svcSp + cps #23 + ldr sp, abortSp + cps #27 + ldr sp, undefSp + cps #31 + ldr sp, userSp + bx lr + +userSp .word 0x08000000+0x00001000 +svcSp .word 0x08000000+0x00001000+0x00000100 +fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100 +irqSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000200 +abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000200+0x00000100 +undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000200+0x00000100+0x00000100 + + .endasmfunc + +;------------------------------------------------------------------------------- +; Get CPSR Value +; SourceId : CORE_SourceId_003 +; DesignId : CORE_DesignId_003 +; Requirements: + + .def _getCPSRValue_ + .asmfunc + +_getCPSRValue_ + + mrs r0, CPSR + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Take CPU to IDLE state +; SourceId : CORE_SourceId_004 +; DesignId : CORE_DesignId_004 +; Requirements: HL_SR493 + + .def _gotoCPUIdle_ + .asmfunc + +_gotoCPUIdle_ + + WFI + nop + nop + nop + nop + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Enable VFP Unit +; SourceId : CORE_SourceId_005 +; DesignId : CORE_DesignId_006 +; Requirements: HL_SR492, HL_SR476 + + .def _coreEnableVfp_ + .asmfunc + +_coreEnableVfp_ + + mrc p15, #0x00, r0, c1, c0, #0x02 + orr r0, r0, #0xF00000 + mcr p15, #0x00, r0, c1, c0, #0x02 + mov r0, #0x40000000 + fmxr fpexc, r0 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Enable Event Bus Export +; SourceId : CORE_SourceId_006 +; DesignId : CORE_DesignId_007 +; Requirements: HL_SR479 + + .def _coreEnableEventBusExport_ + .asmfunc + +_coreEnableEventBusExport_ + + mrc p15, #0x00, r0, c9, c12, #0x00 + orr r0, r0, #0x10 + mcr p15, #0x00, r0, c9, c12, #0x00 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Disable Event Bus Export +; SourceId : CORE_SourceId_007 +; DesignId : CORE_DesignId_008 +; Requirements: HL_SR481 + + + .def _coreDisableEventBusExport_ + .asmfunc + +_coreDisableEventBusExport_ + + mrc p15, #0x00, r0, c9, c12, #0x00 + bic r0, r0, #0x10 + mcr p15, #0x00, r0, c9, c12, #0x00 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Enable RAM ECC Support +; SourceId : CORE_SourceId_008 +; DesignId : CORE_DesignId_009 +; Requirements: HL_SR480 + + .def _coreEnableRamEcc_ + .asmfunc + +_coreEnableRamEcc_ + + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Disable RAM ECC Support +; SourceId : CORE_SourceId_009 +; DesignId : CORE_DesignId_010 +; Requirements: HL_SR482 + + .def _coreDisableRamEcc_ + .asmfunc + +_coreDisableRamEcc_ + + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Enable Flash ECC Support +; SourceId : CORE_SourceId_010 +; DesignId : CORE_DesignId_011 +; Requirements: HL_SR480, HL_SR458 + + .def _coreEnableFlashEcc_ + .asmfunc + +_coreEnableFlashEcc_ + + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x02000000 + dmb + mcr p15, #0x00, r0, c1, c0, #0x01 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Disable Flash ECC Support +; SourceId : CORE_SourceId_011 +; DesignId : CORE_DesignId_012 +; Requirements: HL_SR482 + + .def _coreDisableFlashEcc_ + .asmfunc + +_coreDisableFlashEcc_ + + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x02000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Enable Offset via Vic controller +; SourceId : CORE_SourceId_012 +; DesignId : CORE_DesignId_005 +; Requirements: HL_SR483, HL_SR491 + + .def _coreEnableIrqVicOffset_ + .asmfunc + +_coreEnableIrqVicOffset_ + + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x01000000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get data fault status register +; SourceId : CORE_SourceId_013 +; DesignId : CORE_DesignId_013 +; Requirements: HL_SR495 + + .def _coreGetDataFault_ + .asmfunc + +_coreGetDataFault_ + + mrc p15, #0, r0, c5, c0, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Clear data fault status register +; SourceId : CORE_SourceId_014 +; DesignId : CORE_DesignId_014 +; Requirements: HL_SR495 + + .def _coreClearDataFault_ + .asmfunc + +_coreClearDataFault_ + + mov r0, #0 + mcr p15, #0, r0, c5, c0, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get instruction fault status register +; SourceId : CORE_SourceId_015 +; DesignId : CORE_DesignId_015 +; Requirements: HL_SR495 + + .def _coreGetInstructionFault_ + .asmfunc + +_coreGetInstructionFault_ + + mrc p15, #0, r0, c5, c0, #1 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Clear instruction fault status register +; SourceId : CORE_SourceId_016 +; DesignId : CORE_DesignId_016 +; Requirements: HL_SR495 + + .def _coreClearInstructionFault_ + .asmfunc + +_coreClearInstructionFault_ + + mov r0, #0 + mcr p15, #0, r0, c5, c0, #1 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get data fault address register +; SourceId : CORE_SourceId_017 +; DesignId : CORE_DesignId_017 +; Requirements: HL_SR495 + + .def _coreGetDataFaultAddress_ + .asmfunc + +_coreGetDataFaultAddress_ + + mrc p15, #0, r0, c6, c0, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Clear data fault address register +; SourceId : CORE_SourceId_018 +; DesignId : CORE_DesignId_018 +; Requirements: HL_SR495 + + .def _coreClearDataFaultAddress_ + .asmfunc + +_coreClearDataFaultAddress_ + + mov r0, #0 + mcr p15, #0, r0, c6, c0, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get instruction fault address register +; SourceId : CORE_SourceId_019 +; DesignId : CORE_DesignId_019 +; Requirements: HL_SR495 + + .def _coreGetInstructionFaultAddress_ + .asmfunc + +_coreGetInstructionFaultAddress_ + + mrc p15, #0, r0, c6, c0, #2 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Clear instruction fault address register +; SourceId : CORE_SourceId_020 +; DesignId : CORE_DesignId_020 +; Requirements: HL_SR495 + + .def _coreClearInstructionFaultAddress_ + .asmfunc + +_coreClearInstructionFaultAddress_ + + mov r0, #0 + mcr p15, #0, r0, c6, c0, #2 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get auxiliary data fault status register +; SourceId : CORE_SourceId_021 +; DesignId : CORE_DesignId_021 +; Requirements: HL_SR496 + + .def _coreGetAuxiliaryDataFault_ + .asmfunc + +_coreGetAuxiliaryDataFault_ + + mrc p15, #0, r0, c5, c1, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Clear auxiliary data fault status register +; SourceId : CORE_SourceId_022 +; DesignId : CORE_DesignId_022 +; Requirements: HL_SR496 + + .def _coreClearAuxiliaryDataFault_ + .asmfunc + +_coreClearAuxiliaryDataFault_ + + mov r0, #0 + mcr p15, #0, r0, c5, c1, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get auxiliary instruction fault status register +; SourceId : CORE_SourceId_023 +; DesignId : CORE_DesignId_023 +; Requirements: HL_SR496 + + .def _coreGetAuxiliaryInstructionFault_ + .asmfunc + +_coreGetAuxiliaryInstructionFault_ + + mrc p15, #0, r0, c5, c1, #1 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Clear auxiliary instruction fault status register +; SourceId : CORE_SourceId_024 +; DesignId : CORE_DesignId_024 +; Requirements: HL_SR496 + + .def _coreClearAuxiliaryInstructionFault_ + .asmfunc + +_coreClearAuxiliaryInstructionFault_ + + mov r0, #0 + mrc p15, #0, r0, c5, c1, #1 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Disable interrupts - R4 IRQ & FIQ +; SourceId : CORE_SourceId_025 +; DesignId : CORE_DesignId_025 +; Requirements: HL_SR494 + + .def _disable_interrupt_ + .asmfunc + +_disable_interrupt_ + + cpsid if + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Disable FIQ interrupt +; SourceId : CORE_SourceId_026 +; DesignId : CORE_DesignId_026 +; Requirements: HL_SR494 + + .def _disable_FIQ_interrupt_ + .asmfunc + +_disable_FIQ_interrupt_ + + cpsid f + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Disable FIQ interrupt + + .def _disable_IRQ_interrupt_ + .asmfunc + +_disable_IRQ_interrupt_ + + cpsid i + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Enable interrupts - R4 IRQ & FIQ + + .def _enable_interrupt_ + .asmfunc + +_enable_interrupt_ + + cpsie if + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Clear ESM CCM errorss + + .def _esmCcmErrorsClear_ + .asmfunc + +_esmCcmErrorsClear_ + + stmfd sp!, {r0-r2} + ldr r0, ESMSR1_REG ; load the ESMSR1 status register address + ldr r2, ESMSR1_ERR_CLR + str r2, [r0] ; clear the ESMSR1 register + + ldr r0, ESMSR2_REG ; load the ESMSR2 status register address + ldr r2, ESMSR2_ERR_CLR + str r2, [r0] ; clear the ESMSR2 register + + ldr r0, ESMSSR2_REG ; load the ESMSSR2 status register address + ldr r2, ESMSSR2_ERR_CLR + str r2, [r0] ; clear the ESMSSR2 register + + ldr r0, ESMKEY_REG ; load the ESMKEY register address + mov r2, #0x5 ; load R2 with 0x5 + str r2, [r0] ; clear the ESMKEY register + + ldr r0, VIM_INTREQ ; load the INTREQ register address + ldr r2, VIM_INT_CLR + str r2, [r0] ; clear the INTREQ register + ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address + ldr r2, CCMR4_ERR_CLR + str r2, [r0] ; clear the CCMR4 status register + ldmfd sp!, {r0-r2} + bx lr + +ESMSR1_REG .word 0xFFFFF518 +ESMSR2_REG .word 0xFFFFF51C +ESMSR3_REG .word 0xFFFFF520 +ESMKEY_REG .word 0xFFFFF538 +ESMSSR2_REG .word 0xFFFFF53C +CCMR4_STAT_REG .word 0xFFFFF600 +ERR_CLR_WRD .word 0xFFFFFFFF +CCMR4_ERR_CLR .word 0x00010000 +ESMSR1_ERR_CLR .word 0x80000000 +ESMSR2_ERR_CLR .word 0x00000004 +ESMSSR2_ERR_CLR .word 0x00000004 +VIM_INT_CLR .word 0x00000001 +VIM_INTREQ .word 0xFFFFFE20 + + .endasmfunc + +;------------------------------------------------------------------------------- +; Work Around for Errata CORTEX-R4#57: +; +; Errata Description: +; Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags +; Workaround: +; Disable out-of-order single-precision floating point +; multiply-accumulate instruction completion + + .def _errata_CORTEXR4_57_ + .asmfunc + +_errata_CORTEXR4_57_ + + mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register + orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS) + mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register + bx lr + .endasmfunc + +;------------------------------------------------------------------------------- +; Work Around for Errata CORTEX-R4#66: +; +; Errata Description: +; Register Corruption During A Load-Multiple Instruction At +; an Exception Vector +; Workaround: +; Disable out-of-order completion for divide instructions in +; Auxiliary Control register + + .def _errata_CORTEXR4_66_ + .asmfunc + +_errata_CORTEXR4_66_ + + mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register + orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion + ; for divide instructions.) + mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register + bx lr + .endasmfunc +;------------------------------------------------------------------------------- +; C++ construct table pointers + + .def __TI_PINIT_Base, __TI_PINIT_Limit + .weak SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit + +__TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base +__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit + + + +;------------------------------------------------------------------------------- + diff --git a/src/arch/rm46l8lp/halcogen/sys_dma.c b/src/arch/rm46l8lp/halcogen/sys_dma.c new file mode 100644 index 0000000..3bbed4f --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_dma.c @@ -0,0 +1,449 @@ +/** @file dma.c +* @brief DMA Driver Implementation File +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +#include "sys_dma.h" +#include "sys_vim.h" + +/** @fn void dmaEnable(void) +* @brief enables DMA module +* +* This function brings DMA out of reset +*/ +/* SourceId : DMA_SourceId_001 */ +/* DesignId : DMA_DesignId_001 */ +/* Requirements: HL_SR167 */ +void dmaEnable(void) +{ + dmaREG->GCTRL = 0x00010000U; /* enable dma */ + dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */ +} + +/** @fn void dmaDisable(void) +* @brief disables DMA module +* +* This function disables DMA module +*/ +/* SourceId : DMA_SourceId_002 */ +/* DesignId : DMA_DesignId_002 */ +/* Requirements: HL_SR168 */ +void dmaDisable(void) +{ + /* Wait until DMA's external bus has completed data transfer */ + /*SAFETYMCUSW 134 S MR: 12.2 <APPROVED> "Tool issue" */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((dmaREG->GCTRL & DMA_GCTRL_BUSBUSY) != 0U) + { + } /* Wait */ + /* Disable DMA module */ + dmaREG->GCTRL = 0U; +} + + +/** @fn void dmaReqAssign(uint32 channel,uint32 reqline) +* @brief Assign DMA request lines to channels +* @param[in] channel DMA channel +* @param[in] reqline DMA request line +* +* This function assigns DMA request lines to channels +*/ +/* SourceId : DMA_SourceId_003 */ +/* DesignId : DMA_DesignId_005 */ +/* Requirements: HL_SR169 */ +void dmaReqAssign(uint32 channel,uint32 reqline) +{ + register uint32 i=0U,j=0U; + + i = channel >> 2U; /* Find the register to configure */ + j = channel - (i << 2U); /* Find the offset of the type */ + j = 3U - j; /* reverse the byte order */ + j = j << 3U; /* find the bit location */ + + /* mapping channel 'i' to request line 'j' */ + dmaREG->DREQASI[i] &= ~(uint32)((uint32)0xFFU << j); + dmaREG->DREQASI[i] |= (reqline << j); +} + + +/** @fn uint32 dmaGetReq(uint32 channel) +* @brief Gets the request line number mapped to the selected channel +* @param[in] channel DMA channel +* +* This function returns the request line number mapped to the selected channel +*/ +/* SourceId : DMA_SourceId_004 */ +/* DesignId : DMA_DesignId_006 */ +/* Requirements: HL_SR170 */ +uint32 dmaGetReq(uint32 channel) +{ + register uint32 i=0U,j=0U; + + i = channel >> 2U; /* Find the register to configure */ + j = channel - (i << 2U); /* Find the offset of the type */ + j = 3U - j; /* reverse the byte order */ + j = j << 3U; /* find the bit location */ + return ((dmaREG->DREQASI[i] >> j) & 0xFFU); +} + + +/** @fn void dmaSetCtrlPacket(uint32 channel) +* @brief Set control packet +* +* This function sets control packet +*/ +/* SourceId : DMA_SourceId_005 */ +/* DesignId : DMA_DesignId_003 */ +/* Requirements: HL_SR171 */ +void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT) +{ + register uint32 i=0U,j=0U; + + dmaRAMREG->PCP[channel].ISADDR = g_dmaCTRLPKT.SADD; + + dmaRAMREG->PCP[channel].IDADDR = g_dmaCTRLPKT.DADD; + + dmaRAMREG->PCP[channel].ITCOUNT = (g_dmaCTRLPKT.FRCNT << 16U) | g_dmaCTRLPKT.ELCNT; + + dmaRAMREG->PCP[channel].CHCTRL = (g_dmaCTRLPKT.RDSIZE << 14U) | (g_dmaCTRLPKT.WRSIZE << 12U) | (g_dmaCTRLPKT.TTYPE << 8U)| \ + (g_dmaCTRLPKT.ADDMODERD << 3U ) | (g_dmaCTRLPKT.ADDMODEWR << 1U ) | (g_dmaCTRLPKT.AUTOINIT); + + dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16U); + + dmaRAMREG->PCP[channel].EIOFF = (g_dmaCTRLPKT.ELDOFFSET << 16U) | (g_dmaCTRLPKT.ELSOFFSET); + + dmaRAMREG->PCP[channel].FIOFF = (g_dmaCTRLPKT.FRDOFFSET << 16U) | (g_dmaCTRLPKT.FRSOFFSET); + + i = channel >> 3U; /* Find the register to write */ + j = channel - (i << 3U); /* Find the offset of the 4th bit */ + j = 7U - j; /* Reverse the order of the 4th bit offset */ + j = j << 2U; /* Find the bit location of the 4th bit to write */ + + dmaREG->PAR[i] &= ~(uint32)((uint32)0xFU << j); + dmaREG->PAR[i] |= (g_dmaCTRLPKT.PORTASGN << j); +} + + + +/** @fn void dmaSetChEnable(uint32 channel,uint32 type) +* @brief Enable channel +* @param[in] channel DMA channel +* @param[in] type Type of triggering +* - DMA_HW: Enables the selected DMA channel for hardware triggering +* - DMA_SW: Enables the selected DMA channel for software triggering +* +* This function enables the DMA channel for hardware or software triggering +*/ +/* SourceId : DMA_SourceId_006 */ +/* DesignId : DMA_DesignId_004 */ +/* Requirements: HL_SR172 */ +void dmaSetChEnable(uint32 channel,uint32 type) +{ + if(type == (uint32)DMA_HW) + { + dmaREG->HWCHENAS = (uint32)1U << channel; + } + else if(type == (uint32)DMA_SW) + { + dmaREG->SWCHENAS = (uint32)1U << channel; + } + else + { + /* Empty */ + } +} + + + +/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority) +* @brief Assign Priority to the channel +* @param[in] channel DMA channel +* @param[in] priority Priority queue to which channel needs to be assigned +* - LOWPRIORITY : The selected channel will be assigned to low priority queue +* - HIGHPRIORITY: The selected channel will be assigned to high priority queue +* +* This function assigns the selected priority to the selected channel +*/ +/* SourceId : DMA_SourceId_007 */ +/* DesignId : DMA_DesignId_007 */ +/* Requirements: HL_SR173 */ +void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority) +{ + if (priority == LOWPRIORITY) + { + dmaREG->CHPRIOR = (uint32)1U << channel; + } + else + { + dmaREG->CHPRIOS = (uint32)1U << channel; + } +} + + +/** @fn void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype) +* @brief Enable selected interrupt +* @param[in] channel DMA channel +* @param[in] inttype Interrupt to be enabled +* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel +* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel +* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel +* - BTC: Block transfer complete Interrupt will be disabled for the selected channel +* - BER: Bus Error Interrupt will be disabled for the selected channel +* +* This function enables the selected interrupt for the selected channel +*/ +/* SourceId : DMA_SourceId_008 */ +/* DesignId : DMA_DesignId_008 */ +/* Requirements: HL_SR174 */ +void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype) +{ + dmaREG->GCHIENAS = (uint32)1U << channel; + + switch (inttype) + { + case FTC: dmaREG->FTCINTENAS = (uint32)1U << channel; + break; + case LFS: dmaREG->LFSINTENAS = (uint32)1U << channel; + break; + case HBC: dmaREG->HBCINTENAS = (uint32)1U << channel; + break; + case BTC: dmaREG->BTCINTENAS = (uint32)1U << channel; + break; + default : + break; + } +} + + + +/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype) +* @brief Disable selected interrupt +* @param[in] channel DMA channel +* @param[in] inttype Interrupt to be disabled +* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel +* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel +* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel +* - BTC: Block transfer complete Interrupt will be disabled for the selected channel +* - BER: Bus Error Interrupt will be disabled for the selected channel +* +* This function disables the selected interrupt for the selected channel +*/ +/* SourceId : DMA_SourceId_009 */ +/* DesignId : DMA_DesignId_009 */ +/* Requirements: HL_SR175 */ +void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype) +{ + switch (inttype) + { + case FTC: dmaREG->FTCINTENAR = (uint32)1U << channel; + break; + case LFS: dmaREG->LFSINTENAR = (uint32)1U << channel; + break; + case HBC: dmaREG->HBCINTENAR = (uint32)1U << channel; + break; + case BTC: dmaREG->BTCINTENAR = (uint32)1U << channel; + break; + default : + break; + } +} + + + +/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add) +* @brief Configure start and end address of the region +* @param[in] region Memory Region +* - DMA_REGION0 +* - DMA_REGION1 +* - DMA_REGION2 +* - DMA_REGION3 +* @param[in] start_add Start address of the the region +* @param[in] end_add End address of the region +* +* This function configure start and end address of the selected region +*/ +/* SourceId : DMA_SourceId_010 */ +/* DesignId : DMA_DesignId_010 */ +/* Requirements: HL_SR176 */ +void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add) +{ + dmaREG->DMAMPR[region].STARTADD = start_add; + dmaREG->DMAMPR[region].ENDADD = end_add; +} + + + +/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable) +* @brief Enable the selected region +* @param[in] region Memory Region +* - DMA_REGION0 +* - DMA_REGION1 +* - DMA_REGION2 +* - DMA_REGION3 +* @param[in] access Access permission of the selected region +* - FULLACCESS +* - READONLY +* - WRITEONLY +* - NOACCESS +* @param[in] intenable Interrupt to be enabled or not +* - INTERRUPT_ENABLE : Enable interrupt for the selected region +* - INTERRUPT_DISABLE: Disable interrupt for the selected region +* +* This function enables the selected region with selected access permission with or without interrupt enable +*/ +/* SourceId : DMA_SourceId_011 */ +/* DesignId : DMA_DesignId_011 */ +/* Requirements: HL_SR177 */ +void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable) +{ + dmaREG->DMAMPCTRL &= ~(uint32)((uint32)0xFFU << (region*8U)); + + /* Enable the region */ + dmaREG->DMAMPCTRL |= (uint32)1U << (region*8U); + + /* Set access permission for the region */ + dmaREG->DMAMPCTRL |= (uint32)access << ((region*8U) + 1U); + + if(intenable) + { + /* Enable interrupt */ + dmaREG->DMAMPCTRL |= (uint32)1U << ((region*8U) + 3U); + } +} + + + +/** @fn void dmaDisableRegion(dmaREGION_t region) +* @brief Disable the selected region +* @param[in] region Memory Region +* - DMA_REGION0 +* - DMA_REGION1 +* - DMA_REGION2 +* - DMA_REGION3 +* +* This function disables the selected region(no address checking done). +*/ +/* SourceId : DMA_SourceId_012 */ +/* DesignId : DMA_DesignId_012 */ +/* Requirements: HL_SR178 */ +void dmaDisableRegion(dmaREGION_t region) +{ + dmaREG->DMAMPCTRL &= ~(uint32)((uint32)1U << ((uint32)region*8U)); +} + + + +/** @fn void dmaEnableParityCheck(void) +* @brief Enable Parity Check +* +* This function enables parity check +*/ +/* SourceId : DMA_SourceId_013 */ +/* DesignId : DMA_DesignId_013 */ +/* Requirements: HL_SR179 */ +void dmaEnableParityCheck(void) +{ + dmaREG->DMAPCR = 0xAU; +} + + + +/** @fn void dmaDisableParityCheck(void) +* @brief Disable Parity Check +* +* This function disables parity check +*/ +/* SourceId : DMA_SourceId_014 */ +/* DesignId : DMA_DesignId_014 */ +/* Requirements: HL_SR180 */ +void dmaDisableParityCheck(void) +{ + dmaREG->DMAPCR = 0x5U; +} + +/** @fn void dmaGetConfigValue(dma_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : DMA_SourceId_015 */ +/* DesignId : DMA_DesignId_015 */ +/* Requirements: HL_SR183 */ +void dmaGetConfigValue(dma_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + {/* Do not pass Initial value as parameter as there is no DMA initialization API */ + } + else + { + config_reg->CONFIG_CHPRIOS = dmaREG->CHPRIOS; + config_reg->CONFIG_GCHIENAS = dmaREG->GCHIENAS; + config_reg->CONFIG_DREQASI[0U] = dmaREG->DREQASI[0U]; + config_reg->CONFIG_DREQASI[1U] = dmaREG->DREQASI[1U]; + config_reg->CONFIG_DREQASI[2U] = dmaREG->DREQASI[2U]; + config_reg->CONFIG_DREQASI[3U] = dmaREG->DREQASI[3U]; + config_reg->CONFIG_DREQASI[4U] = dmaREG->DREQASI[4U]; + config_reg->CONFIG_DREQASI[5U] = dmaREG->DREQASI[5U]; + config_reg->CONFIG_DREQASI[6U] = dmaREG->DREQASI[6U]; + config_reg->CONFIG_DREQASI[7U] = dmaREG->DREQASI[7U]; + config_reg->CONFIG_FTCINTENAS = dmaREG->FTCINTENAS; + config_reg->CONFIG_LFSINTENAS = dmaREG->LFSINTENAS; + config_reg->CONFIG_HBCINTENAS = dmaREG->HBCINTENAS; + config_reg->CONFIG_BTCINTENAS = dmaREG->BTCINTENAS; + config_reg->CONFIG_DMAPCR = dmaREG->DMAPCR; + config_reg->CONFIG_DMAMPCTRL = dmaREG->DMAMPCTRL; + } +} + + + + + diff --git a/src/arch/rm46l8lp/halcogen/sys_intvecs.asm b/src/arch/rm46l8lp/halcogen/sys_intvecs.asm new file mode 100644 index 0000000..e0833fc --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_intvecs.asm @@ -0,0 +1,66 @@ +;------------------------------------------------------------------------------- +; sys_intvecs.asm +; +; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +; +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; +; + + .sect ".intvecs" + .arm + +;------------------------------------------------------------------------------- +; import reference for interrupt routines + + .ref _c_int00 + .ref _dabort + .ref phantomInterrupt + .def resetEntry + +;------------------------------------------------------------------------------- +; interrupt vectors + +resetEntry + b _c_int00 +undefEntry + b undefEntry +svcEntry + b svcEntry +prefetchEntry + b prefetchEntry + b _dabort + b phantomInterrupt + ldr pc,[pc,#-0x1b0] + ldr pc,[pc,#-0x1b0] + + +;------------------------------------------------------------------------------- diff --git a/src/arch/rm46l8lp/halcogen/sys_link.cmd b/src/arch/rm46l8lp/halcogen/sys_link.cmd new file mode 100644 index 0000000..04ef758c --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_link.cmd @@ -0,0 +1,134 @@ +/*----------------------------------------------------------------------------*/ +/* sys_link.cmd */ +/* */ +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/* */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + + +/*----------------------------------------------------------------------------*/ +/* Linker Settings */ + +--retain="*(.intvecs)" + +/* USER CODE BEGIN (1) */ +#if 1 +/* USER CODE END */ + +/*----------------------------------------------------------------------------*/ +/* Memory Map */ + +MEMORY +{ + VECTORS (X) : origin=0x00000000 length=0x00000020 + FLASH0 (RX) : origin=0x00000020 length=0x0013FFE0 + STACKS (RW) : origin=0x08000000 length=0x00001600 + RAM (RW) : origin=0x08001600 length=0x0002ea00 + +/* USER CODE BEGIN (2) */ +#endif +#if 0 +MEMORY +{ + + VECTORS (X) : origin=0x00000000 length=0x00000020 + FLASH0 (RX) : origin=0x00000020 length=0x0013FF00 + FLASH1 (RX) : origin=0x00180000 length=0x00180000 + + STACKS (RW) : origin=0x08000000 length=0x00001800 + RAM (RW) : origin=0x08001800 length=0x0002E7FF +#endif +/* USER CODE END */ +} + +/* USER CODE BEGIN (3) */ +#if 1 +/* USER CODE END */ + +/*----------------------------------------------------------------------------*/ +/* Section Configuration */ + +SECTIONS +{ + .intvecs : {} > VECTORS + .text : {} > FLASH0 + .const : {} > FLASH0 + .cinit : {} > FLASH0 + .pinit : {} > FLASH0 + .bss : {} > RAM + .data : {} > RAM + .sysmem : {} > RAM + + +/* USER CODE BEGIN (4) */ +#endif +#if 0 +SECTIONS +{ + .intvecs : {} > VECTORS + .text : {} > FLASH0 | FLASH1 + .const : {} > FLASH0 | FLASH1 + .cinit : {} > FLASH0 | FLASH1 + .pinit : {} > FLASH0 | FLASH1 + .bss : {} > RAM + .data : {} > RAM + .sysmem : {} > RAM + + .STACK_DATA_svc : {. += 1024;} > STACKS, RUN_START(StackModeSVC) + .STACK_DATA_fiq : {. += 1024;} > STACKS, RUN_START(StackModeFIQ) + .STACK_DATA_irq : {. += 1024;} > STACKS, RUN_START(StackModeIRQ) + .STACK_DATA_abt : {. += 1024;} > STACKS, RUN_START(StackModeABT) + .STACK_DATA_und : {. += 1024;} > STACKS, RUN_START(StackModeUND) + .STACK_DATA_sys : {. += 1024;} > STACKS, RUN_START(StackModeSYS) + .bss : {} > RAM + .data : {} > RAM + .sysmem : {} > RAM +#endif +/* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + +/*----------------------------------------------------------------------------*/ +/* Misc */ + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ +/*----------------------------------------------------------------------------*/ diff --git a/src/arch/rm46l8lp/halcogen/sys_main.c b/src/arch/rm46l8lp/halcogen/sys_main.c new file mode 100644 index 0000000..a8d5070 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_main.c @@ -0,0 +1,76 @@ +/** @file sys_main.c +* @brief Application main file +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains an empty main function, +* which can be used for the application. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "sys_common.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void main(void) +* @brief Application main function +* @note This function is empty by default. +* +* This function is called after startup. +* The user can use this function to implement the application. +*/ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +int main(void) +{ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + + return 0; +} + + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ diff --git a/src/arch/rm46l8lp/halcogen/sys_mpu.asm b/src/arch/rm46l8lp/halcogen/sys_mpu.asm new file mode 100644 index 0000000..990f177 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_mpu.asm @@ -0,0 +1,470 @@ +;------------------------------------------------------------------------------- +; sys_mpu.asm +; +; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +; +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; +; + + .text + .arm + + +;------------------------------------------------------------------------------- +; Initalize Mpu +; SourceId : MPU_SourceId_001 +; DesignId : MPU_DesignId_001 +; Requirements : HL_SR487 + + .def _mpuInit_ + .asmfunc + +_mpuInit_ + ; Disable mpu + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #1 + dsb + mcr p15, #0, r0, c1, c0, #0 + isb + ; Disable background region + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x20000 + mcr p15, #0, r0, c1, c0, #0 + ; Setup region 1 + mov r0, #0 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r1Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0008 + orr r0, r0, #0x1000 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1F << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + ; Setup region 2 + mov r0, #1 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r2Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0008 + orr r0, r0, #0x0600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + ; Setup region + mov r0, #2 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r3Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0008 + orr r0, r0, #0x0300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + ; Setup region 4 + mov r0, #3 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r4Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0008 + orr r0, r0, #0x0300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + ; Setup region 5 + mov r0, #4 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r5Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0000 + orr r0, r0, #0x0300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x19 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + ; Setup region 6 + mov r0, #5 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r6Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0000 + orr r0, r0, #0x0300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1A << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + ; Setup region 7 + mov r0, #6 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r7Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0008 + orr r0, r0, #0x1200 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x16 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + ; Setup region 8 + mov r0, #7 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r8Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0010 + orr r0, r0, #0x1300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + ; Setup region 9 + mov r0, #8 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r9Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0010 + orr r0, r0, #0x1300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x08 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + ; Setup region 10 + mov r0, #9 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r10Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0010 + orr r0, r0, #0x1300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + ; Setup region 11 + mov r0, #10 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r11Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0008 + orr r0, r0, #0x0300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x0A << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + ; Setup region 12 + mov r0, #11 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r12Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0008 + orr r0, r0, #0x1300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + + + ; Enable mpu background region + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x20000 + mcr p15, #0, r0, c1, c0, #0 + ; Enable mpu + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #1 + dsb + mcr p15, #0, r0, c1, c0, #0 + isb + bx lr + +r1Base .word 0x00000000 +r2Base .word 0x00000000 +r3Base .word 0x08000000 +r4Base .word 0x08400000 +r5Base .word 0x60000000 +r6Base .word 0x80000000 +r7Base .word 0xF0000000 +r8Base .word 0xFC000000 +r9Base .word 0xFE000000 +r10Base .word 0xFF000000 +r11Base .word 0x08001800 +r12Base .word 0x20000000 + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Enable Mpu +; SourceId : MPU_SourceId_002 +; DesignId : MPU_DesignId_002 +; Requirements : HL_SR488 + + .def _mpuEnable_ + .asmfunc + +_mpuEnable_ + + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #1 + dsb + mcr p15, #0, r0, c1, c0, #0 + isb + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Disable Mpu +; SourceId : MPU_SourceId_003 +; DesignId : MPU_DesignId_003 +; Requirements : HL_SR488 + + .def _mpuDisable_ + .asmfunc + +_mpuDisable_ + + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #1 + dsb + mcr p15, #0, r0, c1, c0, #0 + isb + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Enable Mpu background region +; SourceId : MPU_SourceId_004 +; DesignId : MPU_DesignId_004 +; Requirements : HL_SR488 + + .def _mpuEnableBackgroundRegion_ + .asmfunc + +_mpuEnableBackgroundRegion_ + + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x20000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Disable Mpu background region +; SourceId : MPU_SourceId_005 +; DesignId : MPU_DesignId_005 +; Requirements : HL_SR488 + + .def _mpuDisableBackgroundRegion_ + .asmfunc + +_mpuDisableBackgroundRegion_ + + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x20000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Returns number of implemented Mpu regions +; SourceId : MPU_SourceId_006 +; DesignId : MPU_DesignId_006 +; Requirements : HL_SR490 + + .def _mpuGetNumberOfRegions_ + .asmfunc + +_mpuGetNumberOfRegions_ + + mrc p15, #0, r0, c0, c0, #4 + uxtb r0, r0, ROR #8 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Returns the type of the implemented mpu regions +; SourceId : MPU_SourceId_007 +; DesignId : MPU_DesignId_007 +; Requirements : HL_SR490 + + .def _mpuAreRegionsSeparate_ + .asmfunc + +_mpuAreRegionsSeparate_ + + mrc p15, #0, r0, c0, c0, #4 + uxtb r0, r0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Set mpu region number +; SourceId : MPU_SourceId_008 +; DesignId : MPU_DesignId_008 +; Requirements : HL_SR489 + + .def _mpuSetRegion_ + .asmfunc + +_mpuSetRegion_ + + mcr p15, #0, r0, c6, c2, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get mpu region number +; SourceId : MPU_SourceId_009 +; DesignId : MPU_DesignId_009 +; Requirements : HL_SR490 + + .def _mpuGetRegion_ + .asmfunc + +_mpuGetRegion_ + + mrc p15, #0, r0, c6, c2, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Set base address +; SourceId : MPU_SourceId_010 +; DesignId : MPU_DesignId_010 +; Requirements : HL_SR489 + + .def _mpuSetRegionBaseAddress_ + .asmfunc + +_mpuSetRegionBaseAddress_ + + mcr p15, #0, r0, c6, c1, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get base address +; SourceId : MPU_SourceId_011 +; DesignId : MPU_DesignId_011 +; Requirements : HL_SR490 + + .def _mpuGetRegionBaseAddress_ + .asmfunc + +_mpuGetRegionBaseAddress_ + + mrc p15, #0, r0, c6, c1, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Set type and permission +; SourceId : MPU_SourceId_012 +; DesignId : MPU_DesignId_012 +; Requirements : HL_SR489 + + .def _mpuSetRegionTypeAndPermission_ + .asmfunc + +_mpuSetRegionTypeAndPermission_ + + orr r0, r0, r1 + mcr p15, #0, r0, c6, c1, #4 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get type +; SourceId : MPU_SourceId_013 +; DesignId : MPU_DesignId_013 +; Requirements : HL_SR490 + + .def _mpuGetRegionType_ + .asmfunc + +_mpuGetRegionType_ + + mrc p15, #0, r0, c6, c1, #4 + bic r0, r0, #0xFF00 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get permission +; SourceId : MPU_SourceId_014 +; DesignId : MPU_DesignId_014 +; Requirements : HL_SR490 + + .def _mpuGetRegionPermission_ + .asmfunc + +_mpuGetRegionPermission_ + + mrc p15, #0, r0, c6, c1, #4 + bic r0, r0, #0xFF + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Set region size register value +; SourceId : MPU_SourceId_015 +; DesignId : MPU_DesignId_015 +; Requirements : HL_SR489 + + .def _mpuSetRegionSizeRegister_ + .asmfunc + +_mpuSetRegionSizeRegister_ + + + mcr p15, #0, r0, c6, c1, #2 + bx lr + + .endasmfunc + + + +;------------------------------------------------------------------------------- + diff --git a/src/arch/rm46l8lp/halcogen/sys_pcr.c b/src/arch/rm46l8lp/halcogen/sys_pcr.c new file mode 100644 index 0000000..4da7d62 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_pcr.c @@ -0,0 +1,725 @@ +/** @file sys_pcr.c +* @brief PCR Driver Implementation File +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +#include "sys_pcr.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame) +* @brief Set the peripheral protection of the selected frame +* @param[in] peripheral_Frame - Peripheral frame to be protected +* +* This function sets the protection for the selected frame. +*/ +/* SourceId : PCR_SourceId_001 */ +/* DesignId : PCR_DesignId_001 */ +/* Requirements : HL_SR41 */ +void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame) +{ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + + uint32 chip_select_grp; + uint32 Quarant_selct; + + chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U); + Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U)); + + if (chip_select_grp >= 3U) + { + pcrREG->PPROTSET3 = Quarant_selct; + } + else if (chip_select_grp >= 2U) + { + pcrREG->PPROTSET2 = Quarant_selct; + } + else if (chip_select_grp >= 1U) + { + pcrREG->PPROTSET1 = Quarant_selct; + } + else + { + pcrREG->PPROTSET0 = Quarant_selct; + } + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +/** @fn void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame) +* @brief Clear the peripheral protection of the selected frame +* @param[in] peripheral_Frame - Peripheral frame to be out of protection +* +* This function clears the protection set for the selected frame. +*/ +/* SourceId : PCR_SourceId_002 */ +/* DesignId : PCR_DesignId_002 */ +/* Requirements : HL_SR42 */ +void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame) +{ + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + uint32 chip_select_grp; + uint32 Quarant_selct; + + chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U); + Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U)); + + if (chip_select_grp >= 3U) + { + pcrREG->PPROTCLR3 = Quarant_selct; + } + else if (chip_select_grp >= 2U) + { + pcrREG->PPROTCLR2 = Quarant_selct; + } + else if (chip_select_grp >= 1U) + { + pcrREG->PPROTCLR1 = Quarant_selct; + } + else + { + pcrREG->PPROTCLR0 = Quarant_selct; + } + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + +/** @fn void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame) +* @brief Take the selected peripheral to powerdown +* @param[in] peripheral_Frame - Peripheral frame to be taken to powerdown +* +* This function will set the selected peripheral frame to powerdown. +*/ +/* SourceId : PCR_SourceId_003 */ +/* DesignId : PCR_DesignId_003 */ +/* Requirements : HL_SR43 */ +void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame) +{ + +/* USER CODE BEGIN (8) */ +/* USER CODE END */ + + uint32 chip_select_grp; + uint32 Quarant_selct; + + chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U); + Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U)); + + if (chip_select_grp >= 3U) + { + pcrREG->PSPWRDWNSET3 = Quarant_selct; + } + else if (chip_select_grp >= 2U) + { + pcrREG->PSPWRDWNSET2 = Quarant_selct; + } + else if (chip_select_grp >= 1U) + { + pcrREG->PSPWRDWNSET1 = Quarant_selct; + } + else + { + pcrREG->PSPWRDWNSET0 = Quarant_selct; + } + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/** @fn void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame) +* @brief Bring the selected peripheral frame out of powerdown +* @param[in] peripheral_Frame - Peripheral frame to be taken out of powerdown +* +* This function will bring the selected peripheral frame out of powerdown. +*/ +/* SourceId : PCR_SourceId_004 */ +/* DesignId : PCR_DesignId_004 */ +/* Requirements : HL_SR44 */ +void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame) +{ + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ + + uint32 chip_select_grp; + uint32 Quarant_selct; + + chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U); + Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U)); + + if (chip_select_grp >= 3U) + { + pcrREG->PSPWRDWNCLR3 = Quarant_selct; + } + else if (chip_select_grp >= 2U) + { + pcrREG->PSPWRDWNCLR2 = Quarant_selct; + } + else if (chip_select_grp >= 1U) + { + pcrREG->PSPWRDWNCLR1 = Quarant_selct; + } + else + { + pcrREG->PSPWRDWNCLR0 = Quarant_selct; + } +/* USER CODE BEGIN (12) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + +/** @fn void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) +* @brief Set the peripheral memory protection of the selected frame +* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be protected +* +* This function sets the protection for the selected peripheral memory frame. +*/ +/* SourceId : PCR_SourceId_005 */ +/* DesignId : PCR_DesignId_017 */ +/* Requirements : HL_SR57 */ +void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) +{ + +/* USER CODE BEGIN (14) */ +/* USER CODE END */ + + uint32 chip_select_grp; + + chip_select_grp = (peripheral_Memory_Frame_CS >> 5U); + + if (chip_select_grp >= 1U) + { + pcrREG->PMPROTSET1 = (uint32)1U << (peripheral_Memory_Frame_CS & 0xFU); + } + else + { + pcrREG->PMPROTSET0 = (uint32)1U << peripheral_Memory_Frame_CS; + } + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + +/** @fn void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) +* @brief Clear the peripheral memory protection of the selected frame +* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be cleared from protection +* +* This function clears the protection set for the selected peripheral memory frame. +*/ +/* SourceId : PCR_SourceId_006 */ +/* DesignId : PCR_DesignId_018 */ +/* Requirements : HL_SR58 */ +void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) +{ + +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + uint32 chip_select_grp; + + chip_select_grp = (peripheral_Memory_Frame_CS >> 5U); + + if (chip_select_grp >= 1U) + { + pcrREG->PMPROTCLR1 = (uint32)1U << (peripheral_Memory_Frame_CS & 0xFU); + } + else + { + pcrREG->PMPROTCLR0 = (uint32)1U << peripheral_Memory_Frame_CS; + } + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ + +/** @fn void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) +* @brief Take the selected peripheral memory frame to powerdown +* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken to powerdown +* +* This function will set the selected peripheral memory frame to powerdown. +*/ +/* SourceId : PCR_SourceId_007 */ +/* DesignId : PCR_DesignId_019 */ +/* Requirements : HL_SR59 */ +void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) +{ + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ + + uint32 chip_select_grp; + + chip_select_grp = (peripheral_Memory_Frame_CS >> 5U); + + if (chip_select_grp >= 1U) + { + pcrREG->PCSPWRDWNSET0 = (uint32)1U << (peripheral_Memory_Frame_CS & 0xFU); + } + else + { + pcrREG->PCSPWRDWNSET1 = (uint32)1U << peripheral_Memory_Frame_CS; + } + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ + +/** @fn void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) +* @brief Bring the selected peripheral Memory frame out of powerdown +* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken out of powerdown +* +* This function will bring the selected peripheral memory frame out of powerdown. +*/ +/* SourceId : PCR_SourceId_008 */ +/* DesignId : PCR_DesignId_020 */ +/* Requirements : HL_SR60 */ +void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) +{ + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ + + uint32 chip_select_grp; + + chip_select_grp = (peripheral_Memory_Frame_CS >> 5U); + + if (chip_select_grp >= 1U) + { + pcrREG->PCSPWRDWNCLR0 = (uint32)1U << (peripheral_Memory_Frame_CS & 0xFU); + } + else + { + pcrREG->PCSPWRDWNCLR1 = (uint32)1U << peripheral_Memory_Frame_CS; + } + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + +/** @fn void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) +* @brief Set the peripheral protection of all the selected frames +* @param[in] peripheral_Quad_CS - All Peripheral frames to be protected +* +* This function sets the protection for all the selected frames. +*/ +/* SourceId : PCR_SourceId_009 */ +/* DesignId : PCR_DesignId_005 */ +/* Requirements : HL_SR45 */ +void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) +{ + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ + + pcrREG->PPROTSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; + pcrREG->PPROTSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; + pcrREG->PPROTSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; + pcrREG->PPROTSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + +/** @fn void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) +* @brief Clear the peripheral protection of all the selected frames +* @param[in] peripheral_Quad_CS - All Peripheral frames to be out of protection. +* +* This function clears the protection set for all the selected frame. +*/ +/* SourceId : PCR_SourceId_010 */ +/* DesignId : PCR_DesignId_006 */ +/* Requirements : HL_SR46 */ +void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) +{ + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + + pcrREG->PPROTCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; + pcrREG->PPROTCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; + pcrREG->PPROTCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; + pcrREG->PPROTCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + +/** @fn void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) +* @brief Take all the selected peripheral frame to powerdown +* @param[in] peripheral_Quad_CS - Peripheral frames to be taken to powerdown +* +* This function will set all the selected peripheral frame to powerdown. +*/ +/* SourceId : PCR_SourceId_011 */ +/* DesignId : PCR_DesignId_008 */ +/* Requirements : HL_SR48 */ +void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) +{ + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + + pcrREG->PSPWRDWNSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; + pcrREG->PSPWRDWNSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; + pcrREG->PSPWRDWNSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; + pcrREG->PSPWRDWNSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; + +/* USER CODE BEGIN (33) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (34) */ +/* USER CODE END */ + +/** @fn void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) +* @brief Bring all the selected peripheral frame out of powerdown +* @param[in] peripheral_Quad_CS - Peripheral frames to be taken out of powerdown +* +* This function will bring all the selected peripheral frame out of powerdown. +*/ +/* SourceId : PCR_SourceId_012 */ +/* DesignId : PCR_DesignId_009 */ +/* Requirements : HL_SR49 */ +void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) +{ + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ + + pcrREG->PSPWRDWNCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; + pcrREG->PSPWRDWNCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; + pcrREG->PSPWRDWNCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; + pcrREG->PSPWRDWNCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; + +/* USER CODE BEGIN (36) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (37) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) +* @brief Set the peripheral memory protection of all the selected frame +* @param[in] peripheral_Memory_CS - Peripheral memory frames to be protected +* +* This function sets the protection for all the selected peripheral memory frame. +*/ +/* SourceId : PCR_SourceId_013 */ +/* DesignId : PCR_DesignId_011 */ +/* Requirements : HL_SR51 */ +void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) +{ + +/* USER CODE BEGIN (38) */ +/* USER CODE END */ + + pcrREG->PMPROTSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; + pcrREG->PMPROTSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; + +/* USER CODE BEGIN (39) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (40) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) +* @brief Clear the peripheral memory protection of all the selected frame +* @param[in] peripheral_Memory_CS - Peripheral memory frames to be cleared from protection +* +* This function clears the protection set for all the selected peripheral memory frame. +*/ +/* SourceId : PCR_SourceId_014 */ +/* DesignId : PCR_DesignId_012 */ +/* Requirements : HL_SR52 */ +void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) +{ + +/* USER CODE BEGIN (41) */ +/* USER CODE END */ + + pcrREG->PMPROTCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; + pcrREG->PMPROTCLR1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; + +/* USER CODE BEGIN (42) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (43) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) +* @brief Take all the selected peripheral memory frame to powerdown +* @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken to powerdown +* +* This function will set all the selected peripheral memory frame to powerdown. +*/ +/* SourceId : PCR_SourceId_015 */ +/* DesignId : PCR_DesignId_014 */ +/* Requirements : HL_SR54 */ +void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) +{ + +/* USER CODE BEGIN (44) */ +/* USER CODE END */ + + pcrREG->PCSPWRDWNSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; + pcrREG->PCSPWRDWNSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; + +/* USER CODE BEGIN (45) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (46) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) +* @brief Bring all the selected peripheral Memory frame out of powerdown +* @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken out of powerdown +* +* This function will bring all the selected peripheral memory frame out of powerdown. +*/ +/* SourceId : PCR_SourceId_016 */ +/* DesignId : PCR_DesignId_015 */ +/* Requirements : HL_SR55 */ +void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) +{ + +/* USER CODE BEGIN (47) */ +/* USER CODE END */ + + pcrREG->PCSPWRDWNSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; + pcrREG->PCSPWRDWNCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; + +/* USER CODE BEGIN (48) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (49) */ +/* USER CODE END */ + +/** @fn void peripheral_Powerdown_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS) +* @brief Get the powerdown status of the peripheral frames. +* @param[out] peripheral_Quad_CS Peripheral frames power down status +* +* This function gets the powerdown status of the peripheral frames. +*/ +/* SourceId : PCR_SourceId_017 */ +/* DesignId : PCR_DesignId_010 */ +/* Requirements : HL_SR50 */ +void peripheral_Powerdown_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS) +{ + +/* USER CODE BEGIN (50) */ +/* USER CODE END */ + + peripheral_Quad_CS->Peripheral_Quad0_3_CS0_7 = pcrREG->PSPWRDWNSET0; + peripheral_Quad_CS->Peripheral_Quad4_7_CS8_15 = pcrREG->PSPWRDWNSET1; + peripheral_Quad_CS->Peripheral_Quad8_11_CS16_23 = pcrREG->PSPWRDWNSET2; + peripheral_Quad_CS->Peripheral_Quad12_15_CS24_31 = pcrREG->PSPWRDWNSET3; + +/* USER CODE BEGIN (51) */ +/* USER CODE END */ + +} + +/* USER CODE BEGIN (52) */ +/* USER CODE END */ + +/** @fn void peripheral_Protection_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS ) +* @brief Get the protection status of the peripheral frames +* @param[out] peripheral_Quad_CS Peripheral frames protection status +* +* This function gets the protection status of the peripheral frames. +*/ +/* SourceId : PCR_SourceId_018 */ +/* DesignId : PCR_DesignId_007 */ +/* Requirements : HL_SR47 */ +void peripheral_Protection_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS) +{ + +/* USER CODE BEGIN (53) */ +/* USER CODE END */ + + peripheral_Quad_CS->Peripheral_Quad0_3_CS0_7 = pcrREG->PPROTSET0; + peripheral_Quad_CS->Peripheral_Quad4_7_CS8_15 = pcrREG->PPROTSET1; + peripheral_Quad_CS->Peripheral_Quad8_11_CS16_23 = pcrREG->PPROTSET2; + peripheral_Quad_CS->Peripheral_Quad12_15_CS24_31 = pcrREG->PPROTSET3; + +/* USER CODE BEGIN (54) */ +/* USER CODE END */ + +} + +/* USER CODE BEGIN (55) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Protection_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS) +* @brief Get the protection set of all the peripheral Memory frame +* @param[out] peripheral_Memory_CS Peripheral memory frames protection status +* +* This function gets the protection status of all the peripheral Memory frame. +*/ +/* SourceId : PCR_SourceId_019 */ +/* DesignId : PCR_DesignId_013 */ +/* Requirements : HL_SR53 */ +void peripheral_Memory_Protection_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS) +{ + +/* USER CODE BEGIN (56) */ +/* USER CODE END */ + + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Hardware status bit read" */ + peripheral_Memory_CS->Peripheral_Mem_CS0_31 = pcrREG->PMPROTSET0; + peripheral_Memory_CS->Peripheral_Mem_CS32_63 = pcrREG->PMPROTSET1; + +/* USER CODE BEGIN (57) */ +/* USER CODE END */ + +} + +/* USER CODE BEGIN (58) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Powerdown_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS) +* @brief Get the powerdown status of all the peripheral Memory frame +* @param[out] peripheral_Memory_CS Peripheral memory frames powerdown status +* +* This function gets the powerdown status of all the peripheral Memory frame. +*/ +/* SourceId : PCR_SourceId_020 */ +/* DesignId : PCR_DesignId_016 */ +/* Requirements : HL_SR56 */ +void peripheral_Memory_Powerdown_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS) +{ + +/* USER CODE BEGIN (59) */ +/* USER CODE END */ + + peripheral_Memory_CS->Peripheral_Mem_CS0_31 = pcrREG->PCSPWRDWNSET0; + peripheral_Memory_CS->Peripheral_Mem_CS32_63 = pcrREG->PCSPWRDWNSET1; + +/* USER CODE BEGIN (60) */ +/* USER CODE END */ + +} + +/* USER CODE BEGIN (61) */ +/* USER CODE END */ + +/** @fn void pcrGetConfigValue(pcr_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : PCR_SourceId_021 */ +/* DesignId : PCR_DesignId_021 */ +/* Requirements : HL_SR61 */ +void pcrGetConfigValue(pcr_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + {/* Do not pass Initial value as parameter as there is no PCR initialization API */ + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_PMPROTSET0 = pcrREG->PMPROTSET0; + config_reg->CONFIG_PMPROTSET1 = pcrREG->PMPROTSET1; + config_reg->CONFIG_PPROTSET0 = pcrREG->PPROTSET0; + config_reg->CONFIG_PPROTSET1 = pcrREG->PPROTSET1; + config_reg->CONFIG_PPROTSET2 = pcrREG->PPROTSET2; + config_reg->CONFIG_PPROTSET3 = pcrREG->PPROTSET3; + config_reg->CONFIG_PCSPWRDWNSET0 = pcrREG->PCSPWRDWNSET0; + config_reg->CONFIG_PCSPWRDWNSET1 = pcrREG->PCSPWRDWNSET1; + config_reg->CONFIG_PSPWRDWNSET0 = pcrREG->PSPWRDWNSET0; + config_reg->CONFIG_PSPWRDWNSET1 = pcrREG->PSPWRDWNSET1; + config_reg->CONFIG_PSPWRDWNSET2 = pcrREG->PSPWRDWNSET2; + config_reg->CONFIG_PSPWRDWNSET3 = pcrREG->PSPWRDWNSET3; + } +} diff --git a/src/arch/rm46l8lp/halcogen/sys_phantom.c b/src/arch/rm46l8lp/halcogen/sys_phantom.c new file mode 100644 index 0000000..346ff30 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_phantom.c @@ -0,0 +1,67 @@ +/** @file sys_phantom.c +* @brief Phantom Interrupt Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - Phantom Interrupt Handler +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +#include "sys_common.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Phantom Interrupt Handler */ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#pragma CODE_STATE(phantomInterrupt, 32) +#pragma INTERRUPT(phantomInterrupt, IRQ) +#pragma WEAK(phantomInterrupt) + +void phantomInterrupt(void) +{ +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ diff --git a/src/arch/rm46l8lp/halcogen/sys_pmm.c b/src/arch/rm46l8lp/halcogen/sys_pmm.c new file mode 100644 index 0000000..35db7f4 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_pmm.c @@ -0,0 +1,434 @@ +/** @file sys_pmm.c +* @brief PCR Driver Implementation File +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +#include "sys_pmm.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void pmmInit(void) +* @brief Initializes the PMM Driver +* +* This function initializes the PMM module. +*/ +/* SourceId : PMM_SourceId_001 */ +/* DesignId : PMM_DesignId_001 */ +/* Requirements : HL_SR63 */ +void pmmInit(void) +{ + /*Disable clocks to all logic domains*/ + pmmREG->PDCLKDISREG = 0xFU; + /*Enable or disable clock to pmctrl_wakeup block and automatic clock wake up*/ + pmmREG->GLOBALCTRL1 = (uint32)((uint32)0U << 8U) | (uint32)0U; /*from GUI*/ + /*Power on the logic power domains*/ + pmmREG->LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE; + /*Power on the memory-only power domains*/ + pmmREG->MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE; + + /*wait till Logic Power Domain PD2 turns ON*/ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */ + while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD2] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U) + { + }/* Wait */ + /*wait till Logic Power Domain PD3 turns ON*/ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */ + while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD3] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U) + { + }/* Wait */ + /*wait till Logic Power Domain PD3 turns ON*/ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */ + while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD4] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U) + { + }/* Wait */ + /*wait till Logic Power Domain PD5 turns ON*/ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */ + while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD5] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U) + { + }/* Wait */ + + /*wait till Memory Only Power Domain RAM_PD1 turns ON*/ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */ + while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD1] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U) + { + }/* Wait */ + /*wait till Memory Only Power Domain RAM_PD2 turns ON*/ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */ + while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD2] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U) + { + }/* Wait */ + if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U) + { + /* Enable clocks for the selected logic domain */ + pmmREG->PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE; + } + +} + + +/** @fn void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD) +* @brief Turns on Logic Power Domain +* @param[in] logicPD - Power Domain to be turned on +* - PMM_LOGICPD2: Power domain PD2 will be turned on +* - PMM_LOGICPD3: Power domain PD3 will be turned on +* - PMM_LOGICPD4: Power domain PD4 will be turned on +* - PMM_LOGICPD5: Power domain PD5 will be turned on +* +* This function turns on the selected Logic Power Domain +* +*/ +/* SourceId : PMM_SourceId_002 */ +/* DesignId : PMM_DesignId_002 */ +/* Requirements : HL_SR67 */ +void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD) +{ + if (logicPD != PMM_LOGICPD1) + { + /* Power on the domain */ + if (logicPD == PMM_LOGICPD2) + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | 0x05000000U; + } + else if (logicPD == PMM_LOGICPD3) + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | 0x00050000U; + } + else if (logicPD == PMM_LOGICPD4) + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | 0x00000500U; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | 0x00000005U; + } + /* Wait until the power domain turns on */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */ + while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U) + { + }/* Wait */ + if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U) + { + /* Enable clocks to the power domain */ + pmmREG->PDCLKDISCLRREG = (uint32)1U << (uint32)logicPD; + } + } +} + +/** @fn void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD) +* @brief Turns on Memory Power Domain +* @param[in] memPD - Power Domain to be tured on +* - PMM_MEMPD1: Power domain RAM_PD1 will be turned on +* - PMM_MEMPD2: Power domain RAM_PD2 will be turned on +* - PMM_MEMPD3: Power domain RAM_PD3 will be turned on +* +* This function turns on the selected Memory Power Domain +* +*/ +/* SourceId : PMM_SourceId_003 */ +/* DesignId : PMM_DesignId_003 */ +/* Requirements : HL_SR66 */ +void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD) +{ + /* Power on the domain */ + if (memPD == PMM_MEMPD1) + { + pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | 0x05000000U; + } + else if (memPD == PMM_MEMPD2) + { + pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | 0x00050000U; + } + else + { + pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | 0x00000500U; + } + /*Wait until the power domain turns on*/ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */ + while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U) + { + }/* Wait */ +} + +/** @fn void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD) +* @brief Turns off Logic Power Domain +* @param[in] logicPD - Power Domain to be tured off +* - PMM_LOGICPD2: Power domain PD2 will be turned off +* - PMM_LOGICPD3: Power domain PD3 will be turned off +* - PMM_LOGICPD4: Power domain PD4 will be turned off +* - PMM_LOGICPD5: Power doamin PD5 will be turned off +* +* This function turns off the selected Logic Power Domain +* +*/ +/* SourceId : PMM_SourceId_004 */ +/* DesignId : PMM_DesignId_004 */ +/* Requirements : HL_SR67 */ +void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD) +{ + if (logicPD != PMM_LOGICPD1) + { + /* Disable all clocks to the power domain */ + pmmREG->PDCLKDISSETREG = (uint32)1U << (uint32)logicPD; + + /* Power down the domain */ + if (logicPD == PMM_LOGICPD2) + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue*/ + pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | 0x0A000000U; + } + else if (logicPD == PMM_LOGICPD3) + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | 0x000A0000U; + } + else if (logicPD == PMM_LOGICPD4) + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | 0x00000A00U; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | 0x0000000AU; + } + /* Wait until the power domain turns off */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */ + while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U) + { + }/* Wait */ + } +} + +/** @fn void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD) +* @brief Turns off Memory Power Domain +* @param[in] memPD - Power Domain to be tured off +* - PMM_MEMPD1: Power domain RAM_PD1 will be turned off +* - PMM_MEMPD2: Power domain RAM_PD2 will be turned off +* - PMM_MEMPD3: Power domain RAM_PD3 will be turned off +* +* This function turns off the selected Memory Power Domain +* +*/ +/* SourceId : PMM_SourceId_005 */ +/* DesignId : PMM_DesignId_005 */ +/* Requirements : HL_SR66 */ +void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD) +{ + /* Power down the domain */ + if (memPD == PMM_MEMPD1) + { + pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | 0x0A000000U; + } + else if (memPD == PMM_MEMPD2) + { + pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | 0x000A0000U; + } + else + { + pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | 0x00000A00U; + } + /*Wait until the power domain turns off*/ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Wait for hardware status bit" */ + while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_MEMPDPWRSTAT) != 0U) + { + }/* Wait */ +} + +/** @fn boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD) +* @brief Check if the power domain is active or not +* @param[in] logicPD - Power Domain to be be checked +* - PMM_LOGICPD2: Checks whether Power domain PD2 is active or not +* - PMM_LOGICPD3: Checks whether Power domain PD3 is active or not +* - PMM_LOGICPD4: Checks whether Power domain PD4 is active or not +* - PMM_LOGICPD5: Checks whether Power domain PD5 is active or not +* @return The function will return: +* - TRUE : When the selected power domain is in Active state. +* - FALSE: When the selected power domain is in OFF state. +* +* This function checks whether the selected power domain is active or not. +* +*/ +/* SourceId : PMM_SourceId_006 */ +/* DesignId : PMM_DesignId_006 */ +/* Requirements : HL_SR62 */ +boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD) +{ + boolean status; + if ((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U) + { + status = FALSE; + } + else + { + status = TRUE; + } + return status; +} + +/** @fn boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD) +* @brief Check if the power domain is active or not +* @param[in] memPD - Power Domain to be tured off +* - PMM_MEMPD1: Checks whether Power domain RAM_PD1 is active or not +* - PMM_MEMPD2: Checks whether Power domain RAM_PD2 is active or not +* - PMM_MEMPD3: Checks whether Power domain RAM_PD3 is active or not +* @return The function will return: +* - TRUE : When the selected power domain is in Active state. +* - FALSE: When the selected power domain is in OFF state. +* +* This function checks whether the selected power domain is active or not. +* +*/ +/* SourceId : PMM_SourceId_007 */ +/* DesignId : PMM_DesignId_007 */ +/* Requirements : HL_SR65 */ +boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD) +{ + boolean status; + if ((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U) + { + status = FALSE; + } + else + { + status = TRUE; + } + return status; +} + +/** @fn void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration register +* @param[in] *config_reg - pointer to the struct to which the initial or current value of the configuration registers need to be stored +* @param[in] type - whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg +*/ +/* SourceId : PMM_SourceId_008 */ +/* DesignId : PMM_DesignId_008 */ +/* Requirements : HL_SR64 */ +void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE; + config_reg->CONFIG_MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE; + config_reg->CONFIG_PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE; + config_reg->CONFIG_GLOBALCTRL1 = PMM_GLOBALCTRL1_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_LOGICPDPWRCTRL0 = pmmREG->LOGICPDPWRCTRL0; + config_reg->CONFIG_MEMPDPWRCTRL0 = pmmREG->MEMPDPWRCTRL0; + config_reg->CONFIG_PDCLKDISREG = pmmREG->PDCLKDISREG; + config_reg->CONFIG_GLOBALCTRL1 = pmmREG->GLOBALCTRL1; + } +} + +/** @fn void pmmSetMode(pmm_Mode_t mode) +* @brief Set PSCON Compare Block Mode +* @param[in] mode - PSCON Compare Block mode +* - LockStep : PSCON compare block is set to Lock-Step mode +* - SelfTest : PSCON compare block is set to Self-Test mode +* - ErrorForcing : PSCON compare block is set to Error-Forcing mode +* - SelfTestErrorForcing : PSCON compare block is set to Self-Test-Error-Forcing mode +* +* This function sets the PSCON Compare block to the selected mode +* +*/ +/* SourceId : PMM_SourceId_009 */ +/* DesignId : PMM_DesignId_009 */ +/* Requirements : HL_SR68 */ +void pmmSetMode(pmm_Mode_t mode) +{ + /* Set PSCON Compare Block Mode */ + pmmREG->PRCKEYREG = mode; +} + +/** @fn boolean pmmPerformSelfTest(void) +* @brief Perform self test and return the result +* +* @return The function will return +* - TRUE if PSCON compare block passed self-test +* - FALSE if PSCON compare block failed in self-test +* +* This function checks whether PSCON compare block passed the self-test or not. +* +*/ +/* SourceId : PMM_SourceId_010 */ +/* DesignId : PMM_DesignId_010 */ +/* Requirements : HL_SR72 */ +boolean pmmPerformSelfTest(void) +{ + boolean status = TRUE; + /*Enter self-test mode*/ + pmmREG->PRCKEYREG = (uint32)SelfTest; + /*Wait till self test is completed*/ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ((pmmREG->LPDDCSTAT1 & 0xFU) != 0xFU) + { + }/* Wait */ + + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ((pmmREG->MPDDCSTAT1 & 0x3U) != 0x3U) + { + }/* Wait */ + + /*Check whether self-test passed or not*/ + if ((pmmREG->LPDDCSTAT2 & 0xFU) != 0U) + { + status = FALSE; + } + if ((pmmREG->MPDDCSTAT2 & 0x7U) != 0U) + { + status = FALSE; + } + /*Enter lock-step mode*/ + pmmREG->PRCKEYREG = (uint32)LockStep; + + return status; +} + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ diff --git a/src/arch/rm46l8lp/halcogen/sys_pmu.asm b/src/arch/rm46l8lp/halcogen/sys_pmu.asm new file mode 100644 index 0000000..0f48047 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_pmu.asm @@ -0,0 +1,277 @@ +;------------------------------------------------------------------------------- +; sys_pmu.asm +; +; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +; +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; +; + + .text + .arm + + +;------------------------------------------------------------------------------- +; Initialize Pmu +; Note: It will reset all counters +; SourceId : PMU_SourceId_001 +; DesignId : PMU_DesignId_001 +; Requirements : HL_SR484 + + .def _pmuInit_ + .asmfunc + +_pmuInit_ + + ; set control register + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #(1 << 4) + 6 + 1 + mcr p15, #0, r0, c9, c12, #0 + ; clear flags + mov r0, #0 + sub r0, r0, #1 + mcr p15, #0, r0, c9, c12, #3 + ; select counter 0 event + mov r0, #0 + mcr p15, #0, r0, c9, c12, #5 ; select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 ; select event + ; select counter 1 event + mov r0, #1 + mcr p15, #0, r0, c9, c12, #5 ; select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 ; select event + ; select counter 2 event + mov r0, #2 + mcr p15, #0, r0, c9, c12, #5 ; select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 ; select event + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Enable Counters Global [Cycle, Event [0..2]] +; Note: It will reset all counters +; SourceId : PMU_SourceId_002 +; DesignId : PMU_DesignId_002 +; Requirements : HL_SR485 + + .def _pmuEnableCountersGlobal_ + .asmfunc + +_pmuEnableCountersGlobal_ + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #7 + mcr p15, #0, r0, c9, c12, #0 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Disable Counters Global [Cycle, Event [0..2]] +; SourceId : PMU_SourceId_003 +; DesignId : PMU_DesignId_003 +; Requirements : HL_SR485 + + .def _pmuDisableCountersGlobal_ + .asmfunc + +_pmuDisableCountersGlobal_ + + mrc p15, #0, r0, c9, c12, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c9, c12, #0 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Reset Cycle Counter +; SourceId : PMU_SourceId_004 +; DesignId : PMU_DesignId_004 +; Requirements : HL_SR485 + + .def _pmuResetCycleCounter_ + .asmfunc + +_pmuResetCycleCounter_ + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #4 + mcr p15, #0, r0, c9, c12, #0 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Reset Event Counters [0..2] +; SourceId : PMU_SourceId_005 +; DesignId : PMU_DesignId_005 +; Requirements : HL_SR485 + + .def _pmuResetEventCounters_ + .asmfunc + +_pmuResetEventCounters_ + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #2 + mcr p15, #0, r0, c9, c12, #0 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Reset Cycle Counter abd Event Counters [0..2] +; SourceId : PMU_SourceId_006 +; DesignId : PMU_DesignId_006 +; Requirements : HL_SR485 + + .def _pmuResetCounters_ + .asmfunc + +_pmuResetCounters_ + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #6 + mcr p15, #0, r0, c9, c12, #0 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Start Counters [Cycle, 0..2] +; SourceId : PMU_SourceId_007 +; DesignId : PMU_DesignId_007 +; Requirements : HL_SR485 + + .def _pmuStartCounters_ + .asmfunc + +_pmuStartCounters_ + + mcr p15, #0, r0, c9, c12, #1 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Stop Counters [Cycle, 0..2] +; SourceId : PMU_SourceId_008 +; DesignId : PMU_DesignId_008 +; Requirements : HL_SR485 + + .def _pmuStopCounters_ + .asmfunc + +_pmuStopCounters_ + + mcr p15, #0, r0, c9, c12, #2 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Set Count event +; SourceId : PMU_SourceId_009 +; DesignId : PMU_DesignId_009 +; Requirements : HL_SR485 + + .def _pmuSetCountEvent_ + .asmfunc + +_pmuSetCountEvent_ + + mcr p15, #0, r0, c9, c12, #5 ; select counter + mcr p15, #0, r1, c9, c13, #1 ; select event + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Get Cycle Count +; SourceId : PMU_SourceId_010 +; DesignId : PMU_DesignId_010 +; Requirements : HL_SR486 + + .def _pmuGetCycleCount_ + .asmfunc + +_pmuGetCycleCount_ + + mrc p15, #0, r0, c9, c13, #0 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Get Event Counter Count Value +; SourceId : PMU_SourceId_011 +; DesignId : PMU_DesignId_011 +; Requirements : HL_SR486 + + .def _pmuGetEventCount_ + .asmfunc + +_pmuGetEventCount_ + + mcr p15, #0, r0, c9, c12, #5 ; select counter + mrc p15, #0, r0, c9, c13, #2 ; read event counter + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Get Overflow Flags +; SourceId : PMU_SourceId_012 +; DesignId : PMU_DesignId_012 +; Requirements : HL_SR486 + + .def _pmuGetOverflow_ + .asmfunc + +_pmuGetOverflow_ + + mrc p15, #0, r0, c9, c12, #3 ; read overflow + mov r1, #0 + sub r1, r1, #1 + mcr p15, #0, r1, c9, c12, #3 ; clear flags + bx lr + + .endasmfunc + + + +;------------------------------------------------------------------------------- + diff --git a/src/arch/rm46l8lp/halcogen/sys_selftest.c b/src/arch/rm46l8lp/halcogen/sys_selftest.c new file mode 100644 index 0000000..d72273e --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_selftest.c @@ -0,0 +1,2985 @@ +/** @file sys_selftest.c +* @brief Selftest Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - Selftest API's +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_selftest.h" +#include "sys_core.h" +#include "sys_pmu.h" + +/** @fn void selftestFailNotification(uint32 flag) +* @brief Self test fail service routine +* +* This function is called if there is a self test fail with appropriate flag +*/ +#pragma WEAK(selftestFailNotification) +void selftestFailNotification(uint32 flag) +{ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/** @fn void ccmSelfCheck(void) +* @brief CCM module self check Driver +* +* This function self checks the CCM module. +*/ +/* SourceId : SELFTEST_SourceId_001 */ +/* DesignId : SELFTEST_DesignId_001 */ +/* Requirements : HL_SR395 */ +void ccmSelfCheck(void) +{ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + + /* Run a diagnostic check on the CCM-R4F module */ + /* This step ensures that the CCM-R4F can actually indicate an error */ + + /* Configure CCM in self-test mode */ + CCMKEYR = 0x6U; + /* Wait for CCM self-test to complete */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ((CCMSR & 0x100U) != 0x100U) + { + }/* Wait */ + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + + /* Check if there was an error during the self-test */ + if ((CCMSR & 0x1U) == 0x1U) + { + /* STE is set */ + selftestFailNotification(CCMSELFCHECK_FAIL1); + } + else + { + /* Check CCM-R4 self-test error flag by itself (without compare error) */ + if ((esmREG->SR1[0U] & 0x80000000U) == 0x80000000U) + { + /* ESM flag is not set */ + selftestFailNotification(CCMSELFCHECK_FAIL2); + } + else + { + /* Configure CCM in error-forcing mode */ + CCMKEYR = 0x9U; + + /* Wait till error-forcing is completed. */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while (CCMKEYR != 0U) + { + }/* Wait */ + + /* check if compare error flag is set */ + if ((esmREG->SR1[1U] & 0x4U) != 0x4U) + { + /* ESM flag is not set */ + selftestFailNotification(CCMSELFCHECK_FAIL3); + } + else + { + /* Check FIQIVEC to ESM High Interrupt flag is set */ + if((vimREG->FIQINDEX & 0x000000FFU) != 1U) + { + /* ESM High Interrupt flag is not set in VIM*/ + selftestFailNotification(CCMSELFCHECK_FAIL4); + } + + /* clear ESM group2 channel 2 flag */ + esmREG->SR1[1U] = 0x4U; + + /* clear ESM group2 shadow status flag */ + esmREG->SSR2 = 0x4U; + + /* ESM self-test error needs to also be cleared */ + esmREG->SR1[0U] = 0x80000000U; + + /* The nERROR pin will become inactive once the LTC counter expires */ + esmREG->EKR = 0x5U; + + /* Configure CCM in selftest error-forcing mode */ + CCMKEYR = 0xFU; + + /* Wait till selftest error-forcing is completed. */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while (CCMKEYR != 0U) + { + }/* Wait */ + + if((esmREG->SR1[0U] & 0x80000000U) != 0x80000000U) + { + /* ESM flag not set */ + selftestFailNotification(CCMSELFCHECK_FAIL2); + } + else + { + /* clear ESM flag */ + esmREG->SR1[0U] = 0x80000000U; + } + } + } + } +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + +/** @fn void memoryInit(uint32 ram) +* @brief Memory Initialization Driver +* +* This function is called to perform Memory initialization of selected RAM's. +*/ +/* SourceId : SELFTEST_SourceId_002 */ +/* DesignId : SELFTEST_DesignId_004 */ +/* Requirements : HL_SR396 */ +void memoryInit(uint32 ram) +{ +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + /* Enable Memory Hardware Initialization */ + systemREG1->MINITGCR = 0xAU; + + /* Enable Memory Hardware Initialization for selected RAM's */ + systemREG1->MSINENA = ram; + + /* Wait until Memory Hardware Initialization complete */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((systemREG1->MSTCGSTAT & 0x00000100U) != 0x00000100U) + { + }/* Wait */ + + /* Disable Memory Hardware Initialization */ + systemREG1->MINITGCR = 0x5U; + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ +} + +/** @fn void stcSelfCheck(void) +* @brief STC module self check Driver +* +* This function is called to perform STC module self check. +*/ +/* SourceId : SELFTEST_SourceId_003 */ +/* DesignId : SELFTEST_DesignId_002 */ +/* Requirements : HL_SR397 */ +void stcSelfCheck(void) +{ +/* USER CODE BEGIN (8) */ +/* USER CODE END */ + volatile uint32 i = 0U; + + /* Run a diagnostic check on the CPU self-test controller */ + /* First set up the STC clock divider as STC is only supported up to 90MHz */ + + /* STC clock is now normal mode CPU clock frequency/2 = 180MHz/2 */ + systemREG2->STCCLKDIV = 0x01000000U; + + /* Select one test interval, restart self-test next time, 0x00010001 */ + stcREG->STCGCR0 = 0x00010001U; + + /* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */ + stcREG->STCSCSCR = 0x1AU; + + /* Maximum time-out period */ + stcREG->STCTPR = 0xFFFFFFFFU; + + /* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ } + + /* Enable self-test */ + stcREG->STCGCR1 = 0xAU; + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + /* Idle the CPU so that the self-test can start */ + _gotoCPUIdle_(); + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ +} + +/** @fn void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test) +* @brief CPU self test Driver +* @param[in] no_of_intervals - Number of Test Intervals to be +* @param[in] max_timeout - Maximum Timeout to complete selected test Intervals +* @param[in] restart_test - Restart the test from Interval 0 or Continue from where it stopped. +* +* This function is called to perform CPU self test using STC module. +*/ +/* SourceId : SELFTEST_SourceId_004 */ +/* DesignId : SELFTEST_DesignId_003 */ +/* Requirements : HL_SR398 */ +void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test) +{ + volatile uint32 i = 0U; + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ + + /* Run specified no of test intervals starting from interval 0 */ + /* Start test from interval 0 or continue the test. */ + stcREG->STCGCR0 = no_of_intervals << 16U; + if(restart_test) + { + stcREG->STCGCR0 |= 0x00000001U; + } + + /* Configure Maximum time-out period */ + stcREG->STCTPR = max_timeout; + + /* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ } + + /* Enable self-test */ + stcREG->STCGCR1 = 0xAU; + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + /* Idle the CPU so that the self-test can start */ + + _gotoCPUIdle_(); + +} + +/** @fn void pbistSelfCheck(void) +* @brief PBIST self test Driver +* +* This function is called to perform PBIST self test. +* +* @note This Function uses register's which are not exposed to users through +* TRM , to run custom algorithm to make PBIST Fail. Users can use this function as Black box. +* +*/ +/* SourceId : SELFTEST_SourceId_005 */ +/* DesignId : SELFTEST_DesignId_005 */ +/* Requirements : HL_SR399 */ +void pbistSelfCheck(void) +{ + volatile uint32 i = 0U; + uint32 PBIST_wait_done_loop = 0U; +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + /* Run a diagnostic check on the memory self-test controller */ + /* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */ + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* PBIST ROM clock frequency = HCLK frequency /2 */ + /* Disable memory self controller */ + systemREG1->MSTGCR = 0x00000105U; + + /* Disable Memory Initialization controller */ + systemREG1->MINITGCR = 0x5U; + + /* Enable memory self controller */ + systemREG1->MSTGCR = 0x0000010AU; + + /* Clear PBIST Done */ + systemREG1->MSTCGSTAT = 0x1U; + + /* Enable PBIST controller */ + systemREG1->MSINENA = 0x1U; + + /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ } + +/* USER CODE BEGIN (14) */ +/* USER CODE END */ + + /* Enable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x3U; + + /* CPU control of PBIST */ + pbistREG->DLR = 0x10U; + + /* Custom always fail algo, this will not use the ROM and just set a fail */ + pbistREG->RAMT = 0x00002000U; + *(volatile uint32 *)0xFFFFE400U = 0x4C000001U; + *(volatile uint32 *)0xFFFFE440U = 0x00000075U; + *(volatile uint32 *)0xFFFFE404U = 0x4C000002U; + *(volatile uint32 *)0xFFFFE444U = 0x00000075U; + *(volatile uint32 *)0xFFFFE408U = 0x4C000003U; + *(volatile uint32 *)0xFFFFE448U = 0x00000075U; + *(volatile uint32 *)0xFFFFE40CU = 0x4C000004U; + *(volatile uint32 *)0xFFFFE44CU = 0x00000075U; + *(volatile uint32 *)0xFFFFE410U = 0x4C000005U; + *(volatile uint32 *)0xFFFFE450U = 0x00000075U; + *(volatile uint32 *)0xFFFFE414U = 0x4C000006U; + *(volatile uint32 *)0xFFFFE454U = 0x00000075U; + *(volatile uint32 *)0xFFFFE418U = 0x00000000U; + *(volatile uint32 *)0xFFFFE458U = 0x00000001U; + + /* PBIST_RUN */ + pbistREG->rsvd1[1U] = 1U; + + /* wait until memory self-test done is indicated */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ((systemREG1->MSTCGSTAT & 0x1U) != 0x1U) + { + PBIST_wait_done_loop++; + }/* Wait */ + + /* Check for the failure */ + if ((pbistREG->FSRF0 & 0x1U) != 0x1U) + { + /* No failure was indicated even if the always fail algorithm was run*/ + selftestFailNotification(PBISTSELFCHECK_FAIL1); + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + } + else + { + /* Check that the algorithm executed in the expected amount of time. */ + /* This time is dependent on the ROMCLKDIV selected above */ + if (PBIST_wait_done_loop >= 2U) + { + selftestFailNotification(PBISTSELFCHECK_FAIL2); + } + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* Disable PBIST */ + systemREG1->MSTGCR &= 0xFFFFFFF0U; + systemREG1->MSTGCR |= 0x5U; + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + } +} + +/** @fn void pbistRun(uint32 raminfoL, uint32 algomask) +* @brief CPU self test Driver +* @param[in] raminfoL - Select the list of RAM to be tested. +* @param[in] algomask - Select the list of Algorithm to be run. +* +* This function performs Memory Built-in Self test using PBIST module. +*/ +/* SourceId : SELFTEST_SourceId_006 */ +/* DesignId : SELFTEST_DesignId_006 */ +/* Requirements : HL_SR400 */ +void pbistRun(uint32 raminfoL, uint32 algomask) +{ + volatile uint32 i = 0U; + +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + /* PBIST ROM clock frequency = HCLK frequency /2 */ + /* Disable memory self controller */ + systemREG1->MSTGCR = 0x00000105U; + + /* Disable Memory Initialization controller */ + systemREG1->MINITGCR = 0x5U; + + /* Enable PBIST controller */ + systemREG1->MSINENA = 0x1U; + + /* Enable memory self controller */ + systemREG1->MSTGCR = 0x0000010AU; + + /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ } + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + + /* Enable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x3U; + + /* Select all algorithms to be tested */ + pbistREG->ALGO = algomask; + + /* Select RAM groups */ + pbistREG->RINFOL = raminfoL; + + /* Select all RAM groups */ + pbistREG->RINFOU = 0x00000000U; + + /* ROM contents will not override RINFOx settings */ + pbistREG->OVER = 0x0U; + + /* Algorithm code is loaded from ROM */ + pbistREG->ROM = 0x3U; + + /* Start PBIST */ + pbistREG->DLR = 0x14U; + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ +} + +/** @fn void pbistStop(void) +* @brief Routine to stop PBIST test enabled. +* +* This function is called to stop PBIST after test is performed. +*/ +/* SourceId : SELFTEST_SourceId_007 */ +/* DesignId : SELFTEST_DesignId_007 */ +/* Requirements : HL_SR523 */ +void pbistStop(void) +{ +/* USER CODE BEGIN (20) */ +/* USER CODE END */ + /* disable pbist clocks and ROM clock */ + pbistREG->PACT = 0x0U; + systemREG1->MSTGCR &= 0xFFFFFFF0U; + systemREG1->MSTGCR |= 0x5U; +/* USER CODE BEGIN (21) */ +/* USER CODE END */ +} + +/** @fn boolean pbistIsTestCompleted(void) +* @brief Checks to see if the PBIST test is completed. +* @return 1 if PBIST test completed, otherwise 0. +* +* Checks to see if the PBIST test is completed. +*/ +/* SourceId : SELFTEST_SourceId_008 */ +/* DesignId : SELFTEST_DesignId_008 */ +/* Requirements : HL_SR401 */ +boolean pbistIsTestCompleted(void) +{ +/* USER CODE BEGIN (22) */ +/* USER CODE END */ + + return ((systemREG1->MSTCGSTAT & 0x1U) != 0U); +/* USER CODE BEGIN (23) */ +/* USER CODE END */ +} + +/** @fn boolean pbistIsTestPassed(void) +* @brief Checks to see if the PBIST test is completed successfully. +* @return 1 if PBIST test passed, otherwise 0. +* +* Checks to see if the PBIST test is completed successfully. +*/ +/* SourceId : SELFTEST_SourceId_009 */ +/* DesignId : SELFTEST_DesignId_009 */ +/* Requirements : HL_SR401 */ +boolean pbistIsTestPassed(void) +{ +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + boolean status; + + if (pbistREG->FSRF0 == 0U) + { + status = TRUE; + } + else + { + status = FALSE; + } +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + return status; +} + +/** @fn boolean pbistPortTestStatus(uint32 port) +* @brief Checks to see if the PBIST Port test is completed successfully. +* @param[in] port - Select the port to get the status. +* @return 1 if PBIST Port test completed successfully, otherwise 0. +* +* Checks to see if the selected PBIST Port test is completed successfully. +*/ +/* SourceId : SELFTEST_SourceId_010 */ +/* DesignId : SELFTEST_DesignId_010 */ +/* Requirements : HL_SR401 */ +boolean pbistPortTestStatus(uint32 port) +{ + boolean status; +/* USER CODE BEGIN (26) */ +/* USER CODE END */ + + if(port == (uint32)PBIST_PORT0) + { + status = (pbistREG->FSRF0 == 0U); + } + else + { + /* Invalid Input */ + status = FALSE; + } + + return status; +} + +/** @fn uint32 efcCheck(void) +* @brief EFUSE module self check Driver +* @return Returns 0 if no error was detected during autoload and Stuck At Zero Test passed +* 1 if no error was detected during autoload but Stuck At Zero Test failed +* 2 if there was a single-bit error detected during autoload +* 3 if some other error occurred during autoload +* +* This function self checks the EFUSE module. +*/ +/* SourceId : SELFTEST_SourceId_011 */ +/* DesignId : SELFTEST_DesignId_012 */ +/* Requirements : HL_SR402 */ +uint32 efcCheck(void) +{ + uint32 efcStatus = 0U; + uint32 status; + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ + + /* read the EFC Error Status Register */ + efcStatus = efcREG->ERROR; + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + + if (efcStatus == 0x0U) + { + /* run stuck-at-zero test and check if it passed */ + if (efcStuckZeroTest()== TRUE) + { + /* start EFC ECC logic self-test */ + efcSelfTest(); + status = 0U; + } + else + { + /* EFC output is stuck-at-zero, device operation unreliable */ + selftestFailNotification(EFCCHECK_FAIL1); + status = 1U; + } + } + /* EFC Error Register is not zero */ + else + { + /* one-bit error detected during autoload */ + if (efcStatus == 0x15U) + { + /* start EFC ECC logic self-test */ + efcSelfTest(); + status = 2U; + } + else + { + /* Some other EFC error was detected */ + selftestFailNotification(EFCCHECK_FAIL1); + status = 3U; + } + } + return status; +} + +/** @fn boolean efcStuckZeroTest(void) +* @brief Checks to see if the EFUSE Stuck at zero test is completed successfully. +* @return 1 if EFUSE Stuck at zero test completed, otherwise 0. +* +* Checks to see if the EFUSE Stuck at zero test is completed successfully. +*/ +/* SourceId : SELFTEST_SourceId_012 */ +/* DesignId : SELFTEST_DesignId_014 */ +/* Requirements : HL_SR402 */ +boolean efcStuckZeroTest(void) +{ +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + + uint32 ESM_ESTATUS4, ESM_ESTATUS1; + + boolean result = FALSE; + uint32 error_checks = EFC_INSTRUCTION_INFO_EN | + EFC_INSTRUCTION_ERROR_EN | + EFC_AUTOLOAD_ERROR_EN | + EFC_SELF_TEST_ERROR_EN ; + + /* configure the output enable for auto load error , instruction info, + instruction error, and self test error using boundary register + and drive values one across all the errors */ + efcREG->BOUNDARY = ((uint32)OUTPUT_ENABLE | error_checks); + + /* Read from the pin register. This register holds the current values + of above errors. This value should be 0x5c00.If not at least one of + the above errors is stuck at 0. */ + if ((efcREG->PINS & 0x5C00U) == 0x5C00U) + { + ESM_ESTATUS4 = esmREG->SR4[0U]; + ESM_ESTATUS1 = esmREG->SR1[2U]; + /* check if the ESM group1 channel 41 is set and group3 channel 1 is set */ + if (((ESM_ESTATUS4 & 0x200U) == 0x200U) && ((ESM_ESTATUS1 & 0x2U) == 0x2U)) + { + /* stuck-at-zero test passed */ + result = TRUE; + } + } + + /* put the pins back low */ + efcREG->BOUNDARY = OUTPUT_ENABLE; + + /* clear group1 flag */ + esmREG->SR4[0U] = 0x200U; + + /* clear group3 flag */ + esmREG->SR1[2U] = 0x2U; + + /* The nERROR pin will become inactive once the LTC counter expires */ + esmREG->EKR = 0x5U; + + return result; +} + +/** @fn void efcSelfTest(void) +* @brief EFUSE module self check Driver +* +* This function self checks the EFSUE module. +*/ +/* SourceId : SELFTEST_SourceId_013 */ +/* DesignId : SELFTEST_DesignId_013 */ +/* Requirements : HL_SR402 */ +void efcSelfTest(void) +{ +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + /* configure self-test cycles */ + efcREG->SELF_TEST_CYCLES = 0x258U; + + /* configure self-test signature */ + efcREG->SELF_TEST_SIGN = 0x5362F97FU; + + /* configure boundary register to start ECC self-test */ + efcREG->BOUNDARY = 0x0000200FU; +} + +/** @fn boolean checkefcSelfTest(void) +* @brief EFUSE module self check Driver +* @return Returns TRUE if EFC Selftest was a PASS, else FALSE +* +* This function returns the status of efcSelfTest. +* Note: This function can be called only after calling efcSelfTest +*/ +/* SourceId : SELFTEST_SourceId_014 */ +/* DesignId : SELFTEST_DesignId_015 */ +/* Requirements : HL_SR403 */ +boolean checkefcSelfTest(void) +{ +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + boolean result = FALSE; + + uint32 EFC_PINS, EFC_ERROR; + uint32 esmCh40Stat, esmCh41Stat = 0U; + + /* wait until EFC self-test is done */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((efcREG->PINS & EFC_SELF_TEST_DONE) == 0U) + { + }/* Wait */ + + /* check if EFC self-test error occurred */ + EFC_PINS = efcREG->PINS; + EFC_ERROR = efcREG->ERROR; + if(((EFC_PINS & EFC_SELF_TEST_ERROR) == 0U) && ((EFC_ERROR & 0x1FU) == 0U)) + { + /* check if EFC self-test error is set */ + esmCh40Stat = esmREG->SR4[0U] & 0x100U; + esmCh41Stat = esmREG->SR4[0U] & 0x200U; + if ((esmCh40Stat == 0U) && (esmCh41Stat == 0U)) + { + result = TRUE; + } + } + return result; +} + +/** @fn void fmcBus2Check(void) +* @brief Self Check Flash Bus2 Interface +* +* This function self checks Flash Bus2 Interface +*/ +/* SourceId : SELFTEST_SourceId_015 */ +/* DesignId : SELFTEST_DesignId_016 */ +/* Requirements : HL_SR404, HL_SR405 */ +void fmcBus2Check(void) +{ +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + /* enable ECC logic inside FMC */ + flashWREG->FEDACCTRL1 = 0x000A060AU; + + if ((esmREG->SR1[0U] & 0x40U) == 0x40U) + { + /* a 1-bit error was detected during flash OTP read by flash module + run a self-check on ECC logic inside FMC */ + + /* clear ESM group1 channel 6 flag */ + esmREG->SR1[0U] = 0x40U; + + fmcECCcheck(); + } + + /* no 2-bit or 1-bit error detected during power-up */ + else + { + fmcECCcheck(); + } +/* USER CODE BEGIN (33) */ +/* USER CODE END */ +} + +/** @fn void fmcECCcheck(void) +* @brief Check Flash ECC Single Bit and multi Bit errors detection logic. +* +* This function Checks Flash ECC Single Bit and multi Bit errors detection logic. +*/ +/* SourceId : SELFTEST_SourceId_016 */ +/* DesignId : SELFTEST_DesignId_017 */ +/* Requirements : HL_SR404, HL_SR405 */ +void fmcECCcheck(void) +{ + volatile uint32 otpread; + volatile uint32 temp; + +/* USER CODE BEGIN (34) */ +/* USER CODE END */ + + /* read location with deliberate 1-bit error */ + otpread = flash1bitError; + if ((esmREG->SR1[0U] & 0x40U) == 0x40U) + { + /* 1-bit failure was indicated and corrected */ + flashWREG->FEDACSTATUS = 0x00010006U; + + /* clear ESM group1 channel 6 flag */ + esmREG->SR1[0U] = 0x40U; + + /* read location with deliberate 2-bit error */ + otpread = flash2bitError; + if ((esmREG->SR1[2U] & 0x80U) == 0x80U) + { + /* 2-bit failure was detected correctly */ + temp = flashWREG->FUNCERRADD; + flashWREG->FEDACSTATUS = 0x00020100U; + + /* clear ESM group3 channel 7 */ + esmREG->SR1[2U] = 0x80U; + + /* The nERROR pin will become inactive once the LTC counter expires */ + esmREG->EKR = 0x5U; + + } + else + { + /* ECC logic inside FMC cannot detect 2-bit error */ + selftestFailNotification(FMCECCCHECK_FAIL1); + } + } + else + { + /* ECC logic inside FMC cannot detect 1-bit error */ + selftestFailNotification(FMCECCCHECK_FAIL1); + } +/* USER CODE BEGIN (35) */ +/* USER CODE END */ +} + +/** @fn void checkB0RAMECC(void) +* @brief Check TCRAM1 ECC error detection logic. +* +* This function checks TCRAM1 ECC error detection logic. +*/ +/* SourceId : SELFTEST_SourceId_017 */ +/* DesignId : SELFTEST_DesignId_019 */ +/* Requirements : HL_SR408 */ +void checkB0RAMECC(void) +{ + volatile uint64 ramread = 0U; + volatile uint32 regread = 0U; + uint32 tcram1ErrStat, tcram2ErrStat = 0U; + + uint64 tcramA1_bk = tcramA1bit; + uint64 tcramA2_bk = tcramA2bit; + volatile uint32 i; +/* USER CODE BEGIN (36) */ +/* USER CODE END */ + + /* enable writes to ECC RAM, enable ECC error response */ + tcram1REG->RAMCTRL = 0x0005010AU; + tcram2REG->RAMCTRL = 0x0005010AU; + + /* the first 1-bit error will cause an error response */ + tcram1REG->RAMTHRESHOLD = 0x1U; + tcram2REG->RAMTHRESHOLD = 0x1U; + + /* allow SERR to be reported to ESM */ + tcram1REG->RAMINTCTRL = 0x1U; + tcram2REG->RAMINTCTRL = 0x1U; + + /* cause a 1-bit ECC error */ + _coreDisableRamEcc_(); + tcramA1bitError ^= 0x1U; + _coreEnableRamEcc_(); + + /* disable writes to ECC RAM */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* read from location with 1-bit ECC error */ + ramread = tcramA1bit; + + /* Check for error status */ + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x1U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x1U; + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */ + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */ + if((tcram1ErrStat == 0U) && (tcram2ErrStat == 0U)) + { + /* TCRAM module does not reflect 1-bit error reported by CPU */ + selftestFailNotification(CHECKB0RAMECC_FAIL1); + } + else + { + /* clear SERR flag */ + tcram1REG->RAMERRSTATUS = 0x1U; + tcram2REG->RAMERRSTATUS = 0x1U; + + /* clear status flags for ESM group1 channels 26 and 28 */ + esmREG->SR1[0U] = 0x14000000U; + } + + /* enable writes to ECC RAM, enable ECC error response */ + tcram1REG->RAMCTRL = 0x0005010AU; + tcram2REG->RAMCTRL = 0x0005010AU; + + /* cause a 2-bit ECC error */ + _coreDisableRamEcc_(); + tcramA2bitError ^= 0x3U; + _coreEnableRamEcc_(); + + /* read from location with 2-bit ECC error this will cause a data abort to be generated */ + ramread = tcramA2bit; + + /* delay before restoring the ram value */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + for(i=0U;i<10U;i++) + { + }/* Wait */ + + regread = tcram1REG->RAMUERRADDR; + regread = tcram2REG->RAMUERRADDR; + + /* disable writes to ECC RAM */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* Compute correct ECC */ + tcramA1bit = tcramA1_bk; + tcramA2bit = tcramA2_bk; + +/* USER CODE BEGIN (37) */ +/* USER CODE END */ +} + +/** @fn void checkB1RAMECC(void) +* @brief Check TCRAM2 ECC error detection logic. +* +* This function checks TCRAM2 ECC error detection logic. +*/ +/* SourceId : SELFTEST_SourceId_018 */ +/* DesignId : SELFTEST_DesignId_019 */ +/* Requirements : HL_SR408 */ +void checkB1RAMECC(void) +{ + volatile uint64 ramread = 0U; + volatile uint32 regread = 0U; + uint32 tcram1ErrStat, tcram2ErrStat = 0U; + + uint64 tcramB1_bk = tcramB1bit; + uint64 tcramB2_bk = tcramB2bit; + volatile uint32 i; +/* USER CODE BEGIN (38) */ +/* USER CODE END */ + + /* enable writes to ECC RAM, enable ECC error response */ + tcram1REG->RAMCTRL = 0x0005010AU; + tcram2REG->RAMCTRL = 0x0005010AU; + + /* the first 1-bit error will cause an error response */ + tcram1REG->RAMTHRESHOLD = 0x1U; + tcram2REG->RAMTHRESHOLD = 0x1U; + + /* allow SERR to be reported to ESM */ + tcram1REG->RAMINTCTRL = 0x1U; + tcram2REG->RAMINTCTRL = 0x1U; + + /* cause a 1-bit ECC error */ + _coreDisableRamEcc_(); + tcramB1bitError ^= 0x1U; + _coreEnableRamEcc_(); + + /* disable writes to ECC RAM */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* read from location with 1-bit ECC error */ + ramread = tcramB1bit; + + /* Check for error status */ + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x1U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x1U; + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */ + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */ + if((tcram1ErrStat == 0U) && (tcram2ErrStat == 0U)) + { + /* TCRAM module does not reflect 1-bit error reported by CPU */ + selftestFailNotification(CHECKB1RAMECC_FAIL1); + } + else + { + /* clear SERR flag */ + tcram1REG->RAMERRSTATUS = 0x1U; + tcram2REG->RAMERRSTATUS = 0x1U; + + /* clear status flags for ESM group1 channels 26 and 28 */ + esmREG->SR1[0U] = 0x14000000U; + } + + /* enable writes to ECC RAM, enable ECC error response */ + tcram1REG->RAMCTRL = 0x0005010AU; + tcram2REG->RAMCTRL = 0x0005010AU; + + /* cause a 2-bit ECC error */ + _coreDisableRamEcc_(); + tcramB2bitError ^= 0x3U; + _coreEnableRamEcc_(); + + /* read from location with 2-bit ECC error this will cause a data abort to be generated */ + ramread = tcramB2bit; + + /* delay before restoring the ram value */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + for(i=0U;i<10U;i++) + { + }/* Wait */ + + regread = tcram1REG->RAMUERRADDR; + regread = tcram2REG->RAMUERRADDR; + + /* disable writes to ECC RAM */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* Compute correct ECC */ + tcramB1bit = tcramB1_bk; + tcramB2bit = tcramB2_bk; + +/* USER CODE BEGIN (39) */ +/* USER CODE END */ +} + +/** @fn void checkFlashECC(void) +* @brief Check Flash ECC error detection logic. +* +* This function checks Flash ECC error detection logic. +*/ +/* SourceId : SELFTEST_SourceId_019 */ +/* DesignId : SELFTEST_DesignId_020 */ +/* Requirements : HL_SR405 */ +void checkFlashECC(void) +{ + /* Routine to check operation of ECC logic inside CPU for accesses to program flash */ + volatile uint32 flashread = 0U; + +/* USER CODE BEGIN (40) */ +/* USER CODE END */ + + /* Flash Module ECC Response enabled */ + flashWREG->FEDACCTRL1 = 0x000A060AU; + + /* Enable diagnostic mode and select diag mode 7 */ + flashWREG->FDIAGCTRL = 0x00050007U; + + /* Select ECC diagnostic mode, single-bit to be corrupted */ + flashWREG->FPAROVR = 0x00005A01U; + + /* Set the trigger for the diagnostic mode */ + flashWREG->FDIAGCTRL |= 0x01000000U; + + /* read a flash location from the mirrored memory map */ + flashread = flashBadECC1; + + /* disable diagnostic mode */ + flashWREG->FDIAGCTRL = 0x000A0007U; + + /* this will have caused a single-bit error to be generated and corrected by CPU */ + /* single-bit error not captured in flash module */ + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + if ((flashWREG->FEDACSTATUS & 0x2U) == 0U) + { + selftestFailNotification(CHECKFLASHECC_FAIL1); + } + else + { + /* clear single-bit error flag */ + flashWREG->FEDACSTATUS = 0x2U; + + /* clear ESM flag */ + esmREG->SR1[0U] = 0x40U; + + /* Enable diagnostic mode and select diag mode 7 */ + flashWREG->FDIAGCTRL = 0x00050007U; + + /* Select ECC diagnostic mode, two bits of ECC to be corrupted */ + flashWREG->FPAROVR = 0x00005A03U; + + /* Set the trigger for the diagnostic mode */ + flashWREG->FDIAGCTRL |= 0x01000000U; + + /* read from flash location from mirrored memory map this will cause a data abort */ + flashread = flashBadECC2; + + /* Read FUNCERRADD register */ + flashread = flashWREG->FUNCERRADD; + + /* disable diagnostic mode */ + flashWREG->FDIAGCTRL = 0x000A0007U; + } + +/* USER CODE BEGIN (41) */ +/* USER CODE END */ +} + +/** @fn void custom_dabort(void) +* @brief Custom Data abort routine for the application. +* +* Custom Data abort routine for the application. +*/ +void custom_dabort(void) +{ + /* Need custom data abort handler here. + * This data abort is not caused due to diagnostic checks of flash and TCRAM ECC logic. + */ +/* USER CODE BEGIN (42) */ +/* USER CODE END */ +} + +/** @fn void stcSelfCheckFail(void) +* @brief STC Self test check fail service routine +* +* This function is called if STC Self test check fail. +*/ +void stcSelfCheckFail(void) +{ +/* USER CODE BEGIN (43) */ +/* USER CODE END */ + /* CPU self-test controller's own self-test failed. + * It is not possible to verify that STC is capable of indicating a CPU self-test error. + * It is not recommended to continue operation. + */ + + /* User can add small piece of code to take system to Safe state using user code section. + * Note: Just removing the for(;;) will take the system to unknown state under ST failure, + * since it is not handled by HALCoGen driver */ +/* USER CODE BEGIN (44) */ +/* USER CODE END */ + /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ + /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ + for(;;) + { + }/* Wait */ +/* USER CODE BEGIN (45) */ +/* USER CODE END */ +} + +/** @fn void cpuSelfTestFail(void) +* @brief CPU Self test check fail service routine +* +* This function is called if CPU Self test check fail. +*/ +void cpuSelfTestFail(void) +{ +/* USER CODE BEGIN (46) */ +/* USER CODE END */ + /* CPU self-test has failed. + * CPU operation is not reliable. + */ +/* USER CODE BEGIN (47) */ +/* USER CODE END */ + /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ + /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ + for(;;) + { + }/* Wait */ +/* USER CODE BEGIN (48) */ +/* USER CODE END */ +} + + +/** @fn void vimParityCheck(void) +* @brief Routine to check VIM RAM parity error detection and signaling mechanism +* +* Routine to check VIM RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_020 */ +/* DesignId : SELFTEST_DesignId_021 */ +/* Requirements : HL_SR385 */ +void vimParityCheck(void) +{ + volatile uint32 vimramread = 0U; + uint32 vimparctl_bk = VIM_PARCTL; + +/* USER CODE BEGIN (49) */ +/* USER CODE END */ + + /* Enable parity checking and parity test mode */ + VIM_PARCTL = 0x0000010AU; + + /* flip a bit in the VIM RAM parity location */ + VIMRAMPARLOC ^= 0x1U; + + /* disable parity test mode */ + VIM_PARCTL = 0x0000000AU; + + /* cause parity error */ + vimramread = VIMRAMLOC; + + /* check if ESM group1 channel 15 is flagged */ + if ((esmREG->SR1[0U] & 0x8000U) ==0U) + { + /* VIM RAM parity error was not flagged to ESM. */ + selftestFailNotification(VIMPARITYCHECK_FAIL1); + } + else + { + /* clear VIM RAM parity error flag in VIM */ + VIM_PARFLG = 0x1U; + + /* clear ESM group1 channel 15 flag */ + esmREG->SR1[0U] = 0x8000U; + + /* Enable parity checking and parity test mode */ + VIM_PARCTL = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + VIMRAMPARLOC ^= 0x1U; + } + + /* Restore Parity Control register */ + VIM_PARCTL = vimparctl_bk; + +/* USER CODE BEGIN (50) */ +/* USER CODE END */ +} + + +/** @fn void dmaParityCheck(void) +* @brief Routine to check DMA control packet RAM parity error detection and signaling mechanism +* +* Routine to check DMA control packet RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_021 */ +/* DesignId : SELFTEST_DesignId_022 */ +/* Requirements : HL_SR388 */ +void dmaParityCheck(void) +{ + volatile uint32 dmaread = 0U; + uint32 dmaparcr_bk = DMA_PARCR; + +/* USER CODE BEGIN (51) */ +/* USER CODE END */ + + /* Enable parity checking and parity test mode */ + DMA_PARCR = 0x0000010AU; + + /* Flip a bit in DMA RAM parity location */ + DMARAMPARLOC ^= 0x1U; + + /* Disable parity test mode */ + DMA_PARCR = 0x0000000AU; + + /* Cause parity error */ + dmaread = DMARAMLOC; + + /* Check if ESM group1 channel 3 is flagged */ + if ((esmREG->SR1[0U] & 0x8U) == 0U) + { + /* DMA RAM parity error was not flagged to ESM. */ + selftestFailNotification(DMAPARITYCHECK_FAIL1); + } + else + { + /* clear DMA parity error flag in DMA */ + DMA_PARADDR = 0x01000000U; + + /* clear ESM group1 channel 3 flag */ + esmREG->SR1[0U] = 0x8U; + + /* Enable parity checking and parity test mode */ + DMA_PARCR = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + DMARAMPARLOC ^= 0x1U; + } + + /* Restrore Parity Control register */ + DMA_PARCR = dmaparcr_bk; + +/* USER CODE BEGIN (52) */ +/* USER CODE END */ +} + + +/** @fn void het1ParityCheck(void) +* @brief Routine to check HET1 RAM parity error detection and signaling mechanism +* +* Routine to check HET1 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_022 */ +/* DesignId : SELFTEST_DesignId_024 */ +/* Requirements : HL_SR389 */ +void het1ParityCheck(void) +{ + volatile uint32 nhetread = 0U; + uint32 hetpcr_bk = hetREG1->PCR; + +/* USER CODE BEGIN (53) */ +/* USER CODE END */ + + /* Set TEST mode and enable parity checking */ + hetREG1->PCR = 0x0000010AU; + + /* flip parity bit */ + NHET1RAMPARLOC ^= 0x1U; + + /* Disable TEST mode */ + hetREG1->PCR = 0x0000000AU; + + /* read to cause parity error */ + nhetread = NHET1RAMLOC; + + /* check if ESM group1 channel 7 is flagged */ + if ((esmREG->SR1[0U] & 0x80U) ==0U) + { + /* NHET1 RAM parity error was not flagged to ESM. */ + selftestFailNotification(HET1PARITYCHECK_FAIL1); + } + else + { + /* clear ESM group1 channel 7 flag */ + esmREG->SR1[0U] = 0x80U; + + /* Set TEST mode and enable parity checking */ + hetREG1->PCR = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + NHET1RAMPARLOC ^= 0x1U; + } + + /* Restore Parity comtrol register */ + hetREG1->PCR = hetpcr_bk; + +/* USER CODE BEGIN (54) */ +/* USER CODE END */ +} + + +/** @fn void htu1ParityCheck(void) +* @brief Routine to check HTU1 RAM parity error detection and signaling mechanism +* +* Routine to check HTU1 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_023 */ +/* DesignId : SELFTEST_DesignId_025 */ +/* Requirements : HL_SR390 */ +void htu1ParityCheck(void) +{ + volatile uint32 hturead = 0U; + uint32 htupcr_bk = htuREG1->PCR; + +/* USER CODE BEGIN (55) */ +/* USER CODE END */ + + /* Enable parity and TEST mode */ + htuREG1->PCR = 0x0000010AU; + + /* flip parity bit */ + HTU1PARLOC ^= 0x1U; + + /* Disable parity RAM test mode */ + htuREG1->PCR = 0x0000000AU; + + /* read to cause parity error */ + hturead = HTU1RAMLOC; + + /* check if ESM group1 channel 8 is flagged */ + if ((esmREG->SR1[0U] & 0x100U) == 0U) + { + /* HTU1 RAM parity error was not flagged to ESM. */ + selftestFailNotification(HTU1PARITYCHECK_FAIL1); + } + else + { + /* Clear HTU parity error flag */ + htuREG1->PAR = 0x00010000U; + esmREG->SR1[0U] = 0x100U; + + /* Enable parity and TEST mode */ + htuREG1->PCR = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + HTU1PARLOC ^= 0x1U; + } + + /* Restore Parity control register */ + htuREG1->PCR = htupcr_bk; + +/* USER CODE BEGIN (56) */ +/* USER CODE END */ + +} + + +/** @fn void het2ParityCheck(void) +* @brief Routine to check HET2 RAM parity error detection and signaling mechanism +* +* Routine to check HET2 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_024 */ +/* DesignId : SELFTEST_DesignId_024 */ +/* Requirements : HL_SR389 */ +void het2ParityCheck(void) +{ + volatile uint32 nhetread = 0U; + uint32 hetpcr_bk = hetREG2->PCR; + uint32 esmCh7Stat, esmCh34Stat = 0U; + +/* USER CODE BEGIN (57) */ +/* USER CODE END */ + + /* Set TEST mode and enable parity checking */ + hetREG2->PCR = 0x0000010AU; + + /* flip parity bit */ + NHET2RAMPARLOC ^= 0x1U; + + /* Disable TEST mode */ + hetREG2->PCR = 0x0000000AU; + + /* read to cause parity error */ + nhetread = NHET2RAMLOC; + + /* check if ESM group1 channel 7 or 34 (If not reserved) is flagged */ + esmCh7Stat = esmREG->SR1[0U] & 0x80U; + esmCh34Stat = esmREG->SR4[0U] & 0x4U; + if ((esmCh7Stat == 0U) && (esmCh34Stat ==0U)) + { + /* NHET2 RAM parity error was not flagged to ESM. */ + selftestFailNotification(HET2PARITYCHECK_FAIL1); + } + else + { + /* clear ESM group1 channel 7 flag */ + esmREG->SR1[0U] = 0x80U; + + /* clear ESM group1 channel 34 flag */ + esmREG->SR4[0U] = 0x4U; + + /* Set TEST mode and enable parity checking */ + hetREG2->PCR = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + NHET2RAMPARLOC ^= 0x1U; + } + + /* Restore parity control register */ + hetREG2->PCR = hetpcr_bk; + +/* USER CODE BEGIN (58) */ +/* USER CODE END */ +} + + +/** @fn void htu2ParityCheck(void) +* @brief Routine to check HTU2 RAM parity error detection and signaling mechanism +* +* Routine to check HTU2 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_025 */ +/* DesignId : SELFTEST_DesignId_025 */ +/* Requirements : HL_SR390 */ +void htu2ParityCheck(void) +{ + volatile uint32 hturead = 0U; + uint32 htupcr_bk = htuREG2->PCR; + +/* USER CODE BEGIN (59) */ +/* USER CODE END */ + + /* Enable parity and TEST mode */ + htuREG2->PCR = 0x0000010AU; + + /* flip parity bit */ + HTU2PARLOC ^= 0x1U; + + /* Disable parity RAM test mode */ + htuREG2->PCR = 0x0000000AU; + + /* read to cause parity error */ + hturead = HTU2RAMLOC; + + /* check if ESM group1 channel 8 is flagged */ + if ((esmREG->SR1[0U] & 0x100U) == 0U) + { + /* HTU2 RAM parity error was not flagged to ESM. */ + selftestFailNotification(HTU2PARITYCHECK_FAIL1); + } + else + { + /* Clear HTU parity error flag */ + htuREG2->PAR = 0x00010000U; + esmREG->SR1[0U] = 0x100U; + + /* Enable parity and TEST mode */ + htuREG2->PCR = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + HTU2PARLOC ^= 0x1U; + } + + /* Restore parity control register*/ + htuREG2->PCR = htupcr_bk; + +/* USER CODE BEGIN (60) */ +/* USER CODE END */ +} + + +/** @fn void adc1ParityCheck(void) +* @brief Routine to check ADC1 RAM parity error detection and signaling mechanism +* +* Routine to check ADC1 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_026 */ +/* DesignId : SELFTEST_DesignId_023 */ +/* Requirements : HL_SR387 */ +void adc1ParityCheck(void) +{ + volatile uint32 adcramread = 0U; + uint32 adcparcr_bk = adcREG1->PARCR; + +/* USER CODE BEGIN (61) */ +/* USER CODE END */ + + /* Set the TEST bit in the PARCR and enable parity checking */ + adcREG1->PARCR = 0x10AU; + + /* Invert the parity bits inside the ADC1 RAM's first location */ + adcPARRAM1 = ~(adcPARRAM1); + + /* clear the TEST bit */ + adcREG1->PARCR = 0x00AU; + + /* This read is expected to trigger a parity error */ + adcramread = adcRAM1; + + /* Check for ESM group1 channel 19 to be flagged */ + if ((esmREG->SR1[0U] & 0x80000U) ==0U) + { + /* no ADC1 RAM parity error was flagged to ESM */ + selftestFailNotification(ADC1PARITYCHECK_FAIL1); + } + else + { + /* clear ADC1 RAM parity error flag */ + esmREG->SR1[0U] = 0x80000U; + + /* Set the TEST bit in the PARCR and enable parity checking */ + adcREG1->PARCR = 0x10AU; + + /* Revert back the parity bits to correct data */ + adcPARRAM1 = ~(adcPARRAM1); + } + + /* Restore parity control register */ + adcREG1->PARCR = adcparcr_bk; + +/* USER CODE BEGIN (62) */ +/* USER CODE END */ +} + + +/** @fn void adc2ParityCheck(void) +* @brief Routine to check ADC2 RAM parity error detection and signaling mechanism +* +* Routine to check ADC2 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_027 */ +/* DesignId : SELFTEST_DesignId_023 */ +/* Requirements : HL_SR387 */ +void adc2ParityCheck(void) +{ + volatile uint32 adcramread = 0U; + uint32 adcparcr_bk = adcREG2->PARCR; + +/* USER CODE BEGIN (63) */ +/* USER CODE END */ + + /* Set the TEST bit in the PARCR and enable parity checking */ + adcREG2->PARCR = 0x10AU; + + /* Invert the parity bits inside the ADC2 RAM's first location */ + adcPARRAM2 = ~(adcPARRAM2); + + /* clear the TEST bit */ + adcREG2->PARCR = 0x00AU; + + /* This read is expected to trigger a parity error */ + adcramread = adcRAM2; + + /* Check for ESM group1 channel 1 to be flagged */ + if ((esmREG->SR1[0U] & 0x2U) == 0U) + { + /* no ADC2 RAM parity error was flagged to ESM */ + selftestFailNotification(ADC2PARITYCHECK_FAIL1); + } + else + { + /* clear ADC2 RAM parity error flag */ + esmREG->SR1[0U] = 0x2U; + + /* Set the TEST bit in the PARCR and enable parity checking */ + adcREG2->PARCR = 0x10AU; + + /* Revert back the parity bits to correct data */ + adcPARRAM2 = ~(adcPARRAM2); + } + + /* Restore parity control register*/ + adcREG2->PARCR = adcparcr_bk; + +/* USER CODE BEGIN (64) */ +/* USER CODE END */ +} + +/** @fn void can1ParityCheck(void) +* @brief Routine to check CAN1 RAM parity error detection and signaling mechanism +* +* Routine to check CAN1 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_028 */ +/* DesignId : SELFTEST_DesignId_026 */ +/* Requirements : HL_SR393 */ +void can1ParityCheck(void) +{ + volatile uint32 canread = 0U; + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + uint32 canctl_bk = canREG1->CTL; + +/* USER CODE BEGIN (65) */ +/* USER CODE END */ + + /* Disable parity, init mode, TEST mode */ + canREG1->CTL = 0x00001481U; + + /* Enable RAM Direct Access mode */ + canREG1->TEST = 0x00000200U; + + /* flip the parity bit */ + canPARRAM1 ^= 0x00001000U; + + /* Enable parity, disable init, still TEST mode */ + canREG1->CTL = 0x00002880U; + + /* Read location with parity error */ + canread = canRAM1; + + /* check if ESM group1 channel 21 is flagged */ + if ((esmREG->SR1[0U] & 0x00200000U) == 0U) + { + /* No DCAN1 RAM parity error was flagged to ESM */ + selftestFailNotification(CAN1PARITYCHECK_FAIL1); + } + else + { + /* clear ESM group1 channel 21 flag */ + esmREG->SR1[0U] = 0x00200000U; + + /* Disable parity, init mode, TEST mode */ + canREG1->CTL = 0x00001481U; + + /* Revert back to correct data, flip bit 0 of the parity location */ + canPARRAM1 ^= 0x00001000U; + } + + /* Disable RAM Direct Access mode */ + canREG1->TEST = 0x00000000U; + + /* Restore CTL register */ + canREG1->CTL = canctl_bk; + + /* Read Error and Status register to clear Parity Error bit */ + canread = canREG1->ES; + +/* USER CODE BEGIN (66) */ +/* USER CODE END */ +} + + +/** @fn void can2ParityCheck(void) +* @brief Routine to check CAN2 RAM parity error detection and signaling mechanism +* +* Routine to check CAN2 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_029 */ +/* DesignId : SELFTEST_DesignId_026 */ +/* Requirements : HL_SR393 */ +void can2ParityCheck(void) +{ + volatile uint32 canread = 0U; + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + uint32 canctl_bk = canREG2->CTL; + +/* USER CODE BEGIN (67) */ +/* USER CODE END */ + + /* Disable parity, init mode, TEST mode */ + canREG2->CTL = 0x00001481U; + + /* Enable RAM Direct Access mode */ + canREG2->TEST = 0x00000200U; + + /* flip the parity bit */ + canPARRAM2 ^= 0x00001000U; + + /* Enable parity, disable init, still TEST mode */ + canREG2->CTL = 0x00002880U; + + /* Read location with parity error */ + canread = canRAM2; + + /* check if ESM group1 channel 23 is flagged */ + if ((esmREG->SR1[0U] & 0x00800000U) == 0U) + { + /* No DCAN2 RAM parity error was flagged to ESM */ + selftestFailNotification(CAN2PARITYCHECK_FAIL1); + } + else + { + /* clear ESM group1 channel 23 flag */ + esmREG->SR1[0U] = 0x00800000U; + + /* Disable parity, init mode, TEST mode */ + canREG2->CTL = 0x00001481U; + + /* Revert back to correct data, flip bit 0 of the parity location */ + canPARRAM2 ^= 0x00001000U; + } + + /* Disable RAM Direct Access mode */ + canREG2->TEST = 0x00000000U; + + /* disable TEST mode */ + canREG2->CTL = canctl_bk; + + /* Read Error and Status register to clear Parity Error bit */ + canread = canREG2->ES; + +/* USER CODE BEGIN (68) */ +/* USER CODE END */ +} + + +/** @fn void can3ParityCheck(void) +* @brief Routine to check CAN3 RAM parity error detection and signaling mechanism +* +* Routine to check CAN3 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_030 */ +/* DesignId : SELFTEST_DesignId_026 */ +/* Requirements : HL_SR393 */ +void can3ParityCheck(void) +{ + volatile uint32 canread = 0U; + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + uint32 canctl_bk = canREG3->CTL; + +/* USER CODE BEGIN (69) */ +/* USER CODE END */ + + /* Disable parity, init mode, TEST mode */ + canREG3->CTL = 0x00001481U; + + /* Enable RAM Direct Access mode */ + canREG3->TEST = 0x00000200U; + + /* flip the parity bit */ + canPARRAM3 ^= 0x00001000U; + + /* Enable parity, disable init, still TEST mode */ + canREG3->CTL = 0x00002880U; + + /* Read location with parity error */ + canread = canRAM3; + + /* check if ESM group1 channel 22 is flagged */ + if ((esmREG->SR1[0U] & 0x00400000U) == 0U) + { + /* No DCAN3 RAM parity error was flagged to ESM */ + selftestFailNotification(CAN3PARITYCHECK_FAIL1); + } + else + { + /* clear ESM group1 channel 22 flag */ + esmREG->SR1[0U] = 0x00400000U; + + /* Disable parity, init mode, TEST mode */ + canREG3->CTL = 0x00001481U; + + /* Revert back to correct data, flip bit 0 of the parity location */ + canPARRAM3 ^= 0x00001000U; + } + + /* Disable RAM Direct Access mode */ + canREG3->TEST = 0x00000000U; + + /* disable TEST mode */ + canREG3->CTL = canctl_bk; + + /* Read Error and Status register to clear Parity Error bit */ + canread = canREG3->ES; + +/* USER CODE BEGIN (70) */ +/* USER CODE END */ +} + + +/** @fn void mibspi1ParityCheck(void) +* @brief Routine to check MIBSPI1 RAM parity error detection and signaling mechanism +* +* Routine to check MIBSPI1 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_031 */ +/* DesignId : SELFTEST_DesignId_027 */ +/* Requirements : HL_SR386 */ +void mibspi1ParityCheck(void) +{ + volatile uint32 spiread = 0U; + uint32 mibspie_bk = mibspiREG1->MIBSPIE; + uint32 mibspictl_bk = mibspiREG1->UERRCTRL; + +/* USER CODE BEGIN (71) */ +/* USER CODE END */ + + /* enable multi-buffered mode */ + mibspiREG1->MIBSPIE = 0x1U; + + /* enable parity error detection */ + mibspiREG1->UERRCTRL = (mibspiREG1->UERRCTRL & 0xFFFFFFF0U) | (0xAU); + + /* enable parity test mode */ + mibspiREG1->UERRCTRL |= 0x00000100U; + + /* flip bit 0 of the parity location */ + mibspiPARRAM1 ^= 0x1U; + + /* disable parity test mode */ + mibspiREG1->UERRCTRL &= 0xFFFFFEFFU; + + /* read from MibSPI1 RAM to cause parity error */ + spiread = MIBSPI1RAMLOC; + + /* check if ESM group1 channel 17 is flagged */ + if ((esmREG->SR1[0U] & 0x20000U) == 0U) + { + /* No MibSPI1 RAM parity error was flagged to ESM. */ + selftestFailNotification(MIBSPI1PARITYCHECK_FAIL1); + } + else + { + /* clear parity error flags */ + mibspiREG1->UERRSTAT = 0x3U; + + /* clear ESM group1 channel 17 flag */ + esmREG->SR1[0U] = 0x20000U; + + /* enable parity test mode */ + mibspiREG1->UERRCTRL |= 0x00000100U; + + /* Revert back to correct data, flip bit 0 of the parity location */ + mibspiPARRAM1 ^= 0x1U; + } + + /* Restore MIBSPI control registers */ + mibspiREG1->UERRCTRL = mibspictl_bk; + mibspiREG1->MIBSPIE = mibspie_bk; + +/* USER CODE BEGIN (72) */ +/* USER CODE END */ +} + +/** @fn void mibspi3ParityCheck(void) +* @brief Routine to check MIBSPI3 RAM parity error detection and signaling mechanism +* +* Routine to check MIBSPI3 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_032 */ +/* DesignId : SELFTEST_DesignId_027 */ +/* Requirements : HL_SR386 */ +void mibspi3ParityCheck(void) +{ + volatile uint32 spiread = 0U; + uint32 mibspie_bk = mibspiREG3->MIBSPIE; + uint32 mibspictl_bk = mibspiREG3->UERRCTRL; + +/* USER CODE BEGIN (73) */ +/* USER CODE END */ + + /* enable multi-buffered mode */ + mibspiREG3->MIBSPIE = 0x1U; + + /* enable parity test mode */ + mibspiREG3->UERRCTRL |= 0x00000100U; + + /* flip bit 0 of the parity location */ + mibspiPARRAM3 ^= 0x1U; + + /* enable parity error detection */ + mibspiREG3->UERRCTRL = (mibspiREG3->UERRCTRL & 0xFFFFFFF0U) | (0xAU); + + /* disable parity test mode */ + mibspiREG3->UERRCTRL &= 0xFFFFFEFFU; + + /* read from MibSPI3 RAM to cause parity error */ + spiread = MIBSPI3RAMLOC; + + /* check if ESM group1 channel 18 is flagged */ + if ((esmREG->SR1[0U] & 0x40000U) == 0U) + { + /* No MibSPI3 RAM parity error was flagged to ESM. */ + selftestFailNotification(MIBSPI3PARITYCHECK_FAIL1); + } + else + { + /* clear parity error flags */ + mibspiREG3->UERRSTAT = 0x3U; + + /* clear ESM group1 channel 18 flag */ + esmREG->SR1[0U] = 0x40000U; + + /* enable parity test mode */ + mibspiREG3->UERRCTRL |= 0x00000100U; + + /* Revert back to correct data, flip bit 0 of the parity location */ + mibspiPARRAM3 ^= 0x1U; + } + + /* Restore MIBSPI control registers */ + mibspiREG3->UERRCTRL = mibspictl_bk; + mibspiREG3->MIBSPIE = mibspie_bk; + +/* USER CODE BEGIN (74) */ +/* USER CODE END */ +} + +/** @fn void mibspi5ParityCheck(void) +* @brief Routine to check MIBSPI5 RAM parity error detection and signaling mechanism +* +* Routine to check MIBSPI5 RAM parity error detection and signaling mechanism +*/ +/* SourceId : SELFTEST_SourceId_033 */ +/* DesignId : SELFTEST_DesignId_027 */ +/* Requirements : HL_SR386 */ +void mibspi5ParityCheck(void) +{ + volatile uint32 spiread = 0U; + uint32 mibspie_bk = mibspiREG5->MIBSPIE; + uint32 mibspictl_bk = mibspiREG5->UERRCTRL; + +/* USER CODE BEGIN (75) */ +/* USER CODE END */ + + /* enable multi-buffered mode */ + mibspiREG5->MIBSPIE = 0x1U; + + /* enable parity test mode */ + mibspiREG5->UERRCTRL |= 0x00000100U; + + /* flip bit 0 of the parity location */ + mibspiPARRAM5 ^= 0x1U; + + /* enable parity error detection */ + mibspiREG5->UERRCTRL = (mibspiREG5->UERRCTRL & 0xFFFFFFF0U) | (0xAU); + + /* disable parity test mode */ + mibspiREG5->UERRCTRL &= 0xFFFFFEFFU; + + /* read from MibSPI5 RAM to cause parity error */ + spiread = MIBSPI5RAMLOC; + + /* check if ESM group1 channel 24 is flagged */ + if ((esmREG->SR1[0U] & 0x01000000U) == 0U) + { + /* No MibSPI5 RAM parity error was flagged to ESM. */ + selftestFailNotification(MIBSPI5PARITYCHECK_FAIL1); + } + else + { + /* clear parity error flags */ + mibspiREG5->UERRSTAT = 0x3U; + + /* clear ESM group1 channel 24 flag */ + esmREG->SR1[0U] = 0x01000000U; + + /* enable parity test mode */ + mibspiREG5->UERRCTRL |= 0x00000100U; + + /* Revert back to correct data, flip bit 0 of the parity location */ + mibspiPARRAM5 ^= 0x1U; + } + + /* Restore MIBSPI control registers */ + mibspiREG5->UERRCTRL = mibspictl_bk; + mibspiREG5->MIBSPIE = mibspie_bk; + +/* USER CODE BEGIN (76) */ +/* USER CODE END */ +} + +/** @fn void checkRAMECC(void) +* @brief Check TCRAM ECC error detection logic. +* +* This function checks TCRAM ECC error detection logic. +*/ +/* SourceId : SELFTEST_SourceId_034 */ +/* DesignId : SELFTEST_DesignId_019 */ +/* Requirements : HL_SR408 */ +void checkRAMECC(void) +{ + volatile uint64 ramread = 0U; + volatile uint32 regread = 0U; + uint32 tcram1ErrStat, tcram2ErrStat = 0U; + + uint64 tcramA1_bk = tcramA1bit; + uint64 tcramB1_bk = tcramB1bit; + uint64 tcramA2_bk = tcramA2bit; + uint64 tcramB2_bk = tcramB2bit; + + /* Clear RAMOCUUR before setting RAMTHRESHOLD register */ + tcram1REG->RAMOCCUR = 0U; + tcram2REG->RAMOCCUR = 0U; + + /* Set Single-bit Error Threshold Count as 1 */ + tcram1REG->RAMTHRESHOLD = 1U; + tcram2REG->RAMTHRESHOLD = 1U; + + /* Enable single bit error generation */ + tcram1REG->RAMINTCTRL = 1U; + tcram2REG->RAMINTCTRL = 1U; + + /* Enable writes to ECC RAM, enable ECC error response */ + tcram1REG->RAMCTRL = 0x0005010AU; + tcram2REG->RAMCTRL = 0x0005010AU; + + /* Force a single bit error in both the banks */ + _coreDisableRamEcc_(); + tcramA1bitError ^= 1U; + tcramB1bitError ^= 1U; + _coreEnableRamEcc_(); + + /* Read the corrupted data to generate single bit error */ + ramread = tcramA1bit; + ramread = tcramB1bit; + + /* Check for error status */ + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x1U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x1U; + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */ + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */ + if((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U)) + { + /* TCRAM module does not reflect 1-bit error reported by CPU */ + selftestFailNotification(CHECKRAMECC_FAIL1); + } + else + { + if((esmREG->SR1[0U] & 0x14000000U) != 0x14000000U) + { + /* TCRAM 1-bit error not flagged in ESM */ + selftestFailNotification(CHECKRAMECC_FAIL2); + } + else + { + /* Clear single bit error flag in TCRAM module */ + tcram1REG->RAMERRSTATUS = 0x1U; + tcram2REG->RAMERRSTATUS = 0x1U; + + /* Clear ESM status */ + esmREG->SR1[0U] = 0x14000000U; + } + } + + /* Force a double bit error in both the banks */ + _coreDisableRamEcc_(); + tcramA2bitError ^= 3U; + tcramB2bitError ^= 3U; + _coreEnableRamEcc_(); + + /* Read the corrupted data to generate double bit error */ + ramread = tcramA2bit; + ramread = tcramB2bit; + + regread = tcram1REG->RAMUERRADDR; + regread = tcram2REG->RAMUERRADDR; + + /* disable writes to ECC RAM */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* Compute correct ECC */ + tcramA1bit = tcramA1_bk; + tcramB1bit = tcramB1_bk; + tcramA2bit = tcramA2_bk; + tcramB2bit = tcramB2_bk; +} + +/** @fn void checkClockMonitor(void) +* @brief Check clock monitor failure detection logic. +* +* This function checks clock monitor failure detection logic. +*/ +/* SourceId : SELFTEST_SourceId_035 */ +/* DesignId : SELFTEST_DesignId_028 */ +/* Requirements : HL_SR394 */ +void checkClockMonitor(void) +{ + uint32 ghvsrc_bk; + + /* Enable clock monitor range detection circuitry */ + systemREG1->CLKTEST |= 0x03000000U; + + /* Backup register GHVSRC */ + ghvsrc_bk = systemREG1->GHVSRC; + + /* Switch all clock domains to HF LPO */ + systemREG1->GHVSRC = 0x05050005U; + + /* Disable oscillator to cause a oscillator fail */ + systemREG1->CSDISSET = 0x1U; + + /* Wait till oscillator fail flag is set */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((systemREG1->GBLSTAT & 0x1U) == 0U) + { + } /* Wait */ + + if((esmREG->SR1[0U] & 0x800U) != 0x800U) + { + selftestFailNotification(CHECKCLOCKMONITOR_FAIL1); + } + else + { + /* Clear ESM flag */ + esmREG->SR1[0U] = 0x800U; + + /* Disable clock monitor range detection circuitry */ + systemREG1->CLKTEST &= ~(0x03000000U); + + /* Enable oscillator */ + systemREG1->CSDISCLR = 0x1U; + + /* Wait until oscillator is enabled */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((systemREG1->CSVSTAT & 0x3U) == 0U) + { + } /* Wait */ + + /* Clear oscillator fail flag and PLL slip flag if any*/ + systemREG1->GBLSTAT = 0x301U; + + /* Switch back all clock domains */ + systemREG1->GHVSRC = ghvsrc_bk; + } +} + +/** @fn void checkFlashEEPROMECC(void) +* @brief Check Flash EEPROM ECC error detection logic. +* +* This function checks Flash EEPROM ECC error detection logic. +*/ +/* SourceId : SELFTEST_SourceId_036 */ +/* DesignId : SELFTEST_DesignId_029 */ +/* Requirements : HL_SR406 */ +void checkFlashEEPROMECC(void) +{ + uint32 ecc; + volatile uint32 regread; + + /* Set Single Error Correction Threshold as 1 */ + flashWREG->EECTRL2 |= 1U; + + /* Enable EEPROM Emulation Error Profiling */ + flashWREG->EECTRL1 |= 0x00000100U; + + /* Load FEMU_XX regs in order to generate ECC */ + flashWREG->FEMUADDR = 0xF0200000U; + flashWREG->FEMUDMSW = 0U; + flashWREG->FEMUDLSW = 0U; + + /* ECC for the correct data*/ + ecc = flashWREG->FEMUECC; + + /* Load data with 1 bit error */ + flashWREG->FEMUDMSW = 0U; + flashWREG->FEMUDLSW = 1U; + + /* Enable Diagnostic ECC data correction mode and select FEE SECDED for diagnostic testing */ + flashWREG->FDIAGCTRL = 0x00055001U; + + flashWREG->FEMUECC = ecc; + + /* Diagnostic trigger */ + flashWREG->FDIAGCTRL |= 0x01000000U; + + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + if((flashWREG->EESTATUS & 0x1U) != 0x1U) + { + /* No single bit error was detected */ + selftestFailNotification(CHECKFLASHEEPROMECC_FAIL1); + } + else + { + if((esmREG->SR4[0U] & 0x8U) != 0x8U) + { + /* EEPROM single bit error not captured in ESM */ + selftestFailNotification(CHECKFLASHEEPROMECC_FAIL2); + } + else + { + /* Clear single bit error flag in flash wrapper */ + flashWREG->EESTATUS = 0xFU; + + /* Clear ESM flag */ + esmREG->SR4[0U] = 0x8U; + } + } + + /* Load data with 2 bit error */ + flashWREG->FEMUDMSW = 0U; + flashWREG->FEMUDLSW = 3U; + + /* Enable Diagnostic ECC data correction mode and select FEE SECDED for diagnostic testing */ + flashWREG->FDIAGCTRL = 0x00055001U; + + flashWREG->FEMUECC = ecc; + + /* Diagnostic trigger */ + flashWREG->FDIAGCTRL |= 0x01000000U; + + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + if((flashWREG->EESTATUS & 0x100U) != 0x100U) + { + /* No double bit error was detected */ + selftestFailNotification(CHECKFLASHEEPROMECC_FAIL3); + } + else + { + if((esmREG->SR4[0U] & 0x10U) != 0x10U) + { + /* EEPROM double bit error not captured in ESM */ + selftestFailNotification(CHECKFLASHEEPROMECC_FAIL4); + } + else + { + /* Clear uncorrectable error flag in flash wrapper */ + flashWREG->EESTATUS = 0x1100U; + + /* Read EEUNCERRADD register */ + regread = flashWREG->EEUNCERRADD; + + /* Clear ESM flag */ + esmREG->SR4[0U] = 0x10U; + + + } + } +} + +/** @fn void checkPLL1Slip(void) +* @brief Check PLL1 Slip detection logic. +* +* This function checks PLL1 Slip detection logic. +*/ +/* SourceId : SELFTEST_SourceId_037 */ +/* DesignId : SELFTEST_DesignId_030 */ +/* Requirements : HL_SR384 */ +void checkPLL1Slip(void) +{ + uint32 ghvsrc_bk, pllctl1_bk; + + /* Back up the the registers GHVSRC and PLLCTRL1 */ + ghvsrc_bk = systemREG1->GHVSRC; + pllctl1_bk = systemREG1->PLLCTL1; + + /* Switch all clock domains to oscillator */ + systemREG1->GHVSRC = 0x00000000U; + + /* Disable Reset on PLL Slip and enable Bypass on PLL slip */ + systemREG1->PLLCTL1 &= 0x1FFFFFFFU; + + /* Force a PLL Slip */ + systemREG1->PLLCTL1 ^= 0x8000U; + + /* Wait till PLL slip flag is set */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((systemREG1->GBLSTAT & 0x300U) == 0U) + { + } /* Wait */ + + if((esmREG->SR1[0U] & 0x400U) != 0x400U) + { + /* ESM flag not set */ + selftestFailNotification(CHECKPLL1SLIP_FAIL1); + } + else + { + /* Disable PLL1 */ + systemREG1->CSDISSET = 0x2U; + + /* Wait till PLL1 is disabled */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((systemREG1->CSDIS & 0x2U) == 0U) + { + } /* Wait */ + + /* Restore the PLL multiplier value */ + systemREG1->PLLCTL1 ^= 0x8000U; + + /* Enable PLL1 */ + systemREG1->CSDISCLR = 0x2U; + + /* Wait till PLL1 is disabled */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((systemREG1->CSDIS & 0x2U) != 0U) + { + } /* Wait */ + + /* Switch back to the initial clock source */ + systemREG1->GHVSRC = ghvsrc_bk; + + /* Clear PLL slip flag */ + systemREG1->GBLSTAT = 0x300U; + + /* Clear ESM flag */ + esmREG->SR1[0U] = 0x400U; + + /* Restore the PLLCTL1 register */ + systemREG1->PLLCTL1 = pllctl1_bk; + } +} + +/** @fn void checkPLL2Slip(void) +* @brief Check PLL2 Slip detection logic. +* +* This function checks PLL2 Slip detection logic. +*/ +/* SourceId : SELFTEST_SourceId_038 */ +/* DesignId : SELFTEST_DesignId_031 */ +/* Requirements : HL_SR384 */ +void checkPLL2Slip(void) +{ + uint32 ghvsrc_bk; + + /* Back up the the register GHVSRC */ + ghvsrc_bk = systemREG1->GHVSRC; + + /* Switch all clock domains to oscillator */ + systemREG1->GHVSRC = 0x00000000U; + + /* Force a PLL2 Slip */ + systemREG2->PLLCTL3 ^= 0x8000U; + + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((esmREG->SR4[0U] & 0x400U) != 0x400U) + { + /* Wait till ESM flag is set */ + } + + /* Disable PLL2 */ + systemREG1->CSDISSET = 0x40U; + + /* Wait till PLL2 is disabled */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((systemREG1->CSDIS & 0x40U) == 0U) + { + } /* Wait */ + + /* Restore the PLL 2 multiplier value */ + systemREG2->PLLCTL3 ^= 0x8000U; + + /* Enable PLL2 */ + systemREG1->CSDISCLR = 0x40U; + + /* Wait till PLL2 is disabled */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((systemREG1->CSDIS & 0x40U) != 0U) + { + } /* Wait */ + + /* Switch back to the initial clock source */ + systemREG1->GHVSRC = ghvsrc_bk; + + /* Clear PLL slip flag */ + systemREG1->GBLSTAT = 0x300U; + + /* Clear ESM flag */ + esmREG->SR4[0U] = 0x400U; +} + + +/** @fn void checkRAMAddrParity(void) +* @brief Check TCRAM Address parity error detection and signaling mechanism. +* +* This function TCRAM Address parity error detection and signaling mechanism. +*/ +/* SourceId : SELFTEST_SourceId_039 */ +/* DesignId : SELFTEST_DesignId_032 */ +/* Requirements : HL_SR409 */ +void checkRAMAddrParity(void) +{ + register uint64 ramread; + volatile uint32 regread; + uint32 tcram1ErrStat, tcram2ErrStat; + + /* Invert Address parity scheme */ + tcram1REG->RAMCTRL = 0x0D05000AU; + tcram2REG->RAMCTRL = 0x0D05000AU; + + /* Read from both RAM banks */ + ramread = tcramA1bit; + ramread = ramread | tcramB1bit; /* XOR-ing with ramread to avoid warnings */ + + /* Switch back to Address parity scheme */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* Check for error status */ + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x100U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x100U; + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */ + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */ + if((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U)) + { + /* No Address parity error detected */ + selftestFailNotification(CHECKRAMADDRPARITY_FAIL1); + } + else + { + if((esmREG->SR1[1U] & 0x1400U) != 0x1400U) + { + /* Address parity error not reported to ESM */ + selftestFailNotification(CHECKRAMADDRPARITY_FAIL2); + } + else + { + /* Clear Address parity error flag */ + tcram1REG->RAMERRSTATUS = 0x300U; + tcram2REG->RAMERRSTATUS = 0x300U; + + /* Clear ESM flag */ + esmREG->SR1[1U] = 0x1400U; + + /* The nERROR pin will become inactive once the LTC counter expires */ + esmREG->EKR = 0x5U; + + regread = tcram1REG->RAMPERADDR; + regread = tcram2REG->RAMPERADDR; + } + } +} + +/** @fn void checkRAMUERRTest(void) +* @brief Run RAM test +* +* This function runs RAM test to test the redundant address decode and compare logic. +*/ +/* SourceId : SELFTEST_SourceId_040 */ +/* DesignId : SELFTEST_DesignId_033 */ +/* Requirements : HL_SR410 */ +void checkRAMUERRTest(void) +{ + uint32 tcram1ErrStat, tcram2ErrStat = 0U; + + /* Trigger equality check */ + tcram1REG->RAMTEST = 0x018AU; + tcram2REG->RAMTEST = 0x018AU; + + /* Wait till test is completed */ + while(tcram1REG->RAMTEST != 0x008AU) + { + } /* Wait */ + while(tcram2REG->RAMTEST != 0x008AU) + { + } /* Wait */ + + /* Check for error status */ + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x10U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x10U; + if((tcram1ErrStat == 0x10U) || (tcram2ErrStat == 0x10U)) + { + /* test failed */ + selftestFailNotification(CHECKRAMUERRTEST_FAIL1); + } + + /* Trigger inequality check */ + tcram1REG->RAMTEST = 0x014AU; + tcram2REG->RAMTEST = 0x014AU; + + /* Wait till test is completed */ + while(tcram1REG->RAMTEST != 0x004AU) + { + }/* Wait */ + while(tcram2REG->RAMTEST != 0x004AU) + { + }/* Wait */ + + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x10U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x10U; + if((tcram1ErrStat == 0x10U) || (tcram2ErrStat == 0x10U)) + { + /* test failed */ + selftestFailNotification(CHECKRAMUERRTEST_FAIL2); + } + else + { + tcram1REG->RAMERRSTATUS = 0x4U; + tcram2REG->RAMERRSTATUS = 0x4U; + + /* Clear ESM flag */ + esmREG->SR1[1U] = 0x140U; + esmREG->SSR2 = 0x140U; + esmREG->EKR = 0x5U; + } + + /* Disable RAM test mode */ + tcram1REG->RAMTEST = 0x5U; + tcram2REG->RAMTEST = 0x5U; +} + +/* SourceId : SELFTEST_SourceId_041 */ +/* DesignId : SELFTEST_DesignId_018 */ +/* Requirements : HL_SR407 */ +void fmcBus1ParityCheck(void) +{ + uint32 regBkupFparOvr,regBckupFdiagctrl; + volatile uint32 flashread = 0U; + + /* Backup registers */ + regBkupFparOvr = flashWREG->FPAROVR; + regBckupFdiagctrl = flashWREG->FDIAGCTRL; + + /* Read to unfreeze the error address registers */ + flashread = flashWREG->FUNCERRADD; + + /* clear status register */ + flashWREG->FEDACSTATUS = 0x400U; + + /* Enable Parity Error */ + flashWREG->FPAROVR = (uint32)((uint32)0x5U << 9U) + | (uint32)((uint32)0x5U << 12U); + + /* set Diag test mode */ + flashWREG->FDIAGCTRL = 0x00050000U | 0x00000007U; + + /* Add parity */ + flashWREG->FPAROVR |= 0x00000100U; + + /* Start Test */ + flashWREG->FDIAGCTRL |= 0x1000000U; + + /* Wait until test done */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + while((flashWREG->FDIAGCTRL & 0x1000000U) == 0x1000000U) + { + }/* Wait */ + + /* Check address Error */ + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + if((flashWREG->FEDACSTATUS & 0x400U) != 0x400U) + { + selftestFailNotification(FMCBUS1PARITYCHECK_FAIL1); + } + else + { + /* clear status register */ + flashWREG->FEDACSTATUS = 0x400U; + + /* check if ESM is flagged */ + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + if((esmREG->SR1[1U] & 0x0000010U) == 0U) + { + selftestFailNotification(FMCBUS1PARITYCHECK_FAIL2); + } + else + { + /* clear ESM flag */ + esmREG->SR1[1U] |= 0x0000010U; + esmREG->SSR2 |= 0x0000010U; + esmREG->EKR = 0x5U; + + /* Stop Diag test mode */ + flashWREG->FDIAGCTRL = regBckupFdiagctrl; + flashWREG->FPAROVR = regBkupFparOvr; + } + } + + /* Read to unfreeze the error address registers */ + flashread = flashWREG->FUNCERRADD; +} + +/* SourceId : SELFTEST_SourceId_042 */ +/* DesignId : SELFTEST_DesignId_011 */ +/* Requirements : HL_SR401 */ +void pbistFail(void) +{ + uint32 PBIST_RAMT, PBIST_FSRA0, PBIST_FSRDL0; + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + PBIST_RAMT = pbistREG->RAMT; + PBIST_FSRA0 = pbistREG->FSRA0; + PBIST_FSRDL0 = pbistREG->FSRDL0; + + if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE) + { + memoryPort0TestFailNotification((uint32)((PBIST_RAMT & 0xFF000000U) >> 24U), (uint32)((PBIST_RAMT & 0x00FF0000U) >> 16U),(uint32)PBIST_FSRA0, (uint32)PBIST_FSRDL0); + } + else + { +/* USER CODE BEGIN (77) */ +/* USER CODE END */ +/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ +/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ +/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ + for(;;) + { + }/* Wait */ + +/* USER CODE BEGIN (78) */ +/* USER CODE END */ + } +} + +/** @fn void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : SELFTEST_SourceId_043 */ +/* DesignId : SELFTEST_DesignId_034 */ +/* Requirements : HL_SR506 */ +void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_RAMT = PBIST_RAMT_CONFIGVALUE; + config_reg->CONFIG_DLR = PBIST_DLR_CONFIGVALUE; + config_reg->CONFIG_PACT = PBIST_PACT_CONFIGVALUE; + config_reg->CONFIG_PBISTID = PBIST_PBISTID_CONFIGVALUE; + config_reg->CONFIG_OVER = PBIST_OVER_CONFIGVALUE; + config_reg->CONFIG_FSRDL1 = PBIST_FSRDL1_CONFIGVALUE; + config_reg->CONFIG_ROM = PBIST_ROM_CONFIGVALUE; + config_reg->CONFIG_ALGO = PBIST_ALGO_CONFIGVALUE; + config_reg->CONFIG_RINFOL = PBIST_RINFOL_CONFIGVALUE; + config_reg->CONFIG_RINFOU = PBIST_RINFOU_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_RAMT = pbistREG->RAMT; + config_reg->CONFIG_DLR = pbistREG->DLR; + config_reg->CONFIG_PACT = pbistREG->PACT; + config_reg->CONFIG_PBISTID = pbistREG->PBISTID; + config_reg->CONFIG_OVER = pbistREG->OVER; + config_reg->CONFIG_FSRDL1 = pbistREG->FSRDL1; + config_reg->CONFIG_ROM = pbistREG->ROM; + config_reg->CONFIG_ALGO = pbistREG->ALGO; + config_reg->CONFIG_RINFOL = pbistREG->RINFOL; + config_reg->CONFIG_RINFOU = pbistREG->RINFOU; + } +} + +/** @fn void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : SELFTEST_SourceId_044 */ +/* DesignId : SELFTEST_DesignId_035 */ +/* Requirements : HL_SR506 */ +void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_STCGCR0 = STC_STCGCR0_CONFIGVALUE; + config_reg->CONFIG_STCGCR1 = STC_STCGCR1_CONFIGVALUE; + config_reg->CONFIG_STCTPR = STC_STCTPR_CONFIGVALUE; + config_reg->CONFIG_STCSCSCR = STC_STCSCSCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_STCGCR0 = stcREG->STCGCR0; + config_reg->CONFIG_STCGCR1 = stcREG->STCGCR1; + config_reg->CONFIG_STCTPR = stcREG->STCTPR; + config_reg->CONFIG_STCSCSCR = stcREG->STCSCSCR; + } +} + + +/** @fn void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : SELFTEST_SourceId_045 */ +/* DesignId : SELFTEST_DesignId_036 */ +/* Requirements : HL_SR506 */ +void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_BOUNDARY = EFC_BOUNDARY_CONFIGVALUE; + config_reg->CONFIG_PINS = EFC_PINS_CONFIGVALUE; + config_reg->CONFIG_SELFTESTCYCLES = EFC_SELFTESTCYCLES_CONFIGVALUE; + config_reg->CONFIG_SELFTESTSIGN = EFC_SELFTESTSIGN_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_BOUNDARY = efcREG->BOUNDARY; + config_reg->CONFIG_PINS = efcREG->PINS; + config_reg->CONFIG_SELFTESTCYCLES = efcREG->SELF_TEST_CYCLES; + config_reg->CONFIG_SELFTESTSIGN = efcREG->SELF_TEST_SIGN; + } +} + + +/** @fn void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : SELFTEST_SourceId_046 */ +/* DesignId : SELFTEST_DesignId_037 */ +/* Requirements : HL_SR506 */ +void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_CCMKEYR = CCMR4_CCMKEYR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_CCMKEYR = CCMKEYR; + } +} + + +/** @fn void errata_PBIST_4(void) +* @brief Workaround for the Errata PBIST#4. +* +* This function is workaround for Errata PBIST#4. +* This function is designed to initialize the ROMs using the PBIST controller. +* The CPU will configure the PBIST controller to test the PBIST ROM and STC ROM. +* This function should be called at startup after system init before using the ROMs. +* +* @note : This Function uses register's which are not exposed to users through +* TRM , to run custom algorithm. User can use this function as Black box. +* +*/ +void errata_PBIST_4(void) +{ + volatile uint32 i = 0U; + uint8 ROM_count; + sint32 PBIST_wait_done_loop; + uint32 pmuCalibration, pmuCount; + + /* PMU calibration */ + _pmuEnableCountersGlobal_(); + _pmuResetCounters_(); + _pmuStartCounters_(pmuCYCLE_COUNTER); + _pmuStopCounters_(pmuCYCLE_COUNTER); + pmuCalibration=_pmuGetCycleCount_(); + + /* ROM_init Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + *(volatile uint32 *)0xFFFF0400U = 0x0000000AU; + *(volatile uint32 *)0xFFFF040CU = 0x0000EE0AU; + + /* Loop for Executing PBIST ROM and STC ROM */ + for (ROM_count = 0U; ROM_count < 2U; ROM_count++) + { + PBIST_wait_done_loop = 0; + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* PBIST Clocks did not disable */ + if(pbistREG->PACT != 0x0U ) + { + selftestFailNotification(PBISTSELFCHECK_FAIL3); + } + else + { + /* PBIST ROM clock frequency = HCLK frequency /2 */ + /* Disable memory self controller */ + systemREG1->MSTGCR = 0x00000105U; + + /* Disable Memory Initialization controller */ + systemREG1->MINITGCR = 0x5U; + + /* Enable memory self controller */ + systemREG1->MSTGCR = 0x0000010AU; + + /* Clear PBIST Done */ + systemREG1->MSTCGSTAT = 0x1U; + + /* Enable PBIST controller */ + systemREG1->MSINENA = 0x1U; + + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ + /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ } + + /* Enable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x3U; + + /* CPU control of PBIST */ + pbistREG->DLR = 0x10U; + + /* Load PBIST ALGO to initialize the ROMs */ + *(volatile uint32 *)0xFFFFE400U = 0x00000001U; + *(volatile uint32 *)0xFFFFE440U = 0x00000025U; + *(volatile uint32 *)0xFFFFE404U = 0x62400001U; + *(volatile uint32 *)0xFFFFE444U = 0x00000004U; + *(volatile uint32 *)0xFFFFE408U = 0x00068003U; + *(volatile uint32 *)0xFFFFE448U = 0x00000000U; + *(volatile uint32 *)0xFFFFE40CU = 0x00000004U; + *(volatile uint32 *)0xFFFFE44CU = 0x00006860U; + *(volatile uint32 *)0xFFFFE410U = 0x00000000U; + *(volatile uint32 *)0xFFFFE450U = 0x00000001U; + *(volatile uint32 *)0xFFFFE540U = 0x000003E8U; + *(volatile uint32 *)0xFFFFE550U = 0x00000001U; + *(volatile uint32 *)0xFFFFE530U = 0x00000000U; + + /* SELECT ROM */ + if (ROM_count == 1U) + { + /* SELECT PBIST ROM */ + *(volatile uint32 *)0xFFFFE520U = 0x00000002U; + *(volatile uint32 *)0xFFFFE524U = 0x00000000U; + pbistREG->RAMT = 0x01002008U; + } + else + { + /* SELECT STC ROM */ + *(volatile uint32 *)0xFFFFE520U = 0xFFF0007CU; + *(volatile uint32 *)0xFFFFE524U = 0x0A63FFFFU; + pbistREG->RAMT = 0x02002008U; + } + + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[4U] = 1U; + pbistREG->rsvd1[0U] = 3U; + + /* Start PMU counter */ + _pmuResetCounters_(); + _pmuStartCounters_(pmuCYCLE_COUNTER); + + /* PBIST_RUN */ + pbistREG->rsvd1[1U] = 1U; + + /* wait until memory self-test done is indicated */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ((systemREG1->MSTCGSTAT & 0x1U) != 0x1U) + { + }/* Wait */ + + /* Stop PMU counter */ + _pmuStopCounters_(pmuCYCLE_COUNTER); + + /* Get CPU cycle count */ + pmuCount =_pmuGetCycleCount_(); + + /* Calculate PBIST test complete time in ROM Clock */ + /* 2 - Divide value ( Default is 2 in HALCoGen) */ + /* 1000 = 0x3E8 - Test Loop count in ROM Algorithm */ + pmuCount = pmuCount - pmuCalibration; + PBIST_wait_done_loop = ((sint32)pmuCount/2) - 1000; + + /* Check PBIST status results (Address, Status, Count, etc...) */ + if ((pbistREG->FSRA0 | pbistREG->FSRA1 | pbistREG->FSRDL0 | pbistREG->rsvd3 | + pbistREG->FSRDL1 | pbistREG->rsvd4[0U] | pbistREG->rsvd4[1U]) != 0U) + { + /* PBIST Failure for the Algorithm chosen above */ + selftestFailNotification(PBISTSELFCHECK_FAIL1); + } + + /* Check that the algorithm executed in the expected amount of time. */ + /* This time is dependent on the ROMCLKDIV selected */ + if ((PBIST_wait_done_loop <= 20) || (PBIST_wait_done_loop >= 200) ) + { + selftestFailNotification(PBISTSELFCHECK_FAIL2); + } + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* Disable PBIST */ + systemREG1->MSTGCR &= 0xFFFFFFF0U; + systemREG1->MSTGCR |= 0x5U; + } + } /* ROM Loop */ + + /* ROM restore default setup */ + /* (must be completed before continuing) */ + *(volatile uint32 *)0xFFFF040CU = 0x0000AA0AU; + *(volatile uint32 *)0xFFFF040CU = 0x0000AA05U; + *(volatile uint32 *)0xFFFF0400U = 0x00000005U; + + _pmuDisableCountersGlobal_(); +} + + +/** @fn void enableParity(void) +* @brief Enable peripheral RAM parity +* +* This function enables RAM parity for all peripherals for which RAM parity check is enabled. +* This function is called before memoryInit in the startup +* +*/ +#pragma WEAK(enableParity) +void enableParity(void) +{ + DMA_PARCR = 0xAU; /* Enable DMA RAM parity */ + VIM_PARCTL = 0xAU; /* Enable VIM RAM parity */ + canREG1->CTL = ((uint32)0xAU << 10U) | 1U; /* Enable CAN1 RAM parity */ + canREG2->CTL = ((uint32)0xAU << 10U) | 1U; /* Enable CAN2 RAM parity */ + canREG3->CTL = ((uint32)0xAU << 10U) | 1U; /* Enable CAN3 RAM parity */ + adcREG1->PARCR = 0xAU; /* Enable ADC1 RAM parity */ + adcREG2->PARCR = 0xAU; /* Enable ADC2 RAM parity */ + hetREG1->PCR = 0xAU; /* Enable HET1 RAM parity */ + htuREG1->PCR = 0xAU; /* Enable HTU1 RAM parity */ + hetREG2->PCR = 0xAU; /* Enable HET2 RAM parity */ + htuREG2->PCR = 0xAU; /* Enable HTU2 RAM parity */ +} + +/** @fn void disableParity(void) +* @brief Disable peripheral RAM parity +* +* This function disables RAM parity for all peripherals for which RAM parity check is enabled. +* This function is called after memoryInit in the startup +* +*/ +#pragma WEAK(disableParity) +void disableParity(void) +{ + DMA_PARCR = 0x5U; /* Disable DMA RAM parity */ + VIM_PARCTL = 0x5U; /* Disable VIM RAM parity */ + canREG1->CTL = ((uint32)0x5U << 10U) | 1U; /* Disable CAN1 RAM parity */ + canREG2->CTL = ((uint32)0x5U << 10U) | 1U; /* Disable CAN2 RAM parity */ + canREG3->CTL = ((uint32)0x5U << 10U) | 1U; /* Disable CAN3 RAM parity */ + adcREG1->PARCR = 0x5U; /* Disable ADC1 RAM parity */ + adcREG2->PARCR = 0x5U; /* Disable ADC2 RAM parity */ + hetREG1->PCR = 0x5U; /* Disable HET1 RAM parity */ + htuREG1->PCR = 0x5U; /* Disable HTU1 RAM parity */ + hetREG2->PCR = 0x5U; /* Disable HET2 RAM parity */ + htuREG2->PCR = 0x5U; /* Disable HTU2 RAM parity */ +} diff --git a/src/arch/rm46l8lp/halcogen/sys_startup.c b/src/arch/rm46l8lp/halcogen/sys_startup.c new file mode 100644 index 0000000..49f312b --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_startup.c @@ -0,0 +1,699 @@ +/** @file sys_startup.c +* @brief Startup Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - Include Files +* - Type Definitions +* - External Functions +* - VIM RAM Setup +* - Startup Routine +* . +* which are relevant for the Startup. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + + +/* Include Files */ + +#include "sys_common.h" +#include "system.h" +#include "sys_vim.h" +#include "sys_core.h" +#include "sys_selftest.h" +#include "esm.h" +#include "mibspi.h" + +#include "errata_SSWF021_45.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + + +/* External Functions */ +/*SAFETYMCUSW 218 S MR:20.2 <APPROVED> "Functions from library" */ +extern void __TI_auto_init(void); +/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(main should be declared by the user)" */ +extern int main(void); +/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */ +/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(Extern declaration present in the library)" */ +extern void exit(int _status); + + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +void handlePLLLockFail(void); +/* Startup Routine */ +void _c_int00(void); +#define PLL_RETRIES 5U +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +#pragma CODE_STATE(_c_int00, 32) +#pragma INTERRUPT(_c_int00, RESET) +#pragma WEAK(_c_int00) + +/* SourceId : STARTUP_SourceId_001 */ +/* DesignId : STARTUP_DesignId_001 */ +/* Requirements : HL_SR508 */ +void _c_int00(void) +{ +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + /* Initialize Core Registers to avoid CCM Error */ + _coreInitRegisters_(); + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + /* Initialize Stack Pointers */ + _coreInitStackPointer_(); + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + + /* Enable CPU Event Export */ + /* This allows the CPU to signal any single-bit or double-bit errors detected + * by its ECC logic for accesses to program flash or data RAM. + */ + _coreEnableEventBusExport_(); +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + /* Enable response to ECC errors indicated by CPU for accesses to flash */ + flashWREG->FEDACCTRL1 = 0x000A060AU; + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + + /* Enable CPU ECC checking for ATCM (flash accesses) */ + _coreEnableFlashEcc_(); + + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ + + /* Workaround for Errata CORTEXR4 66 */ + _errata_CORTEXR4_66_(); + + /* Workaround for Errata CORTEXR4 57 */ + _errata_CORTEXR4_57_(); + + /* Reset handler: the following instructions read from the system exception status register + * to identify the cause of the CPU reset. + */ + + /* check for power-on reset condition */ + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + if ((SYS_EXCEPTION & POWERON_RESET) != 0U) + { +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + /* Add condition to check whether PLL can be started successfully */ + if (_errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U) + { + /* Put system in a safe state */ + handlePLLLockFail(); + } + /* clear all reset status flags */ + SYS_EXCEPTION = 0xFFFFU; + +/* USER CODE BEGIN (13) */ +/* USER CODE END */ +/* USER CODE BEGIN (14) */ +/* USER CODE END */ +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + /* continue with normal start-up sequence */ + } + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U) + { + /* Reset caused due to oscillator failure. + Add user code here to handle oscillator failure */ + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + } + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U) + { + /* Reset caused due + * 1) windowed watchdog violation - Add user code here to handle watchdog violation. + * 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS + */ + /* Check the WatchDog Status register */ + if(WATCHDOG_STATUS != 0U) + { + /* Add user code here to handle watchdog violation. */ +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + /* Clear the Watchdog reset flag in Exception Status register */ + SYS_EXCEPTION = WATCHDOG_RESET; + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + } + else + { + /* Clear the ICEPICK reset flag in Exception Status register */ + SYS_EXCEPTION = ICEPICK_RESET; +/* USER CODE BEGIN (19) */ +/* USER CODE END */ + } + } + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + else if ((SYS_EXCEPTION & CPU_RESET) !=0U) + { + /* Reset caused due to CPU reset. + CPU reset can be caused by CPU self-test completion, or + by toggling the "CPU RESET" bit of the CPU Reset Control Register. */ + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ + + /* clear all reset status flags */ + SYS_EXCEPTION = CPU_RESET; + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + + } + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + else if ((SYS_EXCEPTION & SW_RESET) != 0U) + { + /* Reset caused due to software reset. + Add user code to handle software reset. */ + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ + } + else + { + /* Reset caused by nRST being driven low externally. + Add user code to handle external reset. */ + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ + } + + /* Check if there were ESM group3 errors during power-up. + * These could occur during eFuse auto-load or during reads from flash OTP + * during power-up. Device operation is not reliable and not recommended + * in this case. + * An ESM group3 error only drives the nERROR pin low. An external circuit + * that monitors the nERROR pin must take the appropriate action to ensure that + * the system is placed in a safe state, as determined by the application. + */ + if ((esmREG->SR1[2]) != 0U) + { +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ + /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ + for(;;) + { + }/* Wait */ +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + } + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ + + /* Initialize System - Clock, Flash settings with Efuse self check */ + systemInit(); + + /* Workaround for Errata PBIST#4 */ + errata_PBIST_4(); + + /* Run a diagnostic check on the memory self-test controller. + * This function chooses a RAM test algorithm and runs it on an on-chip ROM. + * The memory self-test is expected to fail. The function ensures that the PBIST controller + * is capable of detecting and indicating a memory self-test failure. + */ + pbistSelfCheck(); + + /* Run PBIST on STC ROM */ + pbistRun((uint32)STC_ROM_PBIST_RAM_GROUP, + ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast)); + + /* Wait for PBIST for STC ROM to be completed */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while(pbistIsTestCompleted() != TRUE) + { + }/* Wait */ + + /* Check if PBIST on STC ROM passed the self-test */ + if( pbistIsTestPassed() != TRUE) + { + /* PBIST and STC ROM failed the self-test. + * Need custom handler to check the memory failure + * and to take the appropriate next step. + */ + + pbistFail(); + + } + + /* Disable PBIST clocks and disable memory self-test mode */ + pbistStop(); + + /* Run PBIST on PBIST ROM */ + pbistRun((uint32)PBIST_ROM_PBIST_RAM_GROUP, + ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast)); + + /* Wait for PBIST for PBIST ROM to be completed */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while(pbistIsTestCompleted() != TRUE) + { + }/* Wait */ + + /* Check if PBIST ROM passed the self-test */ + if( pbistIsTestPassed() != TRUE) + { + /* PBIST and STC ROM failed the self-test. + * Need custom handler to check the memory failure + * and to take the appropriate next step. + */ + + pbistFail(); + + } + + /* Disable PBIST clocks and disable memory self-test mode */ + pbistStop(); +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + + /* Disable RAM ECC before doing PBIST for Main RAM */ + _coreDisableRamEcc_(); + + /* Run PBIST on CPU RAM. + * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs. + * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the + * device datasheet. + */ + pbistRun(0x00300020U, /* ESRAM Single Port PBIST */ + (uint32)PBIST_March13N_SP); + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + + /* Wait for PBIST for CPU RAM to be completed */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while(pbistIsTestCompleted() != TRUE) + { + }/* Wait */ + + +/* USER CODE BEGIN (33) */ +/* USER CODE END */ + + /* Check if CPU RAM passed the self-test */ + if( pbistIsTestPassed() != TRUE) + { + /* CPU RAM failed the self-test. + * Need custom handler to check the memory failure + * and to take the appropriate next step. + */ +/* USER CODE BEGIN (34) */ +/* USER CODE END */ + + pbistFail(); + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ + } + +/* USER CODE BEGIN (36) */ +/* USER CODE END */ + + /* Disable PBIST clocks and disable memory self-test mode */ + pbistStop(); + + +/* USER CODE BEGIN (37) */ +/* USER CODE END */ + + + /* Initialize CPU RAM. + * This function uses the system module's hardware for auto-initialization of memories and their + * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register. + * Hence the value 0x1 passed to the function. + * This function will initialize the entire CPU RAM and the corresponding ECC locations. + */ + memoryInit(0x1U); + +/* USER CODE BEGIN (38) */ +/* USER CODE END */ + + /* Enable ECC checking for TCRAM accesses. + * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM. + */ + _coreEnableRamEcc_(); + +/* USER CODE BEGIN (39) */ +/* USER CODE END */ + + /* Start PBIST on all dual-port memories */ + /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories. + PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. + */ + pbistRun( (uint32)0x00000000U /* EMAC RAM */ + | (uint32)0x00000000U /* USB RAM */ + | (uint32)0x00000800U /* DMA RAM */ + | (uint32)0x00000200U /* VIM RAM */ + | (uint32)0x00000040U /* MIBSPI1 RAM */ + | (uint32)0x00000080U /* MIBSPI3 RAM */ + | (uint32)0x00000100U /* MIBSPI5 RAM */ + | (uint32)0x00000004U /* CAN1 RAM */ + | (uint32)0x00000008U /* CAN2 RAM */ + | (uint32)0x00000010U /* CAN3 RAM */ + | (uint32)0x00000400U /* ADC1 RAM */ + | (uint32)0x00020000U /* ADC2 RAM */ + | (uint32)0x00001000U /* HET1 RAM */ + | (uint32)0x00040000U /* HET2 RAM */ + | (uint32)0x00002000U /* HTU1 RAM */ + | (uint32)0x00080000U /* HTU2 RAM */ + | (uint32)0x00000000U /* RTP RAM */ + | (uint32)0x00000000U /* FRAY RAM */ + ,(uint32) PBIST_March13N_DP); + +/* USER CODE BEGIN (40) */ +/* USER CODE END */ + + /* Test the CPU ECC mechanism for RAM accesses. + * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses + * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error + * in the ECC causes a data abort exception. The data abort handler is written to look for + * deliberately caused exception and to return the code execution to the instruction + * following the one that caused the abort. + */ + checkRAMECC(); + +/* USER CODE BEGIN (41) */ +/* USER CODE END */ + + /* Test the CPU ECC mechanism for Flash accesses. + * The checkFlashECC function uses the flash interface module's diagnostic mode 7 + * to create single-bit and double-bit errors in CPU accesses to the flash. A double-bit + * error on reading from flash causes a data abort exception. + * The data abort handler is written to look for deliberately caused exception and + * to return the code execution to the instruction following the one that was aborted. + * + */ + checkFlashECC(); + flashWREG->FDIAGCTRL = 0x000A0007U; /* disable flash diagnostic mode */ + +/* USER CODE BEGIN (42) */ +/* USER CODE END */ + +/* USER CODE BEGIN (43) */ +/* USER CODE END */ + + /* Wait for PBIST for CPU RAM to be completed */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while(pbistIsTestCompleted() != TRUE) + { + }/* Wait */ + + +/* USER CODE BEGIN (44) */ +/* USER CODE END */ + + /* Check if CPU RAM passed the self-test */ + if( pbistIsTestPassed() != TRUE) + { + +/* USER CODE BEGIN (45) */ +/* USER CODE END */ + + /* CPU RAM failed the self-test. + * Need custom handler to check the memory failure + * and to take the appropriate next step. + */ +/* USER CODE BEGIN (46) */ +/* USER CODE END */ + + pbistFail(); + +/* USER CODE BEGIN (47) */ +/* USER CODE END */ + } + +/* USER CODE BEGIN (48) */ +/* USER CODE END */ + + /* Disable PBIST clocks and disable memory self-test mode */ + pbistStop(); + +/* USER CODE BEGIN (55) */ +/* USER CODE END */ + + /* Release the MibSPI1 modules from local reset. + * This will cause the MibSPI1 RAMs to get initialized along with the parity memory. + */ + mibspiREG1->GCR0 = 0x1U; + + /* Release the MibSPI3 modules from local reset. + * This will cause the MibSPI3 RAMs to get initialized along with the parity memory. + */ + mibspiREG3->GCR0 = 0x1U; + + /* Release the MibSPI5 modules from local reset. + * This will cause the MibSPI5 RAMs to get initialized along with the parity memory. + */ + mibspiREG5->GCR0 = 0x1U; + +/* USER CODE BEGIN (56) */ +/* USER CODE END */ + + /* Enable parity on selected RAMs */ + enableParity(); + + /* Initialize all on-chip SRAMs except for MibSPIx RAMs + * The MibSPIx modules have their own auto-initialization mechanism which is triggered + * as soon as the modules are brought out of local reset. + */ + /* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset. + */ + /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers. + Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. + */ + memoryInit( (uint32)((uint32)1U << 1U) /* DMA RAM */ + | (uint32)((uint32)1U << 2U) /* VIM RAM */ + | (uint32)((uint32)1U << 5U) /* CAN1 RAM */ + | (uint32)((uint32)1U << 6U) /* CAN2 RAM */ + | (uint32)((uint32)1U << 10U) /* CAN3 RAM */ + | (uint32)((uint32)1U << 8U) /* ADC1 RAM */ + | (uint32)((uint32)1U << 14U) /* ADC2 RAM */ + | (uint32)((uint32)1U << 3U) /* HET1 RAM */ + | (uint32)((uint32)1U << 4U) /* HTU1 RAM */ + | (uint32)((uint32)1U << 15U) /* HET2 RAM */ + | (uint32)((uint32)1U << 16U) /* HTU2 RAM */ + ); + + /* Disable parity */ + disableParity(); + + /* Test the parity protection mechanism for peripheral RAMs + NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity. + Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. + */ + +/* USER CODE BEGIN (57) */ +/* USER CODE END */ + + het1ParityCheck(); + +/* USER CODE BEGIN (58) */ +/* USER CODE END */ + + htu1ParityCheck(); + +/* USER CODE BEGIN (59) */ +/* USER CODE END */ + + het2ParityCheck(); + +/* USER CODE BEGIN (60) */ +/* USER CODE END */ + + htu2ParityCheck(); + +/* USER CODE BEGIN (61) */ +/* USER CODE END */ + + adc1ParityCheck(); + +/* USER CODE BEGIN (62) */ +/* USER CODE END */ + + adc2ParityCheck(); + +/* USER CODE BEGIN (63) */ +/* USER CODE END */ + + can1ParityCheck(); + +/* USER CODE BEGIN (64) */ +/* USER CODE END */ + + can2ParityCheck(); + +/* USER CODE BEGIN (65) */ +/* USER CODE END */ + + can3ParityCheck(); + +/* USER CODE BEGIN (66) */ +/* USER CODE END */ + + vimParityCheck(); + +/* USER CODE BEGIN (67) */ +/* USER CODE END */ + + dmaParityCheck(); + + +/* USER CODE BEGIN (68) */ +/* USER CODE END */ + +/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U) + { + }/* Wait */ + /* wait for MibSPI1 RAM to complete initialization */ +/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U) + { + }/* Wait */ + /* wait for MibSPI3 RAM to complete initialization */ +/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U) + { + }/* Wait */ + /* wait for MibSPI5 RAM to complete initialization */ + +/* USER CODE BEGIN (69) */ +/* USER CODE END */ + + mibspi1ParityCheck(); + +/* USER CODE BEGIN (70) */ +/* USER CODE END */ + + mibspi3ParityCheck(); + +/* USER CODE BEGIN (71) */ +/* USER CODE END */ + + mibspi5ParityCheck(); + + +/* USER CODE BEGIN (72) */ +/* USER CODE END */ + + /* Enable IRQ offset via Vic controller */ + _coreEnableIrqVicOffset_(); + + +/* USER CODE BEGIN (73) */ +/* USER CODE END */ + + /* Initialize VIM table */ + vimInit(); + +/* USER CODE BEGIN (74) */ +/* USER CODE END */ + + /* Configure system response to error conditions signaled to the ESM group1 */ + /* This function can be configured from the ESM tab of HALCoGen */ + esmInit(); + /* initialize copy table */ + __TI_auto_init(); +/* USER CODE BEGIN (75) */ +/* USER CODE END */ + + /* call the application */ +/*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */ +/*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */ +/*SAFETYMCUSW 60 D MR:8.8 <APPROVED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */ + main(); + +/* USER CODE BEGIN (76) */ +/* USER CODE END */ +/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */ + exit(0); + +/* USER CODE BEGIN (77) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (78) */ +/* USER CODE END */ +/** @fn void handlePLLLockFail(void) +* @brief This function handles PLL lock fail. +*/ +void handlePLLLockFail(void) +{ +/* USER CODE BEGIN (79) */ +/* USER CODE END */ + while(1) + { + + } +/* USER CODE BEGIN (80) */ +/* USER CODE END */ +} +/* USER CODE BEGIN (81) */ +/* USER CODE END */ diff --git a/src/arch/rm46l8lp/halcogen/sys_vim.c b/src/arch/rm46l8lp/halcogen/sys_vim.c new file mode 100644 index 0000000..ef45422 --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/sys_vim.c @@ -0,0 +1,835 @@ +/** @file sys_vim.c +* @brief VIM Driver Implementation File +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +#include "sys_vim.h" +#include "system.h" +#include "esm.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Vim Ram Definition */ +/** @struct vimRam +* @brief Vim Ram Definition +* +* This type is used to access the Vim Ram. +*/ +/** @typedef vimRAM_t +* @brief Vim Ram Type Definition +* +* This type is used to access the Vim Ram. +*/ +typedef volatile struct vimRam +{ + t_isrFuncPTR ISR[VIM_CHANNELS]; +} vimRAM_t; + +#define vimRAM ((vimRAM_t *)0xFFF82000U) + +static const t_isrFuncPTR s_vim_init[128U] = +{ + &phantomInterrupt, + &esmHighInterrupt, /* Channel 0 */ + &phantomInterrupt, /* Channel 1 */ + &rtiCompare0Interrupt, /* Channel 2 */ + &rtiCompare1Interrupt, /* Channel 3 */ + &rtiCompare2Interrupt, /* Channel 4 */ + &rtiCompare3Interrupt, /* Channel 5 */ + &phantomInterrupt, /* Channel 6 */ + &phantomInterrupt, /* Channel 7 */ + &phantomInterrupt, /* Channel 8 */ + &phantomInterrupt, /* Channel 9 */ + &phantomInterrupt, /* Channel 10 */ + &phantomInterrupt, /* Channel 11 */ + &phantomInterrupt, /* Channel 12 */ + &phantomInterrupt, /* Channel 13 */ + &phantomInterrupt, /* Channel 14 */ + &phantomInterrupt, /* Channel 15 */ + &phantomInterrupt, /* Channel 16 */ + &phantomInterrupt, /* Channel 17 */ + &phantomInterrupt, /* Channel 18 */ + &phantomInterrupt, /* Channel 19 */ + &esmLowInterrupt, /* Channel 20 */ + &phantomInterrupt, /* Channel 21 */ + &phantomInterrupt, /* Channel 22 */ + &phantomInterrupt, /* Channel 23 */ + &phantomInterrupt, /* Channel 24 */ + &phantomInterrupt, /* Channel 25 */ + &phantomInterrupt, /* Channel 26 */ + &phantomInterrupt, /* Channel 27 */ + &phantomInterrupt, /* Channel 28 */ + &phantomInterrupt, /* Channel 29 */ + &phantomInterrupt, /* Channel 30 */ + &phantomInterrupt, /* Channel 31 */ + &phantomInterrupt, /* Channel 32 */ + &phantomInterrupt, /* Channel 33 */ + &phantomInterrupt, /* Channel 34 */ + &phantomInterrupt, /* Channel 35 */ + &phantomInterrupt, /* Channel 36 */ + &phantomInterrupt, /* Channel 37 */ + &phantomInterrupt, /* Channel 38 */ + &phantomInterrupt, /* Channel 39 */ + &phantomInterrupt, /* Channel 40 */ + &phantomInterrupt, /* Channel 41 */ + &phantomInterrupt, /* Channel 42 */ + &phantomInterrupt, /* Channel 43 */ + &phantomInterrupt, /* Channel 44 */ + &phantomInterrupt, /* Channel 45 */ + &phantomInterrupt, /* Channel 46 */ + &phantomInterrupt, /* Channel 47 */ + &phantomInterrupt, /* Channel 48 */ + &phantomInterrupt, /* Channel 49 */ + &phantomInterrupt, /* Channel 50 */ + &phantomInterrupt, /* Channel 51 */ + &phantomInterrupt, /* Channel 52 */ + &phantomInterrupt, /* Channel 53 */ + &phantomInterrupt, /* Channel 54 */ + &phantomInterrupt, /* Channel 55 */ + &phantomInterrupt, /* Channel 56 */ + &phantomInterrupt, /* Channel 57 */ + &phantomInterrupt, /* Channel 58 */ + &phantomInterrupt, /* Channel 59 */ + &phantomInterrupt, /* Channel 60 */ + &phantomInterrupt, /* Channel 61 */ + &phantomInterrupt, /* Channel 62 */ + &phantomInterrupt, /* Channel 63 */ + &phantomInterrupt, /* Channel 64 */ + &phantomInterrupt, /* Channel 65 */ + &phantomInterrupt, /* Channel 66 */ + &phantomInterrupt, /* Channel 67 */ + &phantomInterrupt, /* Channel 68 */ + &phantomInterrupt, /* Channel 69 */ + &phantomInterrupt, /* Channel 70 */ + &phantomInterrupt, /* Channel 71 */ + &phantomInterrupt, /* Channel 72 */ + &phantomInterrupt, /* Channel 73 */ + &phantomInterrupt, /* Channel 74 */ + &phantomInterrupt, /* Channel 75 */ + &phantomInterrupt, /* Channel 76 */ + &phantomInterrupt, /* Channel 77 */ + &phantomInterrupt, /* Channel 78 */ + &phantomInterrupt, /* Channel 79 */ + &phantomInterrupt, /* Channel 80 */ + &phantomInterrupt, /* Channel 81 */ + &phantomInterrupt, /* Channel 82 */ + &phantomInterrupt, /* Channel 83 */ + &phantomInterrupt, /* Channel 84 */ + &phantomInterrupt, /* Channel 85 */ + &phantomInterrupt, /* Channel 86 */ + &phantomInterrupt, /* Channel 87 */ + &phantomInterrupt, /* Channel 88 */ + &phantomInterrupt, /* Channel 89 */ + &phantomInterrupt, /* Channel 90 */ + &phantomInterrupt, /* Channel 91 */ + &phantomInterrupt, /* Channel 92 */ + &phantomInterrupt, /* Channel 93 */ + &phantomInterrupt, /* Channel 94 */ + &phantomInterrupt, /* Channel 95 */ + &phantomInterrupt, /* Channel 96 */ + &phantomInterrupt, /* Channel 97 */ + &phantomInterrupt, /* Channel 98 */ + &phantomInterrupt, /* Channel 99 */ + &phantomInterrupt, /* Channel 100 */ + &phantomInterrupt, /* Channel 101 */ + &phantomInterrupt, /* Channel 102 */ + &phantomInterrupt, /* Channel 103 */ + &phantomInterrupt, /* Channel 104 */ + &phantomInterrupt, /* Channel 105 */ + &phantomInterrupt, /* Channel 106 */ + &phantomInterrupt, /* Channel 107 */ + &phantomInterrupt, /* Channel 108 */ + &phantomInterrupt, /* Channel 109 */ + &phantomInterrupt, /* Channel 110 */ + &phantomInterrupt, /* Channel 111 */ + &phantomInterrupt, /* Channel 112 */ + &phantomInterrupt, /* Channel 113 */ + &phantomInterrupt, /* Channel 114 */ + &phantomInterrupt, /* Channel 115 */ + &phantomInterrupt, /* Channel 116 */ + &phantomInterrupt, /* Channel 117 */ + &phantomInterrupt, /* Channel 118 */ + &phantomInterrupt, /* Channel 119 */ + &phantomInterrupt, /* Channel 120 */ + &phantomInterrupt, /* Channel 121 */ + &phantomInterrupt, /* Channel 122 */ + &phantomInterrupt, /* Channel 123 */ + &phantomInterrupt, /* Channel 124 */ + &phantomInterrupt, /* Channel 125 */ + &phantomInterrupt, /* Channel 126 */ +}; +void vimParityErrorHandler(void); + +/** @fn void vimInit(void) +* @brief Initializes VIM module +* +* This function initializes VIM RAM and registers +*/ +/* SourceId : VIM_SourceId_001 */ +/* DesignId : VIM_DesignId_001 */ +/* Requirements : HL_SR100 */ +void vimInit(void) +{ + /* VIM RAM Parity Enable */ + VIM_PARCTL = 0xAU; + + /* Initialize VIM table */ + { + uint32 i; + + for (i = 0U; i < VIM_CHANNELS; i++) + { + vimRAM->ISR[i] = s_vim_init[i]; + } + } + + /* Set Fall-Back Address Parity Error Register */ + /*SAFETYMCUSW 439 S MR:11.3 <APPROVED> " Need to store the address of a function in a 32 bit register - Advisory as per MISRA" */ + VIM_FBPARERR = (uint32)&vimParityErrorHandler; + + /* set IRQ/FIQ priorities */ + vimREG->FIRQPR0 = (uint32)((uint32)SYS_FIQ << 0U) + | (uint32)((uint32)SYS_FIQ << 1U) + | (uint32)((uint32)SYS_IRQ << 2U) + | (uint32)((uint32)SYS_IRQ << 3U) + | (uint32)((uint32)SYS_IRQ << 4U) + | (uint32)((uint32)SYS_IRQ << 5U) + | (uint32)((uint32)SYS_IRQ << 6U) + | (uint32)((uint32)SYS_IRQ << 7U) + | (uint32)((uint32)SYS_IRQ << 8U) + | (uint32)((uint32)SYS_IRQ << 9U) + | (uint32)((uint32)SYS_IRQ << 10U) + | (uint32)((uint32)SYS_IRQ << 11U) + | (uint32)((uint32)SYS_IRQ << 12U) + | (uint32)((uint32)SYS_IRQ << 13U) + | (uint32)((uint32)SYS_IRQ << 14U) + | (uint32)((uint32)SYS_IRQ << 15U) + | (uint32)((uint32)SYS_IRQ << 16U) + | (uint32)((uint32)SYS_IRQ << 17U) + | (uint32)((uint32)SYS_IRQ << 18U) + | (uint32)((uint32)SYS_IRQ << 19U) + | (uint32)((uint32)SYS_IRQ << 20U) + | (uint32)((uint32)SYS_IRQ << 21U) + | (uint32)((uint32)SYS_IRQ << 22U) + | (uint32)((uint32)SYS_IRQ << 23U) + | (uint32)((uint32)SYS_IRQ << 24U) + | (uint32)((uint32)SYS_IRQ << 25U) + | (uint32)((uint32)SYS_IRQ << 26U) + | (uint32)((uint32)SYS_IRQ << 27U) + | (uint32)((uint32)SYS_IRQ << 28U) + | (uint32)((uint32)SYS_IRQ << 29U) + | (uint32)((uint32)SYS_IRQ << 30U) + | (uint32)((uint32)SYS_IRQ << 31U); + + vimREG->FIRQPR1 = (uint32)((uint32)SYS_IRQ << 0U) + | (uint32)((uint32)SYS_IRQ << 1U) + | (uint32)((uint32)SYS_IRQ << 2U) + | (uint32)((uint32)SYS_IRQ << 3U) + | (uint32)((uint32)SYS_IRQ << 4U) + | (uint32)((uint32)SYS_IRQ << 5U) + | (uint32)((uint32)SYS_IRQ << 6U) + | (uint32)((uint32)SYS_IRQ << 7U) + | (uint32)((uint32)SYS_IRQ << 8U) + | (uint32)((uint32)SYS_IRQ << 9U) + | (uint32)((uint32)SYS_IRQ << 10U) + | (uint32)((uint32)SYS_IRQ << 11U) + | (uint32)((uint32)SYS_IRQ << 12U) + | (uint32)((uint32)SYS_IRQ << 13U) + | (uint32)((uint32)SYS_IRQ << 14U) + | (uint32)((uint32)SYS_IRQ << 15U) + | (uint32)((uint32)SYS_IRQ << 16U) + | (uint32)((uint32)SYS_IRQ << 17U) + | (uint32)((uint32)SYS_IRQ << 18U) + | (uint32)((uint32)SYS_IRQ << 19U) + | (uint32)((uint32)SYS_IRQ << 20U) + | (uint32)((uint32)SYS_IRQ << 21U) + | (uint32)((uint32)SYS_IRQ << 22U) + | (uint32)((uint32)SYS_IRQ << 23U) + | (uint32)((uint32)SYS_IRQ << 24U) + | (uint32)((uint32)SYS_IRQ << 25U) + | (uint32)((uint32)SYS_IRQ << 26U) + | (uint32)((uint32)SYS_IRQ << 27U) + | (uint32)((uint32)SYS_IRQ << 28U) + | (uint32)((uint32)SYS_IRQ << 29U) + | (uint32)((uint32)SYS_IRQ << 30U) + | (uint32)((uint32)SYS_IRQ << 31U); + + + vimREG->FIRQPR2 = (uint32)((uint32)SYS_IRQ << 0U) + | (uint32)((uint32)SYS_IRQ << 1U) + | (uint32)((uint32)SYS_IRQ << 2U) + | (uint32)((uint32)SYS_IRQ << 3U) + | (uint32)((uint32)SYS_IRQ << 4U) + | (uint32)((uint32)SYS_IRQ << 5U) + | (uint32)((uint32)SYS_IRQ << 6U) + | (uint32)((uint32)SYS_IRQ << 7U) + | (uint32)((uint32)SYS_IRQ << 8U) + | (uint32)((uint32)SYS_IRQ << 9U) + | (uint32)((uint32)SYS_IRQ << 10U) + | (uint32)((uint32)SYS_IRQ << 11U) + | (uint32)((uint32)SYS_IRQ << 12U) + | (uint32)((uint32)SYS_IRQ << 13U) + | (uint32)((uint32)SYS_IRQ << 14U) + | (uint32)((uint32)SYS_IRQ << 15U) + | (uint32)((uint32)SYS_IRQ << 16U) + | (uint32)((uint32)SYS_IRQ << 17U) + | (uint32)((uint32)SYS_IRQ << 18U) + | (uint32)((uint32)SYS_IRQ << 19U) + | (uint32)((uint32)SYS_IRQ << 20U) + | (uint32)((uint32)SYS_IRQ << 21U) + | (uint32)((uint32)SYS_IRQ << 22U) + | (uint32)((uint32)SYS_IRQ << 23U) + | (uint32)((uint32)SYS_IRQ << 24U) + | (uint32)((uint32)SYS_IRQ << 25U) + | (uint32)((uint32)SYS_IRQ << 26U) + | (uint32)((uint32)SYS_IRQ << 27U) + | (uint32)((uint32)SYS_IRQ << 28U) + | (uint32)((uint32)SYS_IRQ << 29U) + | (uint32)((uint32)SYS_IRQ << 30U) + | (uint32)((uint32)SYS_IRQ << 31U); + + vimREG->FIRQPR3 = (uint32)((uint32)SYS_IRQ << 0U) + | (uint32)((uint32)SYS_IRQ << 1U) + | (uint32)((uint32)SYS_IRQ << 2U) + | (uint32)((uint32)SYS_IRQ << 3U) + | (uint32)((uint32)SYS_IRQ << 4U) + | (uint32)((uint32)SYS_IRQ << 5U) + | (uint32)((uint32)SYS_IRQ << 6U) + | (uint32)((uint32)SYS_IRQ << 7U) + | (uint32)((uint32)SYS_IRQ << 8U) + | (uint32)((uint32)SYS_IRQ << 9U) + | (uint32)((uint32)SYS_IRQ << 10U) + | (uint32)((uint32)SYS_IRQ << 11U) + | (uint32)((uint32)SYS_IRQ << 12U) + | (uint32)((uint32)SYS_IRQ << 13U) + | (uint32)((uint32)SYS_IRQ << 14U) + | (uint32)((uint32)SYS_IRQ << 15U) + | (uint32)((uint32)SYS_IRQ << 16U) + | (uint32)((uint32)SYS_IRQ << 17U) + | (uint32)((uint32)SYS_IRQ << 18U) + | (uint32)((uint32)SYS_IRQ << 19U) + | (uint32)((uint32)SYS_IRQ << 20U) + | (uint32)((uint32)SYS_IRQ << 21U) + | (uint32)((uint32)SYS_IRQ << 22U) + | (uint32)((uint32)SYS_IRQ << 23U) + | (uint32)((uint32)SYS_IRQ << 24U) + | (uint32)((uint32)SYS_IRQ << 25U) + | (uint32)((uint32)SYS_IRQ << 26U) + | (uint32)((uint32)SYS_IRQ << 27U) + | (uint32)((uint32)SYS_IRQ << 28U) + | (uint32)((uint32)SYS_IRQ << 29U) + | (uint32)((uint32)SYS_IRQ << 30U) + | (uint32)((uint32)SYS_IRQ << 31U); + + + /* enable interrupts */ + vimREG->REQMASKSET0 = (uint32)((uint32)1U << 0U) + | (uint32)((uint32)1U << 1U) + | (uint32)((uint32)1U << 2U) + | (uint32)((uint32)1U << 3U) + | (uint32)((uint32)1U << 4U) + | (uint32)((uint32)1U << 5U) + | (uint32)((uint32)0U << 6U) + | (uint32)((uint32)0U << 7U) + | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)0U << 9U) + | (uint32)((uint32)0U << 10U) + | (uint32)((uint32)0U << 11U) + | (uint32)((uint32)0U << 12U) + | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)0U << 15U) + | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)0U << 17U) + | (uint32)((uint32)0U << 18U) + | (uint32)((uint32)0U << 19U) + | (uint32)((uint32)1U << 20U) + | (uint32)((uint32)0U << 21U) + | (uint32)((uint32)0U << 22U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 25U) + | (uint32)((uint32)0U << 26U) + | (uint32)((uint32)0U << 27U) + | (uint32)((uint32)0U << 28U) + | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)0U << 30U) + | (uint32)((uint32)0U << 31U); + + vimREG->REQMASKSET1 = (uint32)((uint32)0U << 0U) + | (uint32)((uint32)0U << 1U) + | (uint32)((uint32)0U << 2U) + | (uint32)((uint32)0U << 3U) + | (uint32)((uint32)0U << 4U) + | (uint32)((uint32)0U << 5U) + | (uint32)((uint32)0U << 6U) + | (uint32)((uint32)0U << 7U) + | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)0U << 9U) + | (uint32)((uint32)0U << 10U) + | (uint32)((uint32)0U << 11U) + | (uint32)((uint32)0U << 12U) + | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)0U << 15U) + | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)0U << 17U) + | (uint32)((uint32)0U << 18U) + | (uint32)((uint32)0U << 19U) + | (uint32)((uint32)0U << 20U) + | (uint32)((uint32)0U << 21U) + | (uint32)((uint32)0U << 22U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 25U) + | (uint32)((uint32)0U << 26U) + | (uint32)((uint32)0U << 27U) + | (uint32)((uint32)0U << 28U) + | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)0U << 30U) + | (uint32)((uint32)0U << 31U); + + vimREG->REQMASKSET2 = (uint32)((uint32)0U << 0U) + | (uint32)((uint32)0U << 1U) + | (uint32)((uint32)0U << 2U) + | (uint32)((uint32)0U << 3U) + | (uint32)((uint32)0U << 4U) + | (uint32)((uint32)0U << 5U) + | (uint32)((uint32)0U << 6U) + | (uint32)((uint32)0U << 7U) + | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)0U << 9U) + | (uint32)((uint32)0U << 10U) + | (uint32)((uint32)0U << 11U) + | (uint32)((uint32)0U << 12U) + | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)0U << 15U) + | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)0U << 17U) + | (uint32)((uint32)0U << 18U) + | (uint32)((uint32)0U << 19U) + | (uint32)((uint32)0U << 20U) + | (uint32)((uint32)0U << 21U) + | (uint32)((uint32)0U << 22U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 25U) + | (uint32)((uint32)0U << 26U) + | (uint32)((uint32)0U << 27U) + | (uint32)((uint32)0U << 28U) + | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)0U << 30U) + | (uint32)((uint32)0U << 31U); + + vimREG->REQMASKSET3 = (uint32)((uint32)0U << 0U) + | (uint32)((uint32)0U << 1U) + | (uint32)((uint32)0U << 2U) + | (uint32)((uint32)0U << 3U) + | (uint32)((uint32)0U << 4U) + | (uint32)((uint32)0U << 5U) + | (uint32)((uint32)0U << 6U) + | (uint32)((uint32)0U << 7U) + | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)0U << 9U) + | (uint32)((uint32)0U << 10U) + | (uint32)((uint32)0U << 11U) + | (uint32)((uint32)0U << 12U) + | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)0U << 15U) + | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)0U << 17U) + | (uint32)((uint32)0U << 18U) + | (uint32)((uint32)0U << 19U) + | (uint32)((uint32)0U << 20U) + | (uint32)((uint32)0U << 21U) + | (uint32)((uint32)0U << 22U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 25U) + | (uint32)((uint32)0U << 26U) + | (uint32)((uint32)0U << 27U) + | (uint32)((uint32)0U << 28U) + | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)0U << 30U) + | (uint32)((uint32)0U << 31U); + + /* Set Capture event sources */ + vimREG->CAPEVT = ((uint32)((uint32)0U << 0U) + |(uint32)((uint32)0U << 16U)); +} + +/** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler) +* @brief Map selected interrupt request to the selected channel +* +* @param[in] request: Interrupt request number 2..127 +* @param[in] channel: VIM Channel number 2..127 +* @param[in] handler: Address of the interrupt handler +* +* This function will map selected interrupt request to the selected channel. +* +*/ +/* SourceId : VIM_SourceId_002 */ +/* DesignId : VIM_DesignId_002 */ +/* Requirements : HL_SR101 */ +void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler) +{ + uint32 i,j; + i = channel >> 2U; /* Find the register to configure */ + j = channel - (i << 2U); /* Find the offset of the type */ + j = 3U - j; /* reverse the byte order */ + j = j << 3U; /* find the bit location */ + + /*Mapping the required interrupt request to the required channel*/ + vimREG->CHANCTRL[i] &= ~(uint32)((uint32)0xFFU << j); + vimREG->CHANCTRL[i] |= (request << j); + + /*Updating VIMRAM*/ + vimRAM->ISR[channel + 1U] = handler; +} + +/** @fn void vimEnableInterrupt(uint32 channel, boolean inttype) +* @brief Enable interrupt for the the selected channel +* +* @param[in] channel: VIM Channel number 2..127 +* @param[in] inttype: Interrupt type +* - SYS_IRQ: Selected channel will be enabled as IRQ +* - SYS_FIQ: Selected channel will be enabled as FIQ +* +* This function will enable interrupt for the selected channel. +* +*/ +/* SourceId : VIM_SourceId_003 */ +/* DesignId : VIM_DesignId_003 */ +/* Requirements : HL_SR102 */ +void vimEnableInterrupt(uint32 channel, systemInterrupt_t inttype) +{ + if (channel >= 96U) + { + if(inttype == SYS_IRQ) + { + vimREG->FIRQPR3 &= ~(uint32)((uint32)1U << (channel-96U)); + } + else + { + vimREG->FIRQPR3 |= ((uint32)1U << (channel-96U)); + } + vimREG->REQMASKSET3 = (uint32)1U << (channel-96U); + } + else if (channel >= 64U) + { + if(inttype == SYS_IRQ) + { + vimREG->FIRQPR2 &= ~(uint32)((uint32)1U << (channel-64U)); + } + else + { + vimREG->FIRQPR2 |= ((uint32)1U << (channel-64U)); + } + vimREG->REQMASKSET2 = (uint32)1U << (channel-64U); + } + else if (channel >= 32U) + { + if(inttype == SYS_IRQ) + { + vimREG->FIRQPR1 &= ~(uint32)((uint32)1U << (channel-32U)); + } + else + { + vimREG->FIRQPR1 |= ((uint32)1U << (channel-32U)); + } + vimREG->REQMASKSET1 = (uint32)1U << (channel-32U); + } + else if (channel >= 2U) + { + if(inttype == SYS_IRQ) + { + vimREG->FIRQPR0 &= ~(uint32)((uint32)1U << channel); + } + else + { + vimREG->FIRQPR0 |= ((uint32)1U << channel); + } + vimREG->REQMASKSET0 = (uint32)1U << channel; + } + else + { + /* Empty */ + } +} + +/** @fn void vimDisableInterrupt(uint32 channel) +* @brief Disable interrupt for the the selected channel +* +* @param[in] channel: VIM Channel number 2..127 +* +* This function will disable interrupt for the selected channel. +* +*/ +/* SourceId : VIM_SourceId_004 */ +/* DesignId : VIM_DesignId_004 */ +/* Requirements : HL_SR103 */ +void vimDisableInterrupt(uint32 channel) +{ + if (channel >= 96U) + { + vimREG->REQMASKCLR3 = (uint32)1U << (channel-96U); + } + else if (channel >= 64U) + { + vimREG->REQMASKCLR2 = (uint32)1U << (channel-64U); + } + else if (channel >=32U) + { + vimREG->REQMASKCLR1 = (uint32)1U << (channel-32U); + } + else if (channel >= 2U) + { + vimREG->REQMASKCLR0 = (uint32)1U << channel; + } + else + { + /* Empty */ + } +} + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') of the configuration +* registers to the struct pointed by config_reg +* +*/ +/* SourceId : VIM_SourceId_005 */ +/* DesignId : VIM_DesignId_005 */ +/* Requirements : HL_SR104 */ +void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE; + config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE; + config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE; + config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE; + config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[0U] = VIM_CHANCTRL0_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[1U] = VIM_CHANCTRL1_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[2U] = VIM_CHANCTRL2_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[3U] = VIM_CHANCTRL3_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[4U] = VIM_CHANCTRL4_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[5U] = VIM_CHANCTRL5_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[6U] = VIM_CHANCTRL6_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[7U] = VIM_CHANCTRL7_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[8U] = VIM_CHANCTRL8_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[9U] = VIM_CHANCTRL9_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[10U] = VIM_CHANCTRL10_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[11U] = VIM_CHANCTRL11_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[12U] = VIM_CHANCTRL12_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[13U] = VIM_CHANCTRL13_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[14U] = VIM_CHANCTRL14_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[15U] = VIM_CHANCTRL15_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[16U] = VIM_CHANCTRL16_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[17U] = VIM_CHANCTRL17_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[18U] = VIM_CHANCTRL18_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[19U] = VIM_CHANCTRL19_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[20U] = VIM_CHANCTRL20_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[21U] = VIM_CHANCTRL21_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[22U] = VIM_CHANCTRL22_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[23U] = VIM_CHANCTRL23_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[24U] = VIM_CHANCTRL24_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[25U] = VIM_CHANCTRL25_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[26U] = VIM_CHANCTRL26_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[27U] = VIM_CHANCTRL27_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[28U] = VIM_CHANCTRL28_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[29U] = VIM_CHANCTRL29_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[30U] = VIM_CHANCTRL30_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[31U] = VIM_CHANCTRL31_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0; + config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1; + config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2; + config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3; + config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0; + config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1; + config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2; + config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3; + config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0; + config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1; + config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2; + config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3; + config_reg->CONFIG_CAPEVT = vimREG->CAPEVT; + config_reg->CONFIG_CHANCTRL[0U] = vimREG->CHANCTRL[0U]; + config_reg->CONFIG_CHANCTRL[1U] = vimREG->CHANCTRL[1U]; + config_reg->CONFIG_CHANCTRL[2U] = vimREG->CHANCTRL[2U]; + config_reg->CONFIG_CHANCTRL[3U] = vimREG->CHANCTRL[3U]; + config_reg->CONFIG_CHANCTRL[4U] = vimREG->CHANCTRL[4U]; + config_reg->CONFIG_CHANCTRL[5U] = vimREG->CHANCTRL[5U]; + config_reg->CONFIG_CHANCTRL[6U] = vimREG->CHANCTRL[6U]; + config_reg->CONFIG_CHANCTRL[7U] = vimREG->CHANCTRL[7U]; + config_reg->CONFIG_CHANCTRL[8U] = vimREG->CHANCTRL[8U]; + config_reg->CONFIG_CHANCTRL[9U] = vimREG->CHANCTRL[9U]; + config_reg->CONFIG_CHANCTRL[10U] = vimREG->CHANCTRL[10U]; + config_reg->CONFIG_CHANCTRL[11U] = vimREG->CHANCTRL[11U]; + config_reg->CONFIG_CHANCTRL[12U] = vimREG->CHANCTRL[12U]; + config_reg->CONFIG_CHANCTRL[13U] = vimREG->CHANCTRL[13U]; + config_reg->CONFIG_CHANCTRL[14U] = vimREG->CHANCTRL[14U]; + config_reg->CONFIG_CHANCTRL[15U] = vimREG->CHANCTRL[15U]; + config_reg->CONFIG_CHANCTRL[16U] = vimREG->CHANCTRL[16U]; + config_reg->CONFIG_CHANCTRL[17U] = vimREG->CHANCTRL[17U]; + config_reg->CONFIG_CHANCTRL[18U] = vimREG->CHANCTRL[18U]; + config_reg->CONFIG_CHANCTRL[19U] = vimREG->CHANCTRL[19U]; + config_reg->CONFIG_CHANCTRL[20U] = vimREG->CHANCTRL[20U]; + config_reg->CONFIG_CHANCTRL[21U] = vimREG->CHANCTRL[21U]; + config_reg->CONFIG_CHANCTRL[22U] = vimREG->CHANCTRL[22U]; + config_reg->CONFIG_CHANCTRL[23U] = vimREG->CHANCTRL[23U]; + config_reg->CONFIG_CHANCTRL[24U] = vimREG->CHANCTRL[24U]; + config_reg->CONFIG_CHANCTRL[25U] = vimREG->CHANCTRL[25U]; + config_reg->CONFIG_CHANCTRL[26U] = vimREG->CHANCTRL[26U]; + config_reg->CONFIG_CHANCTRL[27U] = vimREG->CHANCTRL[27U]; + config_reg->CONFIG_CHANCTRL[28U] = vimREG->CHANCTRL[28U]; + config_reg->CONFIG_CHANCTRL[29U] = vimREG->CHANCTRL[29U]; + config_reg->CONFIG_CHANCTRL[30U] = vimREG->CHANCTRL[30U]; + config_reg->CONFIG_CHANCTRL[31U] = vimREG->CHANCTRL[31U]; + } +} + + +#pragma CODE_STATE(vimParityErrorHandler, 32) +#pragma INTERRUPT(vimParityErrorHandler, IRQ) +#pragma WEAK(vimParityErrorHandler) + +/* SourceId : VIM_SourceId_006 */ +/* DesignId : VIM_DesignId_006 */ +/* Requirements : HL_SR105 */ +void vimParityErrorHandler(void) +{ + uint32 vec; + + /* Identify the corrupted address */ + uint32 error_addr = VIM_ADDERR; + + /* Identify the channel number */ + uint32 error_channel = ((error_addr & 0x1FFU) >> 2U); + + /* Correct the corrupted location */ + vimRAM->ISR[error_channel] = s_vim_init[error_channel]; + + /* Clear Parity Error Flag */ + VIM_PARFLG = 1U; + + /* Disable and enable the highest priority pending channel */ + if (vimREG->FIQINDEX != 0U) + { + vec = vimREG->FIQINDEX - 1U; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Read 32 bit volatile register" */ + vec = vimREG->IRQINDEX - 1U; + } + if(vec == 0U) + { + vimREG->INTREQ0 = 1U; + vec = esmREG->IOFFHR - 1U; + + if (vec < 32U) + { + esmREG->SR1[0U] = (uint32)1U << vec; + esmGroup1Notification(vec); + } + else if (vec < 64U) + { + esmREG->SR1[1U] = (uint32)1U << (vec-32U); + esmGroup2Notification(vec-32U); + } + else if (vec < 96U) + { + esmREG->SR4[0U] = (uint32)1U << (vec-64U); + esmGroup1Notification(vec-32U); + } + else + { + esmREG->SR4[1U] = (uint32)1U << (vec-96U); + esmGroup2Notification(vec-64U); + } + } + else if (vec < 32U) + { + vimREG->REQMASKCLR0 = (uint32)1U << vec; + vimREG->REQMASKSET0 = (uint32)1U << vec; + } + else if (vec < 64U) + { + vimREG->REQMASKCLR1 = (uint32)1U << (vec-32U); + vimREG->REQMASKSET1 = (uint32)1U << (vec-32U); + } + else if(vec < 96U) + { + vimREG->REQMASKCLR2 = (uint32)1U << (vec-64U); + vimREG->REQMASKSET2 = (uint32)1U << (vec-64U); + } + else + { + vimREG->REQMASKCLR3 = (uint32)1U << (vec-96U); + vimREG->REQMASKSET3 = (uint32)1U << (vec-96U); + } +} diff --git a/src/arch/rm46l8lp/halcogen/system.c b/src/arch/rm46l8lp/halcogen/system.c new file mode 100644 index 0000000..94e976d --- /dev/null +++ b/src/arch/rm46l8lp/halcogen/system.c @@ -0,0 +1,681 @@ +/** @file system.c +* @brief System Driver Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - API Functions +* . +* which are relevant for the System driver. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + + +/* Include Files */ + +#include "system.h" +#include "sys_selftest.h" +#include "sys_pcr.h" +#include "pinmux.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void systemInit(void) +* @brief Initializes System Driver +* +* This function initializes the System driver. +* +*/ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* SourceId : SYSTEM_SourceId_001 */ +/* DesignId : SYSTEM_DesignId_001 */ +/* Requirements : HL_SR451 */ +void setupPLL(void) +{ + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + + /* Disable PLL1 and PLL2 */ + systemREG1->CSDISSET = 0x00000002U | 0x00000040U; + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while((systemREG1->CSDIS & 0x42U) != 0x42U) + { + /* Wait */ + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x301U; + + /** - Configure PLL control registers */ + /** @b Initialize @b Pll1: */ + + /** - Setup pll control register 1: + * - Setup reset on oscillator slip + * - Setup bypass on pll slip + * - setup Pll output clock divider to max before Lock (0x1f + 1 == 32) + * - Setup reset on oscillator fail + * - Setup reference clock divider (5 + 1 == 6) + * - Setup Pll multiplier (0x77 + 1 == 120) + */ + systemREG1->PLLCTL1 = (uint32)0x00000000U + | (uint32)0x20000000U + | (uint32)((uint32)0x1FU << 24U) + | (uint32)0x00000000U + | (uint32)((uint32)(6U - 1U)<< 16U) + | (uint32)(0x7700U); + + /** - Setup pll control register 2 + * - Setup spreading rate + * - Setup bandwidth adjustment + * - Setup internal Pll output divider (1+1 == 2) + * - Setup spreading amount + */ + systemREG1->PLLCTL2 = (uint32)((uint32)255U << 22U) + | (uint32)((uint32)7U << 12U) + | (uint32)((uint32)(2U - 1U) << 9U) + | (uint32)61U; + + /** @b Initialize @b Pll2: */ + + /** - Setup pll2 control register : + * - setup Pll output clock divider to max before Lock + * - Setup reference clock divider + * - Setup internal Pll output divider + * - Setup Pll multiplier + */ + systemREG2->PLLCTL3 = (uint32)((uint32)(2U - 1U) << 29U) + | (uint32)((uint32)0x1FU << 24U) + | (uint32)((uint32)(6U - 1U)<< 16U) + | (uint32)(0x7700U); + + /** - Enable PLL(s) to start up or Lock */ + systemREG1->CSDIS = 0x00000000U + | 0x00000000U + | 0x00000008U + | 0x00000080U + | 0x00000000U + | 0x00000000U + | 0x00000000U; + + // PLL1 output at this point == (oscin / 6) * 120 / (2 * 32) == oscin * 0.3125 +} + +/** @fn void trimLPO(void) +* @brief Initialize LPO trim values +* +* Load TRIM values from OTP if present else call customTrimLPO() function +* +*/ +/* SourceId : SYSTEM_SourceId_002 */ +/* DesignId : SYSTEM_DesignId_002 */ +/* Requirements : HL_SR468 */ +void trimLPO(void) +{ + uint32 u32clocktestConfig; + /* Save user clocktest register configuration */ + u32clocktestConfig = systemREG1->CLKTEST; +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + /*The TRM states OTP TRIM value should be stepped to avoid large changes in the HF LPO clock that would result in a LPOCLKMON fault. At issue is the TRM does not specify what the maximum step is so there is no metric to use for the SW implementation - the routine can temporarily disable the LPOCLKMON range check so the sudden change will not cause a fault.*/ + /* Disable clock range detection*/ + systemREG1->CLKTEST = (systemREG1->CLKTEST + | (uint32)((uint32)0x1U << 24U)) + & (uint32)(~((uint32)0x1U << 25U)); + + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + if(LPO_TRIM_VALUE != 0xFFFFU) + { + + systemREG1->LPOMONCTL = (uint32)((uint32)1U << 24U) + | (uint32)((uint32)LPO_TRIM_VALUE); + } + else + { + + customTrimLPO(); + + } + + /* Restore the user clocktest register value configuration */ + systemREG1->CLKTEST = u32clocktestConfig; + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + +} + +/* SourceId : SYSTEM_SourceId_003 */ +/* DesignId : SYSTEM_DesignId_003 */ +/* Requirements : HL_SR457 */ +void setupFlash(void) +{ + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + /** - Setup flash read mode, address wait states and data wait states */ + flashWREG->FRDCNTL = 0x00000000U + | (uint32)((uint32)3U << 8U) + | (uint32)((uint32)1U << 4U) + | 1U; + + /** - Setup flash access wait states for bank 7 */ + FSM_WR_ENA_HL = 0x5U; + EEPROM_CONFIG_HL = 0x00000002U + | (uint32)((uint32)3U << 16U) ; + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + + /** - Disable write access to flash state machine registers */ + FSM_WR_ENA_HL = 0xAU; + + /** - Setup flash bank power modes */ + flashWREG->FBFALLBACK = 0x00000000U + | (uint32)((uint32)SYS_ACTIVE << 14U) /* BANK 7 */ + | (uint32)((uint32)SYS_ACTIVE << 2U) /* BANK 1 */ + | (uint32)((uint32)SYS_ACTIVE << 0U); /* BANK 0 */ + +/* USER CODE BEGIN (8) */ +/* USER CODE END */ + +} + +/* SourceId : SYSTEM_SourceId_004 */ +/* DesignId : SYSTEM_DesignId_004 */ +/* Requirements : HL_SR470 */ +void periphInit(void) +{ + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + /** - Disable Peripherals before peripheral powerup*/ + systemREG1->CLKCNTL &= 0xFFFFFEFFU; + + /** - Release peripherals from reset and enable clocks to all peripherals */ + /** - Power-up all peripherals */ + pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU; + pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU; + pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU; + pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU; + + /** - Enable Peripherals */ + systemREG1->CLKCNTL |= 0x00000100U; + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +} + +/* SourceId : SYSTEM_SourceId_005 */ +/* DesignId : SYSTEM_DesignId_005 */ +/* Requirements : HL_SR469 */ +void mapClocks(void) +{ + uint32 SYS_CSVSTAT, SYS_CSDIS; + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ + + /** @b Initialize @b Clock @b Tree: */ + /** - Disable / Enable clock domain */ + systemREG1->CDDIS = (uint32)((uint32)0U << 4U ) /* AVCLK1 , 1 - OFF, 0 - ON */ + | (uint32)((uint32)0U << 5U ) /* AVCLK2 , 1 - OFF, 0 - ON */ + | (uint32)((uint32)0U << 8U ) /* VCLK3 , 1 - OFF, 0 - ON */ + | (uint32)((uint32)0U << 9U ) /* VCLK4 , 1 - OFF, 0 - ON */ + | (uint32)((uint32)1U << 10U) /* AVCLK3 , 1 - OFF, 0 - ON */ + | (uint32)((uint32)0U << 11U); /* AVCLK4 , 1 - OFF, 0 - ON */ + + + /* Work Around for Errata SYS#46: + * + * Errata Description: + * Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid + * Workaround: + * Always check the CSDIS register to make sure the clock source is turned on and check + * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock. + */ + /** - Wait for until clocks are locked */ + SYS_CSVSTAT = systemREG1->CSVSTAT; + SYS_CSDIS = systemREG1->CSDIS; + while ((SYS_CSVSTAT & ((SYS_CSDIS ^ 0xFFU) & 0xFFU)) != ((SYS_CSDIS ^ 0xFFU) & 0xFFU)) + { + SYS_CSVSTAT = systemREG1->CSVSTAT; + SYS_CSDIS = systemREG1->CSDIS; + } /* Wait */ + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + + /** - Map device clock domains to desired sources and configure top-level dividers */ + /** - All clock domains are working off the default clock sources until now */ + /** - The below assignments can be easily modified using the HALCoGen GUI */ + + /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */ + systemREG1->GHVSRC = (uint32)((uint32)SYS_OSC << 24U) + | (uint32)((uint32)SYS_OSC << 16U) + | (uint32)((uint32)SYS_PLL1 << 0U); + + /** - Setup RTICLK1 and RTICLK2 clocks */ + systemREG1->RCLKSRC = (uint32)((uint32)1U << 24U) + | (uint32)((uint32)SYS_VCLK << 16U) + | (uint32)((uint32)1U << 8U) + | (uint32)((uint32)SYS_VCLK << 0U); + + /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ + systemREG1->VCLKASRC = (uint32)((uint32)SYS_VCLK << 8U) + | (uint32)((uint32)SYS_VCLK << 0U); + + /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ + systemREG1->CLKCNTL = (systemREG1->CLKCNTL & 0xF0FFFFFFU) + | (uint32)((uint32)1U << 24U); + systemREG1->CLKCNTL = (systemREG1->CLKCNTL & 0xFFF0FFFFU) + | (uint32)((uint32)1U << 16U); + + systemREG2->CLK2CNTL = (systemREG2->CLK2CNTL & 0xFFFFF0F0U) + | (uint32)((uint32)1U << 8U) + | (uint32)((uint32)1U << 0U); + + systemREG2->VCLKACON1 = (uint32)((uint32)(1U - 1U) << 24U) + | (uint32)((uint32)0U << 20U) + | (uint32)((uint32)SYS_VCLK << 16U) + | (uint32)((uint32)(1U - 1U) << 8U) + | (uint32)((uint32)0U << 4U) + | (uint32)((uint32)SYS_VCLK << 0U); + +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + + /* Now the PLLs are locked and the PLL outputs can be sped up */ + /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */ + systemREG1->PLLCTL1 = (systemREG1->PLLCTL1 & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U); + // R = 1 => PLL1 output == (oscin / 6) * 120 / (2 * 1) == oscin * 10 + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + systemREG2->PLLCTL3 = (systemREG2->PLLCTL3 & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U); + + /* Enable/Disable Frequency modulation */ + systemREG1->PLLCTL2 |= 0x00000000U; + +/* USER CODE BEGIN (14) */ +/* USER CODE END */ + +} + +/* SourceId : SYSTEM_SourceId_006 */ +/* DesignId : SYSTEM_DesignId_006 */ +/* Requirements : HL_SR471 */ +void systemInit(void) +{ + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + + /* Configure PLL control registers and enable PLLs. + * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock. + * This initialization sequence performs all the tasks that are not + * required to be done at full application speed while the PLL locks. + */ + setupPLL(); + +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + /* Enable clocks to peripherals and release peripheral reset */ + periphInit(); + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + + /* Configure device-level multiplexing and I/O multiplexing */ + muxInit(); + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ + + /** - Set up flash address and data wait states based on the target CPU clock frequency + * The number of address and data wait states for the target CPU clock frequency are specified + * in the specific part's datasheet. + */ + setupFlash(); + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + + /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */ + trimLPO(); + + + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ + + /** - Wait for PLLs to start up and map clock domains to desired clock sources */ + mapClocks(); + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + + /** - set ECLK pins functional mode */ + systemREG1->SYSPC1 = 0U; + + /** - set ECLK pins default output value */ + systemREG1->SYSPC4 = 0U; + + /** - set ECLK pins output direction */ + systemREG1->SYSPC2 = 1U; + + /** - set ECLK pins open drain enable */ + systemREG1->SYSPC7 = 0U; + + /** - set ECLK pins pullup/pulldown enable */ + systemREG1->SYSPC8 = 0U; + + /** - set ECLK pins pullup/pulldown select */ + systemREG1->SYSPC9 = 1U; + + /** - Setup ECLK */ + systemREG1->ECPCNTL = (uint32)((uint32)0U << 24U) + | (uint32)((uint32)0U << 23U) + | (uint32)((uint32)(8U - 1U) & 0xFFFFU); + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_007 */ +/* DesignId : SYSTEM_DesignId_007 */ +/* Requirements : HL_SR493 */ +void systemPowerDown(uint32 mode) +{ + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ + + /* Disable clock sources */ + systemREG1->CSDISSET = mode & 0x000000FFU; + + /* Disable clock domains */ + systemREG1->CDDIS = (mode >> 8U) & 0x00000FFFU; + + /* Idle CPU */ + _gotoCPUIdle_(); + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ + +} + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + +/** @fn void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : SYSTEM_SourceId_008 */ +/* DesignId : SYSTEM_DesignId_008 */ +/* Requirements : HL_SR506 */ +void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_SYSPC1 = SYS_SYSPC1_CONFIGVALUE; + config_reg->CONFIG_SYSPC2 = SYS_SYSPC2_CONFIGVALUE; + config_reg->CONFIG_SYSPC7 = SYS_SYSPC7_CONFIGVALUE; + config_reg->CONFIG_SYSPC8 = SYS_SYSPC8_CONFIGVALUE; + config_reg->CONFIG_SYSPC9 = SYS_SYSPC9_CONFIGVALUE; + config_reg->CONFIG_CSDIS = SYS_CSDIS_CONFIGVALUE; + config_reg->CONFIG_CDDIS = SYS_CDDIS_CONFIGVALUE; + config_reg->CONFIG_GHVSRC = SYS_GHVSRC_CONFIGVALUE; + config_reg->CONFIG_VCLKASRC = SYS_VCLKASRC_CONFIGVALUE; + config_reg->CONFIG_RCLKSRC = SYS_RCLKSRC_CONFIGVALUE; + config_reg->CONFIG_MSTGCR = SYS_MSTGCR_CONFIGVALUE; + config_reg->CONFIG_MINITGCR = SYS_MINITGCR_CONFIGVALUE; + config_reg->CONFIG_MSINENA = SYS_MSINENA_CONFIGVALUE; + config_reg->CONFIG_PLLCTL1 = SYS_PLLCTL1_CONFIGVALUE_2; + config_reg->CONFIG_PLLCTL2 = SYS_PLLCTL2_CONFIGVALUE; + config_reg->CONFIG_UERFLAG = SYS_UERFLAG_CONFIGVALUE; + /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ + if(LPO_TRIM_VALUE != 0xFFFFU) + { + config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_1; + } + else + { + config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_2; + } + config_reg->CONFIG_CLKTEST = SYS_CLKTEST_CONFIGVALUE; + config_reg->CONFIG_DFTCTRLREG1 = SYS_DFTCTRLREG1_CONFIGVALUE; + config_reg->CONFIG_DFTCTRLREG2 = SYS_DFTCTRLREG2_CONFIGVALUE; + config_reg->CONFIG_GPREG1 = SYS_GPREG1_CONFIGVALUE; + config_reg->CONFIG_RAMGCR = SYS_RAMGCR_CONFIGVALUE; + config_reg->CONFIG_BMMCR1 = SYS_BMMCR1_CONFIGVALUE; + config_reg->CONFIG_MMUGCR = SYS_MMUGCR_CONFIGVALUE; + config_reg->CONFIG_CLKCNTL = SYS_CLKCNTL_CONFIGVALUE; + config_reg->CONFIG_ECPCNTL = SYS_ECPCNTL_CONFIGVALUE; + config_reg->CONFIG_DEVCR1 = SYS_DEVCR1_CONFIGVALUE; + config_reg->CONFIG_SYSECR = SYS_SYSECR_CONFIGVALUE; + + config_reg->CONFIG_PLLCTL3 = SYS2_PLLCTL3_CONFIGVALUE_2; + config_reg->CONFIG_STCCLKDIV = SYS2_STCCLKDIV_CONFIGVALUE; + config_reg->CONFIG_CLK2CNTL = SYS2_CLK2CNTL_CONFIGVALUE; + config_reg->CONFIG_VCLKACON1 = SYS2_VCLKACON1_CONFIGVALUE; + config_reg->CONFIG_CLKSLIP = SYS2_CLKSLIP_CONFIGVALUE; + config_reg->CONFIG_EFC_CTLEN = SYS2_EFC_CTLEN_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_SYSPC1 = systemREG1->SYSPC1; + config_reg->CONFIG_SYSPC2 = systemREG1->SYSPC2; + config_reg->CONFIG_SYSPC7 = systemREG1->SYSPC7; + config_reg->CONFIG_SYSPC8 = systemREG1->SYSPC8; + config_reg->CONFIG_SYSPC9 = systemREG1->SYSPC9; + config_reg->CONFIG_CSDIS = systemREG1->CSDIS; + config_reg->CONFIG_CDDIS = systemREG1->CDDIS; + config_reg->CONFIG_GHVSRC = systemREG1->GHVSRC; + config_reg->CONFIG_VCLKASRC = systemREG1->VCLKASRC; + config_reg->CONFIG_RCLKSRC = systemREG1->RCLKSRC; + config_reg->CONFIG_MSTGCR = systemREG1->MSTGCR; + config_reg->CONFIG_MINITGCR = systemREG1->MINITGCR; + config_reg->CONFIG_MSINENA = systemREG1->MSINENA; + config_reg->CONFIG_PLLCTL1 = systemREG1->PLLCTL1; + config_reg->CONFIG_PLLCTL2 = systemREG1->PLLCTL2; + config_reg->CONFIG_UERFLAG = systemREG1->SYSPC10; + config_reg->CONFIG_LPOMONCTL = systemREG1->LPOMONCTL; + config_reg->CONFIG_CLKTEST = systemREG1->CLKTEST; + config_reg->CONFIG_DFTCTRLREG1 = systemREG1->DFTCTRLREG1; + config_reg->CONFIG_DFTCTRLREG2 = systemREG1->DFTCTRLREG2; + config_reg->CONFIG_GPREG1 = systemREG1->GPREG1; + config_reg->CONFIG_RAMGCR = systemREG1->RAMGCR; + config_reg->CONFIG_BMMCR1 = systemREG1->BMMCR1; + config_reg->CONFIG_MMUGCR = systemREG1->CPURSTCR; + config_reg->CONFIG_CLKCNTL = systemREG1->CLKCNTL; + config_reg->CONFIG_ECPCNTL = systemREG1->ECPCNTL; + config_reg->CONFIG_DEVCR1 = systemREG1->DEVCR1; + config_reg->CONFIG_SYSECR = systemREG1->SYSECR; + + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_PLLCTL3 = systemREG2->PLLCTL3; + config_reg->CONFIG_STCCLKDIV = systemREG2->STCCLKDIV; + config_reg->CONFIG_CLK2CNTL = systemREG2->CLK2CNTL; + config_reg->CONFIG_VCLKACON1 = systemREG2->VCLKACON1; + config_reg->CONFIG_CLKSLIP = systemREG2->CLKSLIP; + config_reg->CONFIG_EFC_CTLEN = systemREG2->EFC_CTLEN; + } +} + +/** @fn void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : SYSTEM_SourceId_009 */ +/* DesignId : SYSTEM_DesignId_009 */ +/* Requirements : HL_SR506 */ +void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_FRDCNTL = TCMFLASH_FRDCNTL_CONFIGVALUE; + config_reg->CONFIG_FEDACCTRL1 = TCMFLASH_FEDACCTRL1_CONFIGVALUE; + config_reg->CONFIG_FEDACCTRL2 = TCMFLASH_FEDACCTRL2_CONFIGVALUE; + config_reg->CONFIG_FEDACSDIS = TCMFLASH_FEDACSDIS_CONFIGVALUE; + config_reg->CONFIG_FBPROT = TCMFLASH_FBPROT_CONFIGVALUE; + config_reg->CONFIG_FBSE = TCMFLASH_FBSE_CONFIGVALUE; + config_reg->CONFIG_FBAC = TCMFLASH_FBAC_CONFIGVALUE; + config_reg->CONFIG_FBFALLBACK = TCMFLASH_FBFALLBACK_CONFIGVALUE; + config_reg->CONFIG_FPAC1 = TCMFLASH_FPAC1_CONFIGVALUE; + config_reg->CONFIG_FPAC2 = TCMFLASH_FPAC2_CONFIGVALUE; + config_reg->CONFIG_FMAC = TCMFLASH_FMAC_CONFIGVALUE; + config_reg->CONFIG_FLOCK = TCMFLASH_FLOCK_CONFIGVALUE; + config_reg->CONFIG_FDIAGCTRL = TCMFLASH_FDIAGCTRL_CONFIGVALUE; + config_reg->CONFIG_FEDACSDIS2 = TCMFLASH_FEDACSDIS2_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_FRDCNTL = flashWREG->FRDCNTL; + config_reg->CONFIG_FEDACCTRL1 = flashWREG->FEDACCTRL1; + config_reg->CONFIG_FEDACCTRL2 = flashWREG->FEDACCTRL2; + config_reg->CONFIG_FEDACSDIS = flashWREG->FEDACSDIS; + config_reg->CONFIG_FBPROT = flashWREG->FBPROT; + config_reg->CONFIG_FBSE = flashWREG->FBSE; + config_reg->CONFIG_FBAC = flashWREG->FBAC; + config_reg->CONFIG_FBFALLBACK = flashWREG->FBFALLBACK; + config_reg->CONFIG_FPAC1 = flashWREG->FPAC1; + config_reg->CONFIG_FPAC2 = flashWREG->FPAC2; + config_reg->CONFIG_FMAC = flashWREG->FMAC; + config_reg->CONFIG_FLOCK = flashWREG->FLOCK; + config_reg->CONFIG_FDIAGCTRL = flashWREG->FDIAGCTRL; + config_reg->CONFIG_FEDACSDIS2 = flashWREG->FEDACSDIS2; + } +} + + + +/** @fn void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : SYSTEM_SourceId_010 */ +/* DesignId : SYSTEM_DesignId_010 */ +/* Requirements : HL_SR506 */ +void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_RAMCTRL[0U] = SRAM_RAMCTRL_CONFIGVALUE; + config_reg->CONFIG_RAMTHRESHOLD[0U] = SRAM_RAMTHRESHOLD_CONFIGVALUE; + config_reg->CONFIG_RAMINTCTRL[0U] = SRAM_RAMINTCTRL_CONFIGVALUE; + config_reg->CONFIG_RAMTEST[0U] = SRAM_RAMTEST_CONFIGVALUE; + config_reg->CONFIG_RAMADDRDECVECT[0U] = SRAM_RAMADDRDECVECT_CONFIGVALUE; + + config_reg->CONFIG_RAMCTRL[1U] = SRAM_RAMCTRL_CONFIGVALUE; + config_reg->CONFIG_RAMTHRESHOLD[1U] = SRAM_RAMTHRESHOLD_CONFIGVALUE; + config_reg->CONFIG_RAMINTCTRL[1U] = SRAM_RAMINTCTRL_CONFIGVALUE; + config_reg->CONFIG_RAMTEST[1U] = SRAM_RAMTEST_CONFIGVALUE; + config_reg->CONFIG_RAMADDRDECVECT[1U] = SRAM_RAMADDRDECVECT_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_RAMCTRL[0U] = tcram1REG->RAMCTRL; + config_reg->CONFIG_RAMTHRESHOLD[0U] = tcram1REG->RAMTHRESHOLD; + config_reg->CONFIG_RAMINTCTRL[0U] = tcram1REG->RAMINTCTRL; + config_reg->CONFIG_RAMTEST[0U] = tcram1REG->RAMTEST; + config_reg->CONFIG_RAMADDRDECVECT[0U] = tcram1REG->RAMADDRDECVECT; + + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + config_reg->CONFIG_RAMCTRL[1U] = tcram2REG->RAMCTRL; + config_reg->CONFIG_RAMTHRESHOLD[1U] = tcram2REG->RAMTHRESHOLD; + config_reg->CONFIG_RAMINTCTRL[1U] = tcram2REG->RAMINTCTRL; + config_reg->CONFIG_RAMTEST[1U] = tcram2REG->RAMTEST; + config_reg->CONFIG_RAMADDRDECVECT[1U] = tcram2REG->RAMADDRDECVECT; + } +} + +/** @fn customTrimLPO(void) +* @brief custom function to initilize LPO trim values +* +* This function initializes default LPO trim values if OTP value is 0XFFFF, +* user can also write their own code to handle this case . +* +*/ +void customTrimLPO(void) +{ + /* User can write logic to handle the case where LPO trim is set to 0xFFFFu */ +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + + /* Load default trimLPO value */ + systemREG1->LPOMONCTL = (uint32)((uint32)1U << 24U) + | (uint32)((uint32)16U << 8U) + | (uint32)((uint32)16U); + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ +} diff --git a/src/arch/rm46l8lp/prompt b/src/arch/rm46l8lp/prompt new file mode 100644 index 0000000..673d232 --- /dev/null +++ b/src/arch/rm46l8lp/prompt @@ -0,0 +1 @@ +Hercules RM46L8 Launchpad |