PrIM -- first commit

12 files changed, 987 insertions, 0 deletions

diff --git a/Microbenchmarks/STREAM/Makefile b/Microbenchmarks/STREAM/Makefile
new file mode 100644
index 0000000..c669857
--- /dev/null
+++ b/Microbenchmarks/STREAM/Makefile
@@ -0,0 +1,46 @@
+DPU_DIR := dpu
+HOST_DIR := host
+BUILDDIR ?= bin
+NR_TASKLETS ?= 16
+BL ?= 10
+NR_DPUS ?= 1
+OP ?= copy
+MEM ?= MRAM
+
+define conf_filename
+	${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_$(4)_$(5).conf
+endef
+CONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${OP},${MEM})
+
+HOST_TARGET := ${BUILDDIR}/host_code
+DPU_TARGET := ${BUILDDIR}/dpu_code
+
+COMMON_INCLUDES := support
+HOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)
+DPU_SOURCES := $(wildcard ${DPU_DIR}/${OP}.c)
+
+.PHONY: all clean test
+
+__dirs := $(shell mkdir -p ${BUILDDIR})
+
+COMMON_FLAGS := -Wall -Wextra -g -I${COMMON_INCLUDES}
+HOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${OP} -D${MEM}
+DPU_FLAGS := ${COMMON_FLAGS} -O2 -flto -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${OP} -D${MEM}
+
+all: ${HOST_TARGET} ${DPU_TARGET}
+
+${CONF}:
+	$(RM) $(call conf_filename,*,*)
+	touch ${CONF}
+
+${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}
+	$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}
+
+${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}
+	dpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}
+
+clean:
+	$(RM) -r $(BUILDDIR)
+
+test: all
+	./${HOST_TARGET}
diff --git a/Microbenchmarks/STREAM/dpu/add.c b/Microbenchmarks/STREAM/dpu/add.c
new file mode 100644
index 0000000..faf6504
--- /dev/null
+++ b/Microbenchmarks/STREAM/dpu/add.c
@@ -0,0 +1,103 @@
+/*
+* STREAM Add
+*
+*/
+#include <stdint.h>
+#include <stdio.h>
+#include <defs.h>
+#include <mram.h>
+#include <alloc.h>
+#include <perfcounter.h>
+#include <barrier.h>
+
+#include "../support/common.h"
+#include "../support/cyclecount.h"
+
+__host dpu_arguments_t DPU_INPUT_ARGUMENTS;
+__host dpu_results_t DPU_RESULTS[NR_TASKLETS];
+
+// Add
+static void add_dpu(T *bufferC, T *bufferA, T *bufferB) {
+
+    #pragma unroll
+    for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++){
+        bufferC[i] = bufferA[i] + bufferB[i];
+    }
+
+}
+
+// Barrier
+BARRIER_INIT(my_barrier, NR_TASKLETS);
+
+extern int main_kernel1(void);
+
+int (*kernels[nr_kernels])(void) = {main_kernel1};
+
+int main(void) { 
+    // Kernel
+    return kernels[DPU_INPUT_ARGUMENTS.kernel](); 
+}
+
+// main_kernel1
+int main_kernel1() {
+    unsigned int tasklet_id = me();
+#if PRINT
+    printf("tasklet_id = %u\n", tasklet_id);
+#endif
+    if (tasklet_id == 0){ // Initialize once the cycle counter
+        mem_reset(); // Reset the heap
+
+        perfcounter_config(COUNT_CYCLES, true);
+    }
+    perfcounter_cycles cycles;
+    // Barrier
+    barrier_wait(&my_barrier);
+#ifndef WRAM
+    timer_start(&cycles); // START TIMER
+#endif
+
+    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);
+
+    dpu_results_t *result = &DPU_RESULTS[tasklet_id];
+    result->cycles = 0;
+
+    // Address of the current processing block in MRAM
+    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));
+    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));
+    uint32_t mram_base_addr_C = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + 2 * input_size_dpu * sizeof(T));
+
+    // Initialize a local cache to store the MRAM block
+    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);
+    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);
+
+    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){
+
+        // Load cache with current MRAM block
+        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);
+        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, BLOCK_SIZE);
+
+#ifdef WRAM
+        // Barrier
+        barrier_wait(&my_barrier);
+        timer_start(&cycles); // START TIMER
+#endif
+
+        // Add
+        add_dpu(cache_B, cache_A, cache_B);
+
+#ifdef WRAM
+        result->cycles += timer_stop(&cycles); // STOP TIMER
+	    // Barrier
+        barrier_wait(&my_barrier);
+#endif
+
+        // Write cache to current MRAM block
+        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_C + byte_index), BLOCK_SIZE);
+
+    }
+
+#ifndef WRAM
+    result->cycles = timer_stop(&cycles); // STOP TIMER
+#endif
+    return 0;
+}
diff --git a/Microbenchmarks/STREAM/dpu/copy.c b/Microbenchmarks/STREAM/dpu/copy.c
new file mode 100644
index 0000000..ff4df42
--- /dev/null
+++ b/Microbenchmarks/STREAM/dpu/copy.c
@@ -0,0 +1,75 @@
+/*
+* STREAM Copy
+*
+*/
+#include <stdint.h>
+#include <stdio.h>
+#include <defs.h>
+#include <mram.h>
+#include <alloc.h>
+#include <perfcounter.h>
+#include <barrier.h>
+
+#include "../support/common.h"
+#include "../support/cyclecount.h"
+
+__host dpu_arguments_t DPU_INPUT_ARGUMENTS;
+__host dpu_results_t DPU_RESULTS[NR_TASKLETS];
+
+// Barrier
+BARRIER_INIT(my_barrier, NR_TASKLETS);
+
+extern int main_kernel1(void);
+
+int (*kernels[nr_kernels])(void) = {main_kernel1};
+
+int main(void) { 
+    // Kernel
+    return kernels[DPU_INPUT_ARGUMENTS.kernel](); 
+}
+
+// main_kernel1
+int main_kernel1() {
+    unsigned int tasklet_id = me();
+#if PRINT
+    printf("tasklet_id = %u\n", tasklet_id);
+#endif
+    if (tasklet_id == 0){ // Initialize once the cycle counter
+        mem_reset(); // Reset the heap
+
+        perfcounter_config(COUNT_CYCLES, true);
+    }
+    perfcounter_cycles cycles;
+    // Barrier
+    barrier_wait(&my_barrier);
+#ifndef WRAM
+    timer_start(&cycles); // START TIMER
+#endif
+
+    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);
+
+    dpu_results_t *result = &DPU_RESULTS[tasklet_id];
+    result->cycles = 0;
+
+    // Address of the current processing block in MRAM
+    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));
+    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));
+
+    // Initialize a local cache to store the MRAM block
+    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);
+
+    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){
+
+        // Load cache with current MRAM block
+        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);
+
+        // Write cache to current MRAM block
+        mram_write(cache_A, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);
+
+    }
+
+#ifndef WRAM
+    result->cycles = timer_stop(&cycles); // STOP TIMER
+#endif
+    return 0;
+}
diff --git a/Microbenchmarks/STREAM/dpu/copyw.c b/Microbenchmarks/STREAM/dpu/copyw.c
new file mode 100644
index 0000000..eff7a3b
--- /dev/null
+++ b/Microbenchmarks/STREAM/dpu/copyw.c
@@ -0,0 +1,101 @@
+/*
+* STREAM Copy (WRAM)
+*
+*/
+#include <stdint.h>
+#include <stdio.h>
+#include <defs.h>
+#include <mram.h>
+#include <alloc.h>
+#include <perfcounter.h>
+#include <barrier.h>
+
+#include "../support/common.h"
+#include "../support/cyclecount.h"
+
+__host dpu_arguments_t DPU_INPUT_ARGUMENTS;
+__host dpu_results_t DPU_RESULTS[NR_TASKLETS];
+
+// Copy
+static void copyw_dpu(T *bufferB, T *bufferA) {
+
+    #pragma unroll
+    for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++){
+        bufferB[i] = bufferA[i];
+    }
+
+}
+
+// Barrier
+BARRIER_INIT(my_barrier, NR_TASKLETS);
+
+extern int main_kernel1(void);
+
+int (*kernels[nr_kernels])(void) = {main_kernel1};
+
+int main(void) { 
+    // Kernel
+    return kernels[DPU_INPUT_ARGUMENTS.kernel](); 
+}
+
+// main_kernel1
+int main_kernel1() {
+    unsigned int tasklet_id = me();
+#if PRINT
+    printf("tasklet_id = %u\n", tasklet_id);
+#endif
+    if (tasklet_id == 0){ // Initialize once the cycle counter
+        mem_reset(); // Reset the heap
+
+        perfcounter_config(COUNT_CYCLES, true);
+    }
+    perfcounter_cycles cycles;
+    // Barrier
+    barrier_wait(&my_barrier);
+#ifndef WRAM
+    timer_start(&cycles); // START TIMER
+#endif
+
+    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);
+
+    dpu_results_t *result = &DPU_RESULTS[tasklet_id];
+    result->cycles = 0;
+
+    // Address of the current processing block in MRAM
+    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));
+    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));
+
+    // Initialize a local cache to store the MRAM block
+    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);
+    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);
+
+    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){
+
+        // Load cache with current MRAM block
+        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);
+
+#ifdef WRAM
+	    // Barrier
+	    barrier_wait(&my_barrier);
+        timer_start(&cycles); // START TIMER
+#endif
+
+        // Copy
+        copyw_dpu(cache_B, cache_A);
+
+#ifdef WRAM
+        result->cycles += timer_stop(&cycles); // STOP TIMER
+	    // Barrier
+	    barrier_wait(&my_barrier);
+#endif
+
+        // Write cache to current MRAM block
+        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);
+
+    }
+
+#ifndef WRAM
+    result->cycles = timer_stop(&cycles); // STOP TIMER
+#endif
+    return 0;
+}
diff --git a/Microbenchmarks/STREAM/dpu/scale.c b/Microbenchmarks/STREAM/dpu/scale.c
new file mode 100644
index 0000000..4247aac
--- /dev/null
+++ b/Microbenchmarks/STREAM/dpu/scale.c
@@ -0,0 +1,103 @@
+/*
+* STREAM Scale
+*
+*/
+#include <stdint.h>
+#include <stdio.h>
+#include <defs.h>
+#include <mram.h>
+#include <alloc.h>
+#include <perfcounter.h>
+#include <barrier.h>
+
+#include "../support/common.h"
+#include "../support/cyclecount.h"
+
+__host dpu_arguments_t DPU_INPUT_ARGUMENTS;
+__host dpu_results_t DPU_RESULTS[NR_TASKLETS];
+
+// Scale
+static void scale_dpu(T *bufferB, T *bufferA, T scalar) {
+
+    #pragma unroll
+    for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++){
+        bufferB[i] = scalar * bufferA[i];
+    }
+
+}
+
+// Barrier
+BARRIER_INIT(my_barrier, NR_TASKLETS);
+
+extern int main_kernel1(void);
+
+int (*kernels[nr_kernels])(void) = {main_kernel1};
+
+int main(void) { 
+    // Kernel
+    return kernels[DPU_INPUT_ARGUMENTS.kernel](); 
+}
+
+// main_kernel1
+int main_kernel1() {
+    unsigned int tasklet_id = me();
+#if PRINT
+    printf("tasklet_id = %u\n", tasklet_id);
+#endif
+    if (tasklet_id == 0){ // Initialize once the cycle counter
+        mem_reset(); // Reset the heap
+
+        perfcounter_config(COUNT_CYCLES, true);
+    }
+    perfcounter_cycles cycles;
+    // Barrier
+    barrier_wait(&my_barrier);
+#ifndef WRAM
+    timer_start(&cycles); // START TIMER
+#endif
+
+    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);
+
+    T scalar = (T)input_size_dpu; // Simply use this number as a scalar
+
+    dpu_results_t *result = &DPU_RESULTS[tasklet_id];
+    result->cycles = 0;
+
+    // Address of the current processing block in MRAM
+    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));
+    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));
+
+    // Initialize a local cache to store the MRAM block
+    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);
+    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);
+
+    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){
+
+        // Load cache with current MRAM block
+        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);
+
+#ifdef WRAM
+	    // Barrier
+	    barrier_wait(&my_barrier);
+        timer_start(&cycles); // START TIMER
+#endif
+
+        // Scale
+        scale_dpu(cache_B, cache_A, scalar);
+
+#ifdef WRAM
+        result->cycles += timer_stop(&cycles); // STOP TIMER
+	    // Barrier
+	    barrier_wait(&my_barrier);
+#endif
+
+        // Write cache to current MRAM block
+        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);
+
+    }
+
+#ifndef WRAM
+    result->cycles = timer_stop(&cycles); // STOP TIMER
+#endif
+    return 0;
+}
diff --git a/Microbenchmarks/STREAM/dpu/triad.c b/Microbenchmarks/STREAM/dpu/triad.c
new file mode 100644
index 0000000..e81cb59
--- /dev/null
+++ b/Microbenchmarks/STREAM/dpu/triad.c
@@ -0,0 +1,105 @@
+/*
+* STREAM Triad
+*
+*/
+#include <stdint.h>
+#include <stdio.h>
+#include <defs.h>
+#include <mram.h>
+#include <alloc.h>
+#include <perfcounter.h>
+#include <barrier.h>
+
+#include "../support/common.h"
+#include "../support/cyclecount.h"
+
+__host dpu_arguments_t DPU_INPUT_ARGUMENTS;
+__host dpu_results_t DPU_RESULTS[NR_TASKLETS];
+
+// Triad
+static void triad_dpu(T *bufferC, T *bufferA, T *bufferB, T scalar) {
+
+    #pragma unroll
+    for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++){
+        bufferC[i] = bufferA[i] + scalar * bufferB[i];
+    }
+
+}
+
+// Barrier
+BARRIER_INIT(my_barrier, NR_TASKLETS);
+
+extern int main_kernel1(void);
+
+int (*kernels[nr_kernels])(void) = {main_kernel1};
+
+int main(void) { 
+    // Kernel
+    return kernels[DPU_INPUT_ARGUMENTS.kernel](); 
+}
+
+// main_kernel1
+int main_kernel1() {
+    unsigned int tasklet_id = me();
+#if PRINT
+    printf("tasklet_id = %u\n", tasklet_id);
+#endif
+    if (tasklet_id == 0){ // Initialize once the cycle counter
+        mem_reset(); // Reset the heap
+
+        perfcounter_config(COUNT_CYCLES, true);
+    }
+    perfcounter_cycles cycles;
+    // Barrier
+    barrier_wait(&my_barrier);
+#ifndef WRAM
+    timer_start(&cycles); // START TIMER
+#endif
+
+    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);
+
+    T scalar = (T)input_size_dpu; // Simply use this number as a scalar
+
+    dpu_results_t *result = &DPU_RESULTS[tasklet_id];
+    result->cycles = 0;
+
+    // Address of the current processing block in MRAM
+    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));
+    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));
+    uint32_t mram_base_addr_C = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + 2 * input_size_dpu * sizeof(T));
+
+    // Initialize a local cache to store the MRAM block
+    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);
+    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);
+
+    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){
+
+        // Load cache with current MRAM block
+        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);
+        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, BLOCK_SIZE);
+
+#ifdef WRAM
+	    // Barrier
+	    barrier_wait(&my_barrier);
+        timer_start(&cycles); // START TIMER
+#endif
+
+        // Triad
+        triad_dpu(cache_B, cache_A, cache_B, scalar);
+
+#ifdef WRAM
+        result->cycles += timer_stop(&cycles); // STOP TIMER
+	    // Barrier
+	    barrier_wait(&my_barrier);
+#endif
+
+        // Write cache to current MRAM block
+        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_C + byte_index), BLOCK_SIZE);
+
+    }
+
+#ifndef WRAM
+    result->cycles = timer_stop(&cycles); // STOP TIMER
+#endif
+    return 0;
+}
diff --git a/Microbenchmarks/STREAM/host/app.c b/Microbenchmarks/STREAM/host/app.c
new file mode 100644
index 0000000..4571e96
--- /dev/null
+++ b/Microbenchmarks/STREAM/host/app.c
@@ -0,0 +1,248 @@
+/**
+* app.c
+* STREAM Host Application Source File
+*
+*/
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <string.h>
+#include <dpu.h>
+#include <dpu_log.h>
+#include <unistd.h>
+#include <getopt.h>
+#include <assert.h>
+
+#include "../support/common.h"
+#include "../support/timer.h"
+#include "../support/params.h"
+
+// Define the DPU Binary path as DPU_BINARY here
+#ifndef DPU_BINARY
+#define DPU_BINARY "./bin/dpu_code"
+#endif
+
+// Pointer declaration
+static T* A;
+static T* B;
+#if defined(add) || defined(triad)
+static T* C;
+#endif
+static T* C2;
+
+// Create input arrays
+static void read_input(T* A, T* B, unsigned int nr_elements) {
+    srand(0);
+    printf("nr_elements\t%u\t", nr_elements);
+    for (unsigned int i = 0; i < nr_elements; i++) {
+        A[i] = (T) (rand());
+        B[i] = (T) (rand());
+    }
+}
+
+// Compute output in the host
+#if defined(add) || defined(triad)
+static void stream_host(T* C, T* B, T* A, unsigned int nr_elements) {
+#else
+static void stream_host(T* C, T* A, unsigned int nr_elements) {
+#endif
+    for (unsigned int i = 0; i < nr_elements; i++) {
+#ifdef scale
+        C[i] = (nr_elements / NR_DPUS) * A[i];
+#elif add
+        C[i] = A[i] + B[i];
+#elif triad
+        C[i] = A[i] + (nr_elements / NR_DPUS) * B[i];
+#else // copy
+        C[i] = A[i];
+#endif
+    }
+}
+
+// Main of the Host Application
+int main(int argc, char **argv) {
+
+    struct Params p = input_params(argc, argv);
+
+    struct dpu_set_t dpu_set, dpu;
+    uint32_t nr_of_dpus;
+    
+    // Allocate DPUs and load binary
+    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));
+    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));
+    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));
+    printf("Allocated %d DPU(s)\n", nr_of_dpus);
+
+    unsigned int i = 0;
+    double cc = 0;
+    double cc_min = 0;
+    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;
+
+    // Input/output allocation
+    A = malloc(input_size * sizeof(T));
+    B = malloc(input_size * sizeof(T));
+    T *bufferA = A;
+    T *bufferB = B;
+#if defined(add) || defined(triad)
+    C = malloc(input_size * sizeof(T));
+    T *bufferC = C;
+#endif
+    C2 = malloc(input_size * sizeof(T));
+
+    // Create an input file with arbitrary data
+    read_input(A, B, input_size);
+
+    // Timer declaration
+    Timer timer;
+
+    printf("NR_TASKLETS\t%d\tBL\t%d\n", NR_TASKLETS, BL);
+
+    // Loop over main kernel
+    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {
+
+        // Compute output on CPU (performance comparison and verification purposes)
+        if(rep >= p.n_warmup)
+            start(&timer, 0, rep - p.n_warmup);
+#if defined(add) || defined(triad)
+        stream_host(C2, B, A, input_size);
+#else
+        stream_host(C2, A, input_size);
+#endif
+        if(rep >= p.n_warmup)
+            stop(&timer, 0);
+
+        printf("Load input data\n");
+        if(rep >= p.n_warmup)
+            start(&timer, 1, rep - p.n_warmup);
+        // Input arguments
+        const unsigned int input_size_dpu = input_size / nr_of_dpus;
+        unsigned int kernel = 0;
+        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel};
+        DPU_ASSERT(dpu_copy_to(dpu_set, "DPU_INPUT_ARGUMENTS", 0, (const void *)&input_arguments, sizeof(input_arguments)));
+        // Copy input arrays
+        i = 0;
+        DPU_FOREACH (dpu_set, dpu) {
+            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferA + input_size_dpu * i, input_size_dpu * sizeof(T)));
+#if defined(add) || defined(triad)
+            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferB + input_size_dpu * i, input_size_dpu * sizeof(T)));
+#endif
+            i++;
+        }
+        if(rep >= p.n_warmup)
+            stop(&timer, 1);
+
+        printf("Run program on DPU(s) \n");
+        // Run DPU kernel
+        if(rep >= p.n_warmup)
+            start(&timer, 2, rep - p.n_warmup);
+        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));
+        if(rep >= p.n_warmup)
+            stop(&timer, 2);
+
+#if PRINT
+        {
+            unsigned int each_dpu = 0;
+            printf("Display DPU Logs\n");
+            DPU_FOREACH (dpu_set, dpu) {
+                printf("DPU#%d:\n", each_dpu);
+                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));
+                each_dpu++;
+            }
+        }
+#endif
+
+        printf("Retrieve results\n");
+        if(rep >= p.n_warmup)
+            start(&timer, 3, rep - p.n_warmup);
+        dpu_results_t results[nr_of_dpus];
+        i = 0;
+        DPU_FOREACH (dpu_set, dpu) {
+            // Copy output array
+#if defined(add) || defined(triad)
+            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, 2 * input_size_dpu * sizeof(T), bufferC + input_size_dpu * i, input_size_dpu * sizeof(T)));
+#else
+            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferB + input_size_dpu * i, input_size_dpu * sizeof(T)));
+#endif
+			
+#if PERF
+            results[i].cycles = 0;
+            // Retrieve tasklet timings
+            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {
+                dpu_results_t result;
+                result.cycles = 0;
+                DPU_ASSERT(dpu_copy_from(dpu, "DPU_RESULTS", each_tasklet * sizeof(dpu_results_t), &result, sizeof(dpu_results_t)));
+                if (result.cycles > results[i].cycles)
+                    results[i].cycles = result.cycles;
+            }
+#endif
+            i++;
+        }
+        if(rep >= p.n_warmup)
+            stop(&timer, 3);
+
+#if PERF
+        uint64_t max_cycles = 0;
+        uint64_t min_cycles = 0xFFFFFFFFFFFFFFFF;
+        // Print performance results
+        if(rep >= p.n_warmup){
+            i = 0;
+            DPU_FOREACH(dpu_set, dpu) {
+                if(results[i].cycles > max_cycles)
+                    max_cycles = results[i].cycles;
+                if(results[i].cycles < min_cycles)
+                    min_cycles = results[i].cycles;
+                i++;
+            }
+            cc += (double)max_cycles;
+            cc_min += (double)min_cycles;
+        }
+#endif
+
+    }
+    printf("DPU cycles  = %g cc\n", cc / p.n_reps);
+
+    // Print timing results
+    printf("CPU ");
+    print(&timer, 0, p.n_reps);
+    printf("CPU-DPU ");
+    print(&timer, 1, p.n_reps);
+    printf("DPU Kernel ");
+    print(&timer, 2, p.n_reps);
+    printf("DPU-CPU ");
+    print(&timer, 3, p.n_reps);
+
+    // Check output
+    bool status = true;
+    for (i = 0; i < input_size; i++) {
+#if defined(add) || defined(triad)
+        if(C2[i] != bufferC[i]){ 
+#else
+        if(C2[i] != bufferB[i]){ 
+#endif
+            status = false;
+#if PRINT
+#if defined(add) || defined(triad)
+            printf("%d: %u -- %u\n", i, C2[i], bufferC[i]);
+#else
+            printf("%d: %u -- %u\n", i, C2[i], bufferB[i]);
+#endif
+#endif
+        }
+    }
+    if (status) {
+        printf("[" ANSI_COLOR_GREEN "OK" ANSI_COLOR_RESET "] Outputs are equal\n");
+    } else {
+        printf("[" ANSI_COLOR_RED "ERROR" ANSI_COLOR_RESET "] Outputs differ!\n");
+    }
+
+    // Deallocation
+    free(A);
+    free(B);
+#if defined(add) || defined(triad)
+    free(C);
+#endif
+    free(C2);
+    DPU_ASSERT(dpu_free(dpu_set));
+	
+    return status ? 0 : -1;
+}
diff --git a/Microbenchmarks/STREAM/run.sh b/Microbenchmarks/STREAM/run.sh
new file mode 100755
index 0000000..141b01c
--- /dev/null
+++ b/Microbenchmarks/STREAM/run.sh
@@ -0,0 +1,35 @@
+#!/bin/bash
+
+# MRAM
+for i in copy copyw add scale triad
+do
+	for j in 1 
+	do 	
+        for k in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 
+        do 	
+            NR_DPUS=$j NR_TASKLETS=$k BL=10 MEM=MRAM OP=$i make all
+            wait
+            ./bin/host_code -w 0 -e 1 -i 2097152 >& profile/${i}_${j}_tl${k}_MRAM.txt
+            wait
+            make clean
+            wait
+        done
+	done
+done
+
+# WRAM
+for i in copyw add scale triad
+do
+	for j in 1 
+	do 	
+        for k in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 
+        do 	
+            NR_DPUS=$j NR_TASKLETS=$k BL=10 MEM=WRAM OP=$i make all
+            wait
+            ./bin/host_code -w 0 -e 1 -i 2097152 >& profile/${i}_${j}_tl${k}_WRAM.txt
+            wait
+            make clean
+            wait
+        done
+	done
+done
diff --git a/Microbenchmarks/STREAM/support/common.h b/Microbenchmarks/STREAM/support/common.h
new file mode 100755
index 0000000..8e2e59b
--- /dev/null
+++ b/Microbenchmarks/STREAM/support/common.h
@@ -0,0 +1,36 @@
+#ifndef _COMMON_H_
+#define _COMMON_H_
+
+// Structures used by both the host and the dpu to communicate information 
+typedef struct {
+    uint32_t size;
+	enum kernels {
+	    kernel1 = 0,
+	    nr_kernels = 1,
+	} kernel;
+} dpu_arguments_t;
+
+typedef struct {
+    uint64_t cycles;
+} dpu_results_t;
+
+// Transfer size between MRAM and WRAM
+#ifdef BL
+#define BLOCK_SIZE_LOG2 BL
+#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)
+#else
+#define BLOCK_SIZE_LOG2 8
+#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)
+#define BL BLOCK_SIZE_LOG2
+#endif
+
+// Data type
+#define T uint64_t
+
+#define PERF 1 // Use perfcounters?
+#define PRINT 0
+
+#define ANSI_COLOR_RED     "\x1b[31m"
+#define ANSI_COLOR_GREEN   "\x1b[32m"
+#define ANSI_COLOR_RESET   "\x1b[0m"
+#endif
diff --git a/Microbenchmarks/STREAM/support/cyclecount.h b/Microbenchmarks/STREAM/support/cyclecount.h
new file mode 100644
index 0000000..4ef377e
--- /dev/null
+++ b/Microbenchmarks/STREAM/support/cyclecount.h
@@ -0,0 +1,20 @@
+#include <perfcounter.h>
+
+// Timer
+typedef struct perfcounter_cycles{
+    perfcounter_t start;
+    perfcounter_t end;
+    perfcounter_t end2;
+
+}perfcounter_cycles;
+
+void timer_start(perfcounter_cycles *cycles){
+    cycles->start = perfcounter_get(); // START TIMER
+}
+
+uint64_t timer_stop(perfcounter_cycles *cycles){
+    cycles->end = perfcounter_get(); // STOP TIMER
+    cycles->end2 = perfcounter_get(); // STOP TIMER
+    return(((uint64_t)((uint32_t)(((cycles->end >> 4) - (cycles->start >> 4)) - ((cycles->end2 >> 4) - (cycles->end >> 4))))) << 4);
+}
+
diff --git a/Microbenchmarks/STREAM/support/params.h b/Microbenchmarks/STREAM/support/params.h
new file mode 100644
index 0000000..4618411
--- /dev/null
+++ b/Microbenchmarks/STREAM/support/params.h
@@ -0,0 +1,56 @@
+#ifndef _PARAMS_H_
+#define _PARAMS_H_
+
+#include "common.h"
+
+typedef struct Params {
+    unsigned int   input_size;
+    int   n_warmup;
+    int   n_reps;
+    int  exp;
+}Params;
+
+static void usage() {
+    fprintf(stderr,
+        "\nUsage:  ./program [options]"
+        "\n"
+        "\nGeneral options:"
+        "\n    -h        help"
+        "\n    -w <W>    # of untimed warmup iterations (default=1)"
+        "\n    -e <E>    # of timed repetition iterations (default=3)"
+        "\n    -x <X>    Weak (0) or strong (1) scaling (default=0)"
+        "\n"
+        "\nBenchmark-specific options:"
+        "\n    -i <I>    input size (default=8K elements)"
+        "\n");
+}
+
+struct Params input_params(int argc, char **argv) {
+    struct Params p;
+    p.input_size    = 8 << 10;
+    p.n_warmup      = 1;
+    p.n_reps        = 3;
+    p.exp           = 0;
+
+    int opt;
+    while((opt = getopt(argc, argv, "hi:w:e:x:")) >= 0) {
+        switch(opt) {
+        case 'h':
+        usage();
+        exit(0);
+        break;
+        case 'i': p.input_size    = atoi(optarg); break;
+        case 'w': p.n_warmup      = atoi(optarg); break;
+        case 'e': p.n_reps        = atoi(optarg); break;
+        case 'x': p.exp           = atoi(optarg); break;
+        default:
+            fprintf(stderr, "\nUnrecognized option!\n");
+            usage();
+            exit(0);
+        }
+    }
+    assert(NR_DPUS > 0 && "Invalid # of dpus!");
+
+    return p;
+}
+#endif
diff --git a/Microbenchmarks/STREAM/support/timer.h b/Microbenchmarks/STREAM/support/timer.h
new file mode 100755
index 0000000..eedc385
--- /dev/null
+++ b/Microbenchmarks/STREAM/support/timer.h
@@ -0,0 +1,59 @@
+/*

+ * Copyright (c) 2016 University of Cordoba and University of Illinois

+ * All rights reserved.

+ *

+ * Developed by:    IMPACT Research Group

+ *                  University of Cordoba and University of Illinois

+ *                  http://impact.crhc.illinois.edu/

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * with the Software without restriction, including without limitation the 

+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or

+ * sell copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ *      > Redistributions of source code must retain the above copyright notice,

+ *        this list of conditions and the following disclaimers.

+ *      > Redistributions in binary form must reproduce the above copyright

+ *        notice, this list of conditions and the following disclaimers in the

+ *        documentation and/or other materials provided with the distribution.

+ *      > Neither the names of IMPACT Research Group, University of Cordoba, 

+ *        University of Illinois nor the names of its contributors may be used 

+ *        to endorse or promote products derived from this Software without 

+ *        specific prior written permission.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 

+ * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH

+ * THE SOFTWARE.

+ *

+ */

+

+#include <sys/time.h>

+

+typedef struct Timer{

+

+    struct timeval startTime[4];

+    struct timeval stopTime[4];

+    double         time[4];

+

+}Timer;

+

+void start(Timer *timer, int i, int rep) {

+    if(rep == 0) {

+        timer->time[i] = 0.0;

+    }

+    gettimeofday(&timer->startTime[i], NULL);

+}

+

+void stop(Timer *timer, int i) {

+    gettimeofday(&timer->stopTime[i], NULL);

+    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +

+                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);

+}

+

+void print(Timer *timer, int i, int REP) { printf("Time (ms): %f\t", timer->time[i] / (1000 * REP)); }